Memory device and method of manufacturing memory device

Abstract

The present disclosure includes memory devices and methods of manufacturing memory devices. The memory device includes: a channel layer passing through gate lines stacked spaced apart from each other; a channel junction extending on the channel layer; a capping layer surrounded by the channel layer; a void surrounded by the cover layer; a capping pattern surrounded by the channel junction and contacting the void and an upper portion of the capping layer; and a source line on the gate line and contacting the channel junction.

Description

Technical Field

[0001] The present disclosure generally relates to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device manufactured by a wafer bonding technology and a method of manufacturing the memory device manufactured by the wafer bonding technology. Background Art

[0002] The memory device may include a memory cell array in which data is stored, and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation of the memory cell array.

[0003] The memory cell array may include a plurality of memory blocks between the bit lines and the source lines, and each of the plurality of memory blocks may include a cell plug extending in a vertical direction from the substrate. The cell plug may include a source selection transistor, a memory cell, and a drain selection transistor. When the memory block is located on a peripheral circuit, the bit line may be located between the peripheral circuit and the memory block, and the source line may be located on the memory block.

[0004] Because source lines are commonly connected to cell plugs included in each memory block, resistance between the source lines and the cell plugs may increase as the number of memory blocks increases, and thus reliability of operation of a memory device using the source lines may decrease. Summary of the invention

[0005] According to an embodiment of the present disclosure, a memory device may include: a channel layer passing through gate lines stacked apart from each other; a channel junction extending from the channel layer; a covering layer surrounded by the channel layer; a gap surrounded by the covering layer; a covering pattern surrounded by the channel junction and contacting an upper portion of the gap and the covering layer; and a source line located on the gate line and contacting the channel junction.

[0006] According to an embodiment of the present disclosure, a memory device may include: a stacked structure including alternately stacked insulating layers and gate lines; a cell plug included in the stacked structure and passing through the insulating layers and the gate lines; a channel layer included in the cell plug; a gap surrounded by the channel layer; a tunnel insulating layer surrounding the channel layer; a charge trapping layer surrounding the tunnel insulating layer; and a blocking layer surrounding the charge trapping layer; a channel junction included in the cell plug and extending from the channel layer; a covering pattern included in the cell plug and surrounded by at least a portion of the channel layer and the channel junction; and a source line located on the stacked structure and contacting the channel junction and the covering pattern.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a memory device may include the following steps: forming a stacked structure including a cell plug, the cell plug including: a blocking layer passing through alternately stacked first material layers and gate lines, a charge trapping layer surrounded by the blocking layer, a tunnel insulating layer surrounded by the charge trapping layer, a channel layer surrounded by the tunnel insulating layer, a covering layer surrounded by the channel layer, and a gap surrounded by the covering layer; forming a covering pattern of a portion of an upper portion filling the gap; performing an ion implantation process for converting a portion of the channel layer surrounding the covering pattern into a channel junction having an impurity concentration higher than that of the channel layer; and forming a source line contacting the channel junction on the stacked structure.

[0008] According to an embodiment of the present disclosure, a method for manufacturing a memory device may include the following steps: forming a stacked structure including a cell plug, the cell plug including: a blocking layer extending to a portion of a sacrificial structure located at the uppermost end by passing through alternately stacked first material layers and gate lines, a charge trapping layer surrounded by the blocking layer, a tunnel insulating layer surrounded by the charge trapping layer, a channel layer surrounded by the tunnel insulating layer, a covering layer surrounded by the channel layer, and a void surrounded by the covering layer; exposing a protrusion protruding on the stacked structure of the cell plug by removing the sacrificial structure; performing an ion implantation process for converting a portion of the channel layer included in the protrusion into a channel junction having an impurity concentration higher than that of the channel layer; exposing the void by removing a portion of the blocking layer, the charge trapping layer, the tunnel insulating layer, and the channel junction included in the protrusion; forming a covering pattern filling a portion of an upper portion of the void; and forming a source line contacting the channel junction on the stacked structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a memory device.

[0010] Figure 2 is a diagram illustrating a memory cell array.

[0011] Figure 3 is a diagram illustrating a storage block.

[0012] Figure 4 is a diagram illustrating a memory device according to a first embodiment of the present disclosure.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig.5I , Figure 5J , Figure 5K , Figure 5L and Figure 5M is a diagram illustrating a method of manufacturing a memory device according to a first embodiment of the present disclosure.

[0014] Figure 6 is a diagram illustrating a memory device according to a second embodiment of the present disclosure.

[0015] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F and Figure 7G is a diagram illustrating a method of manufacturing a memory device according to a second embodiment of the present disclosure.

[0016] Figure 8 is a diagram illustrating a memory device according to a third embodiment of the present disclosure.

[0017] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G and Figure 9H is a diagram illustrating a method of manufacturing a memory device according to a third embodiment of the present disclosure.

[0018] Fig.10 is a diagram illustrating a memory device according to a fourth embodiment of the present disclosure.

[0019] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E , Fig.11F and Fig.11G is a diagram illustrating a method of manufacturing a memory device according to a fourth embodiment of the present disclosure.

[0020] Fig.12 is a diagram illustrating a memory device according to a fifth embodiment of the present disclosure.

[0021] Fig.13A , Fig. 13B , Fig. 13C , Fig.13D and Fig.13E is a diagram illustrating a method of manufacturing a memory device according to a fifth embodiment of the present disclosure.

[0022] Fig.14 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0023] Fig.15is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0024] The specific structural or functional description disclosed below is exemplified to describe the embodiment according to the concept of the present disclosure. The embodiment according to the concept of the present disclosure is not to be interpreted as being limited to the embodiment described below, and various modifications and replacements may be made with other equivalent embodiments.

[0025] Hereinafter, terms such as first and second can be used to describe various components, but these components are not limited by these terms. These terms are used for the purpose of distinguishing one component from another component. These terms are only used to distinguish one element from another element, and are not intended to imply the order or quantity of the element. Therefore, without departing from the teaching of the present disclosure, the first element in some embodiments can be referred to as the second element in other embodiments. It will be understood that when an element or layer, etc. is referred to as "on" another element or layer, etc., "connected to" or "coupled to" another element or layer, etc., it can be directly on another element or layer, etc., directly connected to or coupled to another element or layer, etc., or there can be an intermediate element or layer, etc. On the contrary, when an element or layer, etc. is referred to as "directly on" another element or layer, etc., "directly connected to" or "directly coupled to" another element or layer, etc., there is no intermediate element or layer, etc.

[0026] Embodiments of the present disclosure provide a memory device capable of reducing resistance between a source line and a cell plug and a method of manufacturing the memory device.

[0027] The embodiments of the present technology can form the impurity concentration of the channel junction uniformly, thereby improving the reliability of the memory device.

[0028] Figure 1 is a diagram illustrating a memory device.

[0029] Reference Figure 1 , the memory device 100 may include a memory cell array 110 and a peripheral circuit 180 .

[0030] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly connected to the first to j-th memory blocks BLK1 to BLKj.

[0031] The first to j-th memory blocks BLK1 to BLKj may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked in a vertical direction on a substrate.

[0032] The memory cell can store 1 bit or 2 bits or more bits of data according to the programming method. For example, the method of storing 1 bit of data in one memory cell is called a single-level cell method, and the method of storing 2 bits of data in one memory cell is called a multi-level cell method. The method of storing 3 bits of data in one memory cell is called a three-level cell method, and the method of storing 4 bits of data in one memory cell is called a four-level cell method. In addition, five or more bits of data can be stored in one memory cell.

[0033] The peripheral circuit 180 may be configured to perform a program operation of storing data in the memory cell array 110, a read operation of outputting data stored in the memory cell array 110, and an erase operation of erasing data stored in the memory cell array 110. For example, the peripheral circuit 180 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0034] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the memory block selected by the row decoder 130.

[0035] The programming voltage may be a voltage applied to a selected word line among word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line during a read operation. A verification voltage may be used to determine whether the threshold voltage of a selected memory cell is increased to a target level during a verification operation. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0036] A read voltage may be applied to a selected word line during a read operation of a selected memory cell. For example, the read voltage may be set to various levels according to a programming method of the selected memory cell. A pass voltage may be a voltage applied to an unselected word line among word lines WL during a programming operation or a read operation, and may be used to turn on a memory cell connected to the unselected word line.

[0037] The erase voltage may be used to erase memory cells included in a selected memory block during an erase operation, and may be applied to the source line SL.

[0038] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0039] The page buffer group 140 may include page buffers PB1 to PBn (not shown) connected to the first to j-th memory blocks BLK1 to BLKj. Each of the page buffers (not shown) may be connected to the first to j-th memory blocks BLK1 to BLKj through a bit line BL. During a read operation, the page buffer (not shown) may sense a current or voltage of a bit line that varies according to a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and store the sensed data.

[0040] The column decoder 150 may be configured so that data is transmitted between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL and may transmit an enable signal through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0041] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external controller to the control circuit 170 through the input / output line I / O, and may send data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0042] The control circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 170 is a command corresponding to a program operation, the control circuit 170 may control a device included in the peripheral circuit 180 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 170 is a command corresponding to a read operation, the control circuit 170 may control a device included in the peripheral circuit 180 to perform a read operation of a memory block selected by the address and output the read data. When the command CMD input to the control circuit 170 is a command corresponding to an erase operation, the control circuit 170 may control a device included in the peripheral circuit 180 to perform an erase operation of a selected memory block.

[0043] Figure 2 is a diagram illustrating a memory cell array.

[0044] Reference Figure 2 , the memory cell array 110 may be located on the peripheral circuit 180. The memory cell array 110 may include a first memory block BLK1 to a j-th memory block BLKj. Each of the first memory block BLK1 to the j-th memory block BLKj may include a cell plug extending in the Z direction. Each of the cell plugs may include a source selection transistor, a memory cell, and a drain selection transistor. The first memory block BLK1 to the j-th memory block BLKj may be arranged to be spaced apart from each other along the Y direction and may extend along the X direction.

[0045] The first to j-th memory blocks BLK1 to BLKj may be located between the source lines SL and the bit lines BL. The source lines SL may be located on the first to j-th memory blocks BLK1 to BLKj, and the bit lines BL may be located below the first to j-th memory blocks BLK1 to BLKj. Therefore, the bit lines BL may be located between the memory cell array 110 and the peripheral circuit 180. The source lines SL may be connected to the cell plugs on the first to j-th memory blocks BLK1 to BLKj, and the bit lines BL may be connected to the cell plugs below the first to j-th memory blocks BLK1 to BLKj.

[0046] Figure 3 is a diagram illustrating a storage block.

[0047] Reference Figure 3 , as an example shows Figure 2 The first memory block BLK1 is shown among the first to j-th memory blocks BLK1 to BLKj.

[0048] The first memory block BLK1 may include a plurality of cell strings ST connected between a source line SL and first to nth bit lines BL1 to BLn. The cell strings ST may be commonly connected to the source line SL. Among the cell strings ST, the cell strings ST arranged along the X direction may be respectively connected to the first to nth bit lines BL1 to BLn, and the cell strings ST arranged along the Y direction may be connected to the same bit line among the first to nth bit lines BL1 to BLn.

[0049] The first to nth bit lines BL1 to BLn may be electrically connected to the first to nth page buffers PB1 to PBn, respectively, included in the page buffer group 140. For example, the first bit line BL1 may be electrically connected to the first page buffer PB1, and the nth bit line BLn may be electrically connected to the nth page buffer PBn.

[0050] Each of the cell strings ST may include a source select transistor SST, first to i-th memory cells MC1 to MCi, and a drain select transistor DST. A cell string ST connected to a first bit line BL1 among the plurality of cell strings ST is described as an example as follows.

[0051] The drain select transistor DST may be connected between the first bit line BL1 and the first memory cell MC1, and the source select transistor SST may be connected between the i-th memory cell MCi and the source line SL. The first to i-th memory cells MC1 to MCi may be connected between the drain select transistor DST and the source select transistor SST. The number of the drain select transistors DST and the source select transistors SST is not limited to Figure 3 In addition to the first to i-th memory cells MC1 to MCi, dummy cells may be connected between the drain selection transistor DST and the source selection transistor SST. The first to i-th memory cells MC1 to MCi may store user data or normal data, and the dummy cells may store dummy data.

[0052] The gates of the drain selection transistors DST included in the different cell strings ST may be connected to the drain selection line DSL. The gates of the first to i-th memory cells MC1 to MCi included in the different cell strings ST may be connected to the first to i-th word lines WL1 to WLi. The gates of the source selection transistors SST included in the different cell strings ST may be connected to the source selection line SSL. A group of memory cells included in the cell strings ST arranged along the X direction and connected to the same word line may become a page PG. In the memory device, a program operation or a read operation of a selected memory block may be performed in units of page PG.

[0053] Figure 4is a diagram illustrating a memory device according to a first embodiment of the present disclosure.

[0054] Reference Figure 4 , the source line SL may be located on the stack structure STK. For example, the source line SL may be located on the gate line GL and may contact the channel junction CHj. The stack structure STK may include elements constituting a memory block. Figure 4 The cross section shown is cut along the XZ plane Figure 3 A diagram of a portion of the diagram shown.

[0055] The stacked structure STK may include alternately stacked first material layers 1MT and gate lines GL, and may include a cell plug CP passing through the first material layer 1MT and the gate line GL. The first material layer 1MT may be formed of an insulating material and is referred to as an insulating layer for insulating the gate lines GL. For example, the first material layer 1MT may be an oxide layer. The gate line GL may be formed of a conductive material. For example, the gate line GL may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or a semiconductor material such as silicon (Si) or polycrystalline silicon (Poly-Si), but is not limited thereto. The gate line GL may be used as a word line WL(i-1) and WLi or a source selection line SSL, and in addition, the gate line GL may be used as Figure 3 The drain select line DSL is shown.

[0056] The cell plugs CP may contact the source lines SL by passing through the first material layer 1MT and the gate lines GL. Each of the cell plugs CP may include a memory layer ML, a channel layer CH, a channel junction CHj, a first capping layer 1CA, a capping pattern CAp, and a void VD. The memory layer ML may surround side surfaces of the channel layer CH and the channel junction CHj.

[0057] The channel layer CH may be formed in a cylindrical shape. The channel layer CH may be formed of polysilicon. The channel junction CHj may be a region where impurities are implanted into the channel layer CH, and may be formed in a portion of the upper region 41 of the channel layer CH. For example, the channel junction CHj may be formed by implanting N-type impurities into the channel layer CH, or may be formed by implanting a mixture of N-type impurities and P-type impurities. For example, the N-type impurities may include phosphorus or arsenic, and the P-type impurities may include boron or BF2. The channel junction CHj may be located between the source line SL and the channel layer CH. For example, as Figure 4As shown, the channel junction CHj may extend from the channel layer CH. Since the channel junction CHj is a junction formed by injecting impurities into the channel layer CH, the channel junction CHj may have an impurity concentration higher than that of the channel layer CH. Therefore, the channel junction CHj may have a resistance lower than that of the channel layer CH. In an embodiment, the resistance between the source line SL and the channel layer CH may be reduced by the channel junction CHj.

[0058] The first cover layer 1CA may be formed along the inner surface of the channel layer CH. The first cover layer 1CA may be an insulating material. For example, the first cover layer 1CA may be an oxide layer. In an embodiment, the first cover layer 1CA does not completely fill the inner region surrounded by the channel layer CH. Therefore, the void VD may be formed in the region surrounded by the first cover layer 1CA.

[0059] The capping pattern CAp may be surrounded by the channel junction CHj and a portion of the channel layer CH located below the channel junction CHj, and may be located between the first capping layer 1CA and the source line SL. Figure 4 As shown, the covering pattern CAp may be in contact with the void VD and the upper portion of the first covering layer 1CA. Depending on the size or position of the void VD, the covering pattern CAp and the void VD may be in contact with each other, or may not be in contact with each other. For example, when the covering pattern CAp and the void VD are not in contact with each other, the first covering layer 1CA may be located between the covering pattern CAp and the void VD (not shown). Hereinafter, an embodiment having a structure in which the covering pattern CAp and the void VD are in contact with each other is described. In an embodiment, the covering pattern CAp may prevent or mitigate the phenomenon that the source line SL flows into the void VD in the manufacturing process of the memory device, and may prevent or mitigate the phenomenon that impurities are excessively injected into the channel layer CH in the impurity injection process for forming the channel junction CHj. Therefore, in an embodiment, a channel junction CHj into which impurities are uniformly injected may be formed. The lower surface of the covering pattern CAp may be located below or above the lower surface of the channel junction CHj. Alternatively, the lower surface of the covering pattern CAp may be located on the same plane as the lower surface of the channel junction CHj. The covering pattern CAp may be formed of an insulating material. For example, the covering pattern CAp may be formed of an oxide layer. The upper surface of the covering pattern CAp may contact the source line SL. The depth of the covering pattern CAp is not limited to a specific depth. For example, the lower surface of the covering pattern CAp may be located in a region where the source selection line SSL is located. The void VD may be an air gap surrounded by the first covering layer 1CA. Because the region surrounded by the first covering layer 1CA is the void VD in an embodiment, interference in the Z direction may be reduced during operation of the memory device. In an embodiment, as Figure 4As shown, upper surfaces of the tunnel insulating layer TX, the charge trapping layer CTL, the blocking layer BX, the channel junction CHj, and the capping pattern CAp are substantially flat with the upper surface of the stack structure STK. In some embodiments, the upper direction may be a Z direction.

[0060] The memory layer ML may include a tunnel insulating layer (tunnel isolation layer) TX surrounding the channel layer CH and the channel junction CHj, a charge trapping layer CTL surrounding the tunnel insulating layer TX, and a blocking layer BX surrounding the charge trapping layer CTL. The tunnel insulating layer TX may be formed of an oxide layer (e.g., a silicon oxide layer). The charge trapping layer CTL may be a layer for trapping negative charges during a programming operation and may be formed of a nitride layer. The blocking layer BX may be formed of an oxide layer (e.g., a silicon oxide layer).

[0061] The source line SL may be located on the stack structure STK and may contact upper surfaces of the first material layer 1MT, the capping pattern CAp, the channel junction CHj, the tunnel insulating layer TX, the charge trap layer CTL, and the blocking layer BX. The source line SL may be formed of a conductive material such as polysilicon.

[0062] A method of manufacturing a memory device according to a first embodiment of the present disclosure is described as follows.

[0063] FIG. 5A to FIG. 5M is a diagram illustrating a method of manufacturing a memory device according to a first embodiment of the present disclosure.

[0064] Reference Figure 5A , the first material layer 1MT and the second material layer 2MT may be alternately stacked on the sacrificial structure SFST. The sacrificial structure SFST may include a first substrate 1SUB and a sacrificial layer SF. The first substrate 1SUB may be a silicon substrate. The sacrificial layer SF may be silicon or polysilicon.

[0065] The first material layer 1MT may be an insulating material, and the second material layer 2MT may be a sacrificial material. The sacrificial material is a material that is removed in a subsequent process. For example, the first material layer 1MT may be an oxide layer, and the second material layer 2MT may be a nitride layer. The first material layer 1MT may be located at the lowermost and uppermost portions of the alternately stacked first material layers 1MT and second material layers 2MT.

[0066] Reference Figure 5B, the first opening 1OP may be formed in the first material layer 1MT, the second material layer 2MT and a portion of the sacrificial structure SFST. For example, an etching process for forming the first opening 1OP extending to a portion of the sacrificial structure SFST by passing through the first material layer 1MT and the second material layer 2MT may be performed. The etching process may be performed as an anisotropic dry etching process. The etching process may be performed until the sacrificial layer SF is exposed. Therefore, a portion of the first material layer 1MT and the second material layer 2MT and a portion of the sacrificial layer SF may be exposed through the side surface of the first opening 1OP, and a portion of the sacrificial layer SF may be exposed through the lower surface of the first opening 1OP.

[0067] Reference Figure 5C , the cell plug CP can be formed in Figure 5B In the first opening 1OP of the cell plug CP. For example, the blocking layer BX, the charge trapping layer CTL, the tunnel insulating layer TX, the channel layer CH and the first covering layer 1CA may be sequentially formed along the side surface and the lower surface of the first opening 1OP. The blocking layer BX may be formed of an oxide layer. The charge trapping layer CTL may be formed of a nitride layer. The tunnel insulating layer TX may be formed of an oxide layer. The channel layer CH may be formed of a polysilicon layer. After the channel layer CH is formed, the first covering layer 1CA may be formed on the entire structure in a state where the area surrounded by the channel layer CH is empty. In order to form a gap VD in the cell plug CP, the first covering layer 1CA may be formed of a material with low step coverage. For example, the first covering layer 1CA may be formed of an insulating material. For example, the first covering layer 1CA may be formed as an oxide layer. The first covering layer 1CA may be formed along the surface of the area surrounded by the channel layer CH. When the first cover layer 1CA is formed, before the region surrounded by the channel layer CH is completely filled with the first cover layer 1CA, the upper portion of the opening surrounded by the channel layer CH may be covered by the first cover layer 1CA. Therefore, a void VD as an empty space in the cell plug CP may be formed. For example, the first cover layer 1CA may be formed in the side, upper, and lower portions of the void VD.

[0068] Reference Figure 5D , an etching process for forming the second opening 2OP in the local area between the cell plugs CP may be performed. For example, the second opening 2OP may be an etching process for forming Figure 2The groove or hole of the slit SLT. The etching process for forming the second opening 2OP can be performed according to an anisotropic dry etching process method. The second opening 2OP can expose a portion of the sacrificial structure SFST by passing through the first cover layer 1CA and the first material layer 1MT and the second material layer 2MT. For example, the first cover layer 1CA, a portion of the first material layer 1MT and the second material layer 2MT, and a portion of the sacrificial layer SF can be exposed through the side surface of the second opening 2OP, and a portion of the sacrificial layer SF can be exposed through the lower surface of the second opening 2OP.

[0069] Reference Figure 5E , a process for removing the exposed portion through the second opening 2OP may be performed. Figure 5D The etching process of the second material layer 2MT is performed. For example, the etching process may be performed according to a wet etching method.

[0070] Reference Fig. 5F , the gate line GL may be formed between the first material layers 1MT. The gate line GL may be formed of a conductive material. The conductive material for the gate line GL may be formed through the second opening 2OP. The conductive material for the gate line GL may be a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), and nickel (Ni), or a semiconductor such as silicon (Si) or polycrystalline silicon (Poly-Si), but is not limited thereto. When forming the conductive material for the gate line GL, since the conductive material may extend in a vertical direction along the side surface of the second opening 2OP, an etching process for electrically blocking the gate line GL formed in different layers may be further performed. Through the etching process, the alternately stacked first material layers 1MT and the gate line GL may be exposed through the side surface of the second opening 2OP.

[0071] Reference Figure 5G , the slit SLT can be formed in Fig. 5F The slit SLT may be formed of an insulating material or a conductive material. When the slit SLT is formed of a conductive material, an insulating material that electrically blocks the conductive material and the gate line GL from each other may be further formed.

[0072] Reference Figure 5H, the first interlayer insulating layer 1ITL, the first contact plug 1CT and the bit line BL may be formed on the entire structure including the slit SLT. For example, the first contact plug 1CT may contact the upper portion of the cell plug CP respectively. The bit line BL may contact the upper portion of the first contact plug 1CT respectively. The bit line BL may be formed of a conductive material. The first contact plug 1CT may be formed of a conductive material to electrically connect the bit line BL and the channel layer CH of the cell plug CP. The first interlayer insulating layer 1ITL may be an insulating material filled between the first contact plug 1CT and the bit line BL. Therefore, the stacked structure STK may be formed on the sacrificial structure SFST. When the slit SLT is formed of a conductive material, a slit contact plug SCT for transmitting a voltage to the slit SLT may be further formed on the slit SLT.

[0073] Reference Fig.5I , can be formed including Figure 1 The peripheral structure PST of the peripheral circuit 180. The peripheral circuit may be formed on the second substrate 2SUB. For example, the peripheral circuit may include a transistor TR, a peripheral contact plug PCT, and a peripheral line PL. The transistor TR, the peripheral contact plug PCT, and the peripheral line PL may have various patterns according to the peripheral circuit. The second interlayer insulating layer 2ITL may be formed between the transistor TR, the peripheral contact plug PCT, and the peripheral line PL.

[0074] Then, refer to Figure 5H The sacrificial structure SFST and the stacked structure STK described are flipped, and the flipped stacked structure STK is brought into contact with the peripheral structure PST. For example, the stacked structure STK can be brought into contact with the peripheral structure PST using wafer bonding technology. Therefore, the stacked structure STK can be located on the peripheral structure PST, and the sacrificial structure SFST can be located on the stacked structure STK.

[0075] From the following drawings, in order to specifically describe the area 51 corresponding to the features of the present disclosure, an enlarged view of the corresponding area 51 is referred to.

[0076] Reference Figure 5J , a planarization process may be performed to expose the first material layer 1MT located at the uppermost end of the stacked structure STK. For example, the planarization process may be performed to remove Fig.5IThe sacrificial structure SFST and a portion of the cell plug CP protruding into the sacrificial structure SFST. A portion of the first cover layer 1CA may be exposed by a planarization process. Subsequently, an etching process for removing a portion of the exposed first cover layer 1CA may be performed. By the etching process for removing a portion of the first cover layer 1CA, the void VD may be exposed or may not be exposed. That is, because an etching process for removing a portion of the first cover layer 1CA is performed to lower the height of the first cover layer 1CA, the void VD may be exposed or may not be exposed depending on the size and position. In the first embodiment described below, a structure in which the void VD is exposed is described as an embodiment.

[0077] Reference Figure 5K , a second covering layer 2CA for covering the upper portion of the exposed void VD may be formed. The second covering layer 2CA may be formed of a material having low step coverage. For example, the second covering layer 2CA may be formed of an insulating material. For example, the second covering layer 2CA may be formed of an oxide layer. In the second covering layer 2CA, the second covering layer 2CA filled in the region 52 surrounded by the channel layer CH may become a second covering pattern 2CAp. Therefore, the lower surface of the second covering pattern 2CAp may contact the void VD and the first covering layer 1CA.

[0078] Reference Figure 5L , a method for maintaining the second capping pattern 2CAp formed in the cell plug and removing the second capping pattern 2CAp formed on the upper surface of the stacked structure may be performed. Figure 5K An etching process or a planarization process of the second capping layer 2CA may be performed. Subsequently, an ion implantation process IMPt for converting the upper local region 53 of the channel layer CH into a channel junction CHj may be performed. For example, the ion implantation process IMPt may be performed as an inclined ion implantation process in which the implantation angle of the impurity is inclined. For example, during the ion implantation process IMPt, the implantation angle of the impurity may be less than or greater than 90 degrees relative to the X or Y direction. For example, during the ion implantation process IMPt, the implantation angle of the impurity relative to the substrate may be set to be less than or greater than 90 degrees. As the impurity, an N-type impurity may be used, or a mixture of an N-type impurity and a P-type impurity may be used. When a mixture of an N-type impurity and a P-type impurity is used, a P-type impurity may be implanted after the N-type impurity is implanted, or an N-type impurity may be implanted after the P-type impurity is implanted. The N-type impurity may include phosphorus or arsenic, and the P-type impurity may include boron or boron difluoride (BF2).

[0079] Because the implantation angle of the impurities during the ion implantation process IMPt is inclined, the impurities can be uniformly implanted into the upper region of the channel layer CH. That is, in an embodiment, the over-implantation of impurities can be prevented or mitigated by the second capping pattern 2CAp. For example, when the second capping pattern 2CAp does not exist and only the void VD exists in the upper local region 53 surrounded by the channel layer CH, the impurities passing through the channel layer CH can be implanted into the channel layer CH on the opposite side through the void VD or into the lower region of the void VD. Therefore, in the present embodiment, the second capping pattern 2CAp can prevent or mitigate the over-implantation of impurities, and thus a channel junction CHj with a uniform concentration of impurities can be formed in the target region. Because a portion of the implanted impurities of the channel layer CH becomes amorphous, a heat treatment process for changing the amorphous portion into a crystalline portion can be performed after the ion implantation process IMPt. For example, a laser heat treatment process can be performed.

[0080] Reference Figure 5M The source line SL may be formed on the entire structure including the channel junction CHj and the second capping pattern 2CAp. The source line SL may be formed of a conductive material. For example, the source line SL may be formed of polysilicon.

[0081] Figure 6 is a diagram illustrating a memory device according to a second embodiment of the present disclosure.

[0082] Reference Figure 6 , the cell plug CP of the memory device according to the second embodiment may protrude in the source line SL direction more than the cell plug CP of the memory device according to the first embodiment. For example, a channel junction CHj and a portion of the second cover pattern 2CAp included in the cell plug CP may protrude in the source line SL direction. Since the remaining configuration except the channel junction CHj and the second cover pattern 2CAp is similar to that of the first embodiment, the description of the configuration overlapping with the configuration of the first embodiment is omitted.

[0083] In the memory device according to the second embodiment, the channel junction CHj may protrude from the stack structure STK in the direction of the source line SL, and the second covering pattern 2CAp may extend to the area surrounded by the protruding channel junction CHj. That is, the upper surface of the channel junction CHj and the upper surface of the second covering pattern 2CAp may be located on the same plane. When the channel junction CHj protrudes into the source line SL by passing through the stack structure STK, because the contact surface of the channel junction CHj and the source line SL increases, when the memory device is operated, the amount of current between the channel junction CHj and the source line SL may increase.

[0084] A method of manufacturing a memory device according to a second embodiment of the present disclosure is described as follows.

[0085] FIG. 7A to FIG. 7G is a diagram illustrating a method of manufacturing a memory device according to a second embodiment of the present disclosure.

[0086] In the method of manufacturing the memory device described in the first embodiment, referring to FIG. 5A to FIG. 5I The manufacturing method described overlaps with the method of manufacturing the memory device according to the second embodiment, and therefore in reference to Fig.5I The described steps are followed by a description of a method of manufacturing a memory device according to the second embodiment.

[0087] Reference Fig. 7A , in reference Fig.5I After the steps described, you can perform Fig.5I The first substrate 1SUB and Fig.5I The etching process of the sacrificial layer SF may be performed as a dry etching process or a wet etching process. The etching process may be performed so as to maintain a protrusion PRT of the cell plug protruding from the stacked structure in the Z direction. For example, the protrusion PRT may include a first cover layer 1CA, a channel layer CH surrounding the first cover layer 1CA, a tunnel insulating layer TX surrounding the channel layer CH, a charge trapping layer CTL surrounding the tunnel insulating layer TX, and a blocking layer BX surrounding the charge trapping layer CTL.

[0088] Reference Figure 7B , an ion implantation process IMPt for converting the upper local region 71 of the channel layer CH into a channel junction CHj may be performed. For example, the ion implantation process IMPt may be performed as an inclined ion implantation process in which the implantation angle of the impurity is inclined. For example, during the ion implantation process IMPt, the implantation angle of the impurity may be less than or greater than 90 degrees relative to the X or Y direction. As the impurity, an N-type impurity may be used, or a mixture of an N-type impurity and a P-type impurity may be used. When a mixture of an N-type impurity and a P-type impurity is used, a P-type impurity may be implanted after the N-type impurity is implanted, or an N-type impurity may be implanted after the P-type impurity is implanted. The N-type impurity may include phosphorus or arsenic, and the P-type impurity may include boron or BF2.

[0089] Because the implantation angle of the impurities during the ion implantation process IMPt is inclined, the impurities can be implanted into the channel layer CH according to the energy of the ion implantation process IMPt. At this time, in an embodiment, the excessive implantation of impurities can be prevented or mitigated by the tunnel insulating layer TX, the charge trap layer CTL, the blocking layer BX, and the first capping layer 1CA surrounding the channel layer CH. Therefore, in an embodiment, a channel junction CHj with a uniform concentration of impurities can be formed.

[0090] Reference Figure 7C, an etching process for removing the blocking layer BX, the charge trapping layer CTL, and the tunnel insulating layer TX of the protrusion PRT protruding to the upper portion of the stacked structure STK may be performed. The etching process may be performed as a dry etching process or a wet etching process. As the tunnel insulating layer TX, the charge trapping layer CTL, and the blocking layer BX surrounding the channel junction CHj are removed, the first capping layer 1CA surrounded by the channel junction CHj may be exposed.

[0091] Reference Fig.7D , an etching process for removing a portion of the first cover layer 1CA surrounded by the channel junction CHj may be performed. At this time, the channel junction CHj protruding toward the upper portion of the stacked structure STK may be maintained. By the etching process for removing a portion of the first cover layer 1CA, the void VD may be exposed or may not be exposed. That is, because the etching process for removing a portion of the first cover layer 1CA is performed to lower the height of the first cover layer 1CA, the void VD may be exposed or may not be exposed depending on the size and position. In the second embodiment described below, a structure in which the void VD is exposed is described as an embodiment.

[0092] Reference Fig. 7E , a second covering layer 2CA for covering the upper portion of the exposed void VD may be formed. The second covering layer 2CA may be formed of a material having low step coverage. For example, the second covering layer 2CA may be formed of an insulating material. For example, the second covering layer 2CA may be formed of an oxide layer. A portion of the second covering layer 2CA surrounded by the channel junction CHj may become a second covering pattern 2CAp. The lower surface of the second covering pattern 2CAp may contact the void VD and the first covering layer 1CA. Therefore, the second covering pattern 2CAp may be surrounded by the channel layer CH.

[0093] Reference Figure 7F , an etching process for removing the second cover layer 2CA surrounding the channel junction CHj and the outside of the stack structure STK may be performed. During the etching process, because the exposed area of ​​the second cover pattern 2CAp is smaller than the exposed area of ​​the second cover layer 2CA, even if the second cover pattern 2CAp is etched, the second cover pattern 2CAp may be etched more slowly than the second cover layer 2CA. Therefore, even if the second cover layer 2CA is removed, the second cover pattern 2CAp may remain in the area surrounded by the channel junction CHj.

[0094] Reference Figure 7G The source line SL may be formed on the entire structure including the channel junction CHj and the second capping pattern 2CAp. The source line SL may be formed of a conductive material. For example, the source line SL may be formed of polysilicon.

[0095] Figure 8is a diagram illustrating a memory device according to a third embodiment of the present disclosure.

[0096] Reference Figure 8 , the source line SL of the memory device according to the third embodiment may include a first source layer 1SL and a second source layer 2SL. For example, the first source layer 1SL may be formed along the protrusion PRT of the cell plug and the upper surface of the stacked structure STK, and the second source layer 2SL may be formed on the first source layer 1SL. Since the remaining configuration except the source line SL is similar to that of the second embodiment, the description of the configuration overlapping with the configuration of the second embodiment is omitted.

[0097] A method of manufacturing a memory device according to a third embodiment of the present disclosure is described as follows.

[0098] 9A to 9H is a diagram illustrating a method of manufacturing a memory device according to a third embodiment of the present disclosure.

[0099] Reference Fig.9A , in reference Fig.5I After the steps described, you can perform Fig.5I The first substrate 1SUB and Fig.5I The etching process of the sacrificial layer SF may be performed as a dry etching process or a wet etching process. The etching process may be performed so as to maintain a protrusion PRT of the cell plug protruding from the stacked structure in the Z direction. For example, the protrusion PRT may include a first cover layer 1CA, a channel layer CH surrounding the first cover layer 1CA, a tunnel insulating layer TX surrounding the channel layer CH, a charge trapping layer CTL surrounding the tunnel insulating layer TX, and a blocking layer BX surrounding the charge trapping layer CTL.

[0100] Reference Fig. 9B , an etching process for removing the blocking layer BX, the charge trapping layer CTL, and the tunnel insulating layer TX protruding toward the upper portion of the stacked structure STK may be performed. The etching process may be performed as a dry etching process or a wet etching process. As the tunnel insulating layer TX, the charge trapping layer CTL, and the blocking layer BX surrounding the channel layer CH are removed, the first capping layer 1CA surrounded by the channel layer CH may be exposed.

[0101] Reference Fig. 9C, an etching process for removing a portion of the first cover layer 1CA surrounded by the channel layer CH may be performed. At this time, the channel layer CH protruding toward the upper portion of the stacked structure STK may be maintained. Through the etching process for removing a portion of the first cover layer 1CA, the void VD may be exposed or may not be exposed. That is, because the etching process for removing a portion of the first cover layer 1CA is performed to lower the height of the first cover layer 1CA, the void VD may be exposed or may not be exposed depending on the size and position. In the third embodiment described below, a structure in which the void VD is exposed is described as an embodiment.

[0102] Reference Fig.9D , a second covering layer 2CA for covering the upper portion of the exposed void VD may be formed. The second covering layer 2CA may be formed of a material having low step coverage. For example, the second covering layer 2CA may be formed of an insulating material. For example, the second covering layer 2CA may be formed of an oxide layer. A portion of the second covering layer 2CA surrounded by the channel layer CH may become a second covering pattern 2CAp. The lower surface of the second covering pattern 2CAp may contact the void VD and the first covering layer 1CA. Therefore, the second covering pattern 2CAp may be surrounded by the channel layer CH.

[0103] Reference Fig.9E , a method for removing the outer portion around the channel layer CH and the stack structure STK may be performed. Fig.9D During the etching process, because the exposed area of ​​the second covering pattern 2CAp is smaller than the exposed area of ​​the second covering layer 2CA, even if the second covering pattern 2CAp is etched, the second covering pattern 2CAp may be etched more slowly than the second covering layer 2CA. Therefore, even if the second covering layer 2CA is removed, the second covering pattern 2CAp may remain in the region surrounded by the channel layer CH.

[0104] Reference Fig.9F , a first source layer 1SL may be formed along the channel layer CH and the second cover pattern 2CAp protruding from the stack structure STK and the surface of the stack structure STK. The first source layer 1SL may be formed of a conductive material. For example, the first source layer 1SL may be formed of polysilicon. When a main source line corresponding to the main source line is formed Figure 9H When the second source layer 2SL is formed, the first source layer 1SL may be used as a seed layer.

[0105] Reference Figure 9G, an ion implantation process IMPt for converting the upper local region 91 of the channel layer CH into a channel junction CHj may be performed. For example, the ion implantation process IMPt may be performed as an inclined ion implantation process in which the implantation angle of the impurity is inclined. For example, during the ion implantation process IMPt, the implantation angle of the impurity may be less than or greater than 90 degrees relative to the X or Y direction. As the impurity, an N-type impurity may be used, or a mixture of an N-type impurity and a P-type impurity may be used. When a mixture of an N-type impurity and a P-type impurity is used, a P-type impurity may be implanted after the N-type impurity is implanted, or an N-type impurity may be implanted after the P-type impurity is implanted. The N-type impurity may include phosphorus or arsenic, and the P-type impurity may include boron or BF2.

[0106] Because the injection angle of impurities during the ion implantation process IMPt is inclined, impurities can be implanted into the channel layer CH according to the energy of the ion implantation process IMPt. At this time, in an embodiment, excessive injection of impurities can be prevented or mitigated by the second capping pattern 2CAp. For example, when the second capping pattern 2CAp does not exist and only the void VD exists in the upper local area 91 surrounded by the channel layer CH, impurities passing through the channel layer CH can be injected into the channel layer CH on the opposite side through the void VD or injected into the lower area of ​​the void VD. Therefore, in the present embodiment, the second capping pattern 2CAp can prevent or mitigate excessive injection of impurities, and thus a channel junction CHj with a uniform concentration of impurities can be formed in the target area.

[0107] Reference Figure 9H , the second source layer 2SL may be formed on the first source layer 1SL. The second source layer 2SL may be formed of the same material as the first source layer 1SL. For example, the second source layer 2SL may be formed of polysilicon. When the second source layer 2SL is formed, since the first source layer 1SL may be used as a seed layer, the second source layer 2SL may be formed. When the second source layer 2SL is formed, a source line SL including the first source layer 1SL and the second source layer 2SL may be formed.

[0108] Fig.10 is a diagram illustrating a memory device according to a fourth embodiment of the present disclosure.

[0109] Reference Fig.10In the memory device according to the fourth embodiment, the protrusion PRT of the cell plug may include a tunnel insulating layer TX, a charge trapping layer CTL, and a blocking layer BX. For example, the tunnel insulating layer TX, the charge trapping layer CTL, and the blocking layer BX may be located on the side surface of the channel junction CHj protruding from the stack structure STK in the Z direction, and the upper surfaces of the second capping pattern 2CAp, the channel junction CHj, the tunnel insulating layer TX, the charge trapping layer CTL, and the blocking layer BX may contact the first source layer 1SL.

[0110] Since the remaining configuration except for the protrusion PRT is similar to that of the third embodiment, the description of the configuration overlapping with that of the third embodiment is omitted.

[0111] A method of manufacturing a memory device according to a fourth embodiment of the present disclosure is described as follows.

[0112] FIG. 11A to FIG. 11G is a diagram illustrating a method of manufacturing a memory device according to a fourth embodiment of the present disclosure.

[0113] Reference Fig.11A , in reference Fig.5I After the steps described, you can perform Fig.5I The first substrate 1SUB and Fig.5I The etching process of the sacrificial layer SF may be performed as a dry etching process or a wet etching process. The etching process may be performed so as to maintain a protrusion PRT of the cell plug protruding from the stacked structure in the Z direction. For example, the protrusion PRT may include a first cover layer 1CA, a channel layer CH surrounding the first cover layer 1CA, a tunnel insulating layer TX surrounding the channel layer CH, a charge trapping layer CTL surrounding the tunnel insulating layer TX, and a blocking layer BX surrounding the charge trapping layer CTL.

[0114] Reference Fig. 11B, the blocking layer BX, the charge trapping layer CTL, the tunnel insulating layer TX, and the channel layer CH formed on the protrusion PRT may be removed to expose a portion of the first cover layer 1CA, and an etching process for removing the exposed portion of the first cover layer 1CA may be performed. The etching process may be performed as a dry etching process or a wet etching process. During the etching process, the channel layer CH, the tunnel insulating layer TX, the charge trapping layer CTL, and the blocking layer BX located on the side of the protrusion PRT protruding to the upper portion of the stacked structure STK may be maintained. By the etching process for removing a portion of the first cover layer 1CA, the void VD may be exposed or may not be exposed. That is, because the etching process for removing a portion of the first cover layer 1CA is performed to reduce the height of the first cover layer 1CA, the void VD may be exposed or may not be exposed depending on the size and position. In the fourth embodiment described below, a structure in which the void VD is exposed is described as an embodiment.

[0115] Reference Fig. 11C , a second covering layer 2CA for covering the upper portion of the exposed void VD may be formed. The second covering layer 2CA may be formed of a material having low step coverage. For example, the second covering layer 2CA may be formed of an insulating material. For example, the second covering layer 2CA may be formed of an oxide layer. A portion of the second covering layer 2CA surrounded by the channel layer CH may become a second covering pattern 2CAp. The second covering pattern 2CAp may contact the void VD and the first covering layer 1CA. Therefore, the second covering pattern 2CAp may be surrounded by the channel layer CH.

[0116] Reference Fig.11D , an etching process for removing the second cover layer 2CA except the second cover pattern 2CAp surrounded by the channel layer CH may be performed. During the etching process, since the exposed area of ​​the second cover pattern 2CAp is smaller than the exposed area of ​​the second cover layer 2CA, even if the second cover pattern 2CAp is etched, the second cover pattern 2CAp may be etched slower than the second cover layer 2CA. Therefore, even if the second cover layer 2CA is removed, the second cover pattern 2CAp may remain in the area surrounded by the channel layer CH.

[0117] Reference Fig.11E , a first source layer 1SL may be formed along the surface of the protrusion PRT and the stacked structure STK. The first source layer 1SL may be formed of a conductive material. For example, the first source layer 1SL may be formed of polysilicon. When a main source line corresponding to the main source line is formed Fig.11G When the second source layer 2SL is formed, the first source layer 1SL may be used as a seed layer.

[0118] Reference Fig.11F, an ion implantation process IMPt for converting the upper local region 111 of the channel layer CH into a channel junction CHj may be performed. For example, the ion implantation process IMPt may be performed as an inclined ion implantation process in which the implantation angle of the impurity is inclined. For example, during the ion implantation process IMPt, the implantation angle of the impurity may be less than or greater than 90 degrees relative to the X or Y direction. As the impurity, an N-type impurity may be used, or a mixture of an N-type impurity and a P-type impurity may be used. When a mixture of an N-type impurity and a P-type impurity is used, a P-type impurity may be implanted after the N-type impurity is implanted, or an N-type impurity may be implanted after the P-type impurity is implanted. The N-type impurity may include phosphorus or arsenic, and the P-type impurity may include boron or BF2.

[0119] Because the implantation angle of impurities during the ion implantation process IMPt is inclined, impurities can be implanted into the channel layer CH according to the energy of the ion implantation process IMPt. At this time, in an embodiment, excessive implantation of impurities can be prevented or mitigated by the second capping pattern 2CAp. For example, when the second capping pattern 2CAp does not exist and only the void VD exists in the upper local area 111 surrounded by the channel layer CH, impurities passing through the channel layer CH can be implanted into the channel layer CH on the opposite side through the void VD or into the lower area of ​​the void VD. Therefore, in the present embodiment, the second capping pattern 2CAp can prevent or mitigate excessive implantation of impurities, and thus a channel junction CHj with a uniform concentration of impurities can be formed in the target area.

[0120] Reference Fig.11G , the second source layer 2SL may be formed on the first source layer 1SL. The second source layer 2SL may be formed of the same material as the first source layer 1SL. For example, the second source layer 2SL may be formed of polysilicon. When the second source layer 2SL is formed, since the first source layer 1SL may be used as a seed layer, the second source layer 2SL may be formed. When the second source layer 2SL is formed, a source line SL including the first source layer 1SL and the second source layer 2SL may be formed.

[0121] Fig.12 is a diagram illustrating a memory device according to a fifth embodiment of the present disclosure.

[0122] Reference Fig.12In the memory device according to the fifth embodiment, the protrusion PRT of the cell plug may include a first cover layer 1CA, a channel junction CHj, a tunnel insulating layer TX, a charge trap layer CTL, and a blocking layer BX. For example, the channel junction CHj, the tunnel insulating layer TX, the charge trap layer CTL, and the blocking layer BX may be sequentially located on a side surface of the first cover layer 1CA protruding from the stack structure STK in the Z direction, and the upper surfaces of the first cover layer 1CA, the channel junction CHj, the tunnel insulating layer TX, the charge trap layer CTL, and the blocking layer BX and the side surfaces of the blocking layer BX may contact the first source layer 1SL.

[0123] Since the remaining configuration except for the protrusion PRT is similar to that of the fourth embodiment, the description of the configuration overlapping with that of the fourth embodiment is omitted.

[0124] A method of manufacturing a memory device according to a fifth embodiment of the present disclosure is described as follows.

[0125] FIG. 13A to FIG. 13E is a diagram illustrating a method of manufacturing a memory device according to a fifth embodiment of the present disclosure.

[0126] Reference Fig.13A , in reference Fig.5I After the steps described, you can perform Fig.5I The first substrate 1SUB and Fig.5I The etching process of the sacrificial layer SF may be performed as a dry etching process or a wet etching process. The etching process may be performed so as to maintain a protrusion PRT of the cell plug protruding from the stacked structure in the Z direction. For example, the protrusion PRT may include a first cover layer 1CA, a channel layer CH surrounding the first cover layer 1CA, a tunnel insulating layer TX surrounding the channel layer CH, a charge trapping layer CTL surrounding the tunnel insulating layer TX, and a blocking layer BX surrounding the charge trapping layer CTL.

[0127] Reference Fig. 13B , an etching process for exposing a portion of the first cover layer 1CA by removing the blocking layer BX, the charge trapping layer CTL, the tunnel insulating layer TX, and the channel layer CH formed on the protrusion PRT may be performed. The etching process may be performed as a dry etching process or a wet etching process. During the etching process, the channel layer CH, the tunnel insulating layer TX, the charge trapping layer CTL, and the blocking layer BX located on the side of the protrusion PRT protruding to the upper portion of the stack structure STK may be maintained.

[0128] Reference Fig. 13C, a first source layer 1SL may be formed along the surface of the protrusion PRT and the stacked structure STK. The first source layer 1SL may be formed of a conductive material. For example, the first source layer 1SL may be formed of polysilicon. When a main source line corresponding to the main source line is formed Fig.13E When the second source layer 2SL is formed, the first source layer 1SL may be used as a seed layer.

[0129] Reference Fig.13D , an ion implantation process IMPt for converting the upper local region 113 of the channel layer CH into a channel junction CHj may be performed. For example, the ion implantation process IMPt may be performed as an inclined ion implantation process in which the implantation angle of the impurity is inclined. For example, during the ion implantation process IMPt, the implantation angle of the impurity may be less than or greater than 90 degrees relative to the X or Y direction. As the impurity, an N-type impurity may be used, or a mixture of an N-type impurity and a P-type impurity may be used. When a mixture of an N-type impurity and a P-type impurity is used, a P-type impurity may be implanted after the N-type impurity is implanted, or an N-type impurity may be implanted after the P-type impurity is implanted. The N-type impurity may include phosphorus or arsenic, and the P-type impurity may include boron or BF2.

[0130] Because the implantation angle of impurities during the ion implantation process IMPt is inclined, impurities can be implanted into the channel layer CH according to the energy of the ion implantation process IMPt. At this time, in an embodiment, excessive implantation of impurities can be prevented or mitigated by the first capping layer 1CA. For example, when the first capping layer 1CA does not exist and only the void VD exists in the upper local area 113 surrounded by the channel layer CH, impurities passing through the channel layer CH can be implanted into the channel layer CH on the opposite side through the void VD or into the lower area of ​​the void VD. Therefore, in the present embodiment, the first capping layer 1CA can prevent or mitigate excessive implantation of impurities, and thus a channel junction CHj with a uniform concentration of impurities can be formed in the target area.

[0131] Reference Fig.13E , the second source layer 2SL may be formed on the first source layer 1SL. The second source layer 2SL may be formed of the same material as the first source layer 1SL. For example, the second source layer 2SL may be formed of polysilicon. When the second source layer 2SL is formed, since the first source layer 1SL may be used as a seed layer, the second source layer 2SL may be formed. When the second source layer 2SL is formed, a source line SL including the first source layer 1SL and the second source layer 2SL may be formed.

[0132] Fig.14 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0133] Reference Fig.14, the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0134] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control a programming operation, a read operation, or an erase operation of the memory device 3200 or to control a background operation. The controller 3100 is configured to provide an interface between the memory device 3200 and a host. The controller 3100 is configured to drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0135] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 is configured to communicate with an external device through at least one of various communication standards such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0136] The memory device 3200 may include a plurality of memory cells and may be Figure 1 The illustrated memory devices 100 are configured identically.

[0137] The controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash card (CF), a Smart Memory Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, Micro MMC or eMMC), an SD card (SD, Mini SD, Micro SD or SDHC), and a Universal Flash Storage (UFS).

[0138] Fig.15 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0139] Reference Fig.15 , the SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0140] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. For example, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA, a parallel ATA, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0141] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured to Figure 1 The illustrated memory devices 100 are identical. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 through channels CH1 to CHn.

[0142] The auxiliary power supply 4230 is connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive a power supply voltage from the host 4100 and be charged with the power supply voltage. When the power supply from the host 4100 is not stable, the auxiliary power supply 4230 may provide the power supply voltage of the SSD 4200. For example, the auxiliary power supply 4230 may be located in the SSD 4200 or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and may provide auxiliary power to the SSD 4200.

[0143] The buffer memory 4240 operates as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0144] CROSS-REFERENCE TO RELATED APPLICATIONS

[0145] This application claims the priority of Korean Patent Application No. 10-2023-0135145 filed on October 11, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a channel layer passing through the gate lines, wherein the gate lines are stacked and spaced apart from each other; a channel junction extending from the channel layer; a cover layer, the cover layer being surrounded by the channel layer; a void surrounded by the cover layer; a capping pattern surrounded by the channel junction and contacting the gap and an upper portion of the capping layer; and A source line is located on the gate line and contacts the channel junction.

2. The memory device according to claim 1, wherein: The channel junction has an impurity concentration higher than an impurity concentration of the channel layer.

3. The memory device according to claim 1, wherein: The channel junction is formed by implanting N-type impurities into the channel layer.

4. The memory device according to claim 3, wherein: The N-type impurities include phosphorus or arsenic.

5. The memory device according to claim 1, wherein: The channel junction is formed by implanting N-type impurities and P-type impurities into the channel layer.

6. The memory device according to claim 5, in, The N-type impurities include phosphorus or arsenic, and Wherein, the P-type impurities include boron or BF2.

7. The memory device according to claim 1, wherein: The channel layer is polysilicon.

8. The memory device of claim 1, further comprising: a tunnel insulating layer, the tunnel insulating layer surrounding a side surface of the channel layer; a charge trapping layer, the charge trapping layer surrounding a side surface of the tunnel insulating layer; as well as A blocking layer surrounds a side surface of the charge trapping layer.

9. The memory device according to claim 8, wherein: Upper surfaces of the tunnel insulating layer, the charge trap layer, and the blocking layer are located on substantially the same plane as upper surfaces of the channel junction and the capping pattern.

10. The memory device according to claim 9, wherein: The source line comprises: a first source layer contacting the channel junction and an upper surface of the capping pattern; and A second source layer, wherein the second source layer is located on the first source layer.

11. The memory device according to claim 8, wherein: The channel junction protrudes from the tunnel insulating layer, the charge trapping layer, and the blocking layer into the source line.

12. The memory device according to claim 11, wherein: The source line comprises: a first source layer contacting side surfaces and upper surfaces of the protruding channel junction and contacting an upper surface of the capping pattern; and A second source layer, wherein the second source layer is located on the first source layer.

13. The memory device according to claim 1, wherein: The cover pattern and the cover layer are insulating materials.

14. A memory device, the memory device comprising: A stacked structure comprising insulating layers and gate lines stacked alternately; a cell plug included in the stacked structure and passing through the insulating layer and the gate line; A channel layer including a cell plug, a void surrounded by the channel layer, a tunnel insulating layer surrounding the channel layer, a charge trapping layer surrounding the tunnel insulating layer, and a blocking layer surrounding the charge trapping layer; a channel junction included in the cell plug and extending from the channel layer; a capping pattern included in the cell plug and surrounded by at least a portion of the channel layer and the channel junction; as well as A source line is located on the stack structure and contacts the channel junction and the capping pattern.

15. The memory device of claim 14, further comprising: A cover layer is located between the channel layer and the void and surrounds the void.

16. The memory device of claim 14, wherein: Upper surfaces of the tunnel insulating layer, the charge trap layer, the blocking layer, the channel junction, and the capping pattern are substantially flat with an upper surface of the stack structure.

17. The memory device according to claim 14, in, The tunnel insulating layer, the charge trapping layer and the blocking layer are flat with the upper surface of the stacked structure, and The channel junction and the capping pattern protrude from the stacked structure in an upper direction.

18. The memory device of claim 17, wherein: The source line contacts a side surface of the protruding channel junction.

19. The memory device of claim 17, wherein: The source line comprises: a first source layer contacting upper surfaces of the stacked structure, the tunnel insulating layer, the charge trapping layer, and the blocking layer, a side surface of the channel junction, and upper surfaces of the channel junction and the capping pattern; and A second source layer, wherein the second source layer is located on the first source layer.

20. The memory device of claim 14, wherein: The tunnel insulating layer, the charge trap layer, the blocking layer, the channel junction, and the capping pattern protrude from the stack structure in an upper direction.

21. The memory device of claim 20, wherein: The source line comprises: a first source layer contacting an upper surface of the stacked structure, a side surface of the blocking layer, and upper surfaces of the tunnel insulating layer, the charge trapping layer, the blocking layer, the channel junction, and the capping pattern; and A second source layer, wherein the second source layer is located on the first source layer.

22. A method of manufacturing a memory device, the method comprising the steps of: forming a stacked structure including a cell plug, the cell plug including: a blocking layer passing through alternately stacked first material layers and gate lines, a charge trapping layer surrounded by the blocking layer, a tunnel insulating layer surrounded by the charge trapping layer, a channel layer surrounded by the tunnel insulating layer, a capping layer surrounded by the channel layer, and a gap surrounded by the capping layer; forming a covering pattern filling at least a portion of an upper portion of the gap; performing an ion implantation process for converting a portion of the channel layer surrounding the capping pattern into a channel junction having an impurity concentration higher than that of the channel layer; and A source line is formed on the stacked structure to contact the channel junction.

23. The method according to claim 22, wherein: The step of forming the stacked structure comprises the following steps: Alternatingly stacking the first material layer and the second material layer on the sacrificial structure; forming a first opening passing through the first material layer and the second material layer and exposing a portion of the sacrificial structure; forming the blocking layer, the charge trapping layer, the tunnel insulating layer and the channel layer along the inner surface of the first opening; forming the capping layer and the gap in the channel layer; forming a second opening through the first material layer and the second material layer; removing the second material layer exposed through the second opening; forming the gate line in the region where the second material layer is removed; forming a slit in the second opening; flipping the entire structure so that the sacrificial structure is located at the upper part; and The sacrificial structure is removed.

24. The method according to claim 23, wherein: In the step of forming the capping layer and the void, the capping layer is formed of an oxide layer having low step coverage, so that the void is formed inside the channel layer.

25. The method according to claim 22, wherein: The covering pattern and the covering layer are formed of substantially the same material.

26. The method according to claim 25, wherein: The capping pattern is formed of an oxide layer having low step coverage so as to fill at least a portion of the interior of the gap.

27. The method of claim 22, wherein: During the ion implantation process, an implantation angle of the impurities with respect to the substrate is set to be smaller than or greater than approximately 90 degrees.

28. The method according to claim 27, wherein: The impurity is an N-type impurity or an impurity obtained by mixing the N-type impurity and a P-type impurity. The method according to claim 28 , wherein the N-type impurities include phosphorus or arsenic.

30. The method of claim 28, wherein: The P-type impurities include boron or boron difluoride BF2.

31. The method of claim 22, wherein: The step of forming the source line comprises the following steps: forming a first source layer on the stacked structure in contact with the channel junction; and A second source layer is formed on the first source layer.

32. The method according to claim 22, further comprising the steps of: Before forming the capping pattern, a planarization process is performed for planarizing an upper portion of the stack structure and exposing the capping layer.

33. The method according to claim 22, further comprising the steps of: forming a protrusion in which a portion of the unit plug protrudes in an upper direction of the stacked structure; as well as Before forming the capping pattern, the capping layer is exposed by removing the blocking layer, the charge trap layer, and the tunnel insulating layer formed on the upper and side surfaces of the protrusion and removing the channel layer formed on the upper surface of the protrusion.

34. The method according to claim 22, further comprising the steps of: forming a protrusion in which a portion of the unit plug protrudes in an upper direction of the stacked structure; as well as Before forming the capping pattern, the gap is exposed by removing a portion of the blocking layer, the charge trap layer, the tunnel insulating layer, the channel layer, and the capping layer formed on the upper surface of the protrusion.

35. A method of manufacturing a memory device, the method comprising the steps of: forming a stacked structure including a cell plug, the cell plug including: a blocking layer extending to a portion of a sacrificial structure located at an uppermost end by passing through alternately stacked first material layers and gate lines, a charge trapping layer surrounded by the blocking layer, a tunnel insulating layer surrounded by the charge trapping layer, a channel layer surrounded by the tunnel insulating layer, a capping layer surrounded by the channel layer, and a void surrounded by the capping layer; exposing a protrusion of the cell plug protruding on the stacked structure by removing the sacrificial structure; performing an ion implantation process for converting a portion of the channel layer included in the protrusion into a channel junction having an impurity concentration higher than that of the channel layer; exposing the void by removing a portion of the blocking layer, the charge trap layer, the tunnel insulating layer, and the channel junction included in the protrusion; forming a covering pattern filling a portion of an upper portion of the gap; and A source line is formed on the stacked structure to contact the channel junction.

36. The method of claim 35, wherein: The step of forming the source line comprises the following steps: forming a first source layer on the stacked structure in contact with the channel junction; and A second source layer is formed on the first source layer.

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