Memory gate planarization method and semiconductor structure
By using two etching methods to planarize the floating gate layer in the memory, the uniformity and control problems of floating gate planarization processing in the prior art are solved, and the planarization and height uniformity of the gate layer are achieved, and the problems of bridge and depression are avoided.
Patent Information
- Application Number
- CN202510013779.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-11
AI Technical Summary
In the prior art, floating gate planarization treatment has problems such as poor process uniformity, difficulty in controlling, easy to cause large surface depression and height differences in the gate layer, and the polysilicon gate remains at STI, resulting in semiconductor devices failure.
The memory gate surface is planarized by two etching methods, and the gate layer on one side of the isolation structure is removed by photolithography and etching, and the bottom anti-reflection layer is coated and etched thereon, ensuring planarization and high uniformity of the gate layer.
The bridge between gates is effectively avoided, the uniformity of memory gate height is ensured, the problem of large height differences is solved, the surface of the gate layer is depressed, and a gate with a flat surface and a size meets the requirements is obtained.
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Figure CN119815833A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a memory gate planarization method and a semiconductor structure. Background Art
[0002] Nor Flash has a more complex process than logic devices. As the feature size continues to shrink, the process difficulty continues to increase, and process stability has become a big problem. Among them, the floating gate planarization process is extremely challenging, requiring the floating gate thickness to hit the target value, and at the same time requiring it to have no polysilicon residue on the STI (shallow trench isolation). In the prior art, the planarization of the polysilicon floating gate is generally achieved through a two-step CMP (Chemical-Mechanical Polishing) process. However, the uniformity of the traditional CMP process is poor, and its process is relatively difficult to control. On the one hand, the CMP process will cause the polysilicon floating gate to form a surface depression, affecting the shape of the floating gate. Secondly, the CMP process will cause the floating gate thickness from the center to the edge of the wafer to have a large height difference, and it is impossible to ensure that the polysilicon floating gate feature size hits the target value comprehensively. On the other hand, the CMP process has the risk of residual polysilicon gates on the STI, causing bridges between polysilicon gates, resulting in failure of semiconductor devices.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0004] In response to the problems in the prior art, the purpose of the present application is to provide a memory gate flattening method and a semiconductor structure, which uses two etchings to flatten the surface of the memory gate, avoid bridging between gates, and effectively control the uniformity of the memory gate height, thereby solving the problem of large differences in memory gate height.
[0005] The present application provides a memory gate planarization method, comprising:
[0006] Providing a substrate, the substrate comprising a substrate, an isolation structure and a gate layer;
[0007] Removing the gate layer on one side of the isolation structure by photolithography and etching;
[0008] Applying a bottom anti-reflection layer for planarization;
[0009] The bottom anti-reflection layer and the gate layer are etched to remove the bottom anti-reflection layer and planarize the surface of the gate layer.
[0010] In some embodiments, removing the gate layer on one side of the isolation structure by photolithography and etching comprises the following steps:
[0011] coating a photoresist on one side of the substrate;
[0012] Removing the photoresist at the corresponding position of the isolation structure by a photolithography process;
[0013] The gate layer on one side of the isolation structure is removed by dry etching.
[0014] In some embodiments, the step of removing the gate layer on one side of the isolation structure by dry etching comprises the following steps:
[0015] An over-etching method is used to remove the gate layer on one side of the isolation structure.
[0016] In some embodiments, when removing the gate layer on one side of the isolation structure, the over-etching amount is 10% to 20% of the gate layer.
[0017] In some embodiments, the step of coating a bottom anti-reflection layer for planarization comprises the following steps:
[0018] A bottom anti-reflection layer is coated on one side of the gate layer and the isolation structure by spin coating, and the upper surface of the bottom anti-reflection layer is a flat surface.
[0019] In some embodiments, etching the bottom anti-reflection layer and the gate layer to remove the bottom anti-reflection layer and planarize the surface of the gate layer comprises the following steps:
[0020] The bottom anti-reflection layer and the gate layer are etched by a dry etching method to remove the bottom anti-reflection layer and planarize the surface of the gate layer.
[0021] In some embodiments, when etching the bottom anti-reflection layer and the gate layer, an online film thickness detection system is used to detect the thickness of the gate layer, and etching is stopped when the thickness of the gate layer reaches a preset thickness.
[0022] In some embodiments, the memory is flash memory.
[0023] In some embodiments, the gate layer is a polysilicon floating gate layer.
[0024] An embodiment of the present application also provides a semiconductor structure obtained by using the memory gate planarization method.
[0025] The memory gate planarization method and semiconductor structure provided in the present application have the following advantages:
[0026] By adopting the present application, it is not necessary to use the CMP process to achieve the flattening of the gate layer, thereby avoiding the problems of poor process uniformity, relatively difficult process control, and easy bridging between gate layers in the CMP process. The present application uses two etchings to flatten the surface of the memory gate, which can completely eliminate the gate layer on one side of the isolation structure, effectively avoid bridging between gates, and effectively control the uniformity of the height of the memory gate, solve the problem of large differences in the height of the memory gate, avoid the formation of surface depressions in the gate layer, and more easily obtain a gate with a flat surface and a size that meets the requirements.
[0027] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0029] Figure 1 is a flow chart of a memory gate planarization method according to an embodiment of the present application;
[0030] Figure 2 is a schematic diagram of providing a substrate according to an embodiment of the present application;
[0031] Figure 3 is a schematic diagram of a substrate after photolithography according to an embodiment of the present application;
[0032] Figure 4 is a schematic diagram of etching and removing a gate layer on one side of an isolation structure according to an embodiment of the present application;
[0033] Figure 5 is a schematic diagram of an embodiment of the present application after coating a bottom anti-reflection layer;
[0034] Figure 6 It is a schematic diagram of an embodiment of the present application after etching away the bottom anti-reflection layer and planarizing the gate layer. DETAILED DESCRIPTION
[0035] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.
[0036] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.
[0037] In the prior art, the planarization of the polysilicon floating gate is generally achieved through a two-step CMP process. However, the conventional CMP process has poor uniformity and is relatively difficult to control, which causes the polysilicon floating gate to form a surface depression, affecting the shape of the floating gate. In addition, the CMP process causes a large height difference in the thickness of the floating gate from the center to the edge of the wafer, and it is impossible to ensure that the characteristic size of the polysilicon floating gate hits the target value in all aspects. In addition, the CMP process has the risk of residual polysilicon gate on the STI, causing bridges between polysilicon gates, resulting in failure of the semiconductor device. Based on this, the present application aims to provide a memory gate planarization method, which uses two etchings to planarize the surface of the memory gate, avoids bridging between gates, and effectively controls the uniformity of the memory gate height to solve the problem of large differences in memory gate height.
[0038] like Figure 1 As shown, an embodiment of the present application provides a memory gate planarization method, comprising:
[0039] S100: providing a substrate, wherein the substrate comprises a substrate, an isolation structure and a gate layer;
[0040] In this embodiment, the substrate is, for example, a substrate with a line width of 55 nanometers, the substrate is, for example, a silicon substrate, and the isolation structure is, for example, an oxide STI (Shallow Trench Isolation) structure, which is a technology for isolating adjacent semiconductor units, and is formed by etching shallow trenches in a silicon substrate and then filling these trenches with insulating materials (such as silicon dioxide) to achieve electrical isolation between units; silicon dioxide is a high-quality insulator, and the oxide isolation layer formed by STI can effectively prevent leakage between adjacent devices. This isolation effect is crucial to ensuring the normal operation and high performance of integrated circuits, especially in high-frequency and high-integration circuit applications; the size of the substrate here is only an example, and can be set and adjusted according to the product requirements of the memory, all of which belong to the protection scope of this application;
[0041] In this embodiment, a gate oxide layer is further provided between the substrate and the gate layer; the gate oxide layer is a very thin dielectric layer that separates the gate from the semiconductor substrate to prevent direct conductive contact between the gate and the channel; the specific thickness of the gate oxide can be set according to the needs of the memory product to achieve the purpose of isolating the gate from the semiconductor substrate;
[0042] In the substrate provided in step S100, the gate layer on the isolation structure side is often higher than the gate layer on the active region side, so the surface of the gate layer is uneven and needs to be flattened in subsequent steps;
[0043] S200: removing the gate layer on one side of the isolation structure by photolithography and etching;
[0044] In this embodiment, the gate layer is, for example, a polysilicon floating gate layer; the polysilicon floating gate layer is a structure that plays a key role in non-volatile memory, which is mainly composed of polysilicon material, is a conductive layer surrounded by an insulating layer, is located between the source and the drain, and is opposite to the control gate. From a structural point of view, its suspended characteristic enables it to store charge, which is the basis for realizing data storage;
[0045] Photolithography is a micro-nano processing technology that transfers the pattern on the mask to the substrate surface. After removing the photoresist on one side of the isolation structure through photolithography, etching is performed to remove the gate layer on one side of the isolation structure, while the gate layer corresponding to the non-isolation structure position is protected by the photoresist during etching. After the etching is completed, the residual photoresist is removed;
[0046] S300: coating a bottom anti-reflection layer for planarization;
[0047] Bottom Anti-Reflective Coating (BARC) is a material coating used in the photolithography process. BARC material has specific optical absorption properties. When reflected light enters the bottom anti-reflective layer, it can absorb light within a certain wavelength range and convert the energy of light into other forms such as heat energy.
[0048] Here, the thickness of the bottom anti-reflection layer is set according to the shape and size of the current gate layer, so as to be able to substantially cover the lower gate layer and provide protection for the lower gate layer during subsequent etching;
[0049] S400: Etching the bottom anti-reflection layer and the gate layer, removing the bottom anti-reflection layer and flattening the surface of the gate layer. During the etching process, the high gate layer will be continuously etched, while the short gate layer will be protected by the bottom anti-reflection layer. As the bottom anti-reflection layer is etched, the uneven upper surface of the gate layer will eventually be etched into a plane, thereby flattening the gate layer. The thickness of the final gate layer needs to meet the product requirements of the memory. When the thickness of the gate reaches the target range during the etching process, the etching is stopped.
[0050] By adopting the present application, it is not necessary to use the CMP process to achieve the flattening of the gate layer, thereby avoiding the problems of poor process uniformity, relatively difficult process control, and easy bridging between gate layers in the CMP process. The present application uses two etchings to flatten the surface of the memory gate, which can completely eliminate the gate layer on one side of the isolation structure, effectively avoid bridging between gates, and effectively control the uniformity of the memory gate height, solve the problem of large differences in the height of the memory gate, avoid the formation of surface depressions in the gate layer, and more easily obtain a gate with a flat surface and a size that meets the requirements. The uniformity of the polysilicon gate height can also be maintained for the wafer in wafer process.
[0051] In this embodiment, the memory is a flash memory Nor Flash. Flash memory is a non-volatile semiconductor memory that can save data even after power failure. The storage unit of NOR Flash is connected in parallel to the data bus, which can achieve random reading and faster reading speed.
[0052] In this embodiment, the step S200: removing the gate layer on one side of the isolation structure by photolithography and etching includes the following steps:
[0053] A photoresist is coated on one side of the substrate; the photoresist is a light-sensitive organic polymer material that reacts under radiation. When light is irradiated on the photoresist, the chemical structure of the polymer changes, causing a difference in the solubility of the illuminated part and the unilluminated part in the developer, thereby achieving pattern transfer;
[0054] Removing the photoresist at the corresponding position of the isolation structure by a photolithography process;
[0055] Specifically, the substrate and the mask are precisely aligned to ensure that the pattern on the mask can be accurately transferred to the specified position of the substrate. After alignment, a light source of a specific wavelength is used to irradiate the photoresist through the mask. Depending on the type of photoresist and the exposure dose, the chemical structure of the photoresist will change accordingly. The exposed substrate is immersed in a developer for a certain period of time, or developed using a spray-type developing device. The developer will dissolve the positions in the photoresist corresponding to the isolation structure after exposure, while retaining the positions in the photoresist that do not correspond to the isolation structure;
[0056] The gate layer on one side of the isolation structure is removed by dry etching. Dry etching is an etching technique that uses gaseous chemicals and plasma to remove atoms on the surface of the substrate material during semiconductor processing. During the dry etching process, the gate layer on one side of the isolation structure is etched away, while the gate layer on the non-isolation structure side is protected by the photoresist and is not etched. After the etching is completed, the residual photoresist is removed.
[0057] In this embodiment, removing the gate layer on one side of the isolation structure by dry etching comprises the following steps:
[0058] The gate layer on one side of the isolation structure is removed by an over-etching method. Optionally, when removing the gate layer on one side of the isolation structure, the over-etching amount is 10% to 20% of the gate layer. By adopting the over-etching method, it can be further ensured that the gate layer on one side of the isolation structure is completely removed, avoiding the gate layer remaining on the isolation structure side and causing bridging abnormalities.
[0059] In this embodiment, the step S300: coating a bottom anti-reflection layer for planarization processing includes the following steps:
[0060] A bottom anti-reflection layer is coated on one side of the gate layer and the isolation structure by spin coating, and the upper surface of the bottom anti-reflection layer is a flat surface. Spin coating is a technology for preparing a uniform thin film on a flat substrate. Its basic principle is to use the centrifugal force generated by rotation to spread the solution evenly on the surface of the substrate. When the solution is dropped on the center of the substrate, the substrate starts to rotate at high speed. Under the action of centrifugal force, the solution flows to the edge of the substrate and gradually becomes thinner, eventually forming a uniform thin film.
[0061] In this embodiment, the step S400: etching the bottom anti-reflection layer and the gate layer to remove the bottom anti-reflection layer and planarize the surface of the gate layer, comprises the following steps:
[0062] The bottom anti-reflection layer and the gate layer are etched by a dry etching method to remove the bottom anti-reflection layer and planarize the surface of the gate layer.
[0063] In this embodiment, when etching the bottom anti-reflection layer and the gate layer, an online film thickness detection system is used to detect the thickness of the gate layer, and etching is stopped when the thickness of the gate layer reaches a preset thickness. An online film thickness detection system is a device that can measure and monitor the thickness of a thin film in real time and continuously during the preparation of a material thin film. Therefore, in this embodiment, by using an online film thickness measurement system to monitor the thickness of the gate layer in real time, the uniformity of the height of the memory gate is further effectively controlled to solve the problem of large differences in the height of the memory gate.
[0064] Combine the following Figures 2 to 6 The specific implementation process of the memory gate flattening method in a specific example is introduced. It is understandable that the structure shown in the drawings and the following description are only examples and are not intended to limit the scope of protection of the present application. The shapes and sizes of the various film layers shown in the drawings are only examples and are not intended to limit the scope of protection of the present application. In different embodiments, the shapes and sizes of each film layer can be adaptively selected and adjusted according to the structural requirements and process requirements of the semiconductor device, and all fall within the scope of protection of the present application. The following description takes the memory as a flash memory and the gate as a polysilicon floating gate as an example, but the present application is not limited to this.
[0065] Figure 2 1 is a schematic diagram of providing a substrate according to an embodiment of the present application. Corresponding to step S100, a substrate is provided, the substrate comprising a silicon substrate 100, an isolation structure 200, a gate oxide layer 300 and a gate layer 400; optionally, the substrate is, for example, a substrate with a line width of 55 nanometers, the isolation structure 200 is an oxide shallow trench isolation structure, and the gate layer 400 is, for example, a polysilicon floating gate layer. Figure 2As shown, the height of the gate layer 400 corresponding to the isolation structure 200 is higher than the height of the gate layer 400 corresponding to the active area. The gate layer 400 needs to be flattened through subsequent steps, and the gate above the isolation structure 200 is completely removed to avoid bridging.
[0066] Figure 3 FIG. 1 is a schematic diagram of a substrate after photolithography according to an embodiment of the present application. Figure 4 Schematic diagram of etching and removing the gate layer on one side of the isolation structure according to an embodiment of the present application. Corresponding to step S200, the gate layer 400 on one side of the isolation structure 200 is removed by photolithography and etching. This step specifically includes: coating a photoresist 500 on one side of the substrate; removing the photoresist at the corresponding position of the isolation structure 200 by photolithography, and obtaining Figure 3 Then, the gate layer on one side of the isolation structure 200 is removed by dry etching to obtain the structure shown in FIG. Figure 4 The structure shown in FIG. 2 is a structure of a semiconductor device, and a semiconductor device 210 is used to form a semiconductor device 210. ...
[0067] Figure 5 1 is a schematic diagram of an embodiment of the present application after coating a bottom anti-reflection layer. Corresponding to step S300, a bottom anti-reflection layer 600 is coated for planarization, the purpose of which is to subsequently etch a flat surface. In this embodiment, the bottom anti-reflection layer 600 is coated on one side of the gate layer 400 and the isolation structure 200 by spin coating, and the upper surface of the bottom anti-reflection layer 600 is a flat surface.
[0068] Figure 6 Schematic diagram of etching and removing the bottom anti-reflection layer and flattening the gate layer in one embodiment of the present application. Corresponding to step S400, the bottom anti-reflection layer 600 and the gate layer 400 are etched to remove the bottom anti-reflection layer 600 and flatten the surface of the gate layer. Figure 6The flattened gate layer is marked as 400'. In this embodiment, the bottom anti-reflection layer 600 and the gate layer are etched by a dry etching method. In addition, when etching the bottom anti-reflection layer 600 and the gate layer, an online film thickness detection system is used to detect the thickness of the gate layer, and the etching is stopped when the thickness of the gate layer reaches a preset thickness. During the etching process, the tall polysilicon gate will be continuously etched, and the short polysilicon gate will be protected. As the bottom anti-reflection layer 600 is etched, the uneven upper surface of the polysilicon gate will eventually be etched into a plane. The etching process can also be controlled by time.
[0069] The present application also provides a semiconductor structure obtained by using the memory gate planarization method. The example structure of the semiconductor structure is as follows: Figure 6 As shown, it includes a substrate 100, an isolation structure 200, a gate oxide layer 300 and a flattened gate layer 400'. The semiconductor structure is obtained by the memory gate flattening method, and there is no need to use a CMP process to achieve flattening of the gate layer, thereby avoiding the problems of poor process uniformity, relatively difficult process control, and easy bridging between gate layers in the CMP process. The present application uses two etchings to flatten the surface of the memory gate, which can completely eliminate the gate layer on one side of the isolation structure, effectively avoid bridging between gates, and effectively control the uniformity of the memory gate height, solve the problem of large differences in the height of the memory gate, avoid the gate layer from forming surface depressions, and more easily obtain a gate with a flat surface and a size that meets the requirements. Therefore, the semiconductor structure obtained by using the memory gate flattening method and the semiconductor device having the semiconductor structure have better product performance.
[0070] In summary, the memory gate planarization method and semiconductor structure provided by the present application have the following advantages:
[0071] By adopting the present application, it is not necessary to use the CMP process to achieve the flattening of the gate layer, thereby avoiding the problems of poor process uniformity, relatively difficult process control, and easy bridging between gate layers in the CMP process. The present application uses two etchings to flatten the surface of the memory gate, which can completely eliminate the gate layer on one side of the isolation structure, effectively avoid bridging between gates, and effectively control the uniformity of the height of the memory gate, solve the problem of large differences in the height of the memory gate, avoid the formation of surface depressions in the gate layer, and more easily obtain a gate with a flat surface and a size that meets the requirements.
[0072] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.
Claims
1. A memory gate planarization method, characterized in that: include: Providing a substrate, the substrate comprising a substrate, an isolation structure and a gate layer; Removing the gate layer on one side of the isolation structure by photolithography and etching; Applying a bottom anti-reflection layer for planarization; The bottom anti-reflection layer and the gate layer are etched to remove the bottom anti-reflection layer and planarize the surface of the gate layer.
2. The memory gate planarization method according to claim 1, characterized in that: The method of removing the gate layer on one side of the isolation structure by photolithography and etching comprises the following steps: coating a photoresist on one side of the substrate; Removing the photoresist at the corresponding position of the isolation structure by a photolithography process; The gate layer on one side of the isolation structure is removed by dry etching.
3. The memory gate planarization method according to claim 2, characterized in that: The step of removing the gate layer on one side of the isolation structure by dry etching comprises the following steps: An over-etching method is used to remove the gate layer on one side of the isolation structure.
4. The memory gate planarization method according to claim 3, characterized in that: When removing the gate layer on one side of the isolation structure, the over-etching amount is 10% to 20% of the gate layer.
5. The memory gate planarization method according to claim 1, characterized in that: The process of coating a bottom anti-reflection layer for planarization comprises the following steps: A bottom anti-reflection layer is coated on one side of the gate layer and the isolation structure by spin coating, and the upper surface of the bottom anti-reflection layer is a flat surface.
6. The memory gate planarization method according to claim 1, characterized in that: Etching the bottom anti-reflection layer and the gate layer to remove the bottom anti-reflection layer and planarize the surface of the gate layer comprises the following steps: The bottom anti-reflection layer and the gate layer are etched by a dry etching method to remove the bottom anti-reflection layer and planarize the surface of the gate layer.
7. The memory gate planarization method according to claim 1, characterized in that: When etching the bottom anti-reflection layer and the gate layer, an online film thickness detection system is used to detect the thickness of the gate layer, and etching is stopped when the thickness of the gate layer reaches a preset thickness.
8. The memory gate planarization method according to claim 1, characterized in that: The memory is a flash memory.
9. The memory gate planarization method according to claim 1, characterized in that: The gate layer is a polysilicon floating gate layer.
10. A semiconductor structure, characterized in that: Obtained by using the memory gate flattening method according to any one of claims 1 to 9.