Reverse conducting IGBT (Insulated Gate Bipolar Translator) device and preparation method thereof

Abstract

The invention provides a reverse conducting IGBT (Insulated Gate Bipolar Translator) device and a preparation method thereof, the reverse conducting IGBT device comprises a substrate, a trench structure, a base region, a first contact region, a second contact region, an emitter region, an interlayer dielectric layer, a collector region, an emitter, a grid and a collector, the trench structure comprises a first trench, a second trench, a grid dielectric layer, a first conducting layer and a second conducting layer, the plurality of first and second grooves are arranged at intervals along the X direction, and the first and second conductive layers are respectively filled in the first and second grooves; the base region is positioned on the upper surface layer of the substrate; the first contact region is located on the upper surface layer of the base region and is adjacent to the side wall of the second groove; the emitter region is located on the upper surface of the base region; the interlayer dielectric layer covers the substrate and the upper surface of the groove structure; the collector region and the second contact region are positioned on the lower surface layer of the substrate; the emitter fills the contact hole, and the gate and the collector are electrically connected with the corresponding areas respectively. By optimizing the distribution of the IGBT functional area and the FRD functional area, the latch-up effect of the device and the current characteristic of the diode are improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a reverse conducting IGBT device and a preparation method thereof. Background Art

[0002] The insulated gate bipolar transistor (IGBT) combines the voltage control of the metal-oxide semiconductor field-effect transistor (MOS) and the conductivity modulation current characteristics of the bipolar junction transistor (BJT). It has the characteristics of high input impedance, low switching loss, fast speed, and low voltage drive power. It is widely used in many fields such as power transmission and transformation, high-speed train traction, industrial drive, and clean energy.

[0003] IGBT does not have reverse conduction capability and usually needs to be packaged with a fast recovery diode (FRD) so that the FRD can play a freewheeling role when the IGBT is turned off. Since the IGBT and FRD are packaged together, the IGBT and FRD chips need to be packaged in a double chip format. The packaging structure has a large area, and there is a temperature difference between the IGBT and FRD wafers, which can easily make the device unstable during application.

[0004] The reverse-conducting insulated gate bipolar transistor (RC-IGBT) can significantly reduce the chip area and save manufacturing costs by integrating the IGBT function and the FRD function. It can also eliminate the adverse factors caused by the chip temperature difference and improve the stability of RC-IGBT applications. However, due to the parasitic PNPN structure in the IGBT device, it is very easy to cause the latch effect and device failure, which limits its use in certain fields. Figure 1 As shown, it is a schematic diagram of the cross-sectional structure of a reverse-conducting IGBT device, including a substrate 01, a base region 011, a carrier storage layer 012, an emitter region 013, a first contact region 014, a collector region 015, a second contact region 016, a trench structure 02, a trench 021, a gate dielectric layer 022, a conductive layer 023, an interlayer dielectric layer 03, a contact hole 031 and an emitter 04. In the IGBT functional region of the device, a parasitic PNPN structure is formed by an N+ emitter region, a P-type base region, an N-drift region and a P+ collector region. When the collector current is very large, the voltage drop generated by the collector current through the base resistance makes the PN junction composed of the P-type base region and the N+ emitter region forwardly conductive, and the current no longer passes through the conductive channel of the device, but flows directly from the P-type base region to the emitter. The gate loses control of the IGBT, the current rises sharply, and the voltage decreases. At this time, the sum of the current amplification factors of the PNP tube and the NPN tube is α PNP +α NPN =1, this phenomenon is usually called latch effect. In order to improve the latch effect of the device, it is usually considered to reduce α PNP and α NPNCurrently, the more commonly used method is to increase the concentration of the P-type base region below the N+ emitter region and reduce the resistance of the P-type base region to achieve the purpose of improving latch-up. However, holes are still extracted through the original channel, and the hole current passes through a large area of ​​the PN junction. As the current increases, latch-up effect will still occur. The ability to improve latch-up is very limited, and the improvement effect is not good.

[0005] Therefore, there is an urgent need to find a method for preparing a reverse conducting IGBT device that can effectively improve the latch-up effect of the device. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a reverse conducting IGBT device and a preparation method thereof, so as to solve the problem that the latch effect of the reverse conducting IGBT device in the prior art is not well improved.

[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a reverse conducting IGBT device, comprising the following steps:

[0008] Providing a first conductive type substrate, and forming a plurality of first grooves and second grooves spaced apart along the X direction on the upper surface layer of the substrate, with at least one first groove spaced apart between two adjacent second grooves;

[0009] forming a gate dielectric layer covering the inner walls and bottom surfaces of the first trench and the second trench, and forming a first conductive layer filling the first trench and a second conductive layer filling the second trench, wherein the first trench, the second trench, the gate dielectric layer, the first conductive layer and the second conductive layer constitute a trench structure;

[0010] A second conductive type base region is formed on the upper surface of the substrate, the bottom surface of which is higher than the bottom surfaces of the first conductive layer and the second conductive layer, and a first conductive type emitter region is formed on the upper surface of the base region, the side wall of which is adjacent to the side wall of the first trench;

[0011] forming an interlayer dielectric layer covering the substrate and the upper surface of the trench structure, wherein the interlayer dielectric layer is provided with a contact hole whose bottom surface exposes the second conductive layer and the emitter region;

[0012] forming a first contact region of a second conductivity type spaced apart from a sidewall of the first trench by a preset distance on an upper surface layer of the base region, wherein the sidewalls of the first contact region on both sides of the second trench along the X direction are adjacent to the second trench;

[0013] forming an emitter electrode electrically connected to the second conductive layer, the emitter region and the first contact region, and forming a gate electrode electrically connected to the first conductive layer;

[0014] forming a first conductive type second contact region and a second conductive type collector region adjacent to each other on the lower surface layer of the substrate;

[0015] A collector electrode electrically connected to the collector region and the second contact region is formed.

[0016] Optionally, before forming the first trench and the second trench, the method also includes a step of forming a first conductive type carrier storage layer on the upper surface of the substrate, wherein the bottom surface of the carrier storage layer is higher than the bottom surfaces of the first conductive layer and the second conductive layer, and the base region is located on the upper surface of the carrier storage layer.

[0017] Optionally, a plurality of the first trenches are formed between two adjacent second trenches, and the bottom surface of the contact hole above the region between two adjacent first trenches exposes the emitter region and the first contact region.

[0018] Optionally, the bottom surface of the contact hole above the second trench also exposes the first contact regions on both sides of the second trench along the X direction.

[0019] Optionally, a bottom surface of the contact hole located above the second trench is flush with an upper surface of the substrate.

[0020] Optionally, a bottom surface of the contact hole located above the second trench is lower than a bottom surface of the emitter region, and a side wall thereof exposes a side wall of the emitter region away from the first trench.

[0021] Optionally, a first conductive type field stop layer is further formed on the lower surface layer of the substrate, and the collector region and the second contact region are located on the lower surface layer of the field stop layer.

[0022] Optionally, the second contact region is located below the second trench and the first contact region, and the collector region is located below the emitter region and the first trench.

[0023] Optionally, a projection of the second contact area in the vertical direction does not exceed a projection area of ​​the second groove and the first contact area in the vertical direction.

[0024] The present invention also provides a reverse conducting IGBT device, comprising:

[0025] a first conductive type substrate;

[0026] A trench structure, comprising a first trench, a second trench, a gate dielectric layer, a first conductive layer and a second conductive layer, wherein a plurality of the first trenches and the second trenches are located on the upper surface layer of the substrate and are arranged at intervals along the X direction, and at least one first trench is spaced between two adjacent second trenches, the gate dielectric layer covers the inner walls and bottom surfaces of the first trenches and the second trenches, the first conductive layer fills the first trench, and the second conductive layer fills the second trench;

[0027] A second conductive type base region, located on the upper surface layer of the substrate and having a bottom surface higher than the bottom surfaces of the first conductive layer and the second conductive layer;

[0028] A first contact region of a second conductivity type, located on an upper surface layer of the base region and spaced apart from a sidewall of the first trench by a preset distance, wherein the sidewalls of the first contact region on both sides of the second trench along the X direction are adjacent to the second trench;

[0029] An emitter region of a first conductivity type, located on an upper surface layer of the base region and having one side wall adjacent to a side wall of the first trench;

[0030] an interlayer dielectric layer, covering the substrate and the upper surface of the trench structure, wherein the interlayer dielectric layer is provided with a contact hole whose bottom surface exposes the second conductive layer and the emitter region;

[0031] The second conductive type collector region and the first conductive type second contact region adjacent to each other are both located on the lower surface layer of the substrate;

[0032] An emitter, a gate and a collector, wherein the emitter is electrically connected to the second conductive layer, the emitter region and the first contact region, the gate is electrically connected to the first conductive layer, and the collector is electrically connected to the collector region and the second contact region.

[0033] As described above, the reverse conducting IGBT device and the preparation method thereof of the present invention improve the structure of the device. The groove structure arranged on the upper surface layer of the substrate includes a plurality of the first grooves and the second grooves arranged at intervals along the X direction. The emitter region is spaced apart from the second groove by a preset distance and a side wall is adjacent to the first groove. The first contact region is spaced apart from the first groove by a preset distance. The side walls of the first contact region on both sides of the second groove are adjacent to the second groove. The emitter is electrically connected to the second conductive layer, the first contact region and the emitter region in the second groove. The gate is electrically connected to the first conductive layer, thereby reducing the Miller capacitance of the device and improving the reliability of the device. The bottom surface of the contact hole above the second groove is lower than that of the emitter. The emitter fills the contact hole, so that more holes in the device flow into the emitter from the first contact area directly below the contact hole, and the number of holes flowing into the emitter from the area directly below the emitter area is reduced, thereby reducing the risk of turning on the PN junction between the emitter area and the base area, and improving the anti-latch capability of the device; by arranging the second contact area directly below the first contact area and the second groove, alternating IGBT functional areas and FRD functional areas are formed, thereby optimizing the distribution of the IGBT functional areas and the FRD functional areas, improving the reverse recovery speed of the device, improving the current characteristics of the fast recovery diode, and then improving the performance of the device, which has a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a reverse-conducting IGBT device.

[0035] Figure 2 Shown is a process flow chart of a method for preparing a reverse conducting IGBT device of the present invention.

[0036] Figure 3 It is a schematic diagram showing the cross-sectional structure after forming the carrier storage layer in the method for preparing the reverse conducting IGBT device of the present invention.

[0037] Figure 4 It is a schematic diagram showing the cross-sectional structure after forming the trench structure in the method for preparing the reverse conducting IGBT device of the present invention.

[0038] Figure 5 It is a schematic diagram showing the cross-sectional structure after forming the base region in the method for preparing the reverse conducting IGBT device of the present invention.

[0039] Figure 6 It is a schematic diagram showing the cross-sectional structure after forming the emitter region in the method for preparing the reverse conducting IGBT device of the present invention.

[0040] Figure 7 It is a schematic diagram showing the cross-sectional structure after forming the first contact region in the method for preparing the reverse conducting IGBT device of the present invention.

[0041] Figure 8 It is a schematic diagram showing the cross-sectional structure after the emitter is formed in the method for preparing the reverse conducting IGBT device of the present invention.

[0042] Fig. 9 It is a schematic diagram of the cross-sectional structure after forming the field stop layer in the method for preparing the reverse conducting IGBT device of the present invention.

[0043] Fig.10 It is a schematic diagram of the cross-sectional structure after forming the second contact region in the method for preparing the reverse conducting IGBT device of the present invention.

[0044] Fig.11 It is a schematic diagram of a cross-sectional structure after forming a collector electrode in the method for preparing a reverse conducting IGBT device of the present invention.

[0045] Fig.12 Another schematic diagram of the cross-sectional structure after forming the collector electrode in the method for preparing the reverse conducting IGBT device of the present invention is shown.

[0046] Description of Figure Numbers

[0047] 01 Substrate

[0048] 011 Base Area

[0049] 012 Carrier Storage Layer

[0050] 013 Launch Area

[0051] 014 First Contact Area

[0052] 015 Collector Area

[0053] 016 Second contact area

[0054] 02 Groove structure

[0055] 021 Groove

[0056] 022 Gate dielectric layer

[0057] 023 Conductive layer

[0058] 03 Interlayer dielectric layer

[0059] 031 Contact hole

[0060] 04 Emitter

[0061] 1 Substrate

[0062] 11 Base region

[0063] 12 Carrier storage layer

[0064] 13 Launch Area

[0065] 14 First contact area

[0066] 15 Collector area

[0067] 16 Second contact area

[0068] 17 Field cutoff layer

[0069] 2 Groove structure

[0070] 21 First Groove

[0071] 22 Second groove

[0072] 23. Gate dielectric layer

[0073] 24 first conductive layer

[0074] 25 Second conductive layer

[0075] 3 Interlayer dielectric layer

[0076] 31 Contact hole

[0077] 4 Emitter

[0078] 5 Collector DETAILED DESCRIPTION

[0079] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] See also Figures 2 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0081] Embodiment 1

[0082] This embodiment provides a method for preparing a reverse conducting IGBT device, such as Figure 2 FIG. 1 is a process flow chart of a method for preparing a reverse conducting IGBT device, comprising the following steps:

[0083] S1: providing a first conductive type substrate, and forming a plurality of first grooves and second grooves spaced apart along the X direction on the upper surface layer of the substrate, with at least one first groove spaced apart between two adjacent second grooves;

[0084] S2: forming a gate dielectric layer covering the inner walls and bottom surfaces of the first trench and the second trench, and forming a first conductive layer filling the first trench and a second conductive layer filling the second trench, wherein the first trench, the second trench, the gate dielectric layer, the first conductive layer and the second conductive layer constitute a trench structure;

[0085] S3: forming a second conductive type base region on the upper surface of the substrate, the bottom surface of which is higher than the bottom surfaces of the first conductive layer and the second conductive layer, and forming a first conductive type emitter region on the upper surface of the base region, the side wall of which is adjacent to the side wall of the first trench;

[0086] S4: forming an interlayer dielectric layer covering the substrate and the upper surface of the trench structure, wherein the interlayer dielectric layer is provided with a contact hole whose bottom surface exposes the second conductive layer and the emitter region;

[0087] S5: forming a first contact region of a second conductivity type spaced apart from a sidewall of the first trench by a preset distance on an upper surface layer of the base region, wherein the sidewalls of the first contact region on both sides of the second trench along the X direction are adjacent to the second trench;

[0088] S6: forming an emitter electrode electrically connected to the second conductive layer, the source region and the first contact region, and forming a gate electrode electrically connected to the first conductive layer;

[0089] S7: forming a first conductive type second contact region and a second conductive type collector region adjacent to each other on the lower surface layer of the substrate;

[0090] S8: forming a collector electrode electrically connected to the collector region and the second contact region.

[0091] See also Figures 3 to 6, perform the steps S1, S2 and S3: provide a first conductive type substrate 1, and form a plurality of first trenches 21 and second trenches 22 spaced apart along the X direction on the upper surface layer of the substrate 1, with at least one first trench 21 spaced apart between two adjacent second trenches 22; form a gate dielectric layer 23 covering the inner walls and bottom surfaces of the first trenches 21 and the second trenches 22, and form a first conductive layer 24 filling the first trench 21 and a second conductive layer 25 filling the second trench 22, wherein the first trench 21, the second trench 22, the gate dielectric layer 23, the first conductive layer 24 and the second conductive layer 25 constitute a trench structure 2; form a second conductive type base region 11 having a bottom surface higher than the bottom surfaces of the first conductive layer 24 and the second conductive layer 25 on the upper surface layer of the substrate 1, and form a first conductive type emitter region 13 having a side wall adjacent to the side wall of the first trench 21 on the upper surface layer of the base region 11.

[0092] Specifically, the first conductivity type includes one of N type or P type, the second conductivity type includes one of N type or P type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0093] Specifically, while ensuring device performance, the size, shape, thickness and doping concentration of the substrate 1 can be selected according to actual conditions and are not limited here.

[0094] As an example, Figure 3 As shown, it is a schematic diagram of the cross-sectional structure after the carrier storage layer 12 is formed. Before forming the first groove 21 and the second groove 22, it also includes the step of forming a first conductive type carrier storage layer 12 on the upper surface of the substrate 1. The bottom surface of the carrier storage layer 12 is higher than the bottom surfaces of the first conductive layer 24 and the second conductive layer 25, and the base region 11 is located on the upper surface of the carrier storage layer 12.

[0095] Specifically, the method of forming the carrier storage layer 12 includes ion implantation or other suitable methods.

[0096] Specifically, the doping concentration of the carrier storage layer 12 is greater than the doping concentration of the substrate 1. Under the condition of ensuring the device performance, the thickness and doping concentration of the carrier storage layer 12 can be selected according to the actual situation, and no restrictions are imposed here. The thickness here refers to the distance between the bottom surface of the carrier storage layer 12 and the upper surface of the carrier storage layer 12.

[0097] Specifically, Figure 4As shown, it is a schematic diagram of the cross-sectional structure after the groove structure 2 is formed. The formation of the first groove 21 and the second groove 22 includes the following steps: forming a patterned masking layer (not shown) on the upper surface of the substrate 1; and synchronously forming the first groove 21 and the second groove 22 based on the patterned masking layer.

[0098] Specifically, the process of forming the masking layer and patterning the masking layer is a common photolithography process, which will not be described in detail here.

[0099] Specifically, the opening sizes of the first groove 21 and the second groove 22 formed simultaneously may be the same or different. The method of simultaneously forming the first groove 21 and the second groove 22 includes dry etching, wet etching or other suitable methods.

[0100] Specifically, the bottom surfaces of the first trench 21 and the second trench 22 are both lower than the bottom surface of the carrier storage layer 12 .

[0101] Specifically, under the condition of ensuring device performance, the first trench 21 and the second trench 22 can also be formed in steps; when the first trench 21 and the second trench 22 are formed in steps, the opening sizes of the first trench 21 and the second trench 22 can be the same or different. In this embodiment, the first trench 21 and the second trench 22 are formed simultaneously.

[0102] Specifically, after forming the first trench 21 and the second trench 22 , the method further includes a step of removing the masking layer.

[0103] Specifically, the method for removing the masking layer is a commonly used hard mask and photoresist removal process, which will not be described in detail here.

[0104] Specifically, the method of forming the gate dielectric layer 23 includes thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0105] Specifically, the method for forming the first conductive layer 24 includes chemical vapor deposition, physical vapor deposition or other suitable methods; the method for forming the second conductive layer 25 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0106] Specifically, the gate dielectric layer 23 wraps the sidewalls and bottom surfaces of the first conductive layer 24 and the second conductive layer 25 , respectively.

[0107] Specifically, Figure 5, which is a schematic diagram of the cross-sectional structure after the base region 11 is formed, the base region 11 is located on the upper surface layer of the carrier storage layer 12, and the method of forming the base region 11 includes ion implantation or other suitable methods. In this embodiment, after ion implantation is performed on the upper surface layer of the carrier storage layer 12, a push-up process is performed on the doped region to diffuse the doped particles downward, thereby making the doped ions more evenly distributed.

[0108] Specifically, Figure 6 , which is a schematic diagram of the cross-sectional structure after the emitter region 13 is formed, and the method of forming the emitter region 13 includes ion implantation or other suitable methods. In this embodiment, after the doping region is formed on the upper surface layer of the base region 11 by the ion implantation process, the doping ions are diffused and distributed more evenly by the push-in process.

[0109] Please see again Figure 7 , perform step S4 and step S5: form a second conductive type first contact area 14 on the upper surface of the base area 11 at a preset distance from the sidewall of the first trench 21, and the sidewalls of the first contact area 14 on both sides of the second trench 22 along the X direction are adjacent to the second trench 22; form an interlayer dielectric layer 3 covering the upper surface of the substrate 1 and the trench structure 2, and the interlayer dielectric layer 3 is provided with a contact hole 31 whose bottom surface exposes the second conductive layer 25 and the emitter area 13.

[0110] Specifically, the method of forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition or other suitable methods.

[0111] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0112] Specifically, the contact hole 31 penetrates the interlayer dielectric layer 3 , and a method of forming the contact hole 31 includes dry etching, wet etching or other suitable methods.

[0113] Specifically, Figure 7 , which is a schematic diagram of the cross-sectional structure after the first contact region 14 is formed. The method of forming the first contact region 14 includes ion implantation or other suitable methods.

[0114] As an example, a plurality of first trenches 21 are formed between two adjacent second trenches 22 , and the bottom surface of the contact hole 31 above the area between two adjacent first trenches 21 exposes the emitter region 13 and the first contact region 14 .

[0115] As an example, the bottom surface of the contact hole 31 above the second trench 22 also exposes the first contact regions 14 on both sides of the second trench 22 along the X direction.

[0116] Specifically, the bottom surface of the contact hole 31 above the second trench 22 also exposes the upper surface of the gate dielectric layer 22 covering the sidewall of the second trench 22 .

[0117] Specifically, the area between two adjacent second trenches 22 is the IGBT functional area of ​​the reverse conducting IGBT device, and the area below the contact hole 31 where the second conductive layer 23 is exposed is the FRD functional area of ​​the reverse conducting IGBT device.

[0118] As an example, the bottom surface of the contact hole 31 located above the second trench 22 is flush with the upper surface of the substrate 1 , so as to expose the second conductive layer 25 .

[0119] As an example, the bottom surface of the contact hole 31 located above the second trench 22 is lower than the bottom surface of the emitter region 13 and the sidewalls expose the sidewalls of the emitter region 13, so that when the device is turned off, the holes in the device flow into the emitter through the first contact region 14 to the greatest extent (see the following Figure 8 ), reducing the amount of holes flowing into the emitter through the lower area of ​​the emitter region 13.

[0120] Specifically, while ensuring device performance, the opening size of the contact hole 31 can be selected according to actual conditions and is no longer restricted here; when multiple first grooves 21 are formed between two adjacent second grooves 22, the bottom surface of the contact hole 31 above the area between two adjacent first grooves 21 can be lower than the upper surface of the substrate 1, or can be flush with the upper surface of the substrate 1.

[0121] Specifically, the sidewall of the first contact region 14 close to the first groove 21 is located directly below the emitter region 13 , that is, the sidewall of the first contact region 14 extends to a preset distance directly below the emitter region 13 and is spaced from the first groove by a preset distance.

[0122] Specifically, a plurality of first grooves 21 are formed between two adjacent second grooves 22, the first contact area 14 located between two adjacent first grooves 21 is spaced apart from the first groove 21 by a preset distance, and a side wall of the first contact area 14 located between the first groove 21 and the second groove 22 is adjacent to the second groove 22. While ensuring device performance, the distance between the first contact area 14 and the first groove 21 can be selected according to actual conditions and is no longer restricted here.

[0123] See also Figures 8 to 12 , execute step S6, step S7 and step S8: form an emitter 4 electrically connected to the second conductive layer 25, the emitter region 13 and the first contact region 14, and form a gate (not shown) electrically connected to the first conductive layer 24; form a first conductive type second contact region 15 and a second conductive type collector region 16 adjacent to each other on the lower surface layer of the substrate 1; form a collector electrode 5 electrically connected to the collector region 15 and the second contact region 16.

[0124] Specifically, Figure 8 , which is a schematic diagram of the cross-sectional structure after the emitter 4 is formed. The emitter 4 fills the contact hole 31 and covers the upper surface of the interlayer dielectric layer 3 so that the emitter 4 is electrically connected to the first contact area 14 , the emitter area 13 and the second conductive layer 25 .

[0125] Specifically, the method for forming the emitter 4 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods; the method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0126] As an example, Fig. 9 , which is a schematic cross-sectional structure diagram after forming the field stop layer 17 , a first conductive type field stop layer 17 is further formed on the lower surface of the substrate 1 , and the collector region 15 and the second contact region 16 are located on the lower surface of the field stop layer 17 .

[0127] Specifically, the doping concentration of the field stop layer 17 is higher than the doping concentration of the substrate 1 , so as to reduce the thickness of the device and increase the closing speed of the device.

[0128] Specifically, the method for forming the field stop layer 17 includes ion implantation or other suitable methods. In this embodiment, after ion implantation is performed on the lower surface layer of the substrate 1 , the doped region is annealed by a laser annealing process to obtain the field stop layer 17 .

[0129] Specifically, Fig.10, which is a schematic diagram of the cross-sectional structure after the second contact region 16 is formed, the method for forming the collector region 15 includes ion implantation or other suitable methods; the method for forming the second contact region 16 includes ion implantation or other suitable methods. In this embodiment, B ions are implanted into the lower surface layer of the field stop layer 17 to form a P-type doped region, and then a patterned shielding layer is formed on the lower surface of the substrate 1. Based on the patterned shielding layer, P ions are implanted into the P-type doped region to form a heavily doped inversion layer, so as to obtain the collector region 15 and the second contact region 16 adjacent to each other, and the upper surface of the second contact region 16 is flush with the upper surface of the collector region 15.

[0130] As an example, the second contact region 16 is located below the second trench 22 and the first contact region 14 , and the collector region 15 is located below the emitter region 13 and the first trench 21 .

[0131] Specifically, the second contact region 16 is located below the second trench 22 and the first contact region 14 , which can increase the reverse recovery speed of the device, improve the current characteristics of the fast recovery diode, and enhance the performance of the device.

[0132] As an example, a projection of the second contact region 16 in the vertical direction does not exceed a projection area of ​​the second groove 22 and the first contact region 14 in the vertical direction.

[0133] Specifically, Fig.11 and Fig.12 As shown, they are respectively a schematic diagram of a cross-sectional structure after forming the collector 5 and another schematic diagram of a cross-sectional structure after forming the collector 5. The formation of the collector 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods.

[0134] Specifically, by improving the device formation process, the second groove 22 is formed between two adjacent first grooves 21 along the X direction, and at least one first groove 21 is formed between two adjacent second grooves 22 along the X direction, so that the FRD functional area and the IGBT functional area of ​​the device are alternately arranged along the X direction, and the size of the contact hole 31 located above the second groove 22 is improved, so that the emitter 4 is simultaneously connected to the emitter area 13, the first contact area 14 and the second conductive layer 25 through the contact hole 31, and the second conductive layer 25 in the second groove 22 is electrically connected to the emitter 4. By utilizing the alternating distribution of the IGBT functional area and the FRD functional area, the Miller capacitance of the device is reduced, and then the voltage overshoot between the emitter and the gate when the device is turned off is effectively reduced, thereby improving the reliability of the device.

[0135] Specifically, by making the bottom surface of the contact hole 31 above the second groove 21 lower than the bottom surface of the emitter region 13, the holes in the device flow to the emitter 4 through the first contact region 14 directly below the contact hole 31, and almost do not flow into the emitter 4 through the bottom of the emitter region 13, thereby avoiding the opening of the PN junction between the emitter region 13, the first contact region 14 and the base region 11, and improving the anti-latch characteristic of the device.

[0136] The method for preparing the reverse conducting IGBT device of this embodiment improves the manufacturing process of the device, forms the groove structure 2 including the first groove 21 and the second groove 22 spaced apart along the X direction on the upper surface layer of the substrate 1, the first contact area 14 on both sides of the second groove 22 is adjacent to the side wall of the second groove 22, the bottom surface of the contact hole 31 located above the second groove 22 exposes the gate dielectric layer 23, the second conductive layer 25, the first contact area 14 and the emitter area 13, and the bottom surface of the contact hole 31 located above the second groove 22 is lower than the bottom surface of the emitter area 13, so that the holes in the device almost do not flow into the emitter area through the area below the emitter area 13. The first conductive layer 25 in the second groove 22 is electrically connected to the emitter 4 by alternately arranging the first groove 21 and the second groove 22, thereby forming an alternating IGBT functional area and FRD functional area, reducing the Miller capacitance of the device, thereby effectively reducing the voltage overshoot when the device is turned off, and improving the reliability of the device; by forming the second contact area 16 only directly below the second groove 22 and the first contact area 14, the reverse recovery speed of the device is improved, the current characteristics of the fast recovery diode in the device are improved, and then the performance of the device is improved.

[0137] Embodiment 2

[0138] This embodiment provides a reverse conducting IGBT device, such as Fig.11 and Fig.12As shown, they are respectively a schematic diagram of a cross-sectional structure of the reverse conducting IGBT device and another schematic diagram of a cross-sectional structure of the reverse conducting IGBT device, comprising a first conductive type substrate 1, a trench structure 2, a second conductive type base region 11, a second conductive type first contact region 14, a first conductive type emitter region 13, an interlayer dielectric layer 3, a second conductive type collector region 15, a first conductive type second contact region 16, an emitter 4, a gate and a collector 5, wherein the trench structure 2 comprises a first trench 21, a second trench 22, a gate dielectric layer 23, a first conductive layer 24 and a second conductive layer 25, a plurality of the first trenches 21 and the second trenches 22 are located on the upper surface layer of the substrate 1 and are arranged at intervals along the X direction, at least one first trench 21 is spaced between two adjacent second trenches 22, the gate dielectric layer 23 covers the inner walls and bottom surfaces of the first trench 21 and the second trench 22, the first conductive layer 24 fills the first trench 21, and the second conductive layer 25 fills the second trench 22; The base region 11 is located on the upper surface of the substrate 1 and its bottom surface is higher than the bottom surfaces of the first conductive layer 24 and the second conductive layer 25; the first contact region 14 is located on the upper surface of the base region 11 and is spaced apart from the sidewall of the first trench 21 by a preset distance, and the sidewalls of the first contact region 14 on both sides of the second trench 22 along the X direction are adjacent to the second trench 22; the emitter region 13 is located on the upper surface of the base region 11 and one sidewall is adjacent to the sidewall of the first trench 21; the interlayer dielectric layer 3 covers the The substrate 1 and the upper surface of the groove structure 2, the interlayer dielectric layer 3 is provided with a contact hole 31 whose bottom surface exposes the second conductive layer 25 and the emitter area 13; the mutually adjacent collector area 15 and the second contact area 16 are both located at the lower surface layer of the substrate 1; the emitter 4 is electrically connected to the second conductive layer 25, the emitter area 13 and the first contact area 1, the gate is electrically connected to the first conductive layer 24, and the collector 5 is electrically connected to the collector area 15 and the second contact area 16.

[0139] Specifically, the substrate 1 is made of silicon, silicon germanium, silicon carbide or other suitable semiconductor materials.

[0140] Specifically, a first conductive type carrier storage layer 12 is further provided on the upper surface of the substrate 1 , the bottom surface of the carrier storage layer 12 is higher than the bottom surfaces of the first trench 21 and the second trench 22 , and the base region is located on the upper surface of the carrier storage layer 12 .

[0141] Specifically, under the condition of ensuring the performance of the device, the depth and opening size of the first groove 21 can be selected according to the actual situation, and are not limited here; the depth and opening size of the second groove 22 can be selected according to the actual situation, and are not limited here. In this embodiment, the depth and opening size of the first groove 21 and the second groove 22 are the same.

[0142] Specifically, under the condition of ensuring the device performance, the thickness of the gate dielectric layer 23 can be selected according to actual conditions and is not limited here.

[0143] Specifically, the gate dielectric layer 23 is made of silicon oxide, silicon nitride or other suitable dielectric materials.

[0144] Specifically, the material of the first conductive layer 24 includes polysilicon or other suitable conductive materials; the material of the second conductive layer 25 includes polysilicon or other suitable conductive materials.

[0145] Specifically, when the carrier storage layer 12 is provided on the upper surface of the substrate 1 , the base region 11 is located on the upper surface of the carrier storage layer 12 .

[0146] Specifically, under the condition of ensuring the device performance, the doping concentration and thickness of the base region 11 can be selected according to actual conditions and are not limited here.

[0147] Specifically, under the condition of ensuring the device performance, the doping concentration, thickness and size of the emission region 13 can be selected according to actual conditions and are not limited here.

[0148] Specifically, the emitter region 13 is spaced from the second groove 22 by a preset distance, the first contact region 14 is spaced from the first groove 21 by a preset distance, and at least one side wall of the first contact region 14 along the X direction is located directly below the emitter region 13. While ensuring device performance, the thickness and doping concentration of the first contact region 14 can be selected based on actual conditions and are no longer restricted here.

[0149] Specifically, under the condition of ensuring the device performance, the thickness of the interlayer dielectric layer 3 can be selected according to actual conditions and is not limited here.

[0150] Specifically, the contact hole 31 is located above the area between two adjacent first grooves 21 , and the bottom surface of the contact hole 31 at least exposes the emitter region 13 and the first contact region 14 .

[0151] Specifically, a plurality of the first grooves 21 are arranged between two adjacent second grooves 22, the first contact area 14 between two adjacent first grooves 21 is spaced apart from the first groove 21, and the bottom surface of the contact hole 31 above the second groove 22 exposes the gate dielectric layer 23, the second conductive layer 25, the emitter area 13 and the first contact area 14 on both sides of the second groove 22.

[0152] Specifically, the bottom surface of the contact hole 31 located above the second groove 22 is lower than the bottom surface of the emitter region 13 and the side walls expose the side walls of the emitter region 13, so that the holes in the device flow into the emitter 4 through the first contact region 14 directly below the contact hole 31, and fewer holes flow into the emitter 4 from below the emitter region 13, thereby avoiding the opening of the PN junction between the emitter region 13 and the base region 11, thereby improving the anti-latch capability of the device.

[0153] Specifically, the material of the emitter 4 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials; the material of the gate includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0154] Specifically, a first conductive type field stop layer 17 with a preset thickness is further provided on the lower surface of the substrate 1 , and the collector region 15 and the second contact region 16 are located on the lower surface of the field stop layer 17 .

[0155] Specifically, under the condition of ensuring the device performance, the thickness and doping concentration of the field stop layer 17 can be selected according to actual conditions, and are not limited here.

[0156] Specifically, under the condition of ensuring the performance of the device, the doping concentration and thickness of the collector region 15 can be selected according to the actual situation, and are not limited here; the doping concentration and thickness of the second contact region 16 can be selected according to the actual situation, and are not limited here. In this embodiment, the collector region 15 and the second contact region 16 have the same thickness.

[0157] Specifically, the second contact region 16 is located below the second groove 22 and the first contact region 14 , the collector region 15 is located below the emitter region 13 and the first groove 21 , and the projection of the second contact region 16 in the vertical direction does not exceed the projection area of ​​the second groove 22 and the first contact region 14 in the vertical direction.

[0158] Specifically, since the second contact region 16 is located below the second trench 22 and the first contact region 14 , the reverse recovery speed of the device can be increased, the current characteristics of the fast recovery diode can be improved, and the performance of the device can be improved.

[0159] Specifically, the material of the collector electrode 5 includes titanium, titanium nitride, silver, gold, copper, tungsten, nickel, platinum, aluminum or other suitable conductive materials.

[0160] Specifically, by improving the structure of the device, the first grooves 21 and the second grooves 22 are arranged alternately along the X direction on the upper surface layer of the substrate 1, the emitter 4 is electrically connected to the second conductive layer 25, the first contact area 14 and the emitter area 13, the second contact area 16 is located directly below the first contact area 14 and the second grooves 22, and the gate is electrically connected to the first conductive layer 24, thereby forming an IGBT functional area and an FRD functional area alternating along the X direction, reducing the Miller capacitance of the device, thereby reducing the voltage overshoot between the emitter 4 and the gate in the device, and improving the reliability of the device.

[0161] The reverse conducting IGBT device of this embodiment improves the structure of the device. The first grooves 21 and the second grooves 22 are alternately arranged along the X direction on the upper surface layer of the substrate 1. The emitter 4 is electrically connected to the second conductive layer 25 in the second groove 22, thereby forming alternating IGBT functional areas and FRD functional areas, reducing the Miller capacitance of the device and improving the reliability of the device. At the same time, the bottom surface of the contact hole 31 above the second groove 22 is lower than the bottom surface of the emitter area 13 and the side wall of the emitter area 13 is exposed, so that the holes in the device flow into the emitter 4 through the first contact area 14 directly below the contact hole 31, thereby improving the anti-latch capability of the device.

[0162] In summary, the reverse conducting IGBT device and the preparation method thereof of the present invention improve the structure of the device, and a plurality of first grooves and second grooves spaced apart along the X direction are arranged on the upper surface layer of the substrate, the emitter region is spaced apart from the second groove by a preset distance and a side wall is adjacent to the first groove, the first contact region is spaced apart from the first groove by a preset distance and a side wall is adjacent to the second groove, the emitter is electrically connected to the second conductive layer, the first contact region and the emitter region in the second groove, and the gate is electrically connected to the first conductive layer, thereby reducing the Miller capacitance of the device and improving the reliability of the device; the bottom surface of the contact hole located above the second groove is lower than the lower surface of the emitter region And the side wall of the emitter region away from the first groove is adjacent, so that the holes in the device flow into the emitter through the first contact region directly below the contact hole, reducing the number of holes flowing into the emitter from the area directly below the emitter region, reducing the risk of the PN junction between the emitter region and the base region opening, and improving the anti-latch capability of the device; by arranging the second contact region directly below the first contact region and the second groove, an alternating IGBT functional region and FRD functional region are formed, the distribution of the IGBT functional region and the FRD functional region is optimized, the reverse recovery speed of the device is improved, the current characteristics of the fast recovery diode are improved, and then the performance of the device is improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0163] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a reverse conducting IGBT device, characterized in that: The following steps are involved: Providing a first conductive type substrate, and forming a plurality of first grooves and second grooves spaced apart along the X direction on the upper surface layer of the substrate, with at least one first groove spaced apart between two adjacent second grooves; forming a gate dielectric layer covering the inner walls and bottom surfaces of the first trench and the second trench, and forming a first conductive layer filling the first trench and a second conductive layer filling the second trench, wherein the first trench, the second trench, the gate dielectric layer, the first conductive layer and the second conductive layer constitute a trench structure; A second conductive type base region is formed on the upper surface of the substrate, the bottom surface of which is higher than the bottom surfaces of the first conductive layer and the second conductive layer, and a first conductive type emitter region is formed on the upper surface of the base region, the side wall of which is adjacent to the side wall of the first trench; forming an interlayer dielectric layer covering the substrate and the upper surface of the trench structure, wherein the interlayer dielectric layer is provided with a contact hole whose bottom surface exposes the second conductive layer and the emitter region; forming a first contact region of a second conductivity type spaced apart from a sidewall of the first trench by a preset distance on an upper surface layer of the base region, wherein the sidewalls of the first contact region on both sides of the second trench along the X direction are adjacent to the second trench; forming an emitter electrode electrically connected to the second conductive layer, the emitter region and the first contact region, and forming a gate electrode electrically connected to the first conductive layer; forming a first conductive type second contact region and a second conductive type collector region adjacent to each other on the lower surface layer of the substrate; A collector electrode electrically connected to the collector region and the second contact region is formed.

2. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: Before forming the first groove and the second groove, the method also includes forming a first conductive type carrier storage layer on the upper surface of the substrate, wherein the bottom surface of the carrier storage layer is higher than the bottom surfaces of the first conductive layer and the second conductive layer, and the base region is located on the upper surface of the carrier storage layer.

3. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: A plurality of the first trenches are formed between two adjacent second trenches, and the bottom surface of the contact hole above the region between two adjacent first trenches exposes the emitter region and the first contact region.

4. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: The bottom surface of the contact hole above the second trench also exposes the first contact regions on both sides of the second trench along the X direction.

5. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: A bottom surface of the contact hole located above the second trench is flush with an upper surface of the substrate.

6. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: The bottom surface of the contact hole located above the second trench is lower than the bottom surface of the emitter region, and the side wall thereof exposes the side wall of the emitter region away from the first trench.

7. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: A first conductive type field stop layer is also formed on the lower surface of the substrate, and the collector region and the second contact region are located on the lower surface of the field stop layer.

8. The method for preparing a reverse conducting IGBT device according to claim 1, characterized in that: The second contact region is located below the second trench and the first contact region, and the collector region is located below the emitter region and the first trench.

9. The method for preparing a reverse conducting IGBT device according to claim 8, characterized in that: A projection of the second contact region in the vertical direction does not exceed a projection area of ​​the second groove and the first contact region in the vertical direction.

10. A reverse conducting IGBT device, characterized in that: include: a first conductive type substrate; A trench structure, comprising a first trench, a second trench, a gate dielectric layer, a first conductive layer and a second conductive layer, wherein a plurality of the first trenches and the second trenches are located on the upper surface layer of the substrate and are arranged at intervals along the X direction, and at least one first trench is spaced between two adjacent second trenches, the gate dielectric layer covers the inner walls and bottom surfaces of the first trenches and the second trenches, the first conductive layer fills the first trench, and the second conductive layer fills the second trench; A second conductive type base region, located on the upper surface layer of the substrate and having a bottom surface higher than the bottom surfaces of the first conductive layer and the second conductive layer; A first contact region of a second conductivity type, located on an upper surface layer of the base region and spaced apart from a sidewall of the first trench by a preset distance, wherein the sidewalls of the first contact region on both sides of the second trench along the X direction are adjacent to the second trench; An emitter region of a first conductivity type, located on an upper surface layer of the base region and having one side wall adjacent to a side wall of the first trench; an interlayer dielectric layer, covering the substrate and the upper surface of the trench structure, wherein the interlayer dielectric layer is provided with a contact hole whose bottom surface exposes the second conductive layer and the emitter region; The second conductive type collector region and the first conductive type second contact region adjacent to each other are both located on the lower surface layer of the substrate; An emitter, a gate and a collector, wherein the emitter is electrically connected to the second conductive layer, the emitter region and the first contact region, the gate is electrically connected to the first conductive layer, and the collector is electrically connected to the collector region and the second contact region.

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