Semiconductor device and forming method thereof

Abstract

A method for manufacturing a semiconductor device is disclosed. Methods involve forming a stack of alternating semiconductor channels and interposers on a substrate with sacrificial structures between the interposers. Source / drain openings are formed, and strain in the channel is modified. Source / drain structures are formed in the openings, and a dielectric layer is deposited. The resulting device features a stacked nanostructure having internal spacers of varying height, enabling improved performance in electronic devices. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack including alternating first semiconductor channels and second semiconductor interlayers on a substrate, the stack including a first sacrificial structure located between adjacent pairs of the second semiconductor interlayers, the first sacrificial structure including a third semiconductor layer having an etching selectivity different from that of the first semiconductor channels and the second semiconductor interlayers, the forming of the stack including forming a source / drain opening; replacing the third semiconductor layer with a first dielectric layer; forming a first source / drain structure in a lower portion of the source / drain opening to a level below the first dielectric layer; forming a second dielectric layer on the first source / drain structure; increasing the tensile strain of one of the first semiconductor channels located above the second dielectric layer; and after the increasing of the tensile strain, forming a second source / drain structure in an upper portion of the source / drain opening located above the lower portion and adjacent to the one of the first semiconductor channels.

[0004] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack including alternating nanostructure channels and interlayers on a substrate, the stack including a first sacrificial structure located between adjacent pairs of the interlayers, the first sacrificial structure including a third semiconductor layer having an etching selectivity different from that of the nanostructure channels and the interlayers, the forming of the stack including forming a source / drain opening; after the forming of the source / drain opening, reducing the tensile strain of one of the nanostructure channels; after the reducing of the tensile strain, forming a first source / drain in the source / drain opening, the first source / drain adjacent to the one of the nanostructure channels; forming a first dielectric layer on the first source / drain; and forming a second source / drain in the source / drain opening and on the first dielectric layer.

[0005] Still other embodiments of the present application provide a semiconductor device, comprising: a first nanostructure stack; a second nanostructure stack located above the first nanostructure stack and separated from the first nanostructure stack by a first dielectric layer; a first internal spacer vertically positioned between two adjacent nanostructures of the first nanostructure stack; and a second internal spacer vertically positioned between two adjacent nanostructures of the second nanostructure stack, the second internal spacer having a height exceeding the height of the first internal spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1A to 24 are diagrams of various embodiments of an IC device at various stages of fabrication according to various aspects of the disclosed embodiments.

[0008] Fig.25 is a flow chart of a method of forming an IC device according to various embodiments.

[0009] Fig.26 is a flow chart of a method of forming an IC device according to various embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Terms expressing relative degrees, such as "about," "substantially," and the like, should be interpreted as meaning that one of ordinary skill in the art would understand given the current technical specifications.

[0013] The terms "first", "second", "third", etc. may be used herein to describe the order of events or the sequential order of elements, but may be interchanged or varied in some contexts. For example, a second layer may be formed on a first layer (e.g., sequentially after the first layer), but in some contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0014] The term "surrounding" may be used herein to describe a structure that completely or partially surrounds another element or structure, for example in three dimensions. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In another example, a first structure may partially wrap around a second structure, for example, by wrapping around three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0015] A source / drain region may be referred to as a source or a drain, alone or together depending on the context.

[0016] The disclosed embodiments relate generally to semiconductor devices, and more particularly to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructure FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), etc. A complementary FET or "CFET" is a device that includes vertically stacked FETs that may be different in type, such as an n-type FET (NFET) stacked on a p-type FET (PFET).

[0017] Tensile strain is beneficial to n-type field effect transistor (NFET) performance, and compressive strain is beneficial to p-type field effect transistor (PFET) performance. The nanostructure can have tensile strain due to the SiGe interposer, which can improve NFET device performance, but may reduce PFET device performance. In NFET devices, Ge% above 40% is generally unfavorable due to thickness considerations. For example, Ge% above 40% may cause defects in the nanosheet lattice during the epitaxial process.

[0018] In an embodiment of the present disclosure, after source / drain etching, the SiGe interposer in the NFET device can be replaced with substantially pure Ge (e.g., Ge% is substantially 100%), which is advantageous in increasing tensile strain without reducing thickness. Since the top nanostructure has only one-sided (e.g., bottom) stress, the top nanostructure (which can be the top nanosheet of the NFET device) has less tensile strain than the lower nanostructure (e.g., the second nanosheet and the third nanosheet), while the lower nanostructure has two-sided (e.g., top and bottom) stress. When a top SiGe layer is included above the top nanostructure, the top nanostructure can also benefit from the two-sided stress via its replacement.

[0019] In the PFET device region, the SiGe interposer can be replaced by a dielectric, which changes the tensile strain to a neutral or compressive strain, which is beneficial for enhancing the compressive strain after source / drain epitaxy. It should be understood that the replacement of the SiGe interposer can be implemented in NFET devices (e.g., with pure Ge), PFET devices (e.g., with dielectrics), or both (e.g., pure Ge in NFET devices and dielectrics in PFET devices).

[0020] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, less than the spacing obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0021] Figures 1A to 24 is a diagram of an intermediate stage in the fabrication of a FET, such as a nanostructure FET, according to some embodiments. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23A and Fig. 23B 2 is a view of forming a CFET including an NFET and a PFET, wherein the semiconductor layer 24 in the NFET is replaced with a substantially pure Ge layer 24G, and there is no internal spacer 74 on the upper surface of the uppermost channel 22B. Figure 1C , Figure 1D , Figure 2C , Figure 2D , Figure 3C , Figure 3D , Figure 4C , Figure 4D , Figure 5C , Figure 5D , Figure 6C , Fig.6D , Figure 7C , Fig.7D , Figure 8C , Fig.8D , Fig. 9C , Fig.9D , Fig. 10C , Fig. 10D , Fig. 11C , Fig.11D , Fig. 12C , Fig.12D , Fig. 13C , Fig.13D , Fig. 14C , Fig.14D , Fig. 15C , Fig.15D , Fig. 16C , Fig.16D , Fig. 17C , Fig.17D , Fig.18C , Fig.18D , Fig.19C , Fig.19D , Fig. 20C , Fig.20D , Fig. 21C , Fig.21D , Fig. 22C , Fig.22D , Fig.23C and Fig.23D 2 is a view of forming an NFET and a PFET, wherein the semiconductor layer 24 in the NFET is replaced with a substantially pure Ge layer 24G, and an internal spacer 74 is present on the upper surface of the uppermost channel 22B. Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig. 6E , Fig. 6F , Fig. 7E , Figure 7F , Fig. 8E and Fig.8F 2 is a view of forming an NFET and a PFET, wherein the semiconductor layer 24 in the NFET is replaced with a substantially pure Ge layer 24G, the semiconductor layer 24 in the PFET is replaced with a dielectric layer 24D, and there is an internal spacer 74 on the upper surface of the uppermost channel 22C. It should be noted that Figures 1A to 24 The embodiments described in the foregoing can be combined to form additional embodiments, and in some embodiments some steps can be omitted to form additional embodiments. For example, in some embodiments, replacing semiconductor layer 24 with dielectric layer 24D can be implemented while omitting replacing with substantially pure Ge layer 24G. In another example, in reference to Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig. 6E , Fig. 6F , Fig. 7E , Figure 7F , Fig. 8E and Fig.8F In the described embodiment, the top inner spacer 74 on the upper surface of the channel 22B can be omitted. Figure 5E , Fig. 5F , Figure 5G , Figure 5H , Fig. 6E , Fig. 6F , Fig. 7E , Figure 7F , Fig. 8E and Fig.8F The components described in the replacement of dielectric layer 24D can be used in conjunction with reference Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23A and Fig. 23B The components described above for forming a single-sided strain on the channel 22B are combined.

[0022] Fig.25 and Fig.26 Flowcharts of methods 1000, 2000 for forming an IC device or portion thereof from a workpiece according to one or more aspects of embodiments of the present disclosure are depicted. Methods 1000, 2000 are merely examples and are not intended to limit embodiments of the present disclosure to those explicitly shown in methods 1000, 2000. Additional steps may be provided before, during, and after methods 1000, 2000, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the methods. For the sake of simplicity, not all steps are described in detail herein. According to embodiments of methods 1000, 2000, the following description is provided in conjunction with Figures 1A to 24Methods 1000, 2000 are described with reference to partial perspective views and / or cross-sectional views of the workpiece shown in FIG. 1 at different stages of manufacture. For the avoidance of doubt, throughout the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that because the workpiece can be manufactured as a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0023] Figures 1A to 1D is a schematic cross-sectional side view of a portion of a nanostructured device 10 , which may be a CFET 10 , according to various embodiments. Figure 1A A view in the XZ plane is shown. Figure 1A and Figure 1B The nanostructured device 10 is provided to provide a method for understanding Figures 1A to 24 The CFET 10 may be included in an integrated circuit that includes many CFETs similar in most respects to the CFET 10 that are interconnected to form functional circuits, such as logic circuits, memory circuits, and the like.

[0024] refer to Figures 1A to 1D , CFET 10 may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). Figure 1A and Figure 1B In the view depicted in FIG. 1 , CFET 10 is in an intermediate production stage prior to forming source / drain 82N, 82P, active gate 200, or both. Nanostructure devices are formed over and / or in substrate 110 and generally include semiconductor channels 22A, 22B (optionally referred to as "nanostructures") located over semiconductor fins 32 protruding from and separated by isolation structures 36 (see FIG. 1 ). Figure 1B ). The semiconductor channels 22A and 22B may be collectively referred to as channels 22 , nanostructures 22 or nanosheets 22 .

[0025] The nanostructure devices are shown to each include one channel. That is, a first nanostructure device may include channel 22A, and a second nanostructure device stacked on the first nanostructure device may include channel 22B. In later operations, channels 22A, 22B will be laterally adjacent to source / drain features 82P, 82N, respectively, and covered and surrounded by active gate 200.

[0026] Fig.23A , Fig. 23B1 and 2 depict a device 10 including source / drain 82P, 82N and an active gate 200. Typically, the number of channels 22 is two or more, such as four or six or more. The active gate 200 controls the flow of current to and from the source / drain features 82N, 82P through the channels 22A, 22B based on the voltage applied at the gate structure 200 and the source / drain features 82N, 82P.

[0027] Reference again Figure 1A and Figure 1B In some embodiments, fin structure 32 includes silicon. Source / drain openings 86 may be formed extending into fin 32, resulting in mesas 32M located below channel 22 and between adjacent source / drain 82N and / or 82P.

[0028] Each of the channels 22A, 22B includes a semiconductor material, such as silicon or germanium, or a semiconductor alloy, such as SiGe, GeSn, SiGeSn, etc. Channels 22A, 22B are nanostructures (e.g., having a size in the range of several nanometers), and may also each have an elongated shape and extend in the X direction. In some embodiments, each of the channels 22A, 22B has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of the channels 22A, 22B may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination thereof.

[0029] In some embodiments, the lengths of channels 22A, 22B (e.g., measured in the X direction) may be different from each other, for example due to tapering during a fin etching process. In some embodiments, the length of channel 22B may be less than the length of channel 22A. In some embodiments, when four or more channels 22 are included in a vertical stack, the spacing between adjacent channels 22 may be in a range between about 8 nanometers (nm) and about 12 nm, although ranges above or below the stated ranges may also be advantageous and are contemplated herein.

[0030] exist Figures 1A to 1D In the embodiment, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0031] A multilayer stack or "lattice" including alternating layers of first and second semiconductor layers that will form channel 22 and interposer 24 is then formed over substrate 110. When forming CFET 10, it is advantageous to vertically isolate channel 22B of the upper transistor from channel 22A of the lower transistor. Therefore, in addition to the first and second semiconductor layers that form channel 22 and interposer 24, the multilayer stack may include additional first and third semiconductor layers that will form a sacrificial isolation structure 126S including semiconductor layer 127 and sacrificial layer 129L. The two first semiconductor layers that form semiconductor layer 127 may have thicknesses that are less than those of the first semiconductor layers that form channels 22A, 22B. The third semiconductor layer that forms sacrificial layer 129L may have thicknesses similar to or slightly less than those of channels 22A, 22B. The third semiconductor layer may be formed of a semiconductor material having an etching selectivity different from those of the first, second, and third semiconductor layers. In some embodiments, the third semiconductor layer is or includes a silicon germanium layer having a germanium concentration (Ge%) exceeding about 50% or a substantially pure or pure germanium layer having a germanium concentration exceeding about 99%, such as 100%.

[0032] The formation of the source / drain opening 86 may form the channel 22 and the semiconductor layer 127 by the first semiconductor layer, the interposer 24 by the second semiconductor layer, and the sacrificial layer 129L located between the semiconductor layers 127. In some embodiments, the first semiconductor layer may be formed of a first semiconductor material such as silicon, silicon carbide, etc., and the second semiconductor layer may be formed of a second semiconductor material such as silicon germanium, etc. As described above, the third semiconductor layer forming the sacrificial layer 129L may have a high germanium concentration to increase its etching selectivity relative to the first semiconductor layer and the second semiconductor layer.

[0033] Each of the layers of the multilayer stack may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the germanium concentration of the second semiconductor layer forming the interposer 24 is less than about 40%, which is advantageous when forming a lattice and provides some tensile strain to the channel 22 formed by the first semiconductor layer. A germanium concentration exceeding about 40% may cause germanium to diffuse into the channel 22 in subsequent processes.

[0034] In order to increase the tensile strain in the channel 22B of the N-type FET, one or more of the interposers 24 adjacent to the channel 22B may be replaced in a later operation with a germanium layer 24G having a germanium concentration of more than 40%, such as 50%, 60%, 70%, 80%, 90%, 95%, 98%, 99%, 99.9%, 99.99%, any value therebetween, etc. In some embodiments, the germanium layer 24G is a pure germanium layer 24G having a germanium concentration of 100% or substantially 100%. Throughout the description, the germanium concentration may refer to the atomic percentage of germanium in the germanium layer 24G. The germanium concentration may refer to a weight percentage, a molar fraction, or another suitable measure. When the germanium layer 24G is a SiGe, SiGeSN, or GeSN layer having a high germanium concentration (such as greater than about 50%), a molar ratio of germanium to silicon or tin may be used instead of an absolute concentration. For example, the high-concentration germanium layer 24G according to various embodiments may have a molar ratio of germanium to silicon in the range of about 50:50 to about 99:1.

[0035] Figure 1A and Figure 1B 22A, 22B and three interposers 24 are shown. In some embodiments, the multilayer stack may include fewer or additional pairs of channels 22 and interposers 24. Although the multilayer stack is shown as including interposers 24 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack may be the first semiconductor layer. In some embodiments, the top layer of the multilayer stack is interposer 24, rather than Figure 1A and Figure 1B For example, as shown in FIG. Figure 1C and Figure 1D , the topmost layer may be interposer 24. Including interposer 24 over channel 22B may facilitate increasing strain on channel 22B via replacement of interposer 24 on both the top and bottom sides of channel 22B instead of just on the bottom side of channel 22B.

[0036] exist Figures 1A to 1D In the embodiment, the fin 32 is formed in the substrate 110, and the nanostructures 22, 24 are formed in the multilayer stack, corresponding to Fig.25 , Fig.26 In some embodiments, the nanostructures 22, 24 and the fins 32 may be formed by etching trenches 84 in the multilayer stack and the substrate 110 (see Figure 1B). The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The first nanostructures 22A, 22B (hereinafter also referred to as "channels 22") are formed from the first semiconductor layer, and the second nanostructures or interposer 24 are formed from the second semiconductor layer. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18 nm to about 100 nm, but narrower distances less than about 18 nm are also contemplated herein. For simplicity of description, portions of the device 10 are shown in FIG. Figures 1A to 1D It is shown as including two fins 32 . Fig.25 , Fig.26 The processes 1000, 2000 shown in FIG. 1 can be extended to any number of fins and are not limited to Figures 1A to 23D Two fins 32 are shown in FIG.

[0037] The fin 32 and the nanostructures 22, 24 can be patterned by any suitable method. For example, the fin 32 and the nanostructures 22, 24 can be formed using one or more photolithography processes (including double patterning or multiple patterning processes). Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing a spacing smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer can be formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 32.

[0038] Figure 1B , Figure 1D The fin 32 is shown with tapered sidewalls, such that the width of the fin 32 and / or each of the nanostructures 22, 24 increases continuously in a direction toward the substrate 110. In such an embodiment, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fin 32 and nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0039] exist Figures 1A to 1D In the embodiment, an isolation region, component or structure 36 is formed adjacent to the fin 32, which may be a shallow trench isolation (STI) region, component or structure (see Figure 1B). The isolation region 36 may be formed by depositing an insulating material over the substrate 110, the fins 32, and the nanostructures 22, 24, and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fins 32, and the nanostructures 22, 24. Thereafter, a core material, such as those discussed above, may be formed over the liner.

[0040] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material over the nanostructures 22, 24. After the removal process is completed, the top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material.

[0041] The insulating material is then recessed to form isolation regions 36. After recessing, upper portions of nanostructures 22, 24 and fins 32 may protrude from between adjacent isolation regions 36. Isolation regions 36 may have top surfaces that are flat, convex, concave, or a combination thereof as shown. In some embodiments, isolation regions 36 are recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to insulating materials and leaves fins 32 and nanostructures 22, 24 substantially unchanged.

[0042] One embodiment of forming the fin 32 and nanostructures 22, 24 is described (e.g., etch later). In some embodiments, the fin 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., etch first). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0043] exist Figures 1A to 1D In the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24 and / or isolation regions 36. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, but in-situ doping and implantation doping may be used together.

[0044] exist Figures 1A to 1DIn the embodiment, a dummy or sacrificial gate structure 40 is formed over the fin 32 and / or the nanostructures 22, 24, corresponding to Fig.25 , Fig.26 Steps 1200, 2200. A dummy or sacrificial gate layer 45 is formed over the fins 32 and / or nanostructures 22, 24. The sacrificial gate layer 45 may be or include a material having a high etch selectivity relative to the isolation region 36. The sacrificial gate layer 45 may be a conductive, semiconductive, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon (poly-silicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials.

[0045] A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, etc., is formed over the dummy gate layer 45. In some embodiments, the mask layer 47 includes a first mask layer 47A in contact with the dummy gate layer 45 and a second mask layer 47B located above and in contact with the first mask layer 47A. The first mask layer 47A may be or include a material that is the same as or different from that of the second mask layer 47B.

[0046] In some embodiments, before the dummy gate layer 45 , a gate dielectric layer 43 is formed between the dummy gate layer 45 and the fins 32 and / or nanostructures 22 , 24 .

[0047] A spacer layer 41 is formed over the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the spacer layer 41 is or includes an insulating material such as SiOCN, SiOC, SiCN, etc., and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers. The spacer layer 41 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the sacrificial gate layer 45. According to some embodiments, a portion of the spacer material layer located between the sacrificial gate structures 40 is removed using an anisotropic etching process. In some embodiments, the spacer layer 41 is a multilayer including at least a first spacer layer and a second spacer layer.

[0048] exist Figures 1A to 1D , the source / drain opening 86 is formed by performing an etching process to etch the protruding fin 32 and / or the portion of the nanostructures 22, 24 not covered by the sacrificial gate structure 40, corresponding to Fig.25Step 1300. Source / drain openings 86 extend through the stack of nanostructures 22, 24. The recesses forming source / drain openings 86 may be anisotropic, thereby protecting and substantially not etching portions of fins 32 directly below sacrificial gate structure 40 and spacer layer 41. According to some embodiments, the top surface of recessed fin 32 may be substantially coplanar with the top surface of isolation region 36. According to some other embodiments, the top surface of recessed fin 32 may be lower than the top surface of isolation region 36. In such embodiments, a plurality of fin mesas 32M may be formed in fin 32. For simplicity, Figure 1A Three vertical stacks of nanostructures 22, 24 are depicted after the etching process. In general, the etching process may be used to form fewer or additional vertical stacks of nanostructures 22, 24 over the fins 32 than those depicted. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to the removal of upper portions of the spacer layer 41 during the etching process.

[0049] exist Figure 1C , Figure 1D In the embodiment of the present invention, the optional top second semiconductor layer 24 is included between the sacrificial gate structure 40 and the uppermost channel 22B. The source / drain opening 86 extends through the top second semiconductor layer 24 and the stack of nanostructures 22, 24 and may extend into the fin 32, as shown in FIG. Figure 1A and Figure 1B described.

[0050] Although the source / drain opening 86 is a continuous opening in the vertical direction (e.g., the Z-axis direction), the source / drain opening 86 includes an upper portion 86U and a lower portion 86L that may be associated with an upper transistor and a lower transistor. The upper transistor may include an upper channel 22B, and the lower transistor may include a lower channel 22A. Although not intended to be limiting herein, according to various embodiments, Figure 1A and Figure 1C 86U and 86L. For example, the interface can be located at about the vertical midpoint of the sacrificial fourth semiconductor layer 129L. Typically, the interface is located at a level vertically between the upper and lower limits of the sacrificial isolation structure 126L.

[0051] exist FIG. 2A to FIG. 2D12, the sacrificial layer 129L is removed, and an opening 129O is formed between the semiconductor layers 127. The sacrificial layer 129L can be removed by a suitable etching operation that is selective to the material of the sacrificial layer 129L without attacking the channel 22, the semiconductor layer 127, and the interposer 24. For example, the sacrificial layer 129L can be a high Ge% layer, while the channel 22, the semiconductor layer 127, and the interposer 24 can be low Ge% layers, which allows the sacrificial layer 129L to be removed without substantially removing the material of the channel 22, the semiconductor layer 127, and the interposer 24. In some embodiments, some material at the end portion of the interposer 24 is removed during the removal of the sacrificial layer 129I, which can be low Ge% SiGe. However, because the sacrificial layer 129L is a high Ge% layer, the material of the sacrificial layer 129L is removed much faster than the material of the interposer 24, so that the interposer 24 is mostly unaltered by etching when the sacrificial layer 129L is completely consumed.

[0052] In some embodiments, Figure 2B and Figure 2D , the surface of the semiconductor layer 127 facing the sacrificial layer 129L may have a thin layer 127G having a higher germanium concentration than other portions of the semiconductor layer 127. This may be due to the surface facing the sacrificial layer 129L being in contact with the high Ge% semiconductor material of the sacrificial layer 129L, which may cause germanium to diffuse or mix into the relatively low Ge% semiconductor material of the semiconductor layer 127 near the surface.

[0053] exist FIG. 3A to FIG. 3D In the embodiment of the present invention, after forming the opening 129O, a first dielectric layer 129 is formed in the opening 129O. The first dielectric layer 129 may be or include one or more of SiO, SiN, SiON, SiC, SiOC, SiCN, SiOCN, etc. The formation of the first dielectric layer 129 may include a deposition operation and a subsequent etch-back operation. The deposition operation may be PVD, CVD, ALD, etc. The etch-back operation may be dry etching or wet etching.

[0054] Then, a sacrificial dielectric layer 82D covering the channel 22A can be formed in the lower portion 86L of the source / drain opening 86. The sacrificial dielectric layer 82D can be or include one or more of SiO, SiN, SiON, SiC, SiOC, SiCN, SiOCN, etc. The formation of the sacrificial dielectric layer 82D can include a deposition operation and a subsequent etch-back operation. The deposition operation can be PVD, CVD, ALD, etc. The etch-back operation can be a dry etch or a wet etch. The dielectric material of the sacrificial dielectric layer 82D is different from the dielectric material of the first dielectric layer 129. Therefore, the etch-back operation of etching the sacrificial dielectric layer 82D can remove excess material of the sacrificial dielectric layer 82D without substantially attacking the first dielectric layer 129.

[0055] exist FIG. 4A to FIG. 4D In the embodiment of the present invention, after forming the sacrificial dielectric layer 82D, a sacrificial spacer layer 820 covering and protecting the channel 22B and the interposer 24 immediately adjacent thereto may be formed. The sacrificial spacer layer 820 may be a conformal thin layer of a dielectric material, which may be or include one or more of SiO, SiN, SiON, SiC, SiOC, SiCN, SiOCN, etc. The formation of the sacrificial spacer layer 820 may include a deposition operation and a subsequent etch-back operation. The deposition operation may be PVD, CVD, ALD, etc. The etch-back operation may be an anisotropic etch that removes a horizontal portion of the sacrificial spacer layer 820 to expose the sacrificial dielectric layer 82D. The dielectric material of the sacrificial spacer layer 820 is different from the dielectric material of the sacrificial dielectric layer 82D. Therefore, the etch-back operation of etching the sacrificial spacer layer 820 may remove excess material of the sacrificial spacer layer 820 without substantially eroding the sacrificial dielectric layer 82D. Similarly, when sacrificial dielectric layer 82D is removed in a later operation, sacrificial spacer layer 820 can protect channel 22B and interposer 24 adjacent thereto. Because sacrificial dielectric layer 82D is in place during formation of sacrificial spacer layer 820, sacrificial spacer layer 820 does not extend to lower portion 86L of source / drain opening 86.

[0056] exist FIG. 5A to FIG. 5D , after forming the sacrificial spacer layer 820, an extended lower source / drain opening 82O including the lower portion 86L of the source / drain opening 86 and the first inner spacer recess 74R1 is formed by removing the sacrificial dielectric layer 82D and recessing the interposer 24 in the lower portion 86L of the source / drain opening 86, corresponding to Fig.26 Step 2300 of . That is, the lower source / drain opening 86L is reopened by removing the sacrificial dielectric layer 82D. Then, a first internal spacer recess 74R1 is formed by removing the end portion of the interposer 24 exposed by the lower portion 86L of the source / drain opening 86. The removal of the end portion of the interposer 24 can be performed by a wet etch that is selective to the second semiconductor material (e.g., low Ge% SiGe) of the interposer 24. During the removal of the end portion of the interposer 24, a small amount of material of the upper portion of the channel 22A and the fin 32 can be removed. The exposed portion of the semiconductor layer 127 can also be removed so that the semiconductor layer 127 extends to be substantially coplanar with the side surface of the interposer 24 exposed by the first internal spacer recess 74R1.

[0057] In some embodiments, instead of leaving interposer 24 on top of and below channel 22A, interposer 24 may be removed to reduce the tensile strain of channel 22A to a neutral strain. FIG. 5E to FIG. 5H2 is a schematic cross-sectional view showing a process for forming a dielectric layer 24D or "dielectric interlayer layer 24D" that replaces the nanostructure 24 adjacent to the channel 22A and reduces the tensile strain of the channel 22A, corresponding to Fig.26 Step 2400. Compressive strain is beneficial to PFET performance. Source / drain epitaxy can form compressive strain in the channel 22A in the PFET device. Before the source / drain epitaxy, the channel 22A can have tensile strain due to the SiGe interposer 24 in contact therewith, which can reduce PFET performance. In order to reduce the tensile strain in the PFET device area before the source / drain epitaxy, the SiGe interposer 24 can be replaced with a dielectric interposer layer 24D, which reduces the tensile strain to neutral or compressive strain. The dielectric interposer 24D can convert the tensile strain to neutral, and the tensile strain can be further converted to compressive strain by thermal treatment (e.g., annealing). Then, after the source / drain epitaxy, the compressive strain can be increased relative to the embodiment where the SiGe interposer 24 is not replaced.

[0058] exist Figure 5E and Fig. 5F In FIG. 5 , before the openings 54 are formed, the spacer layer 41 and the sacrificial spacer layer 820 are present on the upper surfaces of the sacrificial gate structure 40 and the interposer 24 and the channel 22B in the upper portion 86U of the source / drain openings 86 .

[0059] After forming the source / drain openings 86 and the sacrificial spacer layer 820, the nanostructures 24 exposed by the openings 820 are removed by a suitable etching operation, and openings 54 are formed above and below the channels 22A. For example, the etching operation may be or include one or more isotropic etching operations, such as wet etching, that remove the nanostructures 24 at a faster rate than the channels 22A. In some embodiments, the channels 22A are slightly thinned by the etching operation that removes the nanostructures 24. In some embodiments, the nanostructures 24 are completely removed by the etching operation. In some embodiments, the nanostructures 24 are partially (e.g., mostly) removed by the etching operation, so that some material of the nanostructures 24 (e.g., low-concentration SiGe) remains on the upper surface or lower surface of one or more of the channels 22A.

[0060] exist Figure 5G and Figure 5H, the NFET region associated with the upper portion 86U of the source / drain opening 86 remains protected, while a dielectric interposer layer 24D is formed adjacent to (e.g., above and / or below) the channel 22A in the opening 54 previously provided with the interposer 24. The dielectric interposer layer 24D may be formed by a suitable deposition operation, such as PVD, CVD, ALD, etc. In some embodiments, the dielectric interposer layer 24D is or includes a dielectric material, such as SiO, SiOC, SiC, SiN, SiON, SiOCN, combinations thereof (e.g., multilayers thereof), etc. Other dielectric materials (such as HfO, Al2O3, etc.) may be included in the dielectric interposer layer 24D. Initially, one or more dielectric material layers including one or more of the just-mentioned dielectric materials may be formed between the openings 54 and optionally outside the openings 54. In some embodiments, the dielectric material layer may partially or completely fill the source / drain openings 86. That is, the dielectric material layer may exist on the side surfaces of the sacrificial spacer layer 820 and the upper surfaces of the fins 32 exposed by the source / drain openings 86 .

[0061] After depositing the dielectric material layer, one or more etching operations may be performed to recess the dielectric material layer to form dielectric interposer layer 24D. In some embodiments, dielectric interposer layer 24D has a width smaller than that of channel 22 after recessing (eg, Figure 5G The inner spacer groove 64 in which the inner spacer is to be formed may exist at the end of the dielectric interposer layer 24D. In some embodiments, the width of the inner spacer groove 64 in the X-axis direction is in the range of about 0.5 nm to about 3 nm.

[0062] exist 6A to 6F In the embodiment, an internal spacer 74 is formed. Fig. 6E and Fig. 6F In forming a reference Figure 5E to Figure 5G The dielectric layer 24D described thereafter continues with the formation of recesses 64 (see Figure 5G ).exist FIG. 6A to FIG. 6D In the embodiment, a selective etching process is performed to recess the end portions of the nanostructures 24 exposed by the openings in the spacer layer 41 without substantially attacking the nanostructures 22. FIG. 6A to FIG. 6D After the selective etching process in the embodiment, a structure similar to Fig. 5F Then, in forming the groove 64 of the groove. FIG. 6A to FIG. 6D The groove or Fig. 5FAfter the recess 64 in the NFET device region is formed, an internal spacer layer is formed to fill (partially or entirely) the recess or recess 64 in the nanostructure 24 formed by the previous selective etching process. The internal spacer layer can be a suitable dielectric material such as SiN, SiCN, SiOCN, SiOC, etc. formed by a suitable deposition method such as PVD, CVD, ALD, etc. In the NFET device region, the internal spacer layer is deposited on the sacrificial spacer layer 820.

[0063] Then, after forming the inner spacer layer, an etching process, such as an anisotropic etching process, is performed to remove the portion of the inner spacer layer disposed outside the recess (e.g., on the side surface of the nanostructure 22A and the upper surface of the fin 32). The remaining portion of the inner spacer layer (e.g., the portion disposed inside the recess in the nanostructure 24 or the dielectric interposer layer 24D) forms the inner spacer 74. The etching process to form the inner spacer 74 can remove the inner spacer layer in the NFET device region above the lower portion 86L of the source / drain opening 86.

[0064] Then, in 7A to 7F In various embodiments, a first source / drain region 82P or “first source / drain 82P” is formed, corresponding to Fig.26 Step 2500. Fig. 7A The formation of a p-type source / drain 82P is depicted. The first source / drain region 82P can be epitaxially grown from an epitaxial material. In some embodiments, the first source / drain region 82P applies stress in the corresponding channel 22A, thereby improving performance. The first source / drain region 82P is formed so that each dummy gate structure 40 is disposed between corresponding adjacent pairs of the first source / drain regions 82P. The first source / drain region 82P can be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. The first source / drain region 82P can apply compressive strain in the channel region.

[0065] like Fig. 7A , in some embodiments, the first source / drain 82P has an upper surface below the level of the bottom surface of the isolation structure 126. That is, the first source / drain 82P may extend upward to a level between the upper and lower surfaces of the inner spacer 74 between the channel 22A and the isolation structure 126.

[0066] Due to the compressive strain from the dielectric interlayer 24D and / or due to the high Ge% SiGe material (eg, about 40% to about 80%) of the first source / drain 82P, the sheet lattice constant of the nanostructure 22A may be within a range of about 0.5% to about 2% smaller than that of the fin mesa 32M.

[0067] exist FIG. 8A to FIG. 8F In the embodiment, after forming the first source / drain 82P, the sacrificial spacer layer 820 is removed, exposing the gate spacer 41, the channel 22B and the interposer 24 above the isolation structure 126. The removal of the sacrificial spacer layer 820 may include wet etching or dry etching, such as using a fluorine-based plasma in RIE.

[0068] from 9A to 9D Initially, no diagram depicting the dielectric interposer 24D is provided. Instead, it should be understood that the interposer adjacent to the first source / drain 82P may be a reference Fig. 8E and Fig.8F The semiconductor interposer 24 shown or the dielectric interposer 24D described. 9A to 9D In the embodiment, the semiconductor interposer 24 is depicted as being adjacent to the first source / drain 82P, but in some embodiments, instead of the semiconductor interposer 24, 9A to 9D The device 10 depicted in FIG. 1 may include a dielectric interposer 24D, and similarly for 10A to 20D . FIG. 21A to FIG. 21D Removal of interposer 24 and / or dielectric interposer 24D to release channels 22A, 22B is depicted. FIG. 21A to FIG. 23D In FIG. 2 , interposer 24 and optional dielectric interposer 24D are no longer present.

[0069] exist 9A to 9D In the embodiment of the present invention, after forming the first source / drain 82P and removing the sacrificial spacer layer 820, a third dielectric layer 910 is formed on the exposed surface of the first source / drain 82P. The third dielectric layer 910 can be or include one or more dielectric materials, such as SiN, SiCN, SiON, SiOCN, SiC, SiO, combinations thereof, etc., and can be deposited by a suitable deposition process, such as PVD, CVD, ALD, etc. The third dielectric layer 910 is beneficial for protecting the first source / drain 82P in subsequent operations, in which the interposer 24 associated with the N-type FET is replaced with a high Ge% interposer 24G. For example, the first source / drain 82P can be or include SiGe, which can be etched during the removal of the interposer 24, which can also include SiGe. Forming the third dielectric layer 910 physically isolates the first source / drain 82P from the etching chemistry (e.g., gas) introduced to remove the interposer 24 above the third dielectric layer 910.

[0070] FIG. 10A to FIG. 17D 2 is a schematic cross-sectional view of a process for replacing the nanostructure 24 in the NFET device region with a high Ge% layer 24G according to various embodiments. The high Ge% layer 24G has an end that is retracted from the outer side surface of the channel 22 to form a second inner spacer recess 74R2 in which the inner spacer 74 is formed. FIG. 10A to FIG. 13DIn the embodiment, a high Ge% layer 24G is formed, followed by the formation of a groove 74R2. FIG. 14A to FIG. 17D In the embodiment, the groove 74R2 is formed, followed by the formation of the high Ge% layer 24G. It should be understood that referring to FIG. 10A to FIG. 13D and FIG. 14A to FIG. 17D The described embodiments can be used with reference to FIG. 1A to FIG. 9D Any combination of the described embodiments.

[0071] exist FIG. 10A to FIG. 13D In the embodiment, the SiGe nanostructure 24 is replaced by an interlayer 24G which is beneficial to increase the tensile strain of the channel 22 in the NFET device region, corresponding to Fig.25 Step 1400. In reference FIG. 10A to FIG. 13D In the description of , the replacement interposer 24G is described as a pure or substantially pure germanium interposer, a high germanium concentration interposer, or a germanium-based semiconductor or a "germanium alloy" interposer having a germanium concentration of more than about 50%. The replacement interposer 24G has the function of increasing the tensile strain in the channel 22. Increasing the tensile strain may include via lattice mismatch and / or thermal expansion mismatch. In some embodiments, the replacement interposer 24G includes a material that can increase the tensile strain of the silicon channel 22 but is different from the pure or substantially pure germanium, the high germanium concentration semiconductor, or the germanium-based semiconductor having a germanium concentration of more than about 50%.

[0072] exist FIG. 10A to FIG. 10D In the process, one or more operations may be performed to form oxide layers 22O, 24O on the outer side surfaces of the channel 22B and the nanostructure 24 associated with the N-type FET, respectively. The oxide layers 22O, 24O may be formed by one or more chemical oxide formation processes, such as exposure to oxygen and / or a cleaning process. The oxide layer 22O is a SiO layer that protects the channel 22A during the growth of the germanium layer 24G in subsequent operations, so that the germanium layer 24G selectively grows on the exposed upper and / or lower surfaces of the channel 22A and the semiconductor layer 127 without substantially growing on the outer side surface of the channel 22A. The oxide layer 24O is a porous layer of SiGeO after the chemical oxide formation process. In some embodiments, the SiGeO layer is a layer including SiO and GeO. For example, the process may cause the silicon in the SiGe alloy to react with oxygen to form silicon dioxide (SiO2). However, germanium oxidation is different from silicon, and may form a less stable germanium oxide (GeO2) that may volatilize at the oxidation temperature. x), affecting the uniformity and quality of the oxide layer. The porosity of the oxide layer 24O allows for the selective removal of the nanostructures 24 and the selective growth of the germanium layer 24G through its pores. The thicknesses of the oxide layers 22O, 24O may be the same, substantially the same, or different from each other. For example, during the chemical oxide formation process, the thickness of the SiGeO of the oxide layer 24O may increase faster, slower, or at the same rate as the thickness of the SiO of the oxide layer 22O.

[0073] exist FIG. 11A to FIG. 11D In some embodiments, the nanostructure 24 is removed by a selective etching process using an etchant that is selective to the material of the nanostructure 24, so that the nanostructure 24 is removed without substantially corroding the nanostructure 22B. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas such as Ar, He, N2, a combination thereof, or the like. Due to the porosity of the oxide layer 24O, the etching gas may enter through the pores of the oxide layer 24O to corrode the SiGe of the nanostructure 24, while being blocked by the oxide layer 22O, so that the Si of the nanostructure 22B is not substantially corroded at its side surface. During the etching process for removing the nanostructure 24, some silicon of the nanostructure 22B may be removed, resulting in a reduced thickness of the nanostructure 22. That is, the width of the nanostructure 22B in the X-axis direction may not significantly change (shorten) due to the protection of the oxide layer 22O, however, the height or thickness of the nanostructure 22B may change (reduce) due to etching the inside of the opening 24H left by the removed nanostructure 24. In a subsequent operation in which the internal spacer 74 is formed in the NFET device region, the reduced thickness of the nanostructure 22 may produce an increased height or thickness (e.g., in the Z-axis direction) of the internal spacer 74 in the NFET device region. The thickness loss in the nanostructure 22B may be in the range of about 0.5 nm to about 2 nm. It should be noted that in Fig. 11C and Fig.11D In the embodiment, due to the removal of the nanostructures 24 on the top and bottom sides of the channel 22B, the channel 22B may be Fig.11A and Fig. 11B The thinning is greater when only one nanostructure 24 is located on the bottom side of the channel 22B as depicted in FIG. Fig. 11C and Fig.11DThe thickness loss of channel 22B depicted in FIG. 2 may be in the range of about 1 nm to about 4 nm. Thus, the thickness of nanostructure 22B may be less than the thickness of nanostructure 22A by a value in the range of about 0.5 nm to about 2 nm. The difference in thickness of nanostructure 22B may be between internal spacers 74, 74N or between gate structures 200 compared to nanostructure 22A just described.

[0074] In some embodiments, the nanostructures 24 are almost completely removed, but a thin layer of low-concentration SiGe may remain on the upper and / or lower surfaces of the channel 22 , which may reduce lattice mismatch when the germanium layer 24G is grown in a subsequent operation.

[0075] exist FIG. 12A to FIG. 12D In the embodiment, after the nanostructure 24 is removed, a germanium layer 24G can be formed in the space 24H previously occupied by the nanostructure 24, i.e., vertically below the channel 22B and optionally above the channel 22B. In embodiments where the topmost nanostructure 24 is present on the uppermost channel 22B, the germanium layer 24G can be formed on the upper surface of the uppermost channel 22B. To improve the tensile strain in the NFET, the nanostructure or interlayer 24 is replaced by a substantially pure germanium layer or interlayer 24G. The substantially pure high Ge% layer 24G can have a germanium concentration of more than about 98%, more than about 99%, more than about 99.9%, more than about 99.99%, etc. In some embodiments, the germanium layer 24G is a high-concentration high Ge% layer 24G having a Ge concentration of more than about 80%, about 85%, about 90%, etc. In some embodiments, the interposer 24G is a Ge alloy layer 24G (eg, a SiGe layer) having a Ge concentration exceeding about 50%, about 60%, about 70%, etc.

[0076] The interposer 24G may be formed by an epitaxial growth process including CVD (such as low pressure CVD), ALD, etc. A germanium precursor gas (such as germane (GeH4)) may be flowed into a heated chamber under reduced pressure. The precursor may decompose on an exposed region of the hot substrate (such as an exposed upper surface and / or lower surface of the channel 22B) so that pure or substantially pure germanium atoms are deposited layer by layer on the channel 22B. In embodiments where a pure or substantially pure high Ge% layer 24G is formed, germane may be the only precursor gas flowed into the chamber. In embodiments where a high concentration high Ge% layer 24G or a Ge alloy layer 24G is formed, germane and silane (SiH4) may be flowed into the chamber simultaneously. Although the interposer 24G is described above as a germanium-containing semiconductor layer having a germanium concentration exceeding about 50%, such as about 99.99% or even 100%, it should be understood that other material layers having qualities that are conducive to increasing tensile strain may be formed on the channel 22, beyond the tensile strain that can be achieved via the nanostructure 24 having a germanium concentration of less than about 40%. For example, instead of pure or high concentrations of germanium, a semiconductor such as ZnSe, AlInAs, or GaSb may be grown on the channel 22 to increase its tensile strain via lattice mismatch, thermal expansion mismatch, or both. Pure or high concentrations of germanium may have the benefit of simpler integration into nanostructure device manufacturing processes that already use silicon and germanium, for example, to form SiGe nanostructures 24.

[0077] Due to interposer 24G, the sheet lattice constant of nanostructure 22B may exceed the sheet lattice constant of nanostructure 22A by a value within a range of about 0.5% to about 2%. Similarly, the sheet lattice constant of nanostructure 22B may exceed the sheet lattice constant of fin mesa 32M by a value within a range of about 0.5% to about 2%. In embodiments where the top and bottom surfaces of nanostructure 22B are adjacent to interposer 24G, two of the values ​​just described may be within a range of about 0.5% to about 4%.

[0078] exist FIG. 13A to FIG. 13D In the embodiment of the present invention, after forming the replacement interposer 24G, the oxide layers 22O, 24O are removed and a second internal spacer recess 74R2 is formed, where the internal spacer 74 will be formed in a subsequent operation. The oxide layers 22O, 24O can be removed by a suitable etching process, such as a wet etch that removes the oxide layers 22O, 24O without substantially attacking other exposed layers (e.g., the spacer layer 41). The formation of the second internal spacer recess 74R2 can be similar in most aspects to the reference embodiment. FIG. 5A to FIG. 5DFor example, a selective etching process is performed to recess the end portion of the replacement interposer 24G without substantially attacking the nanostructure 22. In some embodiments, the etching process that recesses the end portion of the replacement interposer 24G thins the end of the channel 22 so that the end portion of the channel 22 has a thickness that is less than the thickness of the middle portion of the channel 22 that contacts the replacement interposer 24G.

[0079] exist FIG. 10A to FIG. 13D In FIG. 7 , the second inner spacer groove 74R2 is formed after forming the replacement interposer 24G. FIG. 14A to FIG. 18D , the second inner spacer recess 74R2 is formed before forming the replacement interposer 24G.

[0080] exist FIG. 14A to FIG. 14D In the embodiment of the present invention, the second inner spacer recess 74R2 is formed by performing a selective etching process that recesses the end portion of the nanostructure 24 without substantially attacking the nanostructure 22B. The end portion of the nanostructure 22 may be slightly thinned by the selective etching process, such as Fig.14A and Fig. 14C Described in. FIG. 14A to FIG. 14D The recess depicted in the reference is similar in most respects to the FIG. 5A to FIG. 5D Describe the recess.

[0081] exist FIG. 15A to FIG. 15D In the embodiment, the oxide layers 22O, 24O are similar in most respects to those of reference FIG. 10A to FIG. 10D The process described above forms the channel 22B and the nanostructure 24. FIG. 15A to FIG. 15D In the embodiment, the oxide layer 22O extends to the upper and lower surfaces of the end portion of the channel 22B except the side surface of the channel 22B, and the oxide layer 24O is disposed slightly inward from the outer side surface of the channel 22B in the X-axis direction.

[0082] exist FIG. 16A to FIG. 16D In the present invention, the nanostructure 24 is formed by a process similar to that of reference FIG. 11A to FIG. 11D The process described in the reference FIG. 10A to FIG. 13D In the depicted embodiment, the end portion of the channel 22B is etched twice: once during the removal of the nanostructure 24 and once during the formation of the recess 74R2. FIG. 14A to FIG. 18D In the described embodiment, due to the protection of the oxide layer 22O, the end portion of the channel 22 is subjected to one etching during the formation of the recess 74R2 and is not subjected to etching during the removal of the nanostructure 24. FIG. 10A to FIG. 13D When the process is performed, the end portion of the channel 22 may have a thickness slightly smaller than the thickness of the middle portion of the channel 22, and when the process is performed FIG. 14A to FIG. 18D The process may be such that the middle portion has a uniform or substantially uniform thickness.

[0083] exist FIG. 17A to FIG. 17D , replaces interposer 24G via a reference similar in most respects to FIG. 12A to FIG. 12D The process described is formed by the process. FIG. 14A to FIG. 18D In the embodiment of the present invention, since the groove 74R2 is already in the reference FIG. 14A to FIG. 14D The interposer 24G may be replaced without further etching once the formation operation (eg, epitaxial growth of germanium) is completed. 17A to 17D The replacement interposer 24G formed in the embodiment is substantially completed. Due to the presence of the oxide layer 22O that blocks the growth of the high Ge% semiconductor material on the end portion of the channel 22B, 17A to 17D The replacement interposer 24G in FIG. 24B may be formed to a width that is smaller than the width of the channel 22B.

[0084] exist 18A to 18D In the embodiment, the oxide layers 22O, 24O are similar in most respects to those of reference FIG. 13A to FIG. 13D Then, by a process similar in most respects to that of reference 6A to 6F The process described herein forms an internal spacer layer. 18A to 18D In the embodiment of the present invention, an inner spacer layer is formed to fill the recess 74R2 in the NFET device area, while the PFET device area is protected by the third dielectric layer 910. Then, by a method similar in most aspects to the reference 6A to 6F The process described above forms the internal spacer 74N in the N-type FET. 18A to 18D In the embodiment, the internal spacer 74N is formed in the NFET device region. The internal spacer 74N abuts the interposer 24G on either end thereof. Due to the additional etching of the channel 22B during the replacement of the interposer 24 with the interposer 24G, the internal spacer 74N in the NFET device region may have a thickness / height in the Z-axis direction that exceeds the thickness / height of the internal spacer 74 in the PFET device region. This may be more pronounced in embodiments where the interposer 24 is not replaced in the PFET device region than in embodiments where the interposer 24 is replaced with the dielectric layer 24D in the PFET device region. In some embodiments, the internal spacer 74N has a thickness that exceeds the thickness of the internal spacer 74 by a value in the range of about 0.5 nm to about 2 nm.

[0085] exist FIG. 19A to FIG. 19D In the embodiment, a second source / drain or a second source / drain region 82N is formed, corresponding to Fig.25Step 1500. The second source / drain region 82N can be epitaxially grown from an epitaxial material. In some embodiments, the second source / drain region 82N applies stress in the corresponding channel 22B, thereby improving performance. The second source / drain region 82N is formed so that each dummy gate structure 40 is disposed between corresponding adjacent pairs of the second source / drain region 82N. In some embodiments, the spacer layer 41 separates the second source / drain region 82N from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to a subsequently formed gate of the resulting device. In some embodiments, the second source / drain region 82N can be or include SiP, SiAs, SiSb, SiPAs, SiP:As:Sb, etc. The second source / drain region 82N can apply tensile strain in the channel region 22B.

[0086] exist FIG. 20A to FIG. 20D In the embodiment, after forming the second source / drain region 82N, an ILD 130 covering the source / drain regions 82N, 82P and adjacent to the spacer layer 41 may be formed. In some embodiments, an ESL 131 is formed before forming the ILD 130. The ESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from the dielectric material of the ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO2, or the like. x 、HfAlO x 、HfSiO x , Al2O3 or one or more of other suitable materials. After depositing ESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process, including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on glass (SOG), or a combination thereof. The ILD 130 may be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or another deposition process.

[0087] exist FIG. 21A to FIG. 21D, after forming the source / drain 82N, 82P, ESL 131 and ILD 130, an active or replacement gate structure 200 may be formed. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD 130 and the ESL 131. In the planarization process, portions of the hard masks 47A, 47B and the gate spacer 41 are also removed. After the planarization process, the dummy gate layer 45 is exposed. After the planarization process, the top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacer 41. Then, the dummy gate layer 45 is removed in an etching process, thereby forming a gate opening 92. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. The dummy gate dielectric 43 (when present) may be used as an etch stop layer when etching the dummy gate layer 45. Then, after removing the dummy gate layer 45, the dummy gate dielectric 43 may be removed.

[0088] Then, the replacement interposer 24G and the nanostructures 24 or the dielectric layer 24D are removed to release the nanostructures 22, corresponding to Fig.25 , Fig.26 Steps 1600, 2600. After removing the interposer 24G and the nanostructure 24 or the dielectric layer 24D, the nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of the substrate 110). Removing and replacing the interposer 24G and the nanostructure 24 or the dielectric layer 24D can be performed by using one or more selective etching processes with an etchant selective to the material of the nanostructure 24, the interposer 24G or the dielectric layer 24D, so that the nanostructure 24, the interposer 24G or the dielectric layer 24D is removed without substantially attacking the nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, a combination thereof, and the like. In embodiments including dielectric layer 24D, the material of dielectric layer 24D may be selected to have a different etch selectivity and / or be different from the material of ILD 130 , ESL 131 , fin spacers 41 , and isolation regions 36 , which may be advantageous in avoiding corrosion of ILD 130 , ESL 131 , fin spacers 41 , and isolation regions 36 when dielectric layer 24D is removed.

[0089] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the reshaping, the nanosheet 22 may have a dog-bone shape, wherein the middle portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X direction.

[0090] In some embodiments, during the removal of interposer 24G, interposer 24 , and / or dielectric interposer 24D, semiconductor layer 127 of isolation structure 126 is removed, so that isolation structure 126 includes only first dielectric layer 129 .

[0091] exist FIG. 22A to FIG. 22D In release FIG. 21A to FIG. 21D After the channel 22 in the embodiment, a replacement gate 200 is formed, corresponding to Fig.25 , Fig.26 The replacement gate 200 may be referred to as an active gate 200 or a gate structure 200. The gate structure 200 may be formed by a series of deposition operations, such as ALD cycles, of the various layers of the gate structure 200 in the opening, as described below. Fig.24 describe.

[0092] Fig.24 is a detailed view of a portion of a gate structure 200. The gate structure 200 generally includes an interfacial layer (IL, or "first IL" below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0093] refer to Fig.24 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, for example, silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The first IL 210 has a thickness ranging between about 5 angstroms and about 50 angstroms.

[0094] Still reference Fig.24, a gate dielectric layer 600 is formed over the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using between about 40 and 80 deposition cycles at a temperature in a range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as a precursor. Such an ALD process can form the first gate dielectric layer 220 to have a thickness in a range between about 10 angstroms and about 100 angstroms.

[0095] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructure device.

[0096] Further references Fig.24, an optional second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 further provides improved thermal stability for the gate structure 200, and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO or other suitable materials. In one embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited at a temperature of about 400 degrees Celsius to about 450 degrees Celsius using about 40 to about 100 cycles of ALD. In some embodiments, a thermal anneal is then performed to form a second IL 240, which may be or include TiSiNO. After the second IL 240 is formed by the thermal anneal, an atomic layer etch (ALE) with artificial intelligence (AI) control may be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle may include a first pulse of WCl5, followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage adjustment by metal gate patterning.

[0097] In addition, Fig.24 In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function barrier layer 700 is optionally formed on the gate structure 200. The work function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function barrier layer 700 is TiN. The work function barrier layer 700 may have a thickness ranging from about 5 Å to about 20 Å. Including the work function barrier layer 700 provides additional threshold voltage adjustment flexibility. Generally, the work function barrier layer 700 increases the threshold voltage for NFET transistor devices and reduces the threshold voltage (magnitude) for PFET transistor devices.

[0098] In some embodiments, the work function metal layer 900 is formed on the work function barrier layer 700, and the work function metal layer 900 may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating and / or other suitable methods, and has a thickness between about 10A and 20A. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN or another suitable material, and has a thickness between about 10A and 20A. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which will cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer, and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness between about 10 Å and about 20 Å.

[0099] Fig.24 A metal core layer 290 is also shown. In some embodiments, a glue layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can promote and / or enhance the adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride using ALD, such as TiN, TaN, MoN, WN, or another suitable material. In some embodiments, the thickness of the glue layer is between about 10A and about 25A. The metal core layer 290 can be formed on the glue layer and can include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal core layer 290 can be deposited using processes such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510 is formed in the metal core layer 290 vertically located between adjacent channels 22 or between channels 22A and fins 32, and the seam 510 can be an air gap. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. Seams 510 may be formed due to merging of films deposited on the sidewalls during conformal deposition. In some embodiments, seams 510 do not exist between adjacent channels 22.

[0100] In some embodiments, one or more of the metal layers including the core layer 290 and the work function layers 700, 900 in the PFET device may include Ti, Al, Zn, W, Nb, Co, etc., and the total thickness of the combination of the metal layers on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm. In some embodiments, one or more of the metal layers including the core layer 290 and the work function layers 700, 900 in the NFET device may include Ti and / or Al, etc., and the total thickness of the combination of the metal layers on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm.

[0101] exist FIG. 23A to FIG. 23D In the embodiment, after forming the gate structure 200, a source / drain opening may be formed in the ILD 130, and a source / drain contact 120 may be formed in the source / drain opening. The first source / drain 82P and the second source / drain 82N may be collectively referred to as a source / drain 82. A silicide region 118 and a source / drain contact 120 are formed on the source / drain region 82. FIG. 23A to FIG. 23D , only the source / drain contact 120 formed on the source / drain region 82N is shown. In some embodiments, additional source / drain contacts 120 may be formed on the source / drain region 82P in a manner substantially similar to that described with reference to the source / drain region 82N, except that the additional source / drain contacts 120 may be formed after thinning or removing the substrate 110 to expose the back side of the source / drain region 82P.

[0102] In some embodiments, the silicide layer 118 is formed before or during the formation of the source / drain contacts 120. For example, an N-type or P-type metal layer can be formed as a conformal thin layer over the exposed portions of the source / drain regions 82. The metal layer can be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, the silicide layer 118 can be formed by annealing the device 10. After annealing, the silicide layer 118 may be or include one or more of NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide of the silicide layer 118 may diffuse into the area below the ESL 131. The thickness of the silicide layer 118 may be in the range of about 1 nm to about 10 nm. Below about 1 nm, the contact resistance may be too high. Above about 10 nm, the silicide layer 118 may be short-circuited with the channel 22B.

[0103] After or during the formation of the silicide layer 118, the source / drain contacts 120 are formed by filling the openings above the source / drain regions 82 with, for example, a liner layer and a filling layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material that is or includes a conductive material such as Co, W, Ru, combinations thereof, and the like. In some embodiments, the source / drain contacts 120 are or include Co-based, W-based, or Ru-based compounds or alloys, including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, and the like. The source / drain contacts 120 are bonded on the silicide layer 118 and contact the ESL 131.

[0104] Additional processing may be performed to complete the fabrication of the device 10. For example, a gate contact (or gate via) may be formed to electrically couple to the gate structure 200. An interconnect structure may then be formed over the source / drain contacts 120 and the gate contact. The interconnect structure may include multiple dielectric layers (including, for example, a second ILD) surrounding metal features (including conductive traces and conductive vias) that form electrical connections between devices on the substrate 110 and to IC devices external to the IC device 10.

[0105] Embodiments may provide advantages. Replacing the interposer 24 in NFET devices, PFET devices, or both improves the strain in their channels 22. In NFET devices, the interposer 24 is replaced by a high Ge% interposer 24G that increases the tensile strain of the channel 22. The interposer 24G may be a pure or substantially pure germanium layer or other suitable material layer. In PFET devices, the interposer 24 may be replaced by a dielectric layer 24D that reduces tensile strain and / or increases compressive strain.

[0106] According to at least one embodiment, a method is provided, the method comprising: forming a stack including alternating first semiconductor channels and second semiconductor interposers on a substrate, the stack including a first sacrificial structure located between adjacent pairs of second semiconductor interposers, the first sacrificial structure including a third semiconductor layer having a different etch selectivity than the first semiconductor channels and the second semiconductor interposers, forming the stack including forming a source / drain opening. The method also comprises: replacing the third semiconductor layer with a first dielectric layer. The method also comprises: forming a first source / drain structure to a level below the first dielectric layer in a lower portion of the source / drain opening. The method also comprises: forming a second dielectric layer on the first source / drain structure. The method also comprises: increasing a tensile strain of one of the first semiconductor channels located above the second dielectric layer. The method also comprises: after increasing the tensile strain, forming a second source / drain structure located above the lower portion and adjacent to one of the first semiconductor channels in an upper portion of the source / drain opening.

[0107] According to at least one embodiment, a method is provided, the method comprising: forming a stack comprising alternating nanostructure channels and interposers on a substrate, the stack comprising a first sacrificial structure located between adjacent pairs of interposers, the first sacrificial structure comprising a third semiconductor layer having an etch selectivity different from the nanostructure channels and the interposers, forming the stack comprising forming a source / drain opening. The method also comprises: reducing the tensile strain of one of the nanostructure channels after forming the source / drain opening. The method also comprises: forming a first source / drain in the source / drain opening after reducing the tensile strain, the first source / drain adjacent to one of the nanostructure channels. The method also comprises: forming a first dielectric layer on the first source / drain. The method also comprises: forming a second source / drain in the source / drain opening and on the first dielectric layer.

[0108] According to at least one embodiment, a device is provided, the device comprising a first nanostructure stack. The device also comprises: a second nanostructure stack located above the first nanostructure stack and separated from the first nanostructure stack by a first dielectric layer. The device also comprises: a first internal spacer vertically positioned between two adjacent nanostructures of the first nanostructure stack. The device also comprises: a second internal spacer vertically positioned between two adjacent nanostructures of the second nanostructure stack, the second internal spacer having a height exceeding the height of the first internal spacer.

[0109] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack including alternating first semiconductor channels and second semiconductor interlayers on a substrate, the stack including a first sacrificial structure located between adjacent pairs of the second semiconductor interlayers, the first sacrificial structure including a third semiconductor layer having an etching selectivity different from that of the first semiconductor channels and the second semiconductor interlayers, the forming of the stack including forming a source / drain opening; replacing the third semiconductor layer with a first dielectric layer; forming a first source / drain structure in a lower portion of the source / drain opening to a level below the first dielectric layer; forming a second dielectric layer on the first source / drain structure; increasing the tensile strain of one of the first semiconductor channels located above the second dielectric layer; and after the increasing of the tensile strain, forming a second source / drain structure in an upper portion of the source / drain opening located above the lower portion and adjacent to the one of the first semiconductor channels.

[0110] In some embodiments, the increasing the tensile strain comprises replacing one of the second semiconductor interlayers with a replacement interlayer. In some embodiments, replacing one of the second semiconductor interlayers comprises replacing a silicon germanium interlayer with a substantially pure germanium interlayer having a germanium concentration exceeding about 99%. In some embodiments, replacing one of the second semiconductor interlayers comprises replacing a silicon germanium interlayer with a high concentration germanium interlayer having a germanium concentration exceeding about 80%. In some embodiments, replacing one of the second semiconductor interlayers comprises replacing a silicon germanium interlayer having a germanium concentration not exceeding about 40% with a silicon germanium interlayer having a germanium concentration exceeding about 50%. In some embodiments, replacing one of the second semiconductor interlayers with a replacement interlayer comprises: forming a first oxide layer on a side surface of the one of the first semiconductor channels, and forming a second oxide layer on a side surface of the one of the second semiconductor interlayers, the second oxide layer being porous; removing the one of the second semiconductor interlayers through the pores of the second oxide layer; and growing the replacement interlayer through the pores of the second oxide layer. In some embodiments, the method also includes: forming a second internal spacer adjacent to the replacement interposer in the upper portion of the source / drain opening; and before forming the second internal spacer, forming a first internal spacer adjacent to one of the second semiconductor interposers in the lower portion of the source / drain opening, the first internal spacer having a height exceeding the height of the second internal spacer.

[0111] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack including alternating nanostructure channels and interlayers on a substrate, the stack including a first sacrificial structure located between adjacent pairs of the interlayers, the first sacrificial structure including a third semiconductor layer having an etching selectivity different from that of the nanostructure channels and the interlayers, the forming of the stack including forming a source / drain opening; after the forming of the source / drain opening, reducing the tensile strain of one of the nanostructure channels; after the reducing of the tensile strain, forming a first source / drain in the source / drain opening, the first source / drain adjacent to the one of the nanostructure channels; forming a first dielectric layer on the first source / drain; and forming a second source / drain in the source / drain opening and on the first dielectric layer.

[0112] In some embodiments, the reducing the tensile strain comprises replacing one of the interposers with a replacement interposer. In some embodiments, replacing one of the interposers comprises replacing the one of the interposers with a dielectric interposer. In some embodiments, replacing the one of the interposers with a dielectric interposer comprises: forming an opening by removing the one of the interposers; forming the dielectric interposer in the opening; and forming a groove by recessing an end portion of the dielectric interposer. In some embodiments, the method further comprises forming an internal spacer in the groove. In some embodiments, the method further comprises: after the forming of the second source / drain, forming an opening by releasing the nanostructure channel by removing the dielectric interposer; and forming an active gate in the opening. In some embodiments, the method further comprises: after the forming of the first source / drain and before the forming of the second source / drain, increasing the tensile strain of one of the nanostructure channels above the first dielectric layer.

[0113] Still other embodiments of the present application provide a semiconductor device, comprising: a first nanostructure stack; a second nanostructure stack located above the first nanostructure stack and separated from the first nanostructure stack by a first dielectric layer; a first internal spacer vertically positioned between two adjacent nanostructures of the first nanostructure stack; and a second internal spacer vertically positioned between two adjacent nanostructures of the second nanostructure stack, the second internal spacer having a height exceeding the height of the first internal spacer.

[0114] In some embodiments, the semiconductor device further comprises: a third internal spacer vertically positioned above the uppermost nanostructure of the second nanostructure stack. In some embodiments, the thickness of the nanostructure of the first nanostructure stack exceeds the thickness of the nanostructure of the second nanostructure stack. In some embodiments, the semiconductor device further comprises: a fin mesa located below the first nanostructure stack, wherein the lattice constant of the first nanostructure directly above the fin mesa is greater than the lattice constant of the fin mesa. In some embodiments, the nanostructure of the second nanostructure stack has a lattice constant that exceeds the lattice constant of the nanostructure of the first nanostructure stack. In some embodiments, the height of the second internal spacer exceeds the height of the first internal spacer by about 0.5 nm to about 2 nm.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a stack comprising alternating first semiconductor channels and second semiconductor interposers on a substrate, the stack comprising a first sacrificial structure between adjacent pairs of the second semiconductor interposers, the first sacrificial structure comprising a third semiconductor layer having a different etch selectivity than the first semiconductor channels and the second semiconductor interposers, the forming the stack comprising forming source / drain openings; replacing the third semiconductor layer with the first dielectric layer; forming a first source / drain structure in a lower portion of the source / drain opening to a level below the first dielectric layer; forming a second dielectric layer on the first source / drain structure; increasing a tensile strain in one of the first semiconductor channels located above the second dielectric layer; as well as After said increasing the tensile strain, a second source / drain structure is formed in an upper portion of said source / drain opening over said lower portion and adjacent to said one of said first semiconductor channels.

2. The method according to claim 1, wherein: The increasing the tensile strain includes replacing one of the second semiconductor interposers with a replacement interposer.

3. The method according to claim 2, wherein: Replacing one of the second semiconductor interposers includes replacing the silicon germanium interposer with a substantially pure germanium interposer having a germanium concentration exceeding approximately 99%.

4. The method according to claim 2, wherein: Replacing one of the second semiconductor interposers includes replacing a silicon germanium interposer with a high concentration germanium interposer having a germanium concentration exceeding about 80%.

5. The method according to claim 2, wherein: Replacing one of the second semiconductor interposers includes replacing a silicon germanium interposer having a germanium concentration of no more than about 40% with a silicon germanium interposer having a germanium concentration of more than about 50%.

6. The method according to claim 2, wherein: Replacing one of the second semiconductor interposers with a replacement interposer includes: forming a first oxide layer on a side surface of the one of the first semiconductor channels, and forming a second oxide layer on a side surface of the one of the second semiconductor interposers, the second oxide layer being porous; removing the one of the second semiconductor interposers through the hole of the second oxide layer; and The replacement interposer is grown through the holes in the second oxide layer.

7. The method according to claim 2, further comprising: forming a second inner spacer in the upper portion of the source / drain opening adjacent to the replacement interposer; as well as Prior to the forming of the second inner spacer, a first inner spacer is formed in the lower portion of the source / drain openings adjacent to one of the second semiconductor interposers, the first inner spacer having a height exceeding a height of the second inner spacer.

8. A method of forming a semiconductor device, comprising: forming a stack comprising alternating nanostructure channels and interposers on a substrate, the stack comprising a first sacrificial structure located between adjacent pairs of the interposers, the first sacrificial structure comprising a third semiconductor layer having a different etch selectivity than the nanostructure channels and the interposers, the forming the stack comprising forming source / drain openings; After said forming source / drain openings, reducing a tensile strain in one of said nanostructure channels; After said reducing the tensile strain, forming a first source / drain in said source / drain opening, said first source / drain abutting said one of said nanostructure channels; forming a first dielectric layer on the first source / drain; as well as A second source / drain is formed in the source / drain opening and on the first dielectric layer.

9. The method according to claim 8, wherein: The reducing the tensile strain includes replacing one of the interposers with a replacement interposer.

10. A semiconductor device comprising: a first nanostructure stack; a second nanostructure stack, located above the first nanostructure stack and separated from the first nanostructure stack by a first dielectric layer; a first internal spacer vertically positioned between two adjacent nanostructures of the first nanostructure stack; as well as A second inner spacer is vertically positioned between two adjacent nanostructures of the second nanostructure stack, the second inner spacer having a height exceeding a height of the first inner spacer.

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