Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. An exemplary method according to the present disclosure includes forming a dielectric layer on a portion of a substrate, forming an aluminum-containing work function layer on the dielectric layer, where an aluminum concentration in a first portion of the aluminum-containing work function layer is different from an aluminum concentration in a second portion of the aluminum-containing work function layer, and forming a metal layer on the aluminum-containing work function layer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This reduction has also increased the complexity of processing and manufacturing ICs. Integrated circuits include various circuit device components, such as transistors. One characteristic of a transistor is its threshold voltage. As transistors become smaller, it is desirable to find ways to reduce the threshold voltage without adversely affecting other aspects of the transistor. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a dielectric layer on a portion of a substrate; forming an aluminum-containing work function layer on the dielectric layer, wherein an aluminum concentration in a first portion of the aluminum-containing work function layer is different from an aluminum concentration in a second portion of the aluminum-containing work function layer; and forming a metal layer on the aluminum-containing work function layer.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a plurality of nanostructures on a substrate; forming a source / drain component coupled to the plurality of nanostructures; and forming a gate structure surrounding and covering each of the plurality of nanostructures, wherein the gate structure comprises an aluminum-containing work function layer, the aluminum-containing work function layer having a bottom above the plurality of nanostructures and a top above the bottom, and an aluminum concentration in the top is higher than an aluminum concentration in the bottom.

[0006] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a substrate; a dielectric layer located on a portion of the substrate; an aluminum-containing work function layer disposed on the dielectric layer, wherein, within the aluminum-containing work function layer, the aluminum concentration increases from bottom to top; and a conductive layer disposed on the aluminum-containing work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered limiting in scope as the present disclosure may be equally well applied to other embodiments.

[0008] Figure 1 is a flow chart illustrating a method of forming a semiconductor structure according to various embodiments of the present disclosure.

[0009] Figure 2 The present invention shows various aspects of the present disclosure. Figure 1 A partial top view of an exemplary structure undergoing various stages of operation in a method.

[0010] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig.17A , Fig.18A and Fig.19A It is shown that according to various aspects of the present disclosure Figure 1 The various manufacturing stages of the method are along Figure 2 A partial cross-sectional view of the structure taken along line AA' is shown.

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Fig. 17B , Fig.18B and Fig.19B It is shown that according to various aspects of the present disclosure Figure 1 The various manufacturing stages of the method are along Figure 2 A partial cross-sectional view of the structure taken along line BB' is shown.

[0012] Figure 8 , Fig. 9 , Fig.11 , Fig.12 , Fig.14 and Fig.15 Various embodiments according to the present disclosure are shown. Figure 1 During the various manufacturing stages of the method Fig. 7A An enlarged view of a portion of the structure shown.

[0013] Fig.10 , Fig.13 and Fig.16 A graph corresponding to an exemplary ratio distribution of structural portions according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0016] In addition, when a number or a range of numbers is described using "about," "approximately," etc., the term is intended to include numbers within a reasonable range that takes into account variations inherent in the manufacturing process as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances for manufacturing features associated with the number, the number or range covers a reasonable range including the described number, such as within + / -10% of the described number. For example, a material layer with a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where a person of ordinary skill in the art knows that the manufacturing tolerance associated with the deposited material layer is + / -15%. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0017] The functional gate stack of the transistor includes a gate electrode on a gate dielectric layer. The gate electrode may include a work function layer formed by a conductive layer of a metal or metal alloy having an appropriate work function, so that the device performance of the corresponding transistor is enhanced (e.g., the threshold voltage is reduced). As described above, it is desirable to find a method for reducing the threshold voltage without adversely affecting other aspects of the transistor. One method for reducing the threshold voltage is to increase the thickness of the work function metal layer as part of the transistor gate stack. However, when producing smaller circuits, it becomes more difficult to increase the thickness of the work function metal layer. For an embodiment in which the transistor is an N-type transistor and the work function layer includes an aluminum-containing metal alloy layer, another method for reducing the threshold voltage is to increase the aluminum concentration (e.g., atomic percentage) in the aluminum-containing metal alloy layer. However, increasing the aluminum concentration may cause more aluminum atoms to diffuse into the gate dielectric layer, thereby increasing the gate leakage current. Aluminum atoms may also diffuse into the channel region (e.g., nanostructure) of the transistor, resulting in a reduction in carrier mobility.

[0018] The present disclosure relates to transistors with reduced threshold voltage and reduced gate leakage current and methods for forming the same. An N-type transistor according to an embodiment of the present disclosure includes a gate dielectric layer and a gate electrode on the gate dielectric layer. The work function layer of the gate electrode includes a metal alloy layer containing aluminum. In one embodiment, the aluminum concentration in the work function layer is uneven and increases from its bottom surface to its top surface along the thickness of the work function layer. In some embodiments, the work function layer includes titanium aluminum (TiAl), and the ratio of the aluminum concentration in the TiAl-based work function layer to the concentration of titanium in the TiAl-based work function layer has a gradient profile. The upper portion of the TiAl-based work function layer with a higher aluminum concentration can contribute to the modulation of the threshold voltage and the reduction of the deposition thickness of the TiAl-based work function layer. The lower portion of the TiAl-based work function layer with a lower aluminum concentration helps to reduce aluminum diffusion and improve gate leakage current and carrier mobility.

[0019] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart showing a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. Figure 2-19B Describing method 100, Figure 2-19BIt is a partial cross-sectional view or top view of the structure 200 at different manufacturing stages according to an embodiment of the method 100, or a chart corresponding to an exemplary ratio distribution of a portion of the structure. The method 100 is merely an example and is not intended to limit the present disclosure to the contents explicitly shown therein. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, all steps are not described in detail here. Because the structure 200 will be manufactured into a semiconductor structure 200 after the manufacturing process is completed, the structure 200 may be referred to as a semiconductor structure 200 as the context requires. For the avoidance of doubt, the X, Y, and Z directions shown are perpendicular to each other and are used consistently. In the present disclosure, unless otherwise specified, the same reference numerals represent the same features.

[0020] refer to Figure 1 , Figure 2 and Figure 3A-3B , the method 100 includes block 102 , where a structure 200 is received. Figure 3A Shown along Figure 2 A partial cross-sectional view of the structure 200 taken along the line AA′ shown in FIG. Figure 3B A partial cross-sectional view of the structure 100 taken along line BB' is shown. In the illustrated embodiment, the structure 200 includes a first device region 200A for forming an N-type device (e.g., an N-type all-around gate (GAA) transistor) and a second device region 200B for forming a P-type device (e.g., a P-type GAA transistor). The structure 200 includes a substrate 202 (e.g., Figure 3A-3B). In one embodiment, substrate 202 is a bulk silicon substrate (i.e., includes bulk single crystal silicon). In various embodiments, substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some alternative embodiments, substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator substrate, or a germanium-on-insulator substrate, and include a carrier, an insulator on the carrier, and a semiconductor layer on the insulator. Substrate 202 may include various doped regions configured according to the design requirements of semiconductor structure 200. P-type doped regions may include P-type dopants, such as boron, indium, other P-type dopants, or combinations thereof. N-type doped regions may include N-type dopants, such as phosphorus, arsenic, other N-type dopants, or combinations thereof. In some embodiments, substrate 202 includes doped regions formed by a combination of p-type dopants and n-type dopants. Various doped regions may be formed directly on and / or in the substrate 202, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form the various doped regions.

[0021] The structure 200 further includes a plurality of fin-shaped active regions (eg, fin-shaped active regions 205a, 205b) disposed on the substrate 202. In the present embodiment, the fin-shaped active region 205a is formed in the first device region 200A (eg, Figure 2 ), the fin-shaped active region 205b is formed in the second device region 200B of the structure 100. The fin-shaped active regions 205a, 205b may be individually or collectively referred to as fin-shaped active regions 205 or fin-shaped active regions 205. Each fin-shaped active region 205 extends longitudinally along the X direction and is divided into a channel region 205C and a source / drain region 205SD. The source / drain region may be individually or collectively referred to as a source region or a drain region, depending on the context.

[0022] The fin-shaped active region 205 may be formed from a top portion 202T of the substrate 202 and a vertical stack 207 of alternating semiconductor layers 206 and 208 (eg, Figure 3A-3B206). In the depicted embodiment, the vertical stack 207 of alternating semiconductor layers 206 and 208 includes a plurality of channel layers 208 interlaced with a plurality of sacrificial layers 206. Each channel layer 208 may include a semiconductor material, such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, other suitable semiconductor materials, or combinations thereof, while each sacrificial layer 206 has a different composition than the channel layer 208. In one embodiment, the channel layer 208 includes silicon (Si) and the sacrificial layer 206 includes silicon germanium (SiGe). The channel layer 208 and the sacrificial layer 206 may be epitaxially deposited on the substrate 202 using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth processes. In some examples, each fin-shaped active area 205 may include a total of three to ten pairs of alternating sacrificial layers 206 and channel layers 208; of course, other configurations may also be suitable depending on specific design requirements.

[0023] The structure 200 also includes an isolation feature 204 (eg, Figure 3B ) to isolate two adjacent fin-shaped active areas. The isolation feature 204 may also be referred to as a shallow trench isolation (STI) feature. In some embodiments, the STI feature 204 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0024] refer to Figure 2 and Figure 3B The structure 200 further includes a cladding layer 212 extending along the sidewall surface of the fin-shaped active region 205. In some embodiments, the cladding layer 212 may have substantially the same composition as the sacrificial layer 206 so that they can be selectively removed by a common etching process. In one embodiment, the cladding layer 212 is formed of SiGe.

[0025] Still refer to Figure 2 and Figure 3B The structure 200 further includes a hybrid fin 214 formed above the STI component 204 and between two adjacent fin-shaped active regions 205. The hybrid fin 214 is separated from the fin-shaped active region 205 by the cladding layer 212. In some embodiments, the hybrid fin 214 may be a single-layer structure. In some other embodiments, the hybrid fin 214 may include a multi-layer structure. For example, Figure 3BAs shown, the hybrid fin 214 includes a dielectric layer 214b embedded in the dielectric layer 214a. In other words, the dielectric layer 214a extends along the sidewalls and bottom surface of the dielectric layer 214b. The dielectric layer 214a may include silicon nitride, silicon carbon nitride (SiCN), silicon carbon nitride oxide (SiOCN), or other suitable materials. In an embodiment, the dielectric layer 214a is formed of silicon carbon nitride and the dielectric layer 214b is formed of silicon oxide. The hybrid fin 214 also includes a cap layer 214c formed on the dielectric layers 214a-214b. The cap layer 214c may be a high-K dielectric layer and may include silicon nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium oxide aluminum, hafnium oxide, other high-K materials or suitable dielectric materials. In some examples, the capping layer 214 c can be configured to separate the gate stack into a plurality of portions (eg, 240 and 242 ) alone or together with a gate cutting feature disposed on the hybrid fin 214 .

[0026] Still refer to Figure 2 and Figure 3A-3B , the structure 200 also includes dummy gate structures 216a and 216b formed on the channel region 205C of the fin-shaped active region 205. In some embodiments, the dummy gate structures 216a and 216b may share substantially the same composition and size. The channel region 205C and the dummy gate structures 216a and 216b also define source / drain regions 205SD, which do not overlap with the dummy gate structures 216a and 216a in the vertical direction. Each channel region 205C is disposed between two source / drain regions 205SD along the X direction. Figure 2 Two dummy gate structures 216a-216b are shown in the figure, but the structure 200 may include other numbers of dummy gate structures. In this embodiment, a gate replacement process (or a gate-last process) is adopted, in which the dummy gate structures 216a and 216b are used as placeholders for functional gate stacks (e.g., functional gate stacks 240 and / or 242). Other processes for forming functional gate stacks are also possible. In this embodiment, although not shown separately, each of the dummy gate structures 216a and 216b includes a dummy gate dielectric layer (e.g., silicon oxide) and a dummy gate electrode (e.g., polysilicon) disposed on the dummy gate dielectric layer. As discussed in detail below, the dummy gate structures 216a and 216b are configured to be replaced with corresponding functional gate stacks (e.g., functional gate stack 240).

[0027] Still refer to Figure 3A, the structure 200 also includes a gate spacer 218 extending along the sidewalls of the dummy gate structures 216a and 216b. In some embodiments, the gate spacer 218 may include silicon oxide, silicon oxycarbide, silicon oxynitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The gate spacer 218 may be a single-layer structure or a multi-layer structure. In addition, the structure 200 also includes an internal spacer component 219 disposed between two adjacent channel layers 208 and in direct contact with the sacrificial layer 206 in the channel region 205C. The internal spacer component 219 may include silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon carbide, silicon carbide, silicon oxynitride, other suitable materials, or combinations thereof.

[0028] Still refer to Figure 1 , Figure 2 and Figure 3A-3B , method 100 includes block 104, wherein source / drain features 220N and 220P are formed adjacent to channel region 205C, and a contact etch stop layer (CESL) 222 and an interlayer dielectric (ILD) layer 224 are formed on source / drain features 220N and 220P. Source / drain features 220N and 220P are formed in and / or over source / drain region 205SD and coupled to channel layer 208 in channel region 205C. In the present embodiment, source / drain feature 220N is an N-type source / drain feature formed in first device region 200A, and source / drain feature 220P is a P-type source / drain feature formed in second device region 200B. Exemplary n-type source / drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be doped in situ during the epitaxial process by introducing n-type dopants (e.g., phosphorus, arsenic, or antimony), or ex situ using a junction implantation process. Exemplary p-type source / drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be doped in situ during the epitaxial process by introducing p-type dopants (e.g., boron or gallium), or ex situ using a junction implantation process.

[0029] Still refer to Figure 3A , a contact etch stop layer (CESL) 222 and an interlayer dielectric (ILD) layer 224 are formed on the structure 200. The CESL 222 is configured to protect various underlying components during subsequent manufacturing processes, and may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. Figure 3AAs shown, CESL 222 may be formed on the top surface of source / drain features 220N and the sidewalls of gate spacers 218. After depositing CESL 222, an ILD layer 224 is deposited on structure 200 by a CVD process, a PECVD process, or other suitable deposition techniques. ILD layer 224 may include silicon oxide, low-k dielectric material, tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof. After depositing CESL 222 and ILD layer 224, one or more chemical mechanical planarization (CMP) processes may be performed to planarize the top surface of structure 200.

[0030] refer to Figure 1 and Figure 4A-4B , the method 100 includes a block 106, wherein the dummy gate structures 216a-216b are selectively removed to form a gate trench 226 on the channel region 205C. The dummy gate structures 216a-216b are selectively removed by an etching process. The etching process for removing the dummy gate structures 216a-216b may include any suitable process, such as a dry etching process, a wet etching process, or a combination thereof, and is configured to selectively remove the dummy gate structures 216a-216b without substantially etching the channel layer 208, the sacrificial layer 206, the gate spacers 218, the hybrid fins 214, the CESL 222, and the ILD layer 224.

[0031] refer to Figure 1 and Figure 5A-Figure 5B , the method 100 includes a block 108, wherein the sacrificial layer 206 is selectively removed to release the channel layer 208 as a channel member. After the dummy gate structures 216a-216b are selectively removed, one or more etching processes may be performed to selectively remove the capping layer 212 and the sacrificial layer 206 without substantially removing the channel layer 208 to release the channel layer 208 as a channel member. Since the composition of the capping layer 212 is the same as that of the sacrificial layer 206, the capping layer 212 may be removed together with the sacrificial layer 106. In one example, the etching process for removing the sacrificial layer 206 and the capping layer 212 may be a wet etching process that employs an oxidant, such as ammonium hydroxide (NH4OH), ozone (O3), nitric acid (HNO3), hydrogen peroxide (H2O2), other suitable oxidants, and a fluorine-based etchant, such as hydrofluoric acid (HF), ammonium fluoride (NH4F), other suitable etchants, or a combination thereof. Removing the cladding layer 212 forms a trench 228 between the stack of channel members 208 and the hybrid fin 214 , and removing the sacrificial layer 206 forms a gate opening 230 .

[0032] refer to Figure 1 and Figure 6A-6B, the method 100 includes a block 110, wherein a gate dielectric layer 232 is formed on the structure 200. In some embodiments, the gate dielectric layer 232 is a multi-layer structure including an interface layer 232a ( Figure 8 ) and the high-K dielectric layer 232b on the interface layer 232b ( Figure 8 ). In some embodiments, the interface layer 232a may be conformally deposited on the substrate 202, including in the gate trench 226, the trench 228, and the gate opening 230. In some other embodiments, the interface layer 232a may include silicon oxide and may be formed by thermal oxidation. A high-K dielectric layer 232b is then conformally deposited on the structure 200 by performing a deposition process (e.g., CVD, ALD) to have a substantially uniform thickness T0 on the top surface of the structure 200 (e.g., Figure 8 226 and 228 and the gate opening 230. For ease of describing a layer having a substantially uniform thickness over various regions, the term “conformal” may be used herein. The high-K dielectric layer 232 b may include a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of silicon oxide. Exemplary high-K dielectric materials include hafnium, zirconium, tantalum, titanium, oxygen, nitrogen, other suitable components, or combinations thereof. In some embodiments, the high-K dielectric layer 232 b may include a high-K dielectric material, including, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, TiO2, Ta2O5, other suitable high-K dielectric materials, or combinations thereof.

[0033] refer to Figure 1 , Figure 7A-7B , Figure 8 , Fig. 9 and Fig.10 , the method 100 includes block 112, where an aluminum-containing N-type work function layer 234 is conformally deposited on the gate dielectric layer 232. In one embodiment, the aluminum-containing N-type work function layer 234 is conformally deposited on the structure 200 to have a substantially uniform thickness T1 on the top surface of the structure 200, thereby partially filling the gate trench 226, the trench 228, and the gate opening 230. In some embodiments, the aluminum-containing N-type work function layer 234 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), or titanium aluminum nitride (TiAlN), or other suitable materials, and may be deposited using atomic layer deposition (ALD).

[0034] As described above, aluminum can diffuse around, including diffusing upward and downward. For embodiments in which the N-type work function layer includes aluminum, the aluminum in the aluminum-containing N-type work function layer may diffuse to the portion of the gate dielectric layer that is in direct contact with the aluminum-containing N-type work function layer, causing the gate dielectric layer to be contaminated, which may exacerbate the gate leakage current. Aluminum may even diffuse into the channel layer 208, resulting in reduced carrier mobility. In this embodiment, in order to reduce aluminum diffusion without sacrificing the ability of the aluminum-containing N-type work function layer to reduce the transistor threshold voltage Vt, the aluminum concentration (e.g., atomic percentage) in the aluminum-containing N-type work function layer 234 in the present disclosure is non-uniform from bottom to top. In some embodiments, the aluminum concentration in the aluminum-containing N-type work function layer 234 may be a function of the thickness T1 within the aluminum-containing N-type work function layer (e.g., from the bottom surface of the aluminum-containing N-type work function layer toward the top surface of the aluminum-containing N-type work function layer). In one embodiment, the aluminum concentration in the first portion of the aluminum-containing N-type work function layer 234 closer to the gate dielectric layer 232 is lower than the aluminum concentration in the second portion of the aluminum-containing N-type work function layer 234 farther from the gate dielectric layer 232. The concentration of aluminum in the first portion may be substantially uniform or gradient, and the content of aluminum in the second portion may be substantially uniform or gradient. The non-uniform concentration of aluminum in the aluminum-containing N-type work function layer 234 may be achieved by adjusting the flow rate ratio of the precursors. For example, in an embodiment in which the aluminum-containing N-type work function layer 234 is formed of titanium aluminum (TiAl), the flow rates of the Ti precursor (e.g., TiCl4) and the Al precursor (e.g., trimethylaluminum (TMA)) may be adjusted during the ALD process as the titanium aluminum layer is deposited to form an aluminum-containing N-type work function layer 234 having a non-uniform aluminum concentration. That is, the concentrations of aluminum and titanium in the aluminum-containing N-type work function layer 234 may be adjusted without introducing an additional photomask.

[0035] According to one embodiment of the present disclosure, Figure 8 , an enlarged view of a portion 200C of the structure 200 is shown in FIG. An aluminum-containing N-type work function layer 234 having a thickness T1 is disposed above and in direct contact with the gate dielectric layer 232. In one embodiment, the ratio of the thickness T1 of the aluminum-containing N-type work function layer 234 to the thickness T0 of the high-K dielectric layer 232b (i.e., T1 / T0) is in a range of about 1.5:1 to about 3.5:1. If the ratio of T1 to T0 is greater than 3.5:1, the space for forming subsequent layers of the gate stack may be too small, resulting in increased parasitic resistance and increased difficulty in gap filling. If the ratio of T1 to T0 is less than 1.5:1, the aluminum-containing N-type work function layer 234 may be too thin to contribute to the modulation of the threshold voltage Vt of the transistor.

[0036] In this embodiment, the aluminum concentration (e.g., atomic percentage) in the aluminum-containing N-type work function layer 234 gradually increases from bottom to top. That is, the aluminum concentration (e.g., atomic percentage) at the bottom surface 234s1 of the aluminum-containing N-type work function layer 234 is lower than the aluminum concentration (e.g., atomic percentage) at the top surface 234s2 of the aluminum-containing N-type work function layer 234. Figure 8 In the illustrated embodiment, the aluminum-containing N-type work function layer 234 has a first portion 234a and a second portion 234b located above the first portion. A first concentration of aluminum in the first portion 234a of the aluminum-containing N-type work function layer 234 closer to the gate dielectric layer 232 is lower than a second concentration of aluminum in the second portion 234b of the aluminum-containing N-type work function layer 234 farther from the gate dielectric layer 232. The first concentration of aluminum has a gradient profile, and the second concentration of aluminum also has a gradient profile. In other words, the aluminum concentration at the bottom surface 234s1 is the lowest aluminum concentration in the aluminum-containing N-type work function layer 234, and the aluminum content at the top surface 234s2 is the highest aluminum concentration in the aluminum-containing N-type work function layer 234. In some embodiments, the thickness (e.g., T2) of the first portion 234a of the aluminum-containing N-type work function layer 234 is substantially equal to the thickness T2 of the second portion 234b of the aluminum-containing N-type work function layer 234b. That is, each of the first portion 234 a and the second portion 234 b is half of the aluminum-containing N-type work function layer 234 .

[0037] In one embodiment, the aluminum-containing N-type work function layer 234 is formed of titanium aluminum (TiAl), and the ratio of the aluminum concentration (e.g., atomic percentage) in the aluminum-containing N-type work function layer 234 to the titanium concentration (e.g., atomic percentage) in the aluminum-containing N-type work function layer 234 (hereinafter referred to as "ratio R") has a gradient profile that gradually increases from the bottom surface 234s1 to the top surface 234s2 along the thickness T1. The gradient profile of the ratio R can be Fig.10, represented by the straight line 235a, curve 235b, or curve 235c shown in . That is, the ratio can increase linearly or nonlinearly from the ratio R0 to the ratio R1. R0 represents the ratio R at the bottom surface 234s1 of the aluminum-containing N-type work function layer 234, and R1 represents the ratio R at the top surface 234s2 of the aluminum-containing N-type work function layer 234. In one embodiment, the ratio R is in the range between about 0.4 and about 1. If the ratio R is less than 0.4, the aluminum-containing N-type work function layer 234 may not provide sufficient Vt modulation. If the ratio R is greater than 1, there may be too many aluminum atoms diffused. In one embodiment, the ratio R is in the range of about 0.4 to about 0.8, and the ratio of the thickness T1 to the thickness T0 is in the range of about 2.5:1 to about 3.5:1. In one embodiment, the ratio R in the first portion 234a can be in the range of about 0.4 to about 0.6, and the ratio R in the second portion 234b can be in the range of about 0.6 to about 0.8. By providing a graded ratio R profile, the number of aluminum atoms that may diffuse into the gate dielectric layer 232 and the channel layer 208 may be reduced, thereby providing reduced gate leakage current and improved carrier mobility.

[0038] exist Fig. 9 In another embodiment shown, Fig. 9 is an enlarged view of a portion 200C of a structure 200 according to another embodiment of the present disclosure. In order to alleviate the gap filling problem without sacrificing reduced gate leakage current and improved carrier mobility, the thickness of the aluminum-containing N-type work function layer 234 can be reduced from T1 to T1'. In one embodiment, the ratio of the thickness T1' to the thickness T0 of the high-K dielectric layer 232b is in a range between about 1:1.5 and about 1:2.5. In some embodiments, the ratio of the thickness T1' to the thickness T1 is in a range from about 0.7 to about 0.9. Reducing the thickness of the aluminum-containing N-type work function layer 234 can advantageously reduce the difficulty of depositing the aluminum-containing N-type work function layer without generating an air gap, thereby alleviating the gap filling problem. In the present embodiment, in order to compensate for the effect of the reduced thickness of the aluminum-containing N-type work function layer 234 on the threshold voltage Vt, the ratio R of the aluminum concentration to the titanium concentration in the aluminum-containing N-type work function layer 234 can be adjusted. For ease of description, Fig. 9The aluminum-containing N-type work function layer 234 in the illustrated embodiment is hereinafter referred to as the aluminum-containing N-type work function layer 234'. In this embodiment, the aluminum-containing N-type work function layer 234' has a first portion 234a' and a second portion 234b'. The ratio R of the aluminum-containing N-type work function layer 234' may be increased compared to the aluminum-containing N-type work function layer 234 having a ratio R in the range of about 0.4 to about 0.8. More specifically, in one embodiment, the ratio R in the aluminum-containing N-type work function layer 234' is in the range of about 0.5 to about 1. If the ratio R is less than 0.5, the threshold voltage Vt of the device may not be effectively reduced, resulting in higher power consumption; if the ratio R is greater than 1, excessive aluminum atoms may diffuse into the gate dielectric layer 232 and the channel layer 208, resulting in a decrease in device performance. The profile of the ratio R of the aluminum-containing N-type work function layer 234' may be similar in shape to Fig.10 The ratio R of the aluminum-containing N-type work function layer 234 is shown in FIG. 1 , and repeated description may be omitted. In one embodiment, the ratio R in the first portion 234a′ may be in the range of about 0.5 to about 0.75, and greater than Figure 8 The ratio R of the first portion 234a in the second portion 234b' may be in the range of about 0.75 to about 1 and is greater than the ratio R of the first portion 234a' and Figure 8 The ratio R in the second portion 234b of .

[0039] In reference Figure 8-Figure 10 In the above described embodiment, the ratio R gradually increases with the thickness T1 (or T1') from the bottom surface 234s1 to the top surface 234s2. Figure 11-13 and Figure 14-16 In other embodiments described, the ratio R can be increased in a stepwise manner, such as Fig.13 The curves 235d and Fig.16 As shown in curve 235e.

[0040] For example, refer to Fig.11 , the aluminum-containing N-type work function layer 234" in this embodiment has a first portion 234a" with a thickness of T3 and a second portion 234b" with a thickness of T4. The thickness T3 may be greater than, equal to, or less than the thickness T4. In one embodiment, the thickness T3 is equal to the thickness T4. The ratio R0' of the aluminum concentration (e.g., atomic percentage) in the first portion 234a" of the aluminum-containing N-type work function layer 234 to the titanium concentration (e.g., atomic percentage) in the aluminum-containing N-type work function layer 234a" is uniform (constant), and the ratio R1' of the aluminum concentration (e.g., atomic percentage) in the second portion 234b" of the aluminum-containing N-type work function layer 234" to the titanium concentration (e.g., atomic percentage) in the second portion 234b" of the aluminum-containing N-type work function layer 234" is also uniform (constant), and the ratio R1' is greater than the ratio R0'. As has been described with reference to Figure 8 The thickness relationship between thickness T0 and thickness T1 is described, and repeated description is omitted for simplicity. In one embodiment, for similar reasons as above, ratio R0' is in the range of about 0.4 to about 0.6, and ratio R1' is constant and in the range of about 0.6 to about 0.8.

[0041] Reference Fig.12 , the thickness T1 of the aluminum-containing N-type work function layer 234" is reduced to a thickness T1'. For ease of description, the aluminum-containing N-type work function layer 234" with the reduced thickness T1' is referred to as the aluminum-containing N-type work function layer 234"'. In this embodiment, the aluminum-containing N-type work function layer 234"' has a first portion 234a"' and a second portion 234b"'. Compared to the aluminum-containing N-type work function layer 234" having a ratio R in the range of about 0.4 to about 0.8, the ratio R of the aluminum-containing N-type work function layer 234"' can be increased. More specifically, in one embodiment, the ratio R in the aluminum-containing N-type work function layer 234'' is in the range of about 0.5 to about 1. If the ratio R is less than 0.5, the threshold voltage Vt of the device may not be effectively reduced, resulting in higher power consumption; if the ratio R is greater than 1, excessive aluminum atoms may diffuse into the gate dielectric layer 232 and the channel layer 208, resulting in degradation of device performance. The profile of the ratio R of the aluminum-containing N-type work function layer 234'' may be similar in shape to Fig.11 The ratio R of the aluminum-containing N-type work function layer 234"' is shown in FIG. 1 , and repeated description may be omitted. In one embodiment, the ratio R in the first portion 234a"' may be in the range of about 0.5 to about 0.75, and greater than Fig.11 The ratio R of the first portion 234a" and the ratio R of the second portion 234b"' may be in the range of about 0.75 to about 1 and greater than Fig.11 The ratio R of the first portion 234a" and the ratio R of the second portion 234b".

[0042] In reference Figure 11-13 In the above described embodiments, each of the aluminum-containing N-type work function layers 234" or 234"' has two sub-layers. In other embodiments, referring to Figure 14-15 , the aluminum-containing N-type work function layer 234 may have other numbers of sub-layers. Fig.14 The aluminum-containing N-type work function layer 234 in this embodiment (hereinafter referred to as "aluminum-containing N-type work function layer 234A") comprises sub-layers 2341, 2342, ... 234 n , where n is an integer and is greater than 2. Sublayers 2341, 2342, ... 234 nEach of the sublayers has a corresponding uniform (constant) ratio R, and the ratio R of the sublayer formed at a higher level is higher than the ratio R of the sublayer formed at a lower level. For example, sublayer 2342 is formed above sublayer 2341 and below sublayer 2343, and the ratio R of sublayer 2342 is greater than the ratio R (e.g., R0) of sublayer 2341 and less than the ratio R of sublayer 2343. n In the topmost sublayer 234 n The ratio R of the aluminum-containing N-type work function layer 234A is the highest (eg, R1). In an embodiment, the ratio R of the aluminum-containing N-type work function layer 234A is in the range of about 0.4 to about 0.8. n Each of the sub-layers 2341, 2342, ... 234 may have the same thickness or may have different thicknesses. n Have the same thickness. Figure 8 The thickness relationship between the thickness T0 and the thickness T1 is described, and repeated description is omitted for simplicity.

[0043] Reference Fig.15 , the thickness T1 of the aluminum-containing N-type work function layer 234A is reduced to a thickness T1'. For ease of description, the aluminum-containing N-type work function layer 234A having a reduced thickness T1' is referred to as an aluminum-containing N-type work function layer 234B. The aluminum-containing N-type work function layer 234B has a plurality of sublayers 234 i , 234 ii ,…234 m , where m is an integer greater than 2. Sublayer 234 i , 234 ii ,…234 m Each of the sublayers has a corresponding uniform (constant) ratio, and the ratio R of the sublayer formed at a higher level is higher than the ratio R of the sublayer formed at a lower level. ii formed on the sub-layer 234i and the sub-layer 234 iii Below, sublayer 234 ii The ratio R is greater than that of sublayer 234 i The ratio R (eg, R0) is smaller than that of the sublayer 234. iii The ratio R. In all multiple sub-layers 234 i , 234 ii ,…234 m In the top sublayer 234 m Has the highest ratio R. Sublayer 234 i , 234 ii ,…234 mEach of the sub-layers 234 may have the same thickness or may have different thicknesses. i , 234 ii ,…234 m The thickness relationship between thickness T0 and thickness T1' has been referred to Figure 8-Figure 9 In the embodiment, the ratio R of the aluminum-containing N-type work function layer 234B may be in the range of about 0.5 to about 1. The ratio R of the aluminum-containing N-type work function layer 234B may be similar in shape to Fig.15 An outline of the ratio R of the Al-containing N-type work function layer 234 is shown, and repeated description may be omitted.

[0044] The aluminum concentration (and ratio R) in the aluminum-containing N-type work function layer 234 may have other suitable profiles. For example, the lower portion of the aluminum-containing N-type work function layer 234 may have a gradient aluminum concentration profile, while the upper portion of the aluminum-containing N-type work function layer 234B may have a stepped aluminum concentration profile or a uniform aluminum concentration profile. As another example, the lower portion of the aluminum-containing N-type work function layer 234 may have a stepped aluminum concentration profile, while the upper portion of the aluminum-containing N-type work function layer 234B may have a gradient aluminum concentration profile.

[0045] In the above embodiment, an enlarged view of the portion 200C of the structure 200 is described. It should be understood that the profile of the ratio R and the profile of the aluminum concentration can be applied to other portions of the aluminum-containing N-type work function layer 234 in the structure 200 (e.g., Fig. 7A 200D, 200E). It is worth noting that, for an embodiment in which the structure 200 is manufactured to form a GAA transistor, a portion of the aluminum-containing N-type work function layer 234 is disposed below the channel layer 208 and the gate dielectric layer 232. As shown in portion 200E, a portion of the aluminum-containing N-type work function layer 234 disposed below the channel layer 208 that is closer to the gate dielectric layer 232 (e.g., an upper portion) has a lower aluminum concentration, while a portion of the aluminum-containing N-type work function layer 234 disposed below the channel layer 208 that is farther from the gate dielectric layer 232 (e.g., a lower portion) has a higher aluminum concentration.

[0046] refer to Figure 1 and Figure 17A-17B, the method 100 includes a block 114, in which a portion of the aluminum-containing N-type work function layer 234 formed in the second device region 200B is removed. In the present embodiment, in order to substantially prevent aluminum from diffusing in the second device region 200B associated with the aluminum-containing N-type work function layer 234, the portion of the aluminum-containing N-type work function layer 234 formed in the second device region 200B is removed. In an example process, a patterned mask layer (not shown) is formed on the structure 200 to cover the portion of the aluminum-containing N-type work function layer 234 in the first device region 200A, and the portion of the aluminum-containing N-type work function layer 234 formed in the second device region 200B is not covered by the patterned mask layer. The patterned mask layer may include a patterned bottom anti-reflective coating (BARC) layer, a patterned photoresist layer, a patterned hard mask layer, or a combination thereof. While using the patterned mask layer as an etching mask, an etching process is performed to selectively etch away a portion of the aluminum-containing N-type work function layer 234 in the second device region 200B. The etching process may be a dry etching process, a wet etching process, or a suitable etching process. After selectively removing a portion of the aluminum-containing N-type work function layer 234 from the second device region 200B, the patterned mask layer may be selectively removed using a suitable etching process.

[0047] refer to Figure 1 and Figure 18A-18B , the method 100 includes a block 116, wherein a P-type work function layer 236 is formed in the second device region 200B. In some embodiments, the P-type work function layer 236 may include TiN, TaN, Ru, Mo, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WCN, other P-type work function materials, or combinations thereof. In one embodiment, a TiN-based P-type work function layer 236 may also be formed in the first device region 200A and formed above the aluminum-containing N-type work function layer 234 to reduce the diffusion of aluminum in the aluminum-containing N-type work function layer 234 into the metal filling layer formed above the aluminum-containing N-type work function layer 234.

[0048] refer to Figure 1 and Figure 19A-19B, the method 100 includes a frame 118, in which one or more conductive layers 238 are formed on the substrate to complete the fabrication of the functional gate stack. In some embodiments of the present disclosure, one or more conductive layers 238 for devices in the first device region 200A and the second device region 200B can be formed simultaneously or in any order. In one embodiment, one or more conductive layers 238 may include a metal fill layer, such as tungsten (W). In various embodiments, a planarization process (e.g., a chemical mechanical polishing (CMP) process) may be performed to remove excess portions of material on the ILD layer, thereby ultimately completing the structure of the gate stack 240 or the gate stack 242. In one embodiment, the planarization process is stopped until the top surface of the cap layer 214c is exposed.

[0049] Reference Figure 1 , the method 100 includes a block 120 of performing further processing. Such further processing may include forming a silicide layer (not shown) on the source / drain feature 220N and forming a multi-layer interconnect (MLI) structure (not shown) on the structure 200. The MLI may include various interconnect features, such as vias and conductive lines, source / drain contacts, and gate contacts, disposed in dielectric layers, such as etch stop layers and ILD layers (e.g., ILD layer 224). In some embodiments, the vias are vertical interconnect features configured to interconnect device-level contacts, such as source / drain contacts formed on the source / drain feature 220N and gate contacts (not shown) formed on the gate stacks 240 and 242.

[0050] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and their formation. In some embodiments, the present disclosure provides a method for forming an N-type transistor with improved performance (e.g., reducing gate leakage current, enhancing carrier mobility) by providing an aluminum-containing work function layer with a non-uniform aluminum concentration from bottom to top. In some embodiments, the thickness of the aluminum-containing work function layer can be reduced to alleviate the difficulty of gap filling without adversely affecting the threshold voltage of the N-type transistor. Reducing the threshold voltage may also help reduce the threshold voltage variation between different N-type transistors (e.g., pull-down transistors and transfer gate transistors in static random access memory (SRAM) cells), thereby reducing the power consumption and minimum operating voltage Vccmin of the SRAM cell.

[0051] The present disclosure provides many different embodiments. Semiconductor structures and methods of manufacturing the same are disclosed herein. In one exemplary aspect, the present disclosure relates to a method of forming a semiconductor device. The method includes: forming a dielectric layer on a portion of a substrate; forming an aluminum-containing work function layer on the dielectric layer, wherein the aluminum concentration in a first portion of the aluminum-containing work function layer is different from the aluminum concentration in a second portion of the aluminum-containing work function layer; and forming a metal layer on the aluminum-containing work function layer.

[0052] In some embodiments, the ratio of the aluminum concentration in the aluminum-containing work function layer to the total concentration of other elements in the aluminum-containing work function layer has a gradually increasing gradient profile. In some embodiments, the ratio of the aluminum concentration in the aluminum-containing work function layer to the total concentration of other elements in the aluminum-containing work function layer has a step-like profile. In some embodiments, the aluminum-containing work function layer includes a first sublayer and a second sublayer located above the first sublayer, and the first ratio of the aluminum concentration in the first sublayer to the total concentration of other elements in the first sublayer is constant and lower than the second ratio of the aluminum concentration in the second sublayer to the total concentration of other elements in the second sublayer. In some embodiments, the first ratio is constant and is in the range of about 0.4 to about 0.6. In some embodiments, the second ratio is constant and is in the range of about 0.6 to about 0.8. In some embodiments, the thickness of the first sublayer is equal to the thickness of the second sublayer. In some embodiments, the aluminum-containing work function layer is an N-type work function layer and includes TiAl, TiAlC, TaAl, or TiAlN. In some embodiments, the aluminum-containing work function layer is formed of TiAl, and the ratio of the aluminum concentration in the aluminum-containing work function layer to the titanium concentration in the aluminum-containing work function layer is in the range of about 0.4 to about 1. In some embodiments, forming the aluminum-containing work function layer includes performing an atomic layer deposition (ALD) process with a first precursor and a second precursor, and changing a flow rate ratio between the first precursor and the second precursor when depositing the aluminum-containing work function layer during the ALD process.

[0053] In another exemplary aspect, the present disclosure relates to a method of forming a semiconductor device. The method includes: forming a plurality of nanostructures on a substrate; forming a source / drain component coupled to the plurality of nanostructures; and forming a gate structure surrounding and covering each of the plurality of nanostructures, wherein the gate structure includes an aluminum-containing work function layer, the aluminum-containing work function layer having a bottom portion above the plurality of nanostructures and a top portion above the bottom portion, and an aluminum concentration in the top portion is higher than an aluminum concentration in the bottom portion.

[0054] In some embodiments, the ratio of the aluminum concentration in the bottom portion to the total concentration of other elements in the bottom portion has a gradient profile. In some embodiments, the ratio of the aluminum concentration in the top portion to the total concentration of other elements in the top portion has a gradient profile. In some embodiments, the ratio of the aluminum concentration in the aluminum-containing work function layer to the total concentration of other elements in the aluminum-containing work function layer increases in a stepwise manner from the bottom surface of the bottom portion toward the top surface of the top portion. In some embodiments, the aluminum-containing work function layer comprises TiAl, and the ratio of the aluminum concentration in the aluminum-containing work function layer to the titanium concentration in the aluminum-containing work function layer is in a range of about 0.4 to about 1.

[0055] In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device includes: a substrate; a dielectric layer located on a portion of the substrate; an aluminum-containing work function layer disposed on the dielectric layer, wherein the aluminum concentration increases from the bottom to the top of the aluminum-containing work function layer; and a conductive layer disposed on the aluminum-containing work function layer.

[0056] In some embodiments, the semiconductor device may further include: a plurality of nanostructures located on a substrate, wherein the dielectric layer, the aluminum-containing work function layer, and the conductive layer are wrapped and disposed on the plurality of nanostructures. In some embodiments, the aluminum-containing work function layer is an N-type work function layer and includes TiAl, TiAlC, TaAl, or TiAlN. In some embodiments, the ratio of the aluminum concentration in the aluminum-containing work function layer to the total concentration of other elements is in the range of about 0.4 to about 1. In some embodiments, the ratio increases in a stepwise manner.

[0057] The features of several embodiments have been outlined above so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should understand that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. For example, by implementing different thicknesses for the bit line conductors and the word line conductors, different resistances of the conductors may be achieved. However, other techniques may also be used to change the resistance of the metal conductors.

Claims

1. A method for forming a semiconductor device, comprising: forming a dielectric layer on a portion of the substrate; forming an aluminum-containing work function layer on the dielectric layer, wherein a concentration of aluminum in a first portion of the aluminum-containing work function layer is different from a concentration of aluminum in a second portion of the aluminum-containing work function layer; and A metal layer is formed on the aluminum-containing work function layer.

2. The method according to claim 1, wherein: A ratio of an aluminum concentration in the aluminum-containing work function layer to a total concentration of other elements in the aluminum-containing work function layer has a gradually increasing gradient profile.

3. The method according to claim 1, wherein: A ratio of an aluminum concentration in the aluminum-containing work function layer to a total concentration of other elements in the aluminum-containing work function layer has a step-shaped profile.

4. The method according to claim 3, wherein: The aluminum-containing work function layer includes a first sublayer and a second sublayer located above the first sublayer, and a first ratio of the aluminum concentration in the first sublayer to the total concentration of other elements in the first sublayer is constant and lower than a second ratio of the aluminum concentration in the second sublayer to the total concentration of other elements in the second sublayer.

5. The method according to claim 8, wherein: The aluminum-containing work function layer is formed of TiAl, and a ratio of an aluminum concentration in the aluminum-containing work function layer to a titanium concentration in the aluminum-containing work function layer is in a range of about 0.4 to about 1.

6. The method according to claim 1, wherein: The forming of the aluminum-containing work function layer includes performing an atomic layer deposition (ALD) process using a first precursor and a second precursor, and changing a flow rate ratio between the first precursor and the second precursor when depositing the aluminum-containing work function layer during the ALD process.

7. A method of forming a semiconductor device, comprising: forming a plurality of nanostructures on a substrate; forming a source / drain feature coupled to the plurality of nanostructures; as well as forming a gate structure surrounding and covering each of the plurality of nanostructures, The gate structure includes an aluminum work function layer, wherein the aluminum work function layer has a bottom portion above the plurality of nanostructures and a top portion above the bottom portion, and an aluminum concentration in the top portion is higher than an aluminum concentration in the bottom portion.

8. The method according to claim 11, wherein: A ratio of an aluminum concentration in the aluminum-containing work function layer to a total concentration of other elements in the aluminum-containing work function layer increases in a stepwise manner from a bottom surface of the bottom portion toward a top surface of the top portion.

9. A semiconductor device comprising: substrate; a dielectric layer disposed on a portion of the substrate; an aluminum-containing work function layer disposed on the dielectric layer, wherein within the aluminum-containing work function layer, the aluminum concentration increases from the bottom to the top; and The conductive layer is disposed on the aluminum-containing work function layer.

10. The semiconductor device according to claim 9, further comprising: a plurality of nanostructures disposed on the substrate, Wherein, the dielectric layer, the aluminum-containing work function layer and the conductive layer are wrapped and arranged on the multiple nanostructures.

Images