Fabrication process of common-drain double mosfet device and common-drain double mosfet device

Abstract

The application provides a preparation process of a common-drain double MOSFET device and the common-drain double MOSFET device. The symmetric structure is formed on the front surface and the back surface of a wafer, the problems existing in the prior art are solved, and the common-drain double MOSFET wafer with excellent performance, smaller area and stronger packaging performance is produced.

Description

Technical Field

[0001] The embodiments of this application belong to the field of semiconductor technology, and particularly relate to the fabrication process of common-drain dual-MOSFET devices and common-drain dual-MOSFET devices. Background Technology

[0002] In the semiconductor field, MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) wafers are fundamental components of electronic devices, and their performance and manufacturing processes play a crucial role in the development of electronic equipment. Common-drain dual-MOSFET wafers have unique applications in circuits, often used in scenarios such as input / output protection. However, there is currently no perfect and efficient process flow specifically for common-drain dual-MOSFET wafers.

[0003] Existing wafer manufacturing processes are typically general-purpose and cannot adequately meet the specific requirements of common-drain dual-MOSFET wafers. For example, traditional processes lack targeted steps and optimizations for fabricating MOSFETs on the front and back sides of the wafer, resulting in wafers with shortcomings in performance, area, and packageability. Furthermore, traditional processes do not fully consider the characteristics of common-drain dual-MOSFET wafers in terms of material selection, equipment usage, and parameter control, preventing the final product from achieving the desired results.

[0004] These circumstances indicate an urgent need to create a new process flow specifically for common-drain dual MOSFET wafers to improve their performance and production efficiency, and to meet the growing market demand. Summary of the Invention

[0005] To overcome the shortcomings of existing common-drain dual-MOSFET wafer fabrication processes, embodiments of this application provide a fabrication process for a common-drain dual-MOSFET device and a common-drain dual-MOSFET device.

[0006] In a first aspect, embodiments of this application provide a fabrication process for a common-drain dual-MOSFET device, including:

[0007] Photolithography is performed on the front side of the wafer to obtain multiple first trenches disposed on the front side of the wafer;

[0008] Photolithography is performed on the back side of the wafer to obtain a plurality of second trenches disposed on the back side of the wafer, and the second trenches are disposed in a one-to-one correspondence with the first trenches;

[0009] Sacrificial oxide layers are grown on the front and back sides of the wafer, and then the sacrificial oxide layers are etched away.

[0010] A gate oxide layer is grown in the first trench and the second trench;

[0011] Deposit gate polysilicon in the first trench and the second trench;

[0012] A well region and an implantation region are formed on the front and back sides of the wafer, respectively. The implantation region on the front side of the wafer is disposed in the well region on the front side of the wafer. A portion of the first trenches only penetrates the well region on the front side of the wafer, while another portion of the first trenches sequentially penetrates both the implantation region and the well region on the front side of the wafer. The implantation region on the back side of the wafer is disposed in the well region on the back side of the wafer. A portion of the second trenches only penetrates the well region on the back side of the wafer, while another portion of the second trenches sequentially penetrates both the implantation region and the well region on the back side of the wafer. The well regions on the front side and the well regions on the back side of the wafer are positioned correspondingly, and the implantation regions on the front side and the implantation regions on the back side of the wafer are positioned correspondingly.

[0013] Dielectric layers are deposited on the front and back sides of the wafer;

[0014] A first contact hole and a second contact hole are respectively provided in a portion of the first trench on the front side of the wafer and a portion of the second trench on the back side of the wafer. A third contact hole is provided between another portion of the first trenches. The third contact hole extends through the dielectric layer and the implantation area on the front side of the wafer to the well area on the front side of the wafer. A fourth contact hole is provided between another portion of the second trenches. The fourth contact hole extends through the dielectric layer and the implantation area on the back side of the wafer to the well area on the back side of the wafer.

[0015] The first contact hole, the second contact hole, the third contact hole, and the fourth contact hole are all filled with conductive metal;

[0016] A first metal layer, a second metal layer, a third metal layer, and a fourth metal layer are deposited on the upper surfaces of the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole, respectively. The first metal layer and the third metal layer are spaced apart, and the second metal layer and the fourth metal layer are spaced apart.

[0017] In a preferred embodiment of this application, the wafer includes a substrate and a first epitaxial layer disposed on the front side of the substrate and a second epitaxial layer disposed on the back side of the substrate.

[0018] In a preferred embodiment of this application, the substrate, the first epitaxial layer, and the second epitaxial layer have the same doping type, and both are of the first doping type.

[0019] In a preferred embodiment of this application, the well regions on the front and back sides of the wafer are both of the second doping type, and the implantation regions on the front and back sides of the wafer are both of the first doping type.

[0020] Secondly, embodiments of this application also provide a common-drain dual MOSFET device, characterized in that it is fabricated using the process described in any one of the first aspects.

[0021] Compared with the prior art, the embodiments of this application provide a fabrication process for a common-drain dual-MOSFET device and a common-drain dual-MOSFET device, which solves the problems existing in the prior art and produces a common-drain dual-MOSFET wafer with excellent performance, smaller area and stronger packageability. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0023] Figure 1 The structural diagram obtained in step S01;

[0024] Figure 2 The structural diagram obtained in step S02;

[0025] Figure 3 The structural diagram obtained in step S04;

[0026] Figure 4 The structural diagram obtained in step S05;

[0027] Figure 5 The structural diagram obtained in step S06;

[0028] Figure 6 The structural diagram obtained in step S07;

[0029] Figure 7 The structural diagram obtained in step S08;

[0030] Figure 8 The structural diagram obtained in step S09;

[0031] Figure 9 This is the structural diagram obtained in step S10. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0033] This application provides a fabrication process for a common-drain dual-MOSFET device, including the following steps:

[0034] Step S01: Photolithography is performed on the front side of the wafer to obtain a plurality of first trenches disposed on the front side of the wafer;

[0035] like Figure 1 As shown, multiple spaced first trenches are now photolithographically etched on the front side of the wafer. These first trenches have the same depth, and the width of some first trenches 04 is greater than the width of others. The photolithography process is well-known to those skilled in the art and will not be described in detail here. Furthermore, it should be noted that the wafer includes a substrate 01, a first epitaxial layer 02 disposed on the front side of the substrate 01, and a second epitaxial layer 03 disposed on the back side of the substrate 01. Specifically, the substrate 01, the first epitaxial layer 02, and the second epitaxial layer 03 have the same doping type, and are all of the first doping type. In this embodiment, the first doping type is N-type. To fabricate a common-drain dual MOSFET device, in this embodiment, the first epitaxial layer 02 and the second epitaxial layer 03 have the same thickness.

[0036] Step S02: Photolithography is performed on the back side of the wafer to obtain a plurality of second trenches disposed on the back side of the wafer, and the second trenches are disposed in a one-to-one correspondence with the first trenches;

[0037] like Figure 2 As shown, the process is the same as in step S01. Multiple second trenches are photolithographically formed on the back side of the wafer. The depth of the multiple second trenches is the same, and the width of some second trenches 06 is greater than the width of other second trenches 07.

[0038] Step S03: A sacrificial oxide layer is grown on the front and back sides of the wafer, and then the sacrificial oxide layer is etched away.

[0039] It should be noted that by producing sacrificial oxide layers on both the front and back sides of the wafer, the wafer surface can be made smoother.

[0040] Step S04: Growing a gate oxide layer in the first trench and the second trench;

[0041] like Figure 3As shown, a gate oxide layer 08 is grown in the first and second trenches by precisely controlling the oxidation atmosphere, temperature and time.

[0042] Step S05: Deposit gate polysilicon in the first trench and the second trench;

[0043] like Figure 4 As shown, gate polysilicon 09 is deposited in the first and second trenches to serve as the gate for the entire device. The specific deposition process is well known to those skilled in the art and will not be described in detail here.

[0044] Step S06: A well region 10 and an implantation region 11 are formed on the front and back sides of the wafer, respectively. The implantation region 11 on the front side of the wafer is disposed in the well region 10 on the front side of the wafer. A portion of the first trench 04 penetrates only the well region 10 on the front side of the wafer, while another portion of the first trench 05 sequentially penetrates both the implantation region 11 and the well region 10 on the front side of the wafer. The implantation region 13 on the back side of the wafer is disposed in the well region 12 on the back side of the wafer. A portion of the second trench 06 penetrates only the well region 12 on the back side of the wafer. The second trench on the back side of the wafer sequentially penetrates the implantation region 13 and the well region 12 on the back side of the wafer. The well region 10 on the front side of the wafer and the well region 12 on the back side of the wafer are positioned correspondingly, as are the implantation region 11 on the front side of the wafer and the implantation region 13 on the back side of the wafer. Both the well region 10 on the front side of the wafer and the well region 12 on the back side of the wafer are of the second doping type, while both the implantation region on the front side of the wafer and the implantation region 13 on the back side of the wafer are of the first doping type. Specifically, the second doping type is P-type, and the first doping type is N-type.

[0045] like Figure 5 As shown, the source region of the entire device is prepared in step S06 by symmetrically setting the well region and implantation region on the front and back sides of the wafer. The well region and implantation region are formed by ion implantation process. Ion implantation process is a process well known to those skilled in the art and will not be described in detail here. It should be noted that the ion implantation process conditions for the well region and implantation region obtained by ion implantation process on the front and back sides of the wafer are the same.

[0046] Step S07: Deposit dielectric layers on the front and back sides of the wafer;

[0047] like Figure 6 As shown, dielectric layers 14 and 15 are provided on the front and back sides of the wafer, and the dielectric layers serve to protect the wafer.

[0048] In step S08, a first contact hole 16 and a second contact hole 18 are respectively provided in a portion of the first trench 04 on the front side of the wafer and a portion of the second trench 06 on the back side of the wafer. A third contact hole 17 is provided between another portion of the first trench 05. The third contact hole 17 extends through the dielectric layer 14 and the implantation region 11 on the front side of the wafer to the well region 10 on the front side of the wafer. A fourth contact hole 19 is provided between another portion of the second trench 07. The fourth contact hole 19 extends through the dielectric layer 15 and the implantation region 13 on the back side of the wafer to the well region 12 on the back side of the wafer.

[0049] like Figure 7 As shown, contact holes are required to bring out the gate and source of the entire device. Since the device fabricated in this application is a common-drain device, the drain does not need to be brought out. In this application, the first contact hole 16 and the second contact hole 18 are for bringing out the gate, and the third contact hole 17 and the fourth contact hole 19 are for bringing out the source.

[0050] Step S09: Fill the first contact hole 16, the second contact hole 18, the third contact hole 17 and the fourth contact hole 19 with conductive metal.

[0051] like Figure 8 As shown, conductive metal 20, conductive metal 21, conductive metal 22 and conductive metal 23 need to be filled in the first contact hole 16, the second contact hole 18, the third contact hole 17 and the fourth contact hole 19 respectively in order to lead out the corresponding electrodes. In this application, the conductive metal is copper.

[0052] Step S10: A first metal layer 24, a second metal layer 26, a third metal layer 25, and a fourth metal layer 27 are deposited on the upper surfaces of the first contact hole 16, the second contact hole 18, the third contact hole 17, and the fourth contact hole 19, respectively. The first metal layer 24 and the third metal layer 25 are spaced apart, and the second metal layer 26 and the fourth metal layer 27 are spaced apart.

[0053] like Figure 9 As shown, the gate is led out through the first metal layer 24 and the second metal layer 26, and the source is led out through the third metal layer 25 and the fourth metal layer 27.

[0054] The common-drain dual MOSFET device fabrication process provided in this application effectively avoids the increased resistance between the source and source caused by excessive wafer thickness, as well as the excessive process stress and risk of wafer cracking caused by excessive wafer thickness, by precisely controlling the wafer thickness between 150um and 300um, thus significantly improving the wafer yield and reliability.

[0055] Finally, it should be noted that the above embodiments are only examples of the technical solutions provided in the embodiments of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions in the embodiments of this application.

Claims

1. A process for fabricating a common-drain dual MOSFET device, characterized by, The method comprises the following steps: photolithography is performed on the front surface of the wafer to form a plurality of first grooves on the front surface of the wafer; photolithography is performed on the back surface of the wafer to form a plurality of second grooves on the back surface of the wafer, and the second grooves are arranged one by one corresponding to the first grooves; a sacrificial oxide layer is grown on the front and back surfaces of the wafer, and then the sacrificial oxide layer is etched and removed; a gate oxide layer is grown in the first grooves and the second grooves; gate polysilicon is deposited in the first grooves and the second grooves; a well region and an injection region are formed on the front and back surfaces of the wafer respectively, the injection region on the front surface of the wafer is arranged in the well region on the front surface of the wafer, part of the first grooves only penetrates the well region on the front surface of the wafer, and the other part of the first grooves penetrates the injection region on the front surface of the wafer and the well region on the front surface of the wafer in sequence; the injection region on the back surface of the wafer is arranged in the well region on the back surface of the wafer, part of the second grooves only penetrates the well region on the back surface of the wafer, and the other part of the second grooves penetrates the injection region on the back surface of the wafer and the well region on the back surface of the wafer in sequence; and the well region on the front surface of the wafer and the well region on the back surface of the wafer are arranged in position corresponding to each other, and the injection region on the front surface of the wafer and the injection region on the back surface of the wafer are arranged in position corresponding to each other; a dielectric layer is deposited on the front and back surfaces of the wafer; a first contact hole and a second contact hole are arranged in part of the first grooves on the front surface of the wafer and part of the second grooves on the back surface of the wafer respectively, a third contact hole is arranged between the other part of the first grooves, the third contact hole extends to the well region on the front surface of the wafer through the dielectric layer and the injection region on the front surface of the wafer, and a fourth contact hole is arranged between the other part of the second grooves, the fourth contact hole extends to the well region on the back surface of the wafer through the dielectric layer and the injection region on the back surface of the wafer; a conductive metal is filled in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole; a first metal layer, a second metal layer, a third metal layer and a fourth metal layer are deposited on the top surfaces of the first contact hole, the second contact hole, the third contact hole and the fourth contact hole respectively, the first metal layer and the third metal layer are arranged at intervals, and the second metal layer and the fourth metal layer are arranged at intervals.

2. The process for fabricating a common-drain double MOSFET device as claimed in claim 1, wherein, The wafer comprises a substrate, a first epitaxial layer arranged on the front surface of the substrate, and a second epitaxial layer arranged on the back surface of the substrate.

3. The process for fabricating a common-drain double MOSFET device as claimed in claim 2, wherein, The substrate, the first epitaxial layer and the second epitaxial layer have the same doping type, which is a first doping type.

4. The process for fabricating a common-drain double MOSFET device as claimed in claim 1, wherein, The well region on the front surface of the wafer and the well region on the back surface of the wafer are of a second doping type, and the injection region on the front surface of the wafer and the injection region on the back surface of the wafer are of the first doping type.

5. A common-drain double MOSFET device, characterized by, The wafer is prepared by the process according to any one of claims 1 to 4.

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