Transistor and manufacturing method thereof

Abstract

The invention provides a transistor and a manufacturing method thereof, and belongs to the field of semiconductor devices. The transistor comprises a buffer layer, a high-resistance superlattice layer, a channel layer and a barrier layer, wherein the high-resistance superlattice layer, the channel layer and the barrier layer are sequentially stacked on the buffer layer; the buffer layer is an oxygen-doped AlN buffer layer, the high-resistance superlattice layer comprises a superlattice structure formed by a first GaN sub-layer and a second GaN sub-layer, the first GaN sub-layer is a carbon-doped GaN sub-layer, and the second GaN sub-layer is a non-carbon-doped GaN sub-layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor and a method for manufacturing the same. Background Art

[0002] Gallium nitride on silicon is widely used in semiconductors, such as transistors.

[0003] The related art provides a silicon-based gallium nitride transistor, which mainly includes a buffer layer, a channel layer and a barrier layer.

[0004] Among them, the buffer layer is an oxygen-doped AlN layer. The oxygen ions in the buffer layer will diffuse into the channel layer, thereby generating electrons at the interface and forming a leakage channel, which in turn affects the reliability of the transistor. Summary of the Invention

[0005] The embodiments of the present disclosure provide a transistor and a method for manufacturing the same, which can improve the reliability of the transistor. The technical solution is as follows:

[0006] In one aspect, a transistor is provided, comprising:

[0007] A buffer layer, a high-resistance superlattice layer, a channel layer and a barrier layer, wherein the high-resistance superlattice layer, the channel layer and the barrier layer are sequentially stacked on the buffer layer;

[0008] The buffer layer is an oxygen-doped AlN buffer layer, and the high-resistance superlattice layer includes a superlattice structure consisting of a first GaN sublayer and a second GaN sublayer. The first GaN sublayer is a carbon-doped GaN sublayer, and the second GaN sublayer is a non-carbon-doped GaN sublayer.

[0009] Optionally, the thickness of the second GaN sublayer is greater than the thickness of the first GaN sublayer.

[0010] Optionally, the thickness of the first GaN sublayer is 40-80 nm, and the thickness of the second GaN sublayer is 60-100 nm.

[0011] Optionally, along the direction from the buffer layer to the channel layer, the carbon doping concentration in each of the first GaN sub-layers in the high-resistance superlattice layer gradually decreases.

[0012] Optionally, the carbon doping concentration in the first GaN sublayer closest to the buffer layer in the high-resistance superlattice layer is 10 19 ~10 21 cm -3 .

[0013] Optionally, the high-resistance superlattice layer includes a superlattice structure with 15 to 40 periods.

[0014] Optionally, the oxygen doping concentration in the buffer layer is 10 18 ~10 23 cm -3 .

[0015] In another aspect, a method for manufacturing a transistor is provided, the method comprising:

[0016] fabricating a buffer layer, wherein the buffer layer is an oxygen-doped AlN buffer layer;

[0017] A high-resistance superlattice layer, a channel layer and a barrier layer are sequentially fabricated on the buffer layer. The high-resistance superlattice layer includes a superlattice structure consisting of a first GaN sublayer and a second GaN sublayer. The first GaN sublayer is a carbon-doped GaN sublayer, and the second GaN sublayer is a non-carbon-doped GaN sublayer.

[0018] Optionally, manufacturing the high-resistance superlattice layer includes:

[0019] Growing the first GaN sublayer on the buffer layer at a growth temperature of 900-1000° C. and a growth pressure of 50-150 Torr;

[0020] Growing the second GaN sublayer on the first GaN sublayer at a growth temperature of 950-1050° C. and a growth pressure of 50-150 Torr;

[0021] The above growth process is repeated for 15 to 40 cycles to obtain the high-resistance superlattice layer.

[0022] Optionally, the thickness of the second GaN sublayer is greater than the thickness of the first GaN sublayer.

[0023] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:

[0024] In an embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer; the transistor also includes a buffer layer and a high-resistance superlattice layer, the buffer layer is an oxygen-doped AlN buffer layer, and the high-resistance superlattice layer includes a first GaN sublayer and a second GaN sublayer, wherein the first GaN sublayer is a carbon-doped GaN sublayer, which can capture electrons generated by oxygen ions diffused from the buffer layer to the high-resistance superlattice layer, avoid the formation of leakage channels, improve reliability, and improve the voltage resistance performance of the transistor; the second GaN sublayer is a non-carbon-doped GaN sublayer, which can improve the tendency of the first GaN sublayer to deteriorate in crystal quality due to carbon doping, and improve the crystal quality of the subsequently grown channel layer. The first GaN sublayer and the second GaN sublayer form a superlattice layer, which can release stress and is conducive to improving the crystal quality of epitaxy. In summary, the high-resistance superlattice layer can improve reliability, improve the voltage resistance performance of the transistor, release stress, and is conducive to improving the crystal quality of the transistor epitaxy. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 is a schematic structural diagram of a transistor provided by an embodiment of the present disclosure;

[0027] Figure 2 is a schematic structural diagram of another transistor provided by an embodiment of the present disclosure;

[0028] Figure 3 is a flow chart of a method for manufacturing a transistor provided by an embodiment of the present disclosure;

[0029] Figure 4 This is a flow chart of another method for manufacturing a transistor provided in an embodiment of the present disclosure.

[0030] Reference numerals

[0031] 101: buffer layer; 102: high-resistance superlattice layer; 121: first GaN sublayer; 122: second GaN sublayer; 103: channel layer; 104: barrier layer; 105: substrate; 106: passivation layer; 107: gate; 108: source; 109: drain. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0033] Figure 1 A schematic diagram of the structure of a transistor provided by an embodiment of the present disclosure. Figure 1 The transistor includes: a buffer layer 101, a high-resistance superlattice layer 102, a channel layer 103 and a barrier layer 104, wherein the high-resistance superlattice layer 102, the channel layer 103 and the barrier layer 104 are sequentially stacked on the buffer layer 101.

[0034] The buffer layer 101 is an oxygen-doped AlN buffer layer, and the high-resistance superlattice layer 102 includes a superlattice structure composed of a first GaN sublayer 121 and a second GaN sublayer 122 (it should be noted that the number of the first GaN sublayer 121 and the second GaN sublayer 122 in the figure is not limited to the embodiment of the present disclosure, but is only for illustrating the superlattice structure). The first GaN sublayer 121 is a carbon-doped GaN sublayer, and the second GaN sublayer 122 is a non-carbon-doped GaN sublayer.

[0035] In an embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer; the transistor also includes a buffer layer and a high-resistance superlattice layer, the buffer layer is an oxygen-doped AlN buffer layer, and the high-resistance superlattice layer includes a first GaN sublayer and a second GaN sublayer, wherein the first GaN sublayer is a carbon-doped GaN sublayer, which can capture electrons generated by oxygen ions diffused from the buffer layer to the high-resistance superlattice layer, avoid the formation of leakage channels, improve reliability, and improve the voltage resistance performance of the transistor; the second GaN sublayer is a non-carbon-doped GaN sublayer, which can improve the tendency of the first GaN sublayer to deteriorate in crystal quality due to carbon doping, and improve the crystal quality of the subsequently grown channel layer. The first GaN sublayer and the second GaN sublayer form a superlattice layer, which can release stress and is conducive to improving the crystal quality of epitaxy. In summary, the high-resistance superlattice layer can improve reliability, improve the voltage resistance performance of the transistor, release stress, and is conducive to improving the crystal quality of the transistor epitaxy.

[0036] In the embodiment of the present disclosure, the thickness of the second GaN sub-layer 122 is greater than the thickness of the first GaN sub-layer 121 .

[0037] In this implementation, the thickness of the carbon-doped GaN sublayer in each period of the high-resistance superlattice layer is greater than the thickness of the non-carbon-doped GaN sublayer, which can ensure that after the carbon-doped GaN sublayer is doped and captured with oxygen ions, the quality of the epitaxial crystal can be improved by the non-carbon-doped GaN sublayer with a thicker thickness.

[0038] In a possible implementation of the embodiment of the present disclosure, the thickness of the first GaN sublayer in each period is the same, and / or the thickness of the second GaN sublayer in each period is the same.

[0039] Illustratively, the thickness of the first GaN sublayer 121 is 40-80 nm, and the thickness of the second GaN sublayer 122 is 60-100 nm.

[0040] In this implementation, the use of a first GaN sublayer of 40 to 80 nm can fully utilize the role of the carbon-doped GaN sublayer in capturing oxygen ions, thereby reducing leakage and improving withstand voltage; the use of a second GaN sublayer of 60 to 100 nm can fully utilize the effect of the non-carbon-doped GaN sublayer in improving the quality of the epitaxial crystal, thereby improving the crystal quality of the transistor.

[0041] For example, the thickness of the first GaN sublayer 121 is 50 nm, and the thickness of the second GaN sublayer 122 is 80 nm.

[0042] In other possible implementations of the embodiments of the present disclosure, the thickness of the first GaN sublayer in each period is different, and / or the thickness of the second GaN sublayer in each period is different.

[0043] In other embodiments, the thickness of the second GaN sub-layer 122 may not be greater than the thickness of the first GaN sub-layer 121 .

[0044] In the embodiment of the present disclosure, the carbon doping concentration in each of the first GaN sub-layers 121 in the high-resistance superlattice layer 102 gradually decreases along the direction from the buffer layer 101 to the channel layer 103 .

[0045] In this implementation, in the high-resistance superlattice layer, the carbon doping concentration becomes lower and lower from the buffer layer to the channel layer. Correspondingly, the crystal quality of the high-resistance superlattice layer becomes better and better from the buffer layer to the channel layer, which makes the subsequent channel layer epitaxial crystal quality better, thereby increasing the two-dimensional electron gas concentration.

[0046] In the embodiment of the present disclosure, the carbon doping concentration in the first GaN sublayer 121 closest to the buffer layer 101 in the high resistance superlattice layer 102 is 10 19 ~10 21 cm -3 .

[0047] The first GaN sub-layer 121 closest to the buffer layer 101 is also the first GaN sub-layer 121 with the highest carbon doping concentration.

[0048] In this implementation, the carbon doping concentration of the first GaN sublayer with the highest carbon doping concentration is set to 10 19 ~10 21 cm -3, so that each subsequent sub-layer has enough downward airflow, and finally the carbon doping of each sub-layer has a better oxygen ion capture effect, and finally the carbon doping concentration close to the channel layer is not too high to affect the crystal quality of the channel layer.

[0049] For example, the carbon doping concentration in the first GaN sublayer 121 closest to the buffer layer 101 in the high resistance superlattice layer 102 is 10 20 cm -3 .

[0050] In the embodiment of the present disclosure, the carbon doping concentration in each of the first GaN sub-layers 121 may be reduced in a geometric manner or in an arithmetic difference manner.

[0051] In other embodiments, the carbon doping concentration in each of the first GaN sub-layers 121 may be reduced in an irregular manner.

[0052] In the embodiment of the present disclosure, the high-resistance superlattice layer 102 includes a superlattice structure with 15 to 40 periods.

[0053] In this implementation, providing a superlattice structure with 15 to 40 periods can not only ensure the oxygen ion capture effect, but also ensure that the final carbon doping concentration close to the channel layer is not too high to affect the crystal quality of the channel layer.

[0054] Exemplarily, the high-resistance superlattice layer 102 includes a superlattice structure with 25 periods.

[0055] In the embodiment of the present disclosure, the channel layer 103 is a GaN channel layer.

[0056] The channel layer 103 has a thickness of 200-400 nm, for example, 300 nm.

[0057] In the embodiment of the present disclosure, the barrier layer 104 can be a single layer or a composite layer.

[0058] For example, the barrier layer 104 includes Al 0.25 Ga 0.75 N sublayer and GaN sublayer.

[0059] In the embodiment of the present disclosure, Al 0.25 Ga 0.75 The thickness of the N sub-layer may be 20-30 nm, for example, 25 nm. The thickness of the GaN sub-layer may be 1-3 nm, for example, 2 nm.

[0060] See also Figure 2 The transistor may further include a substrate 105 , a buffer layer 101 and a high-resistance superlattice layer 102 sequentially stacked on the substrate 105 .

[0061] In the embodiment of the present disclosure, the substrate 105 may be a single crystal substrate or a composite substrate.

[0062] Exemplarily, the substrate 105 is a sapphire substrate.

[0063] In the disclosed embodiment, the buffer layer 101 is an oxygen-doped AlN buffer layer. This is intended to effectively achieve lattice matching between the sapphire substrate (Al2O3) and the AlN material, reducing the internal stress of the two mismatched materials. However, oxygen ions can diffuse into the GaN channel layer. To address this issue, the disclosed embodiment designs a high-resistance superlattice layer.

[0064] In the embodiment of the present disclosure, the oxygen doping concentration in the buffer layer 101 is 10 18 ~10 23 cm -3 .

[0065] In this implementation, the buffer layer with the above-mentioned doping concentration is used to achieve lattice matching between the sapphire substrate (Al2O3) and the AlN material.

[0066] For example, the oxygen doping concentration in the buffer layer 101 is 10 20 cm -3 .

[0067] In the embodiment of the present disclosure, the buffer layer 101 has a thickness of 20 to 30 nm.

[0068] Exemplarily, the thickness of the buffer layer 101 is 25 nm.

[0069] See also Figure 2 The transistor may further include a passivation layer 106 , where the passivation layer 106 covers the barrier layer 104 .

[0070] For example, the passivation layer 106 may be a silicon oxide, silicon nitride, gallium nitride, or aluminum nitride passivation layer.

[0071] See also Figure 2 The transistor may further include a gate 107 , a source 108 and a drain 109 .

[0072] The gate 107 is located on the passivation layer 106 .

[0073] This transistor is a high electron mobility transistor (HEMT). Current can be transmitted between the drain and source through a conductive channel formed by a two-dimensional electron gas. The gate is connected to the gallium nitride structure through a gate dielectric layer. By controlling the gate voltage, the conduction and cutoff of the transistor's conductive channel can be controlled.

[0074] In one example, the source electrode 108 and the drain electrode 109 pass through the passivation layer 106 and the barrier layer 104 respectively and are connected to the channel layer 103 .

[0075] In another example, the source 108 and the drain 109 pass through the passivation layer 106 and are connected to the barrier layer 104, as shown in FIG. Figure 2 shown.

[0076] Figure 3 This is a flow chart of a method for manufacturing a transistor according to an embodiment of the present disclosure. Figure 3 , the method steps include:

[0077] 301. Prepare a buffer layer, wherein the buffer layer is an oxygen-doped AlN buffer layer.

[0078] 302. A high-resistance superlattice layer, a channel layer, and a barrier layer are sequentially fabricated on the buffer layer, wherein the high-resistance superlattice layer includes a superlattice structure consisting of a first GaN sublayer and a second GaN sublayer, wherein the first GaN sublayer is a carbon-doped GaN sublayer, and the second GaN sublayer is a non-carbon-doped GaN sublayer.

[0079] In an embodiment of the present disclosure, the transistor includes a channel layer, the function of the channel layer is to form a two-dimensional electron gas between the channel layer and the barrier layer; the transistor also includes a buffer layer and a high-resistance superlattice layer, the buffer layer is an oxygen-doped AlN buffer layer, and the high-resistance superlattice layer includes a first GaN sublayer and a second GaN sublayer, wherein the first GaN sublayer is a carbon-doped GaN sublayer, which can capture electrons generated by oxygen ions diffused from the buffer layer to the high-resistance superlattice layer, avoid the formation of leakage channels, improve reliability, and improve the voltage resistance performance of the transistor; the second GaN sublayer is a non-carbon-doped GaN sublayer, which can improve the tendency of the first GaN sublayer to deteriorate in crystal quality due to carbon doping, and improve the crystal quality of the subsequently grown channel layer. The first GaN sublayer and the second GaN sublayer form a superlattice layer, which can release stress and is conducive to improving the crystal quality of epitaxy. In summary, the high-resistance superlattice layer can improve reliability, improve the voltage resistance performance of the transistor, release stress, and is conducive to improving the crystal quality of the transistor epitaxy.

[0080] Figure 4 A flow chart of a method for manufacturing a transistor according to an embodiment of the present disclosure is provided. Figure 4 , the method flow chart includes:

[0081] 401. Provide a substrate.

[0082] In the embodiment of the present disclosure, the substrate 105 may be a single crystal substrate or a composite substrate.

[0083] Exemplarily, the substrate 105 is a Si substrate or a sapphire substrate.

[0084] Optionally, the method may further include:

[0085] The substrate is placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber for nitride epitaxy, hydrogen is introduced as a carrier gas, and the substrate temperature is raised to 1000°C to 1100°C to decompose the oxide on the substrate surface at high temperature to obtain a clean surface.

[0086] For example, a silicon substrate is placed in MOCVD, the substrate temperature is raised to 1050°C, and treated in a H2 atmosphere for 5 to 10 minutes to obtain a clean silicon surface.

[0087] 402. A buffer layer, a high-resistance superlattice layer, a channel layer, and a barrier layer are sequentially fabricated on the substrate.

[0088] In the disclosed embodiment, the buffer layer 101 can be an oxygen-doped AlN layer. The purpose of using an oxygen-doped AlN buffer layer 101 is to effectively transition the lattice matching between the sapphire substrate (Al2O3) and the AlN material, reducing the internal stress of the two mismatched materials. However, oxygen ions can diffuse into the GaN channel layer. To address this problem, the disclosed embodiment designs a high-resistance superlattice layer.

[0089] In the embodiment of the present disclosure, the oxygen doping concentration in the buffer layer 101 is 10 18 ~10 23 cm -3 .

[0090] In this implementation, the buffer layer with the above-mentioned doping concentration is used to achieve lattice matching between the sapphire substrate (Al2O3) and the AlN material.

[0091] For example, the oxygen doping concentration in the buffer layer 101 is 10 20 cm -3 .

[0092] In the embodiment of the present disclosure, the buffer layer 101 has a thickness of 20 to 30 nm.

[0093] Exemplarily, the thickness of the buffer layer 101 is 25 nm.

[0094] In the embodiment of the present disclosure, the high-resistance superlattice layer 102 includes a superlattice structure composed of a first GaN sublayer 121 and a second GaN sublayer 122 . The first GaN sublayer 121 is a carbon-doped GaN sublayer, and the second GaN sublayer 122 is a non-carbon-doped GaN sublayer.

[0095] In the embodiment of the present disclosure, the thickness of the second GaN sub-layer 122 is greater than the thickness of the first GaN sub-layer 121 .

[0096] In this implementation, the thickness of the carbon-doped GaN sublayer in each period of the high-resistance superlattice layer is greater than the thickness of the non-carbon-doped GaN sublayer, which can ensure that after the carbon-doped GaN sublayer is doped and captured with oxygen ions, the quality of the epitaxial crystal can be improved by the non-carbon-doped GaN sublayer with a thicker thickness.

[0097] In a possible implementation of the embodiment of the present disclosure, the thickness of the first GaN sublayer in each period is the same, and / or the thickness of the second GaN sublayer in each period is the same.

[0098] Illustratively, the thickness of the first GaN sublayer 121 is 40-80 nm, and the thickness of the second GaN sublayer 122 is 60-100 nm.

[0099] In this implementation, the use of a first GaN sublayer of 40 to 80 nm can fully utilize the role of the carbon-doped GaN sublayer in capturing oxygen ions, thereby reducing leakage and improving withstand voltage; the use of a second GaN sublayer of 60 to 100 nm can fully utilize the effect of the non-carbon-doped GaN sublayer in improving the quality of the epitaxial crystal, thereby improving the crystal quality of the transistor.

[0100] For example, the thickness of the first GaN sublayer 121 is 50 nm, and the thickness of the second GaN sublayer 122 is 80 nm.

[0101] In other possible implementations of the embodiments of the present disclosure, the thickness of the first GaN sublayer in each period is different, and / or the thickness of the second GaN sublayer in each period is different.

[0102] In other embodiments, the thickness of the second GaN sub-layer 122 may not be greater than the thickness of the first GaN sub-layer 121 .

[0103] In the embodiment of the present disclosure, the carbon doping concentration in each of the first GaN sub-layers 121 in the high-resistance superlattice layer 102 gradually decreases along the direction from the buffer layer 101 to the channel layer 103 .

[0104] In this implementation, in the high-resistance superlattice layer, the carbon doping concentration becomes lower and lower from the buffer layer to the channel layer. Correspondingly, the crystal quality of the high-resistance superlattice layer becomes better and better from the buffer layer to the channel layer, which makes the subsequent channel layer epitaxial crystal quality better, thereby increasing the two-dimensional electron gas concentration.

[0105] In the embodiment of the present disclosure, the carbon doping concentration in the first GaN sublayer 121 closest to the buffer layer 101 in the high resistance superlattice layer 102 is 1019 ~10 21 cm -3 .

[0106] The first GaN sub-layer 121 closest to the buffer layer 101 is also the first GaN sub-layer 121 with the highest carbon doping concentration.

[0107] In this implementation, the carbon doping concentration of the first GaN sublayer with the highest carbon doping concentration is set to 10 19 ~10 21 cm -3 , so that each subsequent sub-layer has enough downward airflow, and finally the carbon doping of each sub-layer has a better oxygen ion capture effect, and finally the carbon doping concentration close to the channel layer is not too high to affect the crystal quality of the channel layer.

[0108] For example, the carbon doping concentration in the first GaN sublayer 121 closest to the buffer layer 101 in the high resistance superlattice layer 102 is 10 20 cm -3 .

[0109] In the embodiment of the present disclosure, the carbon doping concentration in each of the first GaN sub-layers 121 may be reduced in a geometric manner or in an arithmetic difference manner.

[0110] In other embodiments, the carbon doping concentration in each of the first GaN sub-layers 121 may be reduced in an irregular manner.

[0111] In the embodiment of the present disclosure, the high-resistance superlattice layer 102 includes a superlattice structure with 15 to 40 periods.

[0112] In this implementation, providing a superlattice structure with 15 to 40 periods can not only ensure the oxygen ion capture effect, but also ensure that the final carbon doping concentration close to the channel layer is not too high to affect the crystal quality of the channel layer.

[0113] Exemplarily, the high-resistance superlattice layer 102 includes a superlattice structure with 25 periods.

[0114] In the embodiment of the present disclosure, the channel layer 103 is a GaN channel layer.

[0115] The channel layer 103 has a thickness of 200-400 nm, for example, 300 nm.

[0116] In the embodiment of the present disclosure, the barrier layer 104 can be a single layer or a composite layer.

[0117] For example, the barrier layer 104 includes Al 0.25 Ga0.75 N sublayer and GaN sublayer.

[0118] In the embodiment of the present disclosure, Al 0.25 Ga 0.75 The thickness of the N sub-layer may be 20-30 nm, for example, 25 nm. The thickness of the GaN sub-layer may be 1-3 nm, for example, 2 nm.

[0119] In the embodiment of the present disclosure, step 402 may include:

[0120] In the first step, a buffer layer is grown on the substrate using a physical vapor deposition (PVD) technique.

[0121] Oxygen is doped during the growth process of the aluminum-containing target reacting with the nitrogen-containing gas or the plasma based on the nitrogen-containing gas to form an oxygen-doped AlN layer.

[0122] In the second step, a high-resistance superlattice layer is grown on the buffer layer using a Metal-organic Chemical Vapor Deposition (MOCVD) technique.

[0123] In the embodiment of the present disclosure, the second step may include:

[0124] The first GaN sub-layer is grown on the buffer layer under an environment with a growth temperature of 900-1000° C. and a growth pressure of 50-150 Torr.

[0125] The second GaN sub-layer is grown on the first GaN sub-layer under an environment with a growth temperature of 950-1050° C. and a growth pressure of 50-150 Torr.

[0126] The above growth process is repeated for 15 to 40 cycles to obtain the high-resistance superlattice layer.

[0127] In this implementation, a high-quality superlattice layer that blocks oxygen ions can be obtained through the above-mentioned growth environment.

[0128] Exemplarily, the first GaN sub-layer is grown on the buffer layer under an environment of a growth temperature of 950° C. and a growth pressure of 100 Torr.

[0129] The second GaN sub-layer is grown on the first GaN sub-layer at a growth temperature of 1000° C. and a growth pressure of 100 Torr.

[0130] The third step is to grow a channel layer on the high-resistance superlattice layer using MOCVD technology.

[0131] The growth temperature is 950-1100°C.

[0132] The fourth step is to grow a barrier layer on the channel layer using MOCVD technology.

[0133] The growth temperature is 100-1100°C.

[0134] 403. A passivation layer is formed on the barrier layer.

[0135] For example, the passivation layer 106 may be a silicon oxide, silicon nitride, gallium nitride, or aluminum nitride passivation layer.

[0136] 404. Fabricate a gate on the surface of the passivation layer.

[0137] Exemplarily, step 405 may include:

[0138] A gate metal layer is formed on the surface of the passivation layer; and the gate metal layer is patterned to obtain a gate.

[0139] 405. Make source, drain and drain.

[0140] In one example, the source electrode and the drain electrode respectively pass through the passivation layer and the barrier layer and are connected to the channel layer.

[0141] Exemplarily, step 405 may include:

[0142] A source groove and a drain groove are respectively opened on the passivation layer and the barrier layer, and both the source groove and the drain groove are connected to the channel layer; a source and a drain are respectively made in the source groove and the drain groove.

[0143] In another example, the source and the drain respectively pass through the passivation layer and are connected to the barrier layer.

[0144] Exemplarily, step 405 may include:

[0145] A source groove and a drain groove are respectively opened on the passivation layer, and both the source groove and the drain groove are connected to the barrier layer; a source and a drain are respectively made in the source groove and the drain groove.

[0146] The transistor provided by the embodiments of the present disclosure includes a carbon-doped GaN sublayer. This structure is deep-level doped and is similar to a p-type film layer. It can capture electrons generated by oxygen ions, prevent the formation of leakage channels, and improve reliability. Each carbon-doped GaN sublayer is immediately followed by a non-carbon-doped GaN sublayer, which improves the trend of its crystal quality deteriorating due to the introduction of carbon doping and improves the crystal quality of the subsequently grown GaN epitaxial film layer. The thickness of the non-carbon-doped GaN sublayer in each period is greater than the thickness of the carbon-doped GaN sublayer, ensuring high crystal quality of the epitaxial wafer. The doping concentration of each carbon-doped GaN sublayer in the superlattice layer decreases from bottom to top, which can gradually improve the crystal quality of the epitaxial wafer. The closer to the channel layer, the better the crystal quality, thereby improving the crystal quality of the epitaxial layer of the channel layer and further improving the two-dimensional electron gas. The carbon-doped GaN sublayer / non-carbon-doped GaN sublayer forms a superlattice layer. This superlattice layer can release stress, which is beneficial to improving the crystal quality of the epitaxial wafer. As a high-resistance layer, it can improve the withstand voltage of the epitaxial wafer.

[0147] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor comprises: A buffer layer (101), a high-resistance superlattice layer (102), a channel layer (103) and a barrier layer (104), wherein the high-resistance superlattice layer (102), the channel layer (103) and the barrier layer (104) are sequentially stacked on the buffer layer (101); The buffer layer (101) is an oxygen-doped AlN buffer layer, and the high-resistance superlattice layer (102) comprises a superlattice structure composed of a first GaN sublayer (121) and a second GaN sublayer (122), wherein the first GaN sublayer (121) is a carbon-doped GaN sublayer, and the second GaN sublayer (122) is a non-carbon-doped GaN sublayer.

2. The transistor according to claim 1, characterized in that The thickness of the second GaN sublayer (122) is greater than the thickness of the first GaN sublayer (121).

3. The transistor according to claim 2, characterized in that The thickness of the first GaN sublayer (121) is 40-80 nm, and the thickness of the second GaN sublayer (122) is 60-100 nm.

4. The transistor according to any one of claims 1 to 3, characterized in that: Along the direction from the buffer layer (101) to the channel layer (103), the carbon doping concentration in each of the first GaN sublayers (121) in the high-resistance superlattice layer (102) gradually decreases.

5. The transistor according to claim 4, characterized in that The carbon doping concentration in the first GaN sublayer (121) closest to the buffer layer (101) in the high-resistance superlattice layer (102) is 10 19 ~10 21 cm -3 .

6. The transistor according to any one of claims 1 to 3, characterized in that: The high-resistance superlattice layer (102) includes a superlattice structure with 15 to 40 periods.

7. The transistor according to any one of claims 1 to 3, characterized in that: The oxygen doping concentration in the buffer layer (101) is 10 18 ~10 23 cm -3 .

8. A method for manufacturing a transistor, characterized in that: The method comprises: Manufacturing a buffer layer, wherein the buffer layer is an oxygen-doped AlN buffer layer; A high-resistance superlattice layer, a channel layer and a barrier layer are sequentially fabricated on the buffer layer, wherein the high-resistance superlattice layer comprises a superlattice structure consisting of a first GaN sublayer and a second GaN sublayer, wherein the first GaN sublayer is a carbon-doped GaN sublayer, and the second GaN sublayer is a non-carbon-doped GaN sublayer.

9. The method according to claim 8, characterized in that The high-resistance superlattice layer is manufactured, comprising: Growing the first GaN sublayer on the buffer layer at a growth temperature of 900-1000° C. and a growth pressure of 50-150 torr; Growing the second GaN sublayer on the first GaN sublayer at a growth temperature of 950 to 1050° C. and a growth pressure of 50 torr to 150 torr; The above growth process is repeated for 15 to 40 cycles to obtain the high-resistance superlattice layer.

10. The method according to claim 8 or 9, characterized in that: The thickness of the second GaN sublayer is greater than the thickness of the first GaN sublayer.

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