Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problems of low electron mobility and low switching efficiency of the semiconductor device. The semiconductor device comprises a substrate, and a channel layer, a barrier layer and a group-III nitride layer which are sequentially arranged on one side of the substrate, the semiconductor device further comprises a first electrode, a second electrode and a grid electrode located between the first electrode and the second electrode. The III-group nitride layer comprises at least part of a first P-type doping part and an intrinsic part, the grid electrode is located on the side, away from the substrate, of the first P-type doping part, and the first electrode and the second electrode are located on the side, away from the substrate, of the channel layer; the intrinsic portion includes a first portion between the first pole and the gate, and a second portion between the second pole and the gate. The semiconductor device is applied to a power device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a method for preparing the same, and an electronic device. Background Art

[0002] The third generation of semiconductor materials represented by gallium nitride (GaN) have good properties such as large bandgap, high critical breakdown electric field, high electron saturation rate, and strong radiation resistance. They are widely used in optoelectronics, radio frequency, and power electronics, and are the most preferred material system for preparing high-power radio frequency electronic devices and high-efficiency power electronic devices. At the same time, the AlGaN / GaN heterojunction formed based on its unique polarization effect can form a high-concentration, high-mobility two-dimensional electron gas (2DEG). Using this feature and the material advantages of GaN, high electron mobility transistors (HEMT) with lower on-resistance, higher withstand voltage, and greater power density can be prepared.

[0003] In some examples, a P-GaN layer is provided under the gate of the HEMT, and the P-GaN layer depletes the two-dimensional electron gas at the AlGaN / GaN heterojunction interface to form an enhanced HEMT. It is of great significance to improve the switching efficiency of the HEMT and the electron mobility of the HEMT. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device, aiming to solve the problems of low electron mobility and low switching efficiency of semiconductor devices.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor device is provided, which includes: a substrate and a channel layer, a barrier layer and a group III nitride layer arranged in sequence on one side of the substrate, the group III nitride layer including: at least a portion of a first P-type doped portion and an intrinsic portion; the semiconductor device also includes: a first pole, a second pole and a gate located between the first pole and the second pole, the gate being located on a side of the first P-type doped portion away from the substrate, and the first pole and the second pole being located on a side of the channel layer away from the substrate; the intrinsic portion including: a first portion located between the first pole and the gate, and a second portion located between the second pole and the gate.

[0007] The semiconductor device provided by the above-mentioned embodiments of the present disclosure includes a Group III nitride layer, and the Group III nitride layer includes: at least a portion of a first P-type doping portion and an intrinsic portion, the intrinsic portion and the barrier layer will form 2DEG at the interface through spontaneous polarization and piezoelectric polarization effects, thereby increasing the concentration of 2DEG of the semiconductor device; further, the structural setting of the semiconductor device can form the first P-type doping portion by ion implantation, and compared with the first P-type doping portion formed by an etching process, the first P-type doping portion formed by ion implantation can effectively avoid damage to the first P-type doping portion and the barrier layer due to etching, thereby solving the problem of 2DEG capture caused by the damage leading to a decrease in 2DEG concentration, so as to ensure that the semiconductor device has higher electron mobility and switching efficiency, and improve the electrical performance of the semiconductor device.

[0008] In some embodiments, the intrinsic portion further includes: a third portion located between the first P-type doping portion and the barrier layer.

[0009] In some embodiments, a ratio of a thickness of the third portion to a thickness of the first portion is less than or equal to 50%.

[0010] In some embodiments, the first P-type doped portion includes: a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer away from the substrate, the first sublayer and the intrinsic portion are an integral structure, and the second sublayer and the barrier layer are an integral structure.

[0011] In some embodiments, the first P-type doped portion further includes: a third sublayer, the third sublayer is located on a side of the second sublayer close to the substrate, and the third sublayer and the channel layer are an integrated structure.

[0012] In some embodiments, a ratio of a thickness of the third sub-layer to a thickness of the channel layer is less than or equal to 10%.

[0013] In some embodiments, in an orthographic projection onto the substrate, the gate is located within the first P-type doping portion, and there is a distance between the boundary of the gate and the boundary of the first P-type doping portion; the semiconductor device also includes: at least one dielectric layer, the dielectric layer is located on the side of the intrinsic portion away from the substrate; wherein the dielectric layer closest to the intrinsic portion includes: a second P-type doping portion, the doping element of the second P-type doping portion is the same as the doping element of the first P-type doping portion; in an orthographic projection onto the substrate, the second P-type doping portion is located between the boundary of the gate and the boundary of the first P-type doping portion.

[0014] In some embodiments, the maximum thickness of the intrinsic portion is in the range of 30 nm to 200 nm.

[0015] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming a channel layer and a barrier layer in sequence on one side of a substrate; forming a group III nitride layer on a side of the barrier layer away from the substrate, the group III nitride layer comprising: at least a portion of a first P-type doped portion and an intrinsic portion; forming a first pole, a second pole and a gate located between the first pole and the second pole to obtain a semiconductor device; the gate is located on a side of the first P-type doped portion away from the substrate, the first pole and the second pole are located on a side of the channel layer away from the substrate; the intrinsic portion comprises: a first portion located between the first pole and the gate, and a second portion located between the second pole and the gate.

[0016] In some embodiments, a group III nitride layer is formed on a side of the barrier layer away from the substrate, including: forming an initial group III nitride layer on a side of the barrier layer away from the substrate; forming a photoresist layer on a side of the initial group III nitride layer away from the substrate; removing a portion of the photoresist layer located in a first target area; the first target area is an area where a first P-type doping portion is preformed; performing ion implantation in the first target area, and a portion of the initial group III nitride layer located in the first target area forms at least a portion of the first P-type doping portion; removing the remaining portion of the photoresist layer; removing a portion of the initial group III nitride layer located in a second target area, and a remaining portion of the initial group III nitride layer forms an intrinsic portion; the second target area is an area where a first pole and a second pole are preformed.

[0017] In some embodiments, a group III nitride layer is formed on a side of the barrier layer away from the substrate, including: forming an initial group III nitride layer on a side of the barrier layer away from the substrate; forming a first dielectric layer on a side of the initial group III nitride layer away from the substrate; forming a photoresist layer on a side of the first dielectric layer away from the substrate; removing a portion of the photoresist layer located in a first target area; performing ion implantation in the first target area, and the portion of the initial group III nitride layer located in the first target area forms at least a portion of a first P-type doped portion; removing the remaining portion of the photoresist layer; removing the portion of the initial group III nitride layer located in the second target area, and the remaining portion of the initial group III nitride layer forms an intrinsic portion.

[0018] In some embodiments, the semiconductor device also includes: at least one dielectric layer, the dielectric layer is located on the side of the intrinsic portion away from the substrate; wherein the dielectric layer closest to the intrinsic portion includes: a second P-type doping portion; the method for preparing the semiconductor device also includes: forming a second P-type doping portion; the step of forming the second P-type doping portion includes: performing ion implantation in a first target area, and the portion of the first dielectric layer located in the first target area forms an initial second P-type doping portion; removing the portion of the initial second P-type doping portion located in a third target area, and the remaining portion of the initial second P-type doping portion forms a second P-type doping portion; the third target area is an area where a gate is pre-formed.

[0019] In some embodiments, the conditions for ion implantation include at least one of the following: the range of ion implantation dose is 1×10 12 / cm 2 ~1ⅹ10 15 / cm 2 ; The range of ion implantation energy is 10keV~1MeV; The range of ion implantation angle is 0°~20°; The range of ion implantation annealing temperature is 700℃~1500℃; The range of ion implantation time is 10s~30min.

[0020] In yet another aspect, an integrated circuit is provided. The integrated circuit includes the semiconductor device according to any one of the above embodiments.

[0021] On the other hand, an electronic device is provided, comprising: an integrated circuit and a circuit board as described in any of the above embodiments, wherein the integrated circuit is arranged on the circuit board.

[0022] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, integrated circuit, and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0024] Figure 1 is a schematic structural diagram of a HEMT according to some embodiments;

[0025] Figure 2 is a schematic structural diagram of a semiconductor device according to some embodiments;

[0026] Figure 3 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0027] Figure 4 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0028] Figure 5 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0029] Figure 6 is another structural schematic diagram of a semiconductor device according to some embodiments;

[0030] Figure 7 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0031] Figure 8 to Figure 13Schematic diagram of structures corresponding to each step of a method for preparing a semiconductor device according to some embodiments;

[0032] Fig.14 is a schematic structural diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0034] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0037] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0038] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0039] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0040] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0041] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0042] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0043] Semiconductor: A semiconductor is a material whose electrical conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor.

[0044] The third generation semiconductor materials represented by gallium nitride (GaN) have good characteristics such as wide band gap, high critical breakdown electric field, high electron mobility, high electron saturation velocity, etc., which are particularly suitable for making high-power electronic devices with high voltage, high frequency, high efficiency, high temperature resistance and radiation resistance. At present, there are two mainstream directions of GaN power devices: depletion-mode HEMT (high-electron-mobility transistor) and enhancement-mode HEMT.

[0045] In system switching applications, depletion-mode HEMTs require additional device structures or drive circuits to turn off the device to reduce system power consumption, but additional parasitic inductance and capacitance limit the high-frequency application of the system and increase the complexity of system design. Enhancement-mode HEMTs are in the off state when the gate voltage is zero, and are more flexible in system design and switching applications.

[0046] In some examples, such as Figure 1 As shown, the HEMT includes: a substrate 11 , and a channel layer 12 and a barrier layer 13 sequentially arranged on one side of the substrate 11 .

[0047] Exemplarily, the material of the channel layer 12 includes GaN, which can also be called intrinsic GaN; the material of the barrier layer 13 includes at least one of AlN and AlGaN. The following description is made by taking the example that the material of the channel layer 12 is GaN and the material of the barrier layer 13 is AlGaN.

[0048] AlGaN / GaN can form a heterojunction. The AlGaN / GaN heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects. This two-dimensional electron gas is spatially separated from ionized impurities, so it has a very high mobility, which makes the AlGaN / GaN HEMT have a very low on-resistance.

[0049] For example, Figure 1 As shown, the HEMT further includes: a first electrode 21 , a second electrode 22 , and a gate 23 located between the first electrode 21 and the second electrode 22 . The first electrode 21 and the second electrode 22 are located on a side of the channel layer 12 away from the substrate 11 .

[0050] For example, the first electrode 21 is one of the source and the drain of the HEMT, and the second electrode 22 is the other of the source and the drain of the HEMT.

[0051] Exemplarily, the material of the gate 23 is selected from at least one of Ti / Al / Ni / Au, Ti / Al / Ti / TiN, Ti / Al / TiN and Ti / Al / W.

[0052] In order to realize an enhancement-mode HEMT, the HEMT further includes: a first P-type doping portion 301 , and the gate 23 is located at a side of the first P-type doping portion 301 away from the substrate 11 .

[0053] Exemplarily, the material of the first P-type doping part 301 includes at least one of P-type GaN and P-type AlGaN. For example, the doping material of the first P-type doping part 301 includes magnesium (Mg).

[0054] like Figure 1 As shown, the AlGaN / GaN heterojunction composed of the barrier layer 13 and the channel layer 12 forms a 2DEG at its interface, and the first P-type doping part 301 pulls up the conduction band of the AlGaN / GaN heterojunction. Under zero bias, the first P-type doping part 301 depletes the two-dimensional electron gas at the heterojunction interface, and no current passes through the channel, thereby forming an enhanced HEMT, which makes the HEMT in a normally closed state.

[0055] The interface between the barrier layer 13 and the channel layer 12 still maintains 2DEG in the portion between the gate 23 and the first electrode 21 and in the portion between the gate 23 and the second electrode 22. When a certain voltage is applied to the gate 23, the 2DEG under the gate 23 can be re-established, turning on the HEMT.

[0056] In some examples, the first P-type doped portion 301 needs to be formed by an etching process, and problems such as the uniformity, repeatability and etching damage of the etching process will affect the electrical performance of the HEMT. For example, during the rapid switching process of the HEMT, the threshold voltage and the on-resistance will shift over time due to the frequent influence of the gate 23 and the drain stress, which seriously affects the switching efficiency of the HEMT; due to the etching damage, a large number of defects will be introduced on the surface of the first P-type doped portion 301 and the surface of the barrier layer 13, and the defects will capture 2DEG, causing the 2DEG concentration of the HEMT channel layer 12 to decrease, which seriously affects the electrical performance of the HEMT.

[0057] Based on this, Figure 2 As shown, an embodiment of the present disclosure provides a semiconductor device 100, which includes: a substrate 11 and a channel layer 12, a barrier layer 13 and a group III nitride layer 30A arranged in sequence on one side of the substrate 11, and the group III nitride layer 30A includes at least a portion of a first P-type doped portion 301; the semiconductor device 100 also includes: a gate 23, a first pole 21 and a second pole 22.

[0058] For example, the semiconductor device 100 includes an enhanced HEMT. The substrate 11, channel layer 12, barrier layer 13 and first P-type doping portion 301, gate 23, first electrode 21 and second electrode 22 of the semiconductor device 100 are described in the above content and will not be repeated here.

[0059] Exemplarily, in the barrier layer 13, the ratio of the number of Al atoms to the number of AlGaN atoms is in the range of 10% to 40%. For example, in the barrier layer 13, the ratio of the number of Al atoms to the number of AlGaN atoms is 10%, 15%, 20%, 30% or 40%, etc., which is not limited here.

[0060] Exemplarily, the first P-type doping portion 301 includes AlGaN, and the ratio of the mass of Al in the first P-type doping portion 301 to the mass of AlGaN is smaller than the ratio of the mass of Al in the barrier layer 13 to the mass of AlGaN.

[0061] The group III nitride layer 30A further includes an intrinsic portion 302 . The intrinsic portion 302 includes a first portion 3021 located between the first electrode 21 and the gate 23 , and a second portion 3022 located between the second electrode 22 and the gate 23 .

[0062] Exemplarily, the material of the intrinsic part 302 includes at least one of GaN and AlGaN. The intrinsic part 302 refers to a film layer that is a pure semiconductor without impurities and defects, and the concentration of electrons and holes inside the film layer is equal, and the film layer is an intrinsic semiconductor.

[0063] Exemplarily, the maximum thickness d0 of the intrinsic portion 302 ranges from 30 nm to 200 nm; for example, the maximum thickness d0 of the intrinsic portion 302 is 30 nm, 50 nm, 70 nm, 90 nm, 100 nm, 120 nm, 150 nm, 180 nm or 200 nm, etc., which is not limited here.

[0064] For example, the initial group III nitride layer 30 (eg, Figure 8 As shown), a portion of the initial Group III nitride layer 30 is then ion implanted, the portion of the initial Group III nitride layer 30 that is ion implanted forms at least a portion of the first P-type doped portion 301, and the portion of the initial Group III nitride layer 30 that is not ion implanted is used to form the intrinsic portion 302.

[0065] The semiconductor device 100 includes an intrinsic portion 302, and the intrinsic portion 302 and the barrier layer 13 form a 2DEG at the interface through spontaneous polarization and piezoelectric polarization effects, thereby enhancing the electron mobility of the semiconductor device 100. Further, compared with the first P-type doping portion 301 formed by an etching process, the embodiment of the present disclosure can form the first P-type doping portion 301 by an ion implantation method to effectively avoid the damage of the first P-type doping portion 301 and the barrier layer 13 caused by etching, thereby solving the problem of the capture of 2DEG caused by the damage leading to a decrease in 2DEG concentration, so as to ensure that the semiconductor device 100 has a higher electron mobility and switching efficiency, and improve the electrical performance of the semiconductor device.

[0066] The introduction of the preparation method of the group III nitride layer 30A refers to the content of the preparation method of semiconductor devices, and will not be described in detail here.

[0067] In some embodiments, as Figure 3 shown, the intrinsic part 302 further includes: a third part 3023 located between the first P-type doped part 301 and the barrier layer 13.

[0068] Exemplarily, the thickness d1 of the first P-type doped part 301 is less than the thickness d2 of the first part 3021, that is, d1 < d2. For example, when the first P-type doped part 301 is formed by ion implantation, the ion implantation depth into the initial group III nitride layer 30 (as Figure 8 shown) is less than the thickness of the initial group III nitride layer 30. At this time, the un-implanted part of the initial group III nitride layer 30 forms the third part 3023.

[0069] Compared with the case where the thickness d1 of the first P-type doped part 301 is equal to the thickness d2 of the first part 3021, by providing that the intrinsic part 302 includes the third part 3023, when a certain voltage is applied to the gate 23, the 2DEG under the gate 23 can be re-established relatively quickly. Therefore, the threshold voltage of the semiconductor device 100 having the first P-type doped part 301 with a relatively small thickness d1 is relatively small.

[0070] In some examples, as Figure 3 shown, the ratio of the thickness d3 of the third part 3023 to the thickness d2 of the first part 3021 is less than or equal to 50%, that is, d3 / d2 ≤ 50%.

[0071] For example, the ratio of the thickness d3 of the third part 3023 to the thickness d2 of the first part 3021 is 50%, 40%, 30%, 20%, 10% or 5%, etc., and there is no limitation here.

[0072] By providing the third part 3023 with different thicknesses d3, the threshold voltage of the semiconductor device 100 can be adjusted; and the ratio of the thickness d3 of the third part 3023 to the thickness d2 of the first part 3021 is less than or equal to 50%, which can ensure that the first P-type doped part 301 depletes the two-dimensional electron gas at the heterojunction interface, making the semiconductor device 100 in a normally closed state.

[0073] In some examples, as Figure 4 shown, the first P-type doped part 301 includes: a first sub-layer 3011 and a second sub-layer 3012. The first sub-layer 3011 is located on the side of the second sub-layer 3012 away from the substrate 11. The first sub-layer 3011 and the intrinsic part 302 are of an integral structure, and the second sub-layer 3012 and the barrier layer 13 are of an integral structure.

[0074] That is to say, the thickness d11 of the first sub-layer 3011 is equal to the thickness d2 of the intrinsic part 302, that is, d11 = d2.

[0075] Exemplarily, the thickness d12 of the second sub-layer 3012 is equal to the thickness d4 of the barrier layer 13, that is, d12 = d4; or, the thickness d12 of the second sub-layer 3012 is less than the thickness d4 of the barrier layer 13, that is, d12 < d4. For example, the thickness d4 of the barrier layer 13 ranges from 10 nm to 30 nm.

[0076] For example, by the method of ion implantation, the first P-type doping part 301 is formed, and the depth of ion implantation reaches at least part of the barrier layer 13, then the first P-type doping part 301 including the first sub-layer 3011 and the second sub-layer 3012 can be formed.

[0077] By providing that the first P-type doping part 301 includes the first sub-layer 3011 and the second sub-layer 3012, the threshold voltage of the semiconductor device 100 can be adjusted.

[0078] In some examples, as Figure 5 shown, the first P-type doping part 301 further includes: a third sub-layer 3013, the third sub-layer 3013 is located on the side of the second sub-layer 3012 close to the substrate 11, and the third sub-layer 3013 and the channel layer 12 are of an integral structure.

[0079] Exemplarily, the thickness d13 of the third sub-layer 3013 is less than the thickness d5 of the channel layer 12, that is, d13 < d5.

[0080] Exemplarily, the ratio of the thickness d13 of the third sub-layer 3013 to the thickness d5 of the channel layer 12 is less than or equal to 10%.

[0081] For example, the ratio of the thickness d13 of the third sub-layer 3013 to the thickness d5 of the channel layer 12 is 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, etc., and there is no limitation here.

[0082] Exemplarily, the thickness d5 of the channel layer 12 ranges from 100 nm to 300 nm, and the thickness d13 of the third sub-layer 3013 is less than or equal to 20 nm. For example, the thickness d13 of the third sub-layer 3013 is 1 nm, 3 nm, 5 nm, 8 nm, 10 nm or 20 nm, etc., and there is no limitation here.

[0083] For example, by the method of ion implantation, the first P-type doping part 301 is formed, and the depth of ion implantation reaches at least part of the channel layer 12, then the first P-type doping part 301 including the first sub-layer 3011, the second sub-layer 3012 and the third sub-layer 3013 can be formed.

[0084] By configuring the first P-type doping portion 301 to include the first sublayer 3011 , the second sublayer 3012 , and the third sublayer 3013 , the threshold voltage of the semiconductor device 100 may be adjusted.

[0085] In some instances, such as Figure 2 to Figure 5 As shown, the threshold voltage of the semiconductor device 100 ranges from 0.5V to 3V.

[0086] For example, the threshold voltage of the semiconductor device 100 is 0.5V, 0.8V, 0.9V, 1V, 1.2V, 1.4, 1.5V, 2V or 3V, etc., which is not limited here.

[0087] In some embodiments, Figure 6 As shown, in the orthographic projection to the substrate 11, the gate 23 is located within the first P-type doping portion 301, and there is a spacing d6 between the boundary L1 of the gate 23 and the boundary L2 of the first P-type doping portion 301; the semiconductor device 100 also includes: at least one dielectric layer 40, the dielectric layer 40 is located on the side of the intrinsic portion 302 away from the substrate 11; wherein the dielectric layer 40 closest to the intrinsic portion 302 includes: a second P-type doping portion 401, the doping element of the second P-type doping portion 401 is the same as the doping element of the first P-type doping portion 301; in the orthographic projection to the substrate 11, the second P-type doping portion 401 is located between the boundary L1 of the gate 23 and the boundary L2 of the first P-type doping portion 301.

[0088] Exemplarily, the doping element of the second P-type doping part 401 and the first P-type doping part 301 is Mg, for example, the doping concentration of Mg is in the range of 1×10 18 cm -3 ~1×10 20 cm -3 For example, the doping concentration of Mg is 1×10 18 cm -3 , 5×10 18 cm -3 , 1×10 19 cm -3 , 5×10 19 cm -3 or 1×10 20 cm -3 The doping concentration refers to the amount of impurities contained in a material per unit volume or per unit mass, usually expressed in terms of the number of atoms or ions.

[0089] Exemplarily, the first P-type doped portion 301 is formed by ion implantation, and ion implantation is performed from the side of the dielectric layer 40 (referred to as the first dielectric layer 40a) closest to the substrate 11 and away from the substrate 11, so as to obtain the first P-type doped portion 301. The introduction of ion implantation from the side of the dielectric layer 40 closest to the substrate 11 and away from the substrate 11 is referred to the content of the semiconductor device manufacturing method, and will not be described in detail here.

[0090] When the first P-type doped portion 301 is formed by ion implantation from the side of the dielectric layer 40 away from the substrate 11 , the portion of the dielectric layer 40 implanted with ions has implanted ions, and the portion of the dielectric layer 40 that remains in the semiconductor device 100 forms the second P-type doped portion 401 .

[0091] Compared to the initial III-nitride layer 30 (such as Figure 8 Compared with the method in which ion implantation is performed on the side away from the substrate 11 to form the first P-type doped portion 301 as shown in the figure, ion implantation is performed from the side of the dielectric layer 40 closest to the substrate 11 away from the substrate 11. Under the protection of the dielectric layer 40, damage to the first P-type doped portion 301 caused by ion implantation can be effectively prevented, so as to prevent the capture of 2DEG caused by the damage of the ion implantation of the first P-type doped portion 301 and the problem of reducing the electron mobility of the semiconductor device 100, which is beneficial to improving the electron mobility of the semiconductor device 100 and improving the electrical performance of the semiconductor device 100.

[0092] In some examples, such as Figure 6 As shown, the activation rate of the semiconductor device 100 is 0.1% to 1%.

[0093] The activation rate of the semiconductor device 100 is a ratio of the hole concentration of the first P-type doping portion 301 to the concentration of the implanted ions.

[0094] For example, the activation rate of the semiconductor device 100 is 0.1%, 0.3%, 0.4%, 0.5%, 0.7%, 0.8%, 0.9% or 1%, etc., which is not limited here.

[0095] In some embodiments, Figure 6 As shown, the semiconductor device 100 further includes: a nucleation layer (not shown in the figure) and a buffer layer (not shown in the figure), and the substrate 11, the nucleation layer, the buffer layer and the channel layer 12 are arranged in sequence.

[0096] Exemplarily, the material of the nucleation layer includes at least one of AlN, GaN and AlGaN.

[0097] Exemplarily, the material of the buffer layer includes at least one of AlN, AlGaN and GaN.

[0098] Since the buffer layer and the substrate 11 are made of different materials and usually have different lattice constants and thermal expansion coefficients, if the buffer layer is directly disposed on the substrate 11, cracks may be generated in the buffer layer due to lattice mismatch and thermal mismatch, resulting in a decrease in crystal quality. Therefore, a nucleation layer is provided to effectively avoid the generation of cracks in the buffer layer.

[0099] In some embodiments, Figure 6 As shown, the semiconductor device 100 further includes an insertion layer (not shown in the figure), which is located between the channel layer 12 and the barrier layer 13 .

[0100] Exemplarily, the material of the insertion layer includes AlN, and the potential barrier of the insertion layer may be greater than the potential barrier of the barrier layer 13 .

[0101] The provision of the insertion layer can promote the polarization effect between the channel layer 12 and the barrier layer 13 , and increase the 2DEG concentration of the heterojunction between the channel layer 12 and the barrier layer 13 .

[0102] like Figure 6 and Figure 7 As shown, an embodiment of the present disclosure further provides a method for preparing a semiconductor device, the method comprising steps: R1 to R3.

[0103] R1. A channel layer 12 and a barrier layer 13 are sequentially formed on one side of a substrate 11.

[0104] Exemplarily, the material of the substrate 11 includes: silicon, silicon carbide, gallium nitride, sapphire or diamond, etc., which is not limited here.

[0105] Exemplarily, the channel layer 12 and the barrier layer 13 are formed on one side of the substrate 11 by an epitaxial growth method.

[0106] R2. Form a group III nitride layer 30A on a side of the barrier layer 13 away from the substrate 11 . The group III nitride layer 30A includes: at least a portion of the first P-type doping portion 301 and an intrinsic portion 302 .

[0107] In some examples, such as Figure 2 , Figure 8 and Fig. 9 As shown, the step of forming the group III nitride layer 30A on the side of the barrier layer 13 away from the substrate 11 includes: R21-R26.

[0108] R21. Form an initial group III nitride layer 30 on a side of the barrier layer 13 away from the substrate 11.

[0109] Exemplarily, the initial group III nitride layer 30 is formed on a side of the barrier layer 13 away from the substrate 11 by an epitaxial growth method.

[0110] Exemplarily, the material of the initial group III nitride layer 30 includes at least one of GaN and AlGaN.

[0111] R22. Form a photoresist layer 50 on a side of the initial group III nitride layer 30 away from the substrate 11.

[0112] The material of the photoresist layer 50 includes photoresist. The photoresist is a mixed liquid that is sensitive to light. The components of the photoresist include: photosensitive resin, sensitizer and solvent.

[0113] Exemplarily, the material of the photoresist includes: propylene glycol monomethyl ether acetate.

[0114] Exemplarily, the photoresist layer 50 is formed by a coating process.

[0115] R23, removing the portion of the photoresist layer 50 located in the first target area S1; the first target area S1 is an area where the first P-type doping portion 301 is pre-formed.

[0116] Exemplarily, the portion of the photoresist layer 50 located in the first target area S1 is illuminated by a mask, and the portion of the photoresist layer 50 located in the first target area S1 is removed by a developer.

[0117] R24, performing ion implantation in the first target region S1, so that the portion of the initial group III nitride layer 30 located in the first target region S1 forms at least a portion of the first P-type doping portion 301.

[0118] Exemplarily, the conditions for ion implantation include at least one of the following: the range of ion implantation dose is 1×10 12 / cm 2 ~1ⅹ10 15 / cm 2 The range of ion implantation energy is 10 keV to 1 MeV, the range of ion implantation angle is 0° to 20°, the range of ion implantation annealing temperature is 700° C. to 1500° C., and the range of ion implantation time is 10 s to 30 min.

[0119] For example, the ion implantation dose is 1 x 10 12 / cm 2 1 x 10 13 / cm 2 5 x 10 13 / cm 2 1 x 10 14 / cm 2 5 x 10 14 / cm 2 or 1 x 10 15 / cm 2 Etc., there is no limitation here.

[0120] For example, the ion implantation energy ranges from 10 keV, 100 keV, 300 keV, 500 keV, 700 keV, 800 keV, 900 keV or 1 MeV, etc., which is not limited here.

[0121] For example, the angle of ion implantation is 0°, 1°, 2°, 4°, 5°, 7°, 9°, 10°, 12°, 15°, 16°, 17°, 18° or 20°, etc., which is not limited here. The angle of ion implantation is the angle between the direction of ion implantation and the direction perpendicular to the substrate 11.

[0122] For example, the annealing temperature of the ion implantation is 700° C., 800° C., 1000° C., 1100° C., 1200° C., 1300° C., 1400° C., or 1500° C., etc., but is not limited thereto.

[0123] For example, the time for ion implantation is 10 s, 30 s, 1 min, 5 min, 10 min, 15 min, 18 min, 20 min, 25 min or 30 min, etc., which is not limited here.

[0124] By regulating the conditions of ion implantation, the depth of ion implantation can be controlled to obtain the first P-type doped portion 301 with different thicknesses d1. For the introduction of the first P-type doped portion 301 with different structures, please refer to the above content and will not be repeated here.

[0125] R25. Remove the remaining portion of the photoresist layer 50.

[0126] Exemplarily, the remaining portion of the photoresist layer 50 is removed by solvent dissolution.

[0127] R26, removing the portion of the initial III-nitride layer 30 located in the second target area S2 to form an intrinsic portion 302; the second target area S2 is an area where the first pole 21 and the second pole 22 are pre-formed.

[0128] Exemplarily, the step of removing the portion of the initial group III nitride layer 30 located in the second target region S2 to form the intrinsic portion 302 includes: R261 and R262.

[0129] R261. Form a first dielectric layer 40a on a side of the initial group III nitride layer 30 away from the substrate 11.

[0130] Exemplarily, the material of the first dielectric layer 40 a includes at least one of silicon oxide and silicon nitride.

[0131] Exemplarily, the first dielectric layer 40a is formed by a deposition process.

[0132] R262 , removing the first dielectric layer 40 a and the portion of the initial group III nitride layer 30 located in the second target area S2 , and the remaining portion of the initial group III nitride layer 30 forms the intrinsic portion 302 .

[0133] Exemplarily, the first dielectric layer 40 a and the portion of the initial group III nitride layer 30 located in the second target region S2 are removed by an etching process.

[0134] Exemplarily, in this step, the portion of the barrier layer 13 located in the second target region S2 is removed, and at least the portion of the channel layer 12 located in the second target region S2 is removed. For example, the thickness of the removed portion of the channel layer 12 is 20 nm. After the first pole 21 and the second pole 22 are formed in this way, the first pole 21 and the second pole 22 have a good connection with the 2DEG, which can reduce the resistance of the semiconductor device 100.

[0135] The group III nitride layer 30A is formed by an ion implantation process through the above steps R21 to R26, which can effectively avoid the problem of damage to the first P-type doping portion 301 and the barrier layer 13 due to etching.

[0136] In other embodiments, Figure 6 , Fig.12 and Fig.13 As shown, the step of forming the group III nitride layer 30A on the side of the barrier layer 13 away from the substrate 11 includes: T21-T27.

[0137] T21 . Form an initial group III nitride layer 30 on a side of the barrier layer 13 away from the substrate 11 .

[0138] T22 . Form a first dielectric layer 40 a on a side of the initial group III nitride layer 30 away from the substrate 11 .

[0139] T23 . Form a photoresist layer 50 on a side of the first dielectric layer 40 a away from the substrate 11 .

[0140] T24 , removing the portion of the photoresist layer 50 located in the first target area S1 .

[0141] T25 , performing ion implantation in the first target region S1 , so that the portion of the initial group III nitride layer 30 located in the first target region S1 forms at least a portion of the first P-type doping portion 301 .

[0142] T26 , removing the remaining portion of the photoresist layer 50 .

[0143] T27 , removing the portion of the initial group III-nitride layer 30 located in the second target area S2 , and the remaining portion of the initial group III-nitride layer 30 forms the intrinsic portion 302 .

[0144] The III-group nitride layer 30A is formed by the ion implantation process through the above steps T21 to T27, which can effectively avoid the problem of damage to the first P-type doping part 301 and the barrier layer 13 due to etching. In addition, in step T25, ion implantation is performed on the side of the first dielectric layer 40a away from the substrate 11, which can effectively prevent the damage of the ion implantation to the first P-type doping part 301, so as to prevent the damage of the ion implantation of the first P-type doping part 301 from capturing the 2DEG, which is beneficial to improving the electron mobility of the semiconductor device 100 and improving the electrical performance of the semiconductor device 100.

[0145] R3, such as Figure 6 , Fig. 9 and Fig.10 As shown, a first pole 21, a second pole 22 and a gate 23 located between the first pole 21 and the second pole 22 are formed to obtain a semiconductor device 100; the gate 23 is located on the side of the first P-type doped portion 301 away from the substrate 11, and the first pole 21 and the second pole 22 are located on the side of the channel layer 12 away from the substrate 11; the intrinsic portion 302 includes: a first portion 3021 located between the first pole 21 and the gate 23, and a second portion 3022 located between the second pole 22 and the gate 23.

[0146] Exemplarily, forming the first electrode 21 , the second electrode 22 , and the gate 23 located between the first electrode 21 and the second electrode 22 includes steps: R31 - R36 .

[0147] R31. Form a first metal layer 61 on a side of the first dielectric layer 40a away from the substrate 11.

[0148] Exemplarily, the first metal layer 61 is formed by a deposition process.

[0149] R32, removing the portion of the first metal layer 61 outside the second target area S2, and the portion of the first metal layer 61 located in the second target area S2 forms the first electrode 21 and the second electrode 22.

[0150] Exemplarily, the portion of the first metal layer 61 outside the second target area S2 is removed by a photolithography process.

[0151] Exemplarily, after removing the portion of the first metal layer 61 outside the second target area S2 , an annealing process is further included, so that the first electrode 21 and the second electrode 22 form an ohmic contact.

[0152] Among them, ohmic contact refers to the contact formed by metal and semiconductor, and its contact resistance is very small, and the contact current is linearly related to the voltage. In ohmic contact, there is no obvious potential barrier between the metal and the semiconductor, and electrons can freely pass through the contact surface between the metal and the semiconductor to form a good current path. The first pole 21 and the second pole 22 form ohmic contact here, which means that the first pole 21 and the second pole 22 both form ohmic contact with the channel layer 12.

[0153] R33. Form a second dielectric layer 40b on a side of the first dielectric layer 40a away from the substrate 11.

[0154] Exemplarily, the material of the second dielectric layer 40 b includes at least one of silicon oxide and silicon nitride.

[0155] Exemplarily, the second dielectric layer 40 b is formed by a deposition process.

[0156] R34, removing portions of the first dielectric layer 40a and the second dielectric layer 40b located in the third target area S3, where the third target area S3 is a region where the gate 23 is pre-formed.

[0157] Exemplarily, the portions of the first dielectric layer 40 a and the second dielectric layer 40 b located in the third target area S3 are removed by a photolithography process.

[0158] R35. Form a second metal layer 62 on a side of the second dielectric layer 40 b away from the substrate 11 .

[0159] Exemplarily, the second metal layer 62 is formed by a deposition process.

[0160] R36. Remove the portion of the second metal layer 62 located outside the third target area S3. The portion of the second metal layer 62 located in the third target area S3 forms the gate 23 to obtain the semiconductor device 100.

[0161] Exemplarily, the portion of the second metal layer 62 outside the third target area S3 is removed by a photolithography process.

[0162] Exemplarily, after removing the portion of the second metal layer 62 outside the third target area S3 , an annealing process is further included to form a Schottky contact on the gate 23 .

[0163] The Schottky contact refers to the bending of the energy band of the semiconductor at the interface when the gate 23 and the first P-type doped portion 301 are in contact, thereby forming a Schottky barrier.

[0164] Through the above steps R31 to R36 , the first electrode 21 , the second electrode 22 and the gate 23 located between the first electrode 21 and the second electrode 22 are formed to obtain the semiconductor device 100 .

[0165] Through the above steps R1 to R3, a semiconductor device 100 is obtained in which a first P-type doped portion 301 is formed by an ion implantation process, so as to effectively avoid the problem of damage to the first P-type doped portion 301 and the barrier layer 13 due to etching, thereby solving the problem of 2DEG capture caused by the damage leading to a decrease in 2DEG concentration, so as to ensure that the semiconductor device 100 has higher electron mobility and switching efficiency, and improve the electrical performance of the semiconductor device 100.

[0166] In some embodiments, in the method for manufacturing a semiconductor device, a second P-type doping portion 401 of the semiconductor device 100 is also formed.

[0167] like Fig.13 As shown, in step T25, ion implantation is performed in the first target region S1, and the portion of the first dielectric layer 40a located in the first target region S1 forms an initial second P-type doped portion 4010.

[0168] That is to say, when ion implantation is performed in the first target area S1, the doping elements will be simultaneously doped into the portion of the initial group III nitride layer 30 located in the first target area S1 and the portion of the first dielectric layer 40a located in the first target area S1. The portion of the initial group III nitride layer 30 located in the first target area S1 forms at least a portion of the first P-type doping portion 301, and the portion of the first dielectric layer 40a located in the first target area S1 forms an initial second P-type doping portion 4010.

[0169] like Figure 6 and Fig.13 As shown, the portion of the initial second P-type doping portion 4010 located in the third target area S3 is removed, and the remaining portion of the initial second P-type doping portion 4010 forms the second P-type doping portion 401. This step can refer to Fig.10 In step R34, when the portions of the first dielectric layer 40a and the second dielectric layer 40b located in the third target area S3 are removed, the portion of the first dielectric layer 40a located in the third target area S3 is removed. When ion implantation is performed on the portion of the first dielectric layer 40a located in the first target area S1, the remaining portion of the first dielectric layer 40a located in the first target area S1 forms the second P-type doped portion 401.

[0170] In some embodiments, Fig.11 As shown, in order to facilitate further connection of the first electrode 21, the second electrode 22 and the gate 23 of the semiconductor device 100 with the extraction electrodes (not shown in the figure), the semiconductor device 100 is further processed, which includes: R41 and R42.

[0171] R41. Form a third dielectric layer 40c on a side of the second dielectric layer 40b away from the substrate 11.

[0172] Exemplarily, the material of the third dielectric layer 40c includes at least one of silicon oxide and silicon nitride.

[0173] Exemplarily, the third dielectric layer 40c is formed by a deposition process.

[0174] R42, remove at least a portion of the first dielectric layer 40a, the second dielectric layer 40b and the third dielectric layer 40c located in the second target area S2, and remove at least a portion of the first dielectric layer 40a, the second dielectric layer 40b and the third dielectric layer 40c located in the third target area S3, so that the first pole 21, the second pole 22 and the gate 23 are exposed for connecting the lead-out electrode.

[0175] Exemplarily, at least a portion of the first dielectric layer 40a, the second dielectric layer 40b and the third dielectric layer 40c located in the second target area S2 is removed by photolithography, and at least a portion of the first dielectric layer 40a, the second dielectric layer 40b and the third dielectric layer 40c located in the third target area S3 is removed.

[0176] Through the above steps R41 and R42, the first electrode 21, the second electrode 22 and the gate 23 are exposed to facilitate the connection of the extraction electrode.

[0177] An embodiment of the present disclosure further provides an integrated circuit, which includes the semiconductor device 100 as described in any of the above embodiments.

[0178] An integrated circuit is a miniature electronic device or component. Using a certain process, the semiconductor devices 100, resistors, capacitors, inductors and other components and wiring required in a circuit are interconnected together, made on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a tube shell to become a miniature structure with the required circuit function.

[0179] The integrated circuit includes the semiconductor device 100 provided in any of the above embodiments. Therefore, the integrated circuit provided in the embodiments of the present disclosure has all the beneficial effects of the semiconductor device 100 provided in any of the above embodiments, which will not be described in detail here.

[0180] like Fig.14 As shown, an embodiment of the present disclosure further provides an electronic device 1000, which includes an integrated circuit as provided in any of the above embodiments. The electronic device 1000 also includes a circuit board 200, on which the integrated circuit is disposed.

[0181] Exemplarily, the electronic device 1000 further includes an antenna, and the semiconductor device 100 on the integrated circuit is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0182] Exemplarily, the electronic device 1000 is a user device or terminal device of different types such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the electronic device 1000 may also be a network device such as a base station. The electronic device 1000 may also be a device such as a power amplifier used in the above electronic devices, which is not limited here.

[0183] The electronic device 1000 includes the integrated circuit provided in any of the above embodiments. Therefore, the electronic device 1000 provided in the embodiment of the present disclosure has all the beneficial effects of the integrated circuit provided in any of the above embodiments, which will not be described in detail here.

[0184] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate and a channel layer and a barrier layer sequentially disposed on one side of the substrate; as well as, A group III nitride layer, located on a side of the barrier layer away from the substrate; The group III nitride layer includes: at least a portion of a first P-type doping portion and an intrinsic portion; A first electrode, a second electrode, and a gate located between the first electrode and the second electrode, the gate being located on a side of the first P-type doped portion away from the substrate, and the first electrode and the second electrode being located on a side of the channel layer away from the substrate; The intrinsic portion includes a first portion located between the first electrode and the gate, and a second portion located between the second electrode and the gate.

2. The semiconductor device according to claim 1, wherein: The intrinsic portion further includes a third portion located between the first P-type doped portion and the barrier layer.

3. The semiconductor device according to claim 2, characterized in that A ratio of a thickness of the third portion to a thickness of the first portion is less than or equal to 50%.

4. The semiconductor device according to claim 1, wherein: The first P-type doped portion includes: a first sublayer and a second sublayer, the first sublayer is located on a side of the second sublayer away from the substrate, the first sublayer and the intrinsic portion are an integral structure, and the second sublayer and the barrier layer are an integral structure.

5. The semiconductor device according to claim 4, characterized in that The first P-type doped portion further includes: a third sublayer, the third sublayer is located on a side of the second sublayer close to the substrate, and the third sublayer and the channel layer are an integrated structure.

6. The semiconductor device according to claim 5, characterized in that A ratio of a thickness of the third sublayer to a thickness of the channel layer is less than or equal to 10%.

7. The semiconductor device according to claim 1, wherein: In an orthographic projection onto the substrate, the gate is located within the first P-type doped portion, and a distance exists between a boundary of the gate and a boundary of the first P-type doped portion; The semiconductor device further comprises: at least one dielectric layer, the dielectric layer being located on a side of the intrinsic portion away from the substrate; Among them, the dielectric layer closest to the intrinsic part includes: a second P-type doping part, the doping element of the second P-type doping part is the same as the doping element of the first P-type doping part; in the orthographic projection onto the substrate, the second P-type doping part is located between the boundary of the gate and the boundary of the first P-type doping part.

8. The semiconductor device according to claim 1, wherein: The maximum thickness of the intrinsic portion is in the range of 30 nm to 200 nm.

9. A method for preparing a semiconductor device, characterized in that: include: forming a channel layer and a barrier layer in sequence on one side of the substrate; Forming a group III nitride layer on a side of the barrier layer away from the substrate, the group III nitride layer comprising: at least a portion of the first P-type doping portion and an intrinsic portion; A first pole, a second pole and a gate located between the first pole and the second pole are formed to obtain a semiconductor device; the gate is located on a side of the first P-type doped portion away from the substrate, and the first pole and the second pole are located on a side of the channel layer away from the substrate; the intrinsic portion includes: a first portion located between the first pole and the gate, and a second portion located between the second pole and the gate.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The step of forming a group III nitride layer on a side of the barrier layer away from the substrate comprises: forming an initial group III nitride layer on a side of the barrier layer away from the substrate; forming a photoresist layer on a side of the initial group III nitride layer away from the substrate; Removing a portion of the photoresist layer located in a first target area; the first target area is an area where a first P-type doping portion is preformed; Performing ion implantation in the first target region, wherein a portion of the initial group III nitride layer located in the first target region forms at least a portion of a first P-type doping portion; removing the remaining portion of the photoresist layer; The portion of the initial group III nitride layer located in the second target area is removed, and the remaining portion of the initial group III nitride layer forms the intrinsic portion; the second target area is an area where the first pole and the second pole are pre-formed.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: The step of forming a group III nitride layer on a side of the barrier layer away from the substrate comprises: forming an initial group III nitride layer on a side of the barrier layer away from the substrate; forming a first dielectric layer on a side of the initial group III nitride layer away from the substrate; forming a photoresist layer on a side of the first dielectric layer away from the substrate; removing the portion of the photoresist layer located in the first target area; Performing ion implantation in the first target region, wherein a portion of the initial group III nitride layer located in the first target region forms at least a portion of a first P-type doping portion; removing the remaining portion of the photoresist layer; The portion of the initial group III-nitride layer located in the second target region is removed, and the remaining portion of the initial group III-nitride layer forms an intrinsic portion.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The semiconductor device further comprises: at least one dielectric layer, the dielectric layer being located on a side of the intrinsic portion away from the substrate; wherein the dielectric layer closest to the intrinsic portion comprises: a second P-type doped portion; The method for preparing the semiconductor device further includes: forming the second P-type doping portion; The step of forming the second P-type doped portion comprises: performing ion implantation in the first target region, so that a portion of the first dielectric layer located in the first target region forms an initial second P-type doped portion; The portion of the initial second P-type doping portion located in the third target area is removed, and the remaining portion of the initial second P-type doping portion forms the second P-type doping portion; the third target area is the area where the gate is pre-formed.

13. The method for preparing a semiconductor device according to claim 10 or 11, characterized in that: The conditions for the ion implantation include at least one of the following: The ion implantation dose range is 1 x 10 12 / cm 2 ~1ⅹ10 15 / cm 2 ; The ion implantation energy ranges from 10keV to 1MeV; The angle of ion implantation ranges from 0° to 20°; The annealing temperature range for ion implantation is 700°C to 1500°C; The time range of ion implantation is 10s to 30min.

14. An integrated circuit, characterized in that: The invention comprises the semiconductor device according to any one of claims 1 to 8.

15. An electronic device, characterized in that: include: The integrated circuit of claim 14; A circuit board, wherein the integrated circuit is arranged on the circuit board.

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