Trench structure, field effect transistor and reliability evaluation method of trench structure
By designing an alternating trench structure, the problem of small trench spacing is solved, and the problem of difficulty in observing the inner wall of the trench is achieved is realized, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202510007801.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-11
AI Technical Summary
In silicon carbide trench technology, when the trench spacing is small, it is difficult to effectively observe and evaluate the morphology and roughness of the inner wall of the trench, affecting the performance and reliability of the device.
An alternating groove structure is designed, including a first linear groove group and a second linear groove group. The grooves are arranged alternately in the same direction and communicated with the rectangular groove through the third linear groove to ensure that the appearance of the groove side wall can be observed after parallel lobes are performed at any position.
It is realized that in the case of small groove spacing, the lobe position is not required to be carefully controlled, and the morphology and roughness of the groove side wall can be effectively observed and evaluated, thereby improving the reliability evaluation ability of the groove structure.
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Figure CN119815897A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor device preparation, and in particular to a trench structure, a field effect transistor, and a reliability evaluation method for the trench structure. Background Art
[0002] Silicon carbide (SiC) is a IV-VI compound material with unique physical and chemical properties, and has excellent material properties such as high hardness, good chemical stability and high thermal conductivity. In addition, silicon carbide exhibits wide bandgap (2.3ev~3.3ev), high critical electric field strength and high saturation mobility, making silicon carbide a very promising semiconductor material for high-power and high-temperature electronics.
[0003] In actual application scenarios, silicon carbide trench technology is a processing technology that changes the device structure and electrical characteristics by etching a series of trenches on a silicon carbide wafer. Silicon carbide trench technology can reduce the series resistance and inductance of power devices and increase the switching rate; in optoelectronic devices, it can improve the light absorption efficiency and photoelectric conversion efficiency of photodiodes, improve the response speed and wavelength selectivity of photodiodes, and then be applied to silicon carbide photodiodes, laser diodes and other devices.
[0004] At present, the roughness of the side wall after silicon carbide trench etching is an important factor affecting the subsequent process and performance parameters of the trench: one problem of silicon carbide ion etching is the micro-mask effect. Due to the hardness of SiC, heavier ion bombardment is required to cause the metal-based hard mask to be sputtered and re-deposited on the surface to produce significant roughness. The residue may be a serious problem for subsequent processes (such as metal contacts); the micro-groove effect of silicon carbide ion etching is also a common problem. Due to the increase in local etching rate, a V-shaped groove is formed at the bottom near the side wall. The micro-groove will affect the performance of the device such as the breakdown voltage, so it must be avoided. Therefore, the morphology and roughness detection of the silicon carbide groove structure formed by various processes has become an important part of device production.
[0005] For example, Figure 1 A schematic diagram of a planar structure of a groove structure is shown, such as Figure 1As shown, the groove structures 010 are all in the shape of long strips and are arranged at intervals in the horizontal direction. The groove structures 010 are filled with gate polysilicon 011, and there is a certain distance between two adjacent groove structures 010. With the continuous improvement of the degree of integration, the distance between two adjacent groove structures 010 is usually set to a smaller value. Due to the small groove spacing, the observation of the groove sidewall is mainly a combination of vertical groove cross-section observation and top surface observation. It is difficult to evaluate the inner walls of multiple long grooves. At the same time, due to the small groove spacing, it is difficult to ensure that the parallel groove cracks are exactly cracked to the groove position. The grinding method will cause damage to the sidewall roughness and thus affect the experimental observation results, making it difficult to implement the reliability evaluation of the groove structure. Summary of the invention
[0006] In view of the problems in the prior art, the purpose of the present disclosure is to provide a trench structure, a field effect transistor and a reliability assessment method for the trench structure, which can observe and assess the inner wall of the trench even when the trench spacing is small.
[0007] Specifically, a first aspect of the present disclosure provides a trench structure, which is applied to a metal oxide semiconductor field effect transistor, and the trench structure is arranged on a wafer substrate of the metal oxide semiconductor field effect transistor;
[0008] The groove structure includes a first linear groove group and a second linear groove group, specifically:
[0009] The first linear groove group includes a plurality of first rectangular grooves arranged at intervals along a first direction, and the first rectangular grooves extend in a second direction perpendicular to the first direction;
[0010] The second linear groove group includes a plurality of second rectangular grooves arranged at intervals along the first direction, and the second rectangular grooves extend in the second direction; and
[0011] The first rectangular grooves and the second rectangular grooves are alternately arranged in the first direction.
[0012] In a possible implementation of the first aspect above, the groove structure further includes a third linear groove;
[0013] The third linear groove extends in the first direction and is respectively connected with each of the first rectangular grooves and each of the second rectangular grooves.
[0014] In a possible implementation of the first aspect above, surfaces of the first rectangular trench and the second rectangular trench are covered with a thin gate oxide layer;
[0015] Gate polysilicon is deposited in the first rectangular trench and the second rectangular trench.
[0016] In a possible implementation of the first aspect, surfaces of the first rectangular trench, the second rectangular trench, and the third linear trench are covered with a thin gate oxide layer;
[0017] Gate polysilicon is deposited in the first rectangular trench, the second rectangular trench and the third linear trench, and the gate polysilicon deposited in the first rectangular trench, the second rectangular trench and the third linear trench is connected.
[0018] In a possible implementation of the first aspect, the widths of the first rectangular groove and the second rectangular groove in the first direction are the same;
[0019] The first rectangular groove and the second rectangular groove have the same extension length in the second direction.
[0020] In a possible implementation of the first aspect above, in the first direction, the first rectangular groove is located between two adjacent second rectangular grooves, and the second rectangular groove is located between two adjacent first rectangular grooves;
[0021] The spacing distance between adjacent first rectangular grooves in the first direction is less than or equal to the width of the second rectangular groove in the first direction;.
[0022] The spacing distance between adjacent second rectangular grooves in the first direction is less than or equal to the width of the first rectangular groove in the first direction.
[0023] In a possible implementation of the first aspect above, when the wafer substrate is a non-cubic crystal, the first direction forms a non-zero preset angle with at least one edge of the wafer substrate.
[0024] A second aspect of the present disclosure provides a field effect transistor, wherein the field effect transistor includes the trench structure provided by the first aspect.
[0025] A third aspect of the present disclosure provides a reliability evaluation method for a trench structure, which is applied to the trench structure provided in the first aspect;
[0026] The reliability assessment method may specifically include the following steps:
[0027] A selection point on the wafer substrate is randomly selected along a first direction, and a crack selection line is formed by extending the selection point along a second direction perpendicular to the first direction from the selection point as a starting point;
[0028] The wafer substrate is split according to the split selection line, and the surface morphology of the groove structure is evaluated by observing the groove surface of the first rectangular groove and / or the second rectangular groove corresponding to the split position to obtain an evaluation result.
[0029] A fourth aspect of the present disclosure provides another reliability evaluation method for a trench structure, which is applied to the trench structure provided in the first aspect;
[0030] The reliability assessment method may specifically include the following steps:
[0031] growing a thin gate oxide layer on the surface of the first rectangular trench and the second rectangular trench;
[0032] Filling gate polysilicon in the first rectangular trench and the second rectangular trench;
[0033] A forward voltage gradually increasing from zero is applied to the gate terminal until the gate oxide layer is broken down, so as to evaluate the defect characteristics of the oxide layer and generate corresponding evaluation results.
[0034] Compared with the prior art, the present invention has the following beneficial effects:
[0035] The technical solution provided by the present disclosure, through the design of an alternating groove structure, can eliminate the need for fine and precise control of the splitting position when the groove spacing is small. No matter where the splitting is performed, the appearance of the groove sidewall can be observed and evaluated after the splitting, thereby achieving reliability evaluation of the groove structure, and can be used to measure the condition parameters of the online production of etching grooves, which has replicable value. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0037] Figure 1 According to the prior art, a schematic diagram of a planar structure of a groove structure is provided.
[0038] Figure 2 According to an embodiment of the present disclosure, a planar structural schematic diagram of a groove structure is provided.
[0039] Figure 3 According to an embodiment of the present disclosure, a schematic diagram of a planar structure of a groove structure for parallel splitting is provided.
[0040] Figure 4 According to an embodiment of the present disclosure, a schematic diagram of an alternating groove structure with different etching angles is provided.
[0041] Figure 5 According to an embodiment of the present disclosure, a schematic flow chart of a method for evaluating the reliability of a trench structure is provided.
[0042] Figure 6 According to an embodiment of the present disclosure, a schematic flow chart of another method for evaluating the reliability of a trench structure is provided.
[0043] Figure 7 According to an embodiment of the present disclosure, a schematic diagram of a cross-sectional structure of a groove structure is provided. DETAILED DESCRIPTION
[0044] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application systems without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0045] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.
[0046] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials, or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials, or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.
[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0048] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.
[0049] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.
[0050] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.
[0051] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
[0052] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.
[0053] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.
[0054] In order to overcome the problems existing in the prior art, in some embodiments of the present disclosure, Figure 2A schematic diagram of a planar structure of a trench structure is provided. Specifically, the trench structure is applied to a metal oxide semiconductor field effect transistor, and the trench structure is arranged on a wafer substrate portion of the metal oxide semiconductor field effect transistor, wherein the trench structure includes a first linear trench group 100 and a second linear trench group 200, specifically:
[0055] The first linear groove group 100 includes a plurality of first rectangular grooves 101 arranged at intervals along a first direction x, and the first rectangular grooves 101 extend in a second direction y perpendicular to the first direction x; the second linear groove group 200 includes a plurality of second rectangular grooves 201 arranged at intervals along the first direction x, and the second rectangular grooves 201 extend in the second direction y; and the first rectangular grooves 101 and the second rectangular grooves 201 are arranged alternately in the first direction x. It can be understood that, through the above-mentioned alternating arrangement of the groove structure, the cross-sectional observation of the groove structure can be achieved by randomly selecting any position for parallel slicing, and the sidewalls of the grooves can be directly photographed after parallel slicing to evaluate the feasibility of the experimental conditions. Exemplarily, Figure 3 A schematic diagram of a planar structure for parallel splitting of a groove structure is shown. Figure 3 Although the split position shown cannot be used to observe the cross section of the first rectangular groove 101 , the cross section of the second rectangular groove 201 can be observed.
[0056] In the above embodiment, further Figure 2 As shown, the groove structure further includes a third straight groove 300; wherein the third straight groove 300 extends in the first direction x and is respectively connected to each first rectangular groove 101 and each second rectangular groove 201. Further, the surfaces of the first rectangular groove 101, the second rectangular groove 102 and the third straight groove 300 are all covered with a thin gate oxide layer (not shown in the figure), and gate polysilicon 400 is deposited in the first rectangular groove 101, the second rectangular groove 201 and the third straight groove 300. Figure 2 As shown in the figure, the gate polysilicon 400 deposited in the first rectangular trench 101, the second rectangular trench 201 and the third linear trench 300 are connected to realize the relevant functions of the trench structure.
[0057] In the above embodiment, further, the widths of the first rectangular groove 101 and the second rectangular groove 201 in the first direction x can be set to be the same; and the extension lengths of the first rectangular groove 101 and the second rectangular groove 201 in the second direction y can also be set to be the same.
[0058] In the above embodiment, further, in order to ensure that the side wall of the groove can be observed when parallel slicing is performed at any position, it can be further limited that in the first direction x, the first rectangular groove 101 is located between two adjacent second rectangular grooves 201, and the second rectangular groove 201 is located between two adjacent first rectangular grooves 101; the spacing distance between adjacent first rectangular grooves 101 in the first direction x is less than or equal to the width of the second rectangular groove 201 in the first direction x; the spacing distance between adjacent second rectangular grooves 201 in the first direction x is less than or equal to the width of the first rectangular groove 101 in the first direction x.
[0059] In the above embodiment, further, in the case where the wafer substrate belongs to a non-cubic crystal system, the first direction can be configured to be at a non-zero preset angle with at least one edge of the wafer substrate. It can be understood that for non-cubic crystals, they themselves have various anisotropies, that is, they have different properties in different directions, such as growth properties, electrical properties, etc., and the positive and negative sides or different crystal planes in the same direction have different properties. In a specific embodiment of the present disclosure, exemplarily, the SiC MOS prepared using the crystal plane (0-33-8) has the highest channel mobility at all doping concentrations due to its lower interface state density and higher electron free ratio. When a doping concentration of 10^18 / cm3 is used, a high channel mobility of 60cm2V-1s-1 can be achieved, which is higher than the (0001) crystal plane. Therefore, it is possible to design alternating groove structures with different etching angles, so that the sidewall settings of silicon carbide grooves in different crystal directions can be studied. Exemplarily, Figure 4 A schematic diagram of an alternating groove structure with different etching angles is shown. Figure 4 As shown, by designing alternating groove structures with different angles, side walls of different crystal phases can be obtained. Subsequently, the Vramp test involved in the subsequent embodiments can be combined to evaluate the side wall grooves of different crystal orientations to obtain a groove structure with better electrical properties for use.
[0060] In some embodiments of the present disclosure, a field effect transistor is provided, wherein the field effect transistor includes the trench structure provided by the aforementioned embodiments.
[0061] In some embodiments of the present disclosure, Figure 5 A flow chart of a reliability assessment method for a groove structure is also provided. This reliability assessment method is applied to the groove structure provided in the aforementioned embodiment. That is, in the process of observing the physical properties of the groove sidewall and conducting reliability assessment using a parallel split assessment method, there is no need to finely and accurately control the split position. Regardless of the position at which the parallel split is performed, the appearance of the groove sidewall can be observed and assessed after the split.
[0062] Specifically, Figure 5 As shown, the reliability evaluation method may specifically include the following steps:
[0063] Step 001a: arbitrarily select a selection point on the wafer substrate along the first direction, and extend the selection point along the second direction perpendicular to the first direction to form a split selection line. Figure 2 or Figure 3 In the groove structure shown, in the process of generating the split selection line, the selection line extending along the second direction can be determined at the setting position of the third linear groove, which is not limited here.
[0064] Step 001b: Splitting the wafer substrate according to the splitting selection line, and evaluating the surface morphology of the groove structure by observing the groove surface of the first rectangular groove and / or the second rectangular groove corresponding to the splitting position to obtain an evaluation result. Figure 3 As shown in the figure, because the lower side of the lobe is not in the groove position, the upper side cross section Figure 1 The groove position can be seen to evaluate the groove roughness. Similarly, any position can be randomly selected for parallel slicing to achieve cross-sectional observation of the groove structure. After parallel slicing, the sidewall of the groove can be directly photographed to evaluate the feasibility of the experimental conditions.
[0065] In some embodiments of the present disclosure, in addition to directly observing the etched trench by splitting, other reliability means are also used to further evaluate the trench etching condition. For example, Figure 6 According to an embodiment of the present disclosure, another reliability evaluation method for a trench structure is provided, which can also be applied to the trench structure provided in the above embodiment. Figure 6 As shown, the reliability evaluation method may specifically include the following steps:
[0066] Step 001A: growing a thin gate oxide layer on the surface of the first rectangular trench and the second rectangular trench.
[0067] Step 001B: Filling gate polysilicon in the first rectangular trench and the second rectangular trench.
[0068] Step 001C: applying a forward voltage gradually increasing from zero to the gate terminal until the gate oxide layer is broken down, so as to evaluate the defect characteristics of the oxide layer and generate a corresponding evaluation result. Figure 7 FIG. 2 shows a schematic cross-sectional structure diagram of a groove structure. Figure 7As shown, in the silicon substrate 700, a thin gate oxide layer 702 is formed on the surface of the trench structure 701, which is filled with gate polysilicon 703. In this structure, a Vramp reliability test is performed by applying a forward voltage gradually increasing from zero to the gate polysilicon. Vramp is the most common gate oxide layer reliability assessment project. By linearly ramping up the acceleration voltage from the operating voltage V to the oxide layer breakdown, it can be used to quickly assess the defect characteristics of the oxide layer at low voltage, thereby achieving the non-intrinsic behavior characteristics of the gate of the certified electronic device.
[0069] To sum up, the technical solution provided by the present invention, through the design of an alternating groove structure, can eliminate the need for fine and precise control of the splitting position when the groove spacing is small. No matter where the splitting is performed, the morphology of the groove sidewall can be observed and evaluated after the splitting, thereby achieving reliability evaluation of the groove structure, and can be used to measure the condition parameters of the online production of etching grooves, which has replicable value.
[0070] The above content is a further detailed description of the present disclosure in combination with specific preferred implementation modes, and it cannot be determined that the specific implementation of the present disclosure is limited to these descriptions. For ordinary technicians in the technical field to which the present disclosure belongs, several simple deductions or substitutions can be made without departing from the concept of the present disclosure, which should be regarded as falling within the scope of protection of the present disclosure.
Claims
1. A trench structure, applied to a metal oxide semiconductor field effect transistor, wherein the trench structure is arranged on a wafer substrate of the metal oxide semiconductor field effect transistor; It is characterized in that The groove structure includes a first straight groove group and a second straight groove group, wherein: The first linear groove group includes a plurality of first rectangular grooves arranged at intervals along a first direction, and the first rectangular grooves extend in a second direction perpendicular to the first direction; The second linear groove group includes a plurality of second rectangular grooves arranged at intervals along the first direction, and the second rectangular grooves extend in the second direction; and The first rectangular grooves and the second rectangular grooves are alternately arranged in the first direction.
2. The groove structure according to claim 1, characterized in that: The groove structure further includes a third linear groove; The third linear groove extends in the first direction and is respectively connected with each of the first rectangular grooves and each of the second rectangular grooves.
3. The groove structure according to claim 1, characterized in that: The surfaces of the first rectangular trench and the second rectangular trench are covered with a thin gate oxide layer; Gate polysilicon is deposited in the first rectangular trench and the second rectangular trench.
4. The groove structure according to claim 2, characterized in that: The surfaces of the first rectangular trench, the second rectangular trench and the third linear trench are covered with a thin gate oxide layer; Gate polysilicon is deposited in the first rectangular trench, the second rectangular trench, and the third linear trench, and the gate polysilicon deposited in the first rectangular trench, the second rectangular trench, and the third linear trench are connected.
5. The groove structure according to claim 1, characterized in that: The widths of the first rectangular groove and the second rectangular groove in the first direction are the same; The first rectangular groove and the second rectangular groove have the same extension length in the second direction.
6. The groove structure according to claim 1, characterized in that: In the first direction, the first rectangular groove is located between two adjacent second rectangular grooves, and the second rectangular groove is located between two adjacent first rectangular grooves; The spacing distance between adjacent first rectangular grooves in the first direction is less than or equal to the width of the second rectangular groove in the first direction;. The spacing distance between adjacent second rectangular grooves in the first direction is less than or equal to the width of the first rectangular groove in the first direction.
7. The groove structure according to claim 1, characterized in that: In the case where the wafer substrate is a non-cubic crystal, the first direction forms a non-zero preset angle with at least one edge of the wafer substrate.
8. A field effect transistor, characterized in that: The field effect transistor comprises the trench structure according to any one of claims 1 to 7.
9. A reliability evaluation method for a groove structure, characterized in that: Applicable to the groove structure according to any one of claims 1 to 7; The reliability evaluation method comprises the following steps: A selection point on the wafer substrate is randomly selected along a first direction, and the selection point is used as a starting point to extend along a second direction perpendicular to the first direction to form a crack selection line; The wafer substrate is split according to the split selection line, and the surface morphology of the groove structure is evaluated by observing the groove surface of the first rectangular groove and / or the second rectangular groove corresponding to the split position to obtain an evaluation result.
10. A reliability evaluation method for a groove structure, characterized in that: Applicable to the groove structure according to any one of claims 1 to 7; The reliability evaluation method comprises the following steps: growing a thin gate oxide layer on the surface of the first rectangular trench and the second rectangular trench; Filling gate polysilicon in the first rectangular trench and the second rectangular trench; A forward voltage gradually increasing from zero is applied to the gate terminal until the gate oxide layer is broken down, so as to evaluate the defect characteristics of the oxide layer and generate a corresponding evaluation result.