Selectively forming etch stop layers and structures thereof

Abstract

The invention discloses selectively forming an etch stop layer and a structure thereof. A method includes forming a gate stack over a semiconductor region; performing an epitaxial process to form a source / drain region aside the gate stack; forming a source / drain contact plug over and electrically coupled to the source / drain region; forming a gate contact plug over and electrically coupled to the gate stack; a first inhibitor film is selectively formed on the dielectric layer proximate the conductive feature. The conductive feature is selected from the group consisting of a source / drain region, a source / drain contact plug, and a gate contact plug. A first etch stop layer is selectively deposited on the conductive feature, where the first inhibitor film prevents the first etch stop layer from being deposited thereon. The inhibitor membrane is then removed.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to selectively forming an etch stop layer and a structure thereof. Background Art

[0002] Transistors are basic building blocks in integrated circuits. In the development of integrated circuits, fin field effect transistors (FinFETs) and gate all around (GAA) transistors have been used to replace planar transistors. When forming a FinFET, a semiconductor fin is formed, and a dummy gate is formed on the semiconductor fin. The formation of a dummy gate may include: depositing a dummy layer (e.g., a polysilicon layer), and then patterning the dummy layer into a dummy gate. A gate spacer is formed on the sidewalls of the dummy gate stack. A source / drain region is formed by epitaxy based on the semiconductor fin. The dummy gate stack is then removed to form a trench between the gate spacers. A replacement gate is then formed in the trench. Summary of the invention

[0003] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a gate stack above a semiconductor region; performing an epitaxial process to form a source / drain region next to the gate stack; forming a source / drain contact plug above the source / drain region and electrically coupled to the source / drain region; forming a gate contact plug above the gate stack and electrically coupled to the gate stack; selectively forming a first inhibitor film on a dielectric layer near a conductive feature, wherein the conductive feature is selected from the group consisting of the source / drain region, the source / drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon; and removing the first inhibitor film.

[0004] According to a second aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor region; a gate stack located above the semiconductor region; a source / drain region located next to the gate stack; a source / drain silicide region located above and in contact with the source / drain region; a shallow trench isolation region located next to the source / drain region; a first contact etch stop layer located on the source / drain region; and an interlayer dielectric located above the first contact etch stop layer, wherein the interlayer dielectric is in physical contact with both the first contact etch stop layer and the shallow trench isolation region.

[0005] According to a third aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate; a dielectric isolation region located in the semiconductor substrate; a semiconductor fin adjacent to and higher than a top surface of the dielectric isolation region; a gate stack located on the semiconductor fin; a source / drain region coupled to the semiconductor fin and next to the gate stack; a source / drain silicide region located on the source / drain region; a contact etch stop layer located on the source / drain region and spaced apart from the dielectric isolation region; an interlayer dielectric located on the contact etch stop layer and in contact with the contact etch stop layer, wherein the interlayer dielectric is also in contact with the dielectric isolation region; and a source / drain contact plug located above the source / drain silicide region and in contact with the source / drain silicide region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figures 1 to 8 , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Figures 13 to 15 , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Figure 19A-1 , Figure 19A-2 as well as Fig.19B A diagram illustrating an intermediate stage in forming a fin field effect transistor (FinFET) and a contact plug in accordance with some embodiments.

[0008] Fig. 20 A cross-sectional view of a gate all around (GAA) transistor is shown in accordance with some embodiments.

[0009] Fig.21 A top view is shown of some features according to some embodiments.

[0010] Fig. 22 A process flow for forming a transistor according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms (e.g., "below," "beneath," "under," "overlying," "on," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0013] A transistor, a corresponding contact plug, and a method for forming the same are provided. According to some embodiments, conductive features such as epitaxial source / drain regions, gate contact plugs, and source / drain contact plugs are formed. An inhibitor film is selectively formed on a dielectric region near the conductive features. An etch stop layer is selectively formed on the conductive features. Due to the presence of the inhibitor film, an etch stop layer is formed away from the dielectric region. Because the etch stop layer can have a higher dielectric constant (k value) than the nearby dielectric region, the parasitic capacitance between the conductive features can be reduced by reducing the size of the etch stop layer. The resistance of the conductive plug can also be reduced.

[0014] It should be understood that although fin field effect transistors (FinFETs) are discussed as examples, the embodiments may also be applied to other types of transistors, such as planar transistors, gate all-around (GAA) transistors, etc. The purpose of the embodiments discussed herein is to provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figures 1 to 8 , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Figures 13 to 15 , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Figure 19A-1 , Figure 19A-2 as well as Fig.19B 1 shows a view of an intermediate stage of forming a FinFET and a contact plug according to some embodiments. The corresponding process is also schematically reflected in Fig. 22 The process flow 200 is shown.

[0016] refer to Figure 1 , a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination of the foregoing.

[0017] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. Fig. 22The process flow 200 is shown as process 202. The portion of the substrate 20 located between adjacent STI regions 24 is referred to as a semiconductor strip 26. In order to form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then the pad oxide layer 28 and the hard mask layer 30 are patterned. The pad oxide layer 28 can be a thin film formed of silicon oxide. The hard mask layer 30 can be formed of silicon nitride.

[0018] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with (one or more) dielectric materials. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) is performed to remove excess portions of the dielectric material, and the remaining portions of the (one or more) dielectric materials are the STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. The STI regions 24 may also include a dielectric material located above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material located above the liner dielectric may include silicon oxide.

[0019] Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments, semiconductor strips 26 are portions of original substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. According to alternative embodiments, semiconductor strips 26 are replacement strips formed by etching portions of substrate 20 located between STI regions 24 to form recesses, and performing epitaxy to re-grow another semiconductor material in the recesses. Thus, semiconductor strips 26 are formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, carbon-doped silicon, or III-V compound semiconductor materials.

[0020] refer to Figure 3 , the STI region 24 is recessed. Therefore, the top of the semiconductor strip 26 protrudes higher than the top surface 24T of the remaining portion of the STI region 24 to form a protruding fin 36. The corresponding process is Fig. 22The process flow 200 is shown as process 204. Etching can be performed using a dry etching process, wherein, for example, HF and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon gas can also be included. According to an alternative embodiment, the recessing of the STI region 24 is performed using a wet etching process. For example, the etching chemical can include HF. The top surface and the bottom surface of the STI region 24 are referred to as 24T and 24B, respectively.

[0021] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, a double patterning process or a multiple patterning process combines a photolithography process with a self-alignment process, thereby allowing a pattern to be created with a pitch smaller than that obtainable using, for example, a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fins.

[0022] Figures 4 to 6 The formation of a dummy gate stack 44 is shown in accordance with some embodiments. Figure 4 , a dummy dielectric layer 38 is formed on the sidewalls and top surface of the protruding fin 36 and may be located on the top surface of the STI region 24. The corresponding process is Fig. 22 This is shown as process 206 in the illustrated process flow 200. According to some embodiments, dummy dielectric layer 38 is formed by a deposition process, which may include chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The material of dummy dielectric layer 38 may include silicon oxide, but other dielectric materials such as silicon nitride, silicon carbonitride, silicon oxynitride, etc. may also be used.

[0023] Figure 5 FIG. 4 shows the deposition of the dummy gate electrode layer 40. The corresponding process is Fig. 22 The process flow 200 is shown as process 208. The dummy gate electrode layer 40 may be formed of or include polycrystalline silicon or amorphous silicon, but other materials may also be used. The formation process may include a deposition process followed by a planarization process. A hard mask layer 42 is then deposited on the dummy gate electrode layer 40. The corresponding process is shown in FIG. Fig. 22 This is shown as process 212 in the illustrated process flow 200. The hard mask layer 42 may be formed of or include silicon nitride, silicon oxide, silicon oxycarbonitride, or multiple layers thereof.

[0024] Figure 6FIG. 4 shows a patterning process for forming a dummy gate stack 44. The corresponding process is Fig. 22 The process flow 200 is shown as process 210. According to some embodiments, the hard mask layer 42 is first patterned, for example, using a patterned photoresist (not shown) as an etching mask. The resulting hard mask is referred to as hard mask 42'. The underlying dummy gate electrode layer 40 is then etched using hard mask 42' as an etching mask to form dummy gate electrode 40'. The etching is performed using an anisotropic etching process.

[0025] According to an alternative embodiment, the patterning of the dummy gate electrode layer 40 stops on the dummy gate dielectric layer 38 and the dummy gate dielectric layer 38 is not patterned. The gate spacers formed subsequently will be formed on the dummy gate dielectric layer 38 which is not patterned.

[0026] Next, if Figure 7 As shown in FIG. 4 , a gate spacer 46 is formed on the sidewall of the dummy gate stack 44. The corresponding process is Fig. 22 The process flow 200 is shown as process 212. According to some embodiments, the gate spacers 46 are formed of dielectric material(s) (eg, silicon nitride, silicon carbonitride, etc.) and may have a single layer structure or a multi-layer structure including multiple dielectric layers.

[0027] refer to Figure 8 , performing (one or more) etching processes to recess the protruding fins 36. The corresponding process is Fig. 22 The process flow 200 shown is shown as process 214. If there is any portion of the dummy gate dielectric layer 38 that is not directly under the dummy gate stack 44 and the gate spacer 46, the exposed portion of the dummy gate dielectric layer 38 is also removed. The portion of the protruding fin 36 that is not covered by the dummy gate stack 44 and the gate spacer 46 is also etched. The recess can be anisotropic, so the portion of the protruding fin 36 that is directly under the dummy gate stack 44 and the gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24T of the STI region 24. Thus, a recess 50 is formed. The recess 50 includes some portions on the opposite side of the dummy gate stack 44, and some portions between the remaining portions of the protruding fin 36. There may or may not be fin spacers left on the opposite side of the recess 50, which are not shown.

[0028] Next, if Fig. 9C As shown, an epitaxial region (source / drain region) 54 is formed by selectively growing (through epitaxy) a semiconductor material from the recess 50. The corresponding process is Fig. 22This is shown in the illustrated process flow 200 as process 216 . Fig. 9A and Fig. 9B They are shown respectively Fig. 9C Vertical cross-sections 9A-9A and 9B-9B of the structure are shown.

[0029] Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, different materials can be grown in the epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP), etc. can be grown. According to alternative embodiments, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the foregoing items, or multiple layers of the foregoing items.

[0030] After the recess 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 may cause the epitaxial region 54 to expand horizontally, and a facet may be formed. Further growth of the epitaxial region 54 may also cause adjacent epitaxial regions 54 to merge with each other. A void (air gap) 56 may be generated. After the epitaxial step, the epitaxial region 54 may be further implanted with p-type or n-type impurities, which are also indicated using reference numeral 54. According to an alternative embodiment, the implantation step is skipped when the epitaxial region 54 is in-situ doped with p-type or n-type impurities during epitaxy.

[0031] Next, if Fig. 10A and Fig. 10B As shown, an inhibitor film 57 is selectively formed. The corresponding process is Fig. 22 The process flow 200 is shown as process 218. According to some embodiments, the inhibitor film 57 is formed by a deposition process, wherein the wafer 10 is exposed to and immersed in a process gas (precursor) to deposit the inhibitor film 57 thereon. The deposition is performed without turning on the plasma. The deposition temperature can be in a range between about 50° C. and about 300° C., or in a range between about 50° C. and about 200° C., depending on the process gas. The deposition time can be in a range between about 30 seconds and about 60 minutes. During the deposition, the flow rate of the process gas can be in a range between about 500 sccm and about 10,000 sccm.

[0032] The process gas may include a silane-based material, an amine-based material, a phosphate-based material, and / or a thiol-based material. Example process gases may include Si-Cl-based process gases including octadecyltrichlorosilane (CH3(CH2) 17SiCl3), trichloro(1H,1H,2H,2H-perfluorooctyl)silane (CF3(CF2)5(CH2)2SiCl3), dimethyldichlorosilane ((CH3)2SiCl2), (dimethylamino)trimethylsilane ((CH3)2NSi(CH3)3), 1-(trimethylsilyl)pyrrolidine ((CH3)3Si-NC4H8), hexamethyldisilazane ([(CH3)3Si]2NH), bis(dimethylamino)dimethylsilane ([(CH3)2N]2Si(CH3)2), etc. or a combination of the foregoing.

[0033] According to an alternative embodiment, the inhibitor film 57 is formed by soaking the wafer 10 in a chemical solution, wherein one or more of the above-mentioned chemicals or SiO2-based chemicals are dissolved in a solvent. The solvent may include acetone or isopropyl alcohol (IPA). In some other embodiments, the solvent may include demineralized water. The soaking time may be in a range between about 30 seconds and about 60 minutes.

[0034] According to some embodiments, the exposed dielectric materials of wafer 10 (these dielectric materials may include silicon and / or oxide) have OH bonds on their surfaces. The exposed materials may be included in gate spacers 46, hard masks 42', and STI regions 24. When inhibitor film 57 is formed, the OH bonds are broken, and oxygen atoms on the surface of the exposed dielectric material are bonded to molecules in a precursor for forming inhibitor film 57. Therefore, the functional groups in the precursor are connected to oxygen in the underlying dielectric layer (e.g., gate spacers 46, hard masks 42', and STI regions 24), thereby forming inhibitor film 57.

[0035] However, there is no OH bond on the source / drain region 54, and even if the source / drain region 54 is also exposed to the same precursor, this reaction does not occur on the source / drain region 54. Therefore, the inhibitor film 57 is selectively formed on the top surface and sidewalls of the exposed semiconductor region (e.g., the gate spacer 46, the hard mask 42' and the STI region 24), but is not formed on the source / drain region 54. The inhibitor film 57 can be formed as a self-assembled monolayer (SAM). The corresponding process can also be referred to as a SAM process, in which the previously connected molecules terminate the dangling bonds of oxygen, so that no more layers of the inhibitor film 57 can be formed thereon. Therefore, the formation of the inhibitor film 57 can be self-terminating. Depending on the size of the connected molecules, the inhibitor film 57 can have a thickness in the range between about 0.3 nm and about 2 nm.

[0036] Thus, the inhibitor film 57 is selectively formed / deposited. In addition, the inhibitor film 57 may be an organic film and may include functional groups CH3, CH2, CF2, or a combination of the foregoing. The inhibitor film 57 may also include a carbon chain (and a CH3 chain) in which a plurality of carbon atoms are connected to form a chain.

[0037] Fig.11A and Fig. 11B 1 shows the selective deposition of a contact etch stop layer (CESL) 58 according to some embodiments. Fig. 22 The process flow 200 is shown as process 220. The CESL 58 is also an etch stop layer for stopping etching in subsequent processes. According to some embodiments, the formation process may include a thermal deposition process, such as a chemical vapor deposition (CVD) process, an atomic vapor deposition (CVD) process, etc. The deposited CESL 58 may include silicon nitride, silicon carbonitride, silicon carbon nitride oxide, etc., wherein corresponding precursors are performed to produce reactions.

[0038] Due to the presence of the inhibitor film 57, the CESL 58 is selectively grown where the inhibitor film 57 is not formed, and is thus formed on the source / drain region 54. Fig. 11B As shown, the source / drain region 54 may include an upward facing surface and may or may not include a downward facing surface. The downward facing surface may be a downward facing facet surface.

[0039] According to some embodiments, depending on the deposition method and process conditions, the formation of CESL 58 is conformal so that both the upward-facing and downward-facing surfaces have CESL 58 grown thereon. According to alternative embodiments, the upward-facing surfaces of source / drain regions 54 have CESL 58A grown thereon, while some or all portions of the downward-facing surfaces of source / drain regions 54 do not have CESL thereon. Therefore, portions 58B of CESL 58 are marked as dashed lines to indicate that these portions may or may not be formed.

[0040] Next, the inhibitor film 57 is removed. The corresponding process is Fig. 22 This is shown in the illustrated process flow 200 as process 222 . Fig. 12A , Fig. 12B and Fig. 12CThe resulting structure is shown. Depending on the thickness of the inhibitor film 57, the CESL 58 may or may not extend into the region 59 previously occupied by the inhibitor film 57. In other words, the CESL 58 may be spaced apart from the nearest dielectric feature by the space in the region 59. According to some embodiments, the removal of the inhibitor film 57 is performed by a thermal process. For example, the temperature may be above about 200° C. or above about 300° C. A process gas including O2, H2, N2, etc. or a combination of the foregoing may be used. As a result, the inhibitor film 57 is decomposed into a gas and removed.

[0041] Fig.13 FIG. 2 shows a perspective view of forming an interlayer dielectric (ILD) 60. The corresponding process is Fig. 22 The process flow 200 is shown as process 224. The ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. The ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), etc. A planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to make the top surfaces of the ILD 60, the dummy gate stack 44, and the gate spacers 46 flush with each other. Due to the selective formation of the CESL 58, the ILD 60 may be in physical contact with the top surface of the STI region 24. As shown in FIG. Fig.13 As shown, ILD 60 is at the bottom of the downward facing facets of source / drain regions 54 , and the ILD may be in physical contact with source / drain regions 54 .

[0042] Then, the hard mask 42', the dummy gate electrode 40' and the dummy gate dielectric 38' are removed to form a trench 62 between the gate spacers 46. Fig.14 The corresponding process is Fig. 22 The process flow 200 is shown as process 226. According to some embodiments, using Figure 6 The removal of the dummy gate electrode 40' is performed using an anisotropic etching process similar to the patterning process shown. According to an alternative embodiment, the removal of the dummy gate electrode 40' is performed using an isotropic etching process, which can be a wet etching process or a dry etching process. After removing the dummy gate electrode 40', the dummy gate dielectric 38' is exposed through the trench 62.

[0043] Next, the dummy gate dielectric 38' is removed. According to some embodiments, the etching process may be anisotropic, and the process gas may include a mixture of NF3 and NH3, or a mixture of HF and NH3. The etching process may include an isotropic effect and some anisotropic effect to ensure that the sidewall portion of the dummy gate dielectric 38' is removed. According to alternative embodiments, an isotropic etching process may be used, such as a wet etching process. For example, an HF solution may be used. The top surface and sidewalls of the protruding semiconductor fin 36 are thus exposed to the trench 62, such as Fig.14 shown.

[0044] Next, if Fig.15 As shown in FIG. , a replacement gate stack 68 is formed. The corresponding process is shown in FIG. Fig. 22 The process flow 200 is shown as process 228. According to some embodiments, the replacement gate stack 68 includes a gate dielectric 64 and a gate electrode 68. The gate dielectric 64 may also include an interfacial layer (IL) and a high-k dielectric constant above the IL. According to some embodiments, the formation of the IL is formed by an oxidation process. The IL may include silicon oxide (SiO2). According to some embodiments, the IL is deposited. Next, a high-k dielectric layer is deposited over the IL. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc.

[0045] The gate electrode 66 is formed on and in contact with the gate dielectric 64. The gate electrode 66 may include a stacked layer, which may include a diffusion barrier layer (cap layer, not shown) and one or more work function layers on the diffusion barrier layer. The diffusion barrier layer may be formed of TiN, TiSiN, etc.

[0046] The work function layer determines the work function of the gate electrode 66 and includes at least one layer or a plurality of layers formed of different materials. The material of the work function layer can be selected according to whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer can include a TaN layer and a titanium aluminum (TiAl) layer on the TaN layer. When the FinFET is a p-type FinFET, the work function layer can include a TaN layer and a possible TiN layer.

[0047] After the work function layer is deposited, a barrier layer (e.g., a TiN layer) and a metal filling region are deposited to completely fill the trench 62. Next, a planarization process (e.g., a CMP process or a mechanical grinding process) is performed so that the top surface of the gate stack 68 is coplanar with the top surface of the ILD 60. Thus, the FinFET 100 is formed.

[0048] According to some embodiments, Fig.15As shown, the replacement gate stack 68 is etched back, resulting in a recess between the opposing gate spacers 46. Next, a hard mask 70 is formed over the replacement gate stack 68. The hard mask 70 is self-aligned with the underlying gate stack 68. The corresponding process is Fig. 22 The process flow 200 is shown as process 230. According to some embodiments, the formation of the hard mask 70 includes a deposition process for forming a blanket dielectric material filling the recess and a planarization process for removing excess dielectric material above the gate spacers 46 and the ILD 60. The hard mask 70 can be formed of, for example, silicon nitride or other similar dielectric materials. According to alternative embodiments, the replacement gate stack 68 is not recessed, and the hard mask 70 is not formed. Therefore, the hard mask 70 is shown as a dashed line to indicate that the hard mask 70 may or may not be formed.

[0049] In a subsequent process, the ILD 60 and the CESL 58 are etched to form source / drain contact openings 71, as shown in FIG. Fig.16A and Fig. 16B The corresponding process is Fig. 22 This is shown as process 232 in the illustrated process flow 200. Fig.15 5. The location of the source / drain contact opening 71 is also shown in FIG. In the formation process, an etching process is performed to etch the ILD 60 and form the source / drain contact opening 71, and the etching stops on the CESL 58. Next, the CESL 58 is etched to expose the underlying source / drain region 54.

[0050] In the subsequent process, Fig.16A and Fig. 16B As shown in FIG. 1 , a source / drain silicide layer 72 is formed. The corresponding process is Fig. 22 The process flow 200 is shown as process 234. The formation process may include depositing a metal layer extending into the opening 71 to contact the source / drain region 54, performing an annealing process to react the metal layer with the source / drain region 54 and form a source / drain silicide layer 72, and removing the metal layer.

[0051] Fig.17A and Fig. 17B The formation of source / drain contact plugs 74 is shown in FIG. Fig. 22 This is shown as process 236 in the illustrated process flow 200. According to some embodiments, the formation process may include: depositing a conductive material, which may include a metal material such as tungsten, cobalt, etc., performing a CMP process to remove excess portions of the metal material. Before depositing the conductive material, a conductive barrier layer such as a TiN layer may (or may not) be formed.

[0052] According to some embodiments, due to the selective formation of CESL 58, CESL 58 does not include vertical portions ( Fig. 12A and Fig. 12C ). This has two advantages. First, if the CESL 58 has vertical portions on the sidewalls of the gate spacers 46, the vertical portions will occupy space that could otherwise be used by the source / drain contact plugs 74, resulting in an increase in the resistance of the source / drain contact plugs 74. Therefore, by selectively forming the CESL 58, the source / drain contact plugs 74 are formed to be wider and therefore have a lower resistance.

[0053] In addition, CESL 58 has a higher dielectric constant (k value) than that of ILD 60. For example, ILD 60 may have a k value in a range between about 3.1 and about 3.9. On the other hand, CESL 58 may have a k value between about 4 and about 7. By not forming a vertical portion of CESL 58, parasitic capacitance between source / drain contact plugs 74 and gate electrode 66 is reduced.

[0054] Fig.18A and Fig.18B 1 shows the selective formation of an inhibitor film 80 on a dielectric material (which may have OH groups on the surface) according to some embodiments. Fig. 22 This is shown as process 238 in the illustrated process flow 200. According to some embodiments, the precursor, material, and formation process of inhibitor film 80 may be selected from the same set of candidate precursors, candidate materials, and candidate formation processes of inhibitor film 57, respectively, and thus are not repeated. Fig.18A and Fig.18B As shown, an inhibitor film 80 is formed on the ILD 60. When the hard mask 70 is formed, the inhibitor film 80 may be formed on the hard mask 70. Depending on the material of the gate spacer 46, the inhibitor film 80 may or may not be formed on the top of the gate spacer 46. On the other hand, the inhibitor film 80 is not formed on the source / drain contact plugs 74.

[0055] Next, if Fig.18A and Fig.18B As shown, CESL 82 (which is also an etch stop layer, also indicated as 82SD) is selectively deposited. The corresponding process is Fig. 22238 in the illustrated process flow 200. Due to the presence of the inhibitor film 80, the CESL 82 is selectively deposited where the inhibitor film 80 is not formed. Therefore, the CESL 82 is selectively formed on the source / drain contact plugs 74. According to some embodiments in which the inhibitor film 80 is not formed on the top surface of the gate spacer 46, the CESL 82 is also formed on the top surface of the gate spacer 46. Otherwise, the CESL 82 is not formed on the top surface of the gate spacer 46, such as Fig.18A shown.

[0056] After forming the CESL 82, the inhibitor film 80 is removed, for example, in a thermal process using H2, N2 and / or O2 as process gases. Fig. 22 The process flow 200 is shown as process 240 .

[0057] Figure 19A-1 FIG. 2 shows a cross-sectional view of forming an ILD 86 and contact plugs 88 (including a gate contact plug 88A and a source / drain contact plug 88B) according to some embodiments. Fig. 22 The process flow 200 is shown as process 242. According to these embodiments in which the hard mask 70 is formed, an inhibitor film 80 ( Fig.18A ), and thus CESL 82 (also indicated as CESL 82SD) will not be formed on hard mask 70. ILD 86 is therefore in physical contact with hard mask 70. The dashed portion of CESL 82 indicates that CESL 82 may or may not be formed on gate spacers 46.

[0058] In a subsequent process, contact plugs 88 (including gate contact plug 88A and source / drain contact plugs 88B) are formed. The formation process may include etching ILD 86, hard mask 70, and CESL 82SD to form openings, filling the openings with a conductive material (e.g., tungsten, cobalt, copper, TiN, etc.), and performing a planarization process to remove excess conductive material.

[0059] In a subsequent process, an etch stop layer 92 may be selectively formed on the contact plugs 88A and 88B. The formation may include selectively forming an inhibitor film 90 on the ILD 86 but not on the contact plugs 88, and selectively depositing the etch stop layer 92 where the inhibitor film 90 is not formed. The inhibitor film 90 may then be removed. An intermetallic dielectric (IMD) layer (not shown) (which may be a low-k dielectric layer) may then be formed over the CESL 82 and the ILD 86. A metal via (which may be part of a single damascene structure or a dual damascene structure) may then be formed to penetrate the IMD layer and the etch stop layer 92.

[0060] Figure 19A-2 1 shows an embodiment in which the replacement gate stack 68 is not recessed and the hard mask 70 is not formed. Therefore, no inhibitor film will be formed on the replacement gate electrode 66 (refer to Fig.18A ), thereby allowing CESL 82 (also denoted as CESL 82G, Figure 19A-2 ) are formed just above and vertically aligned with the replacement gate electrode 66. Thus, the gate contact plug 88A and the source / drain contact plug 88B penetrate the portion 82G and the portion 82SD of the CESL 82, respectively, to contact the gate electrode 66 and the source / drain contact plug 74, respectively.

[0061] Fig.19B A cross-sectional view is shown, showing the source / drain contact plug 74. An etch stop layer 92 is also selectively formed over the source / drain contact plug 88B, and is formed where the inhibitor film 90 is not formed.

[0062] Fig. 20 An embodiment is shown in which a CESL and an etch stop layer are selectively formed by using an inhibitor film and applied to a GAA transistor 100 ′ according to some embodiments. Fig. 20 The structure shown is obtained from a cross section through a replacement gate stack 68', which includes a gate dielectric 64' and a gate electrode 66'. A semiconductor nanostructure 69 is surrounded by the gate stack 68' to act as a channel. The structure of the source / drain region 54 of the GAA transistor 100' is substantially the same as Fig. 16B , 17B , 18B and 19B are the same.

[0063] Fig.21 A top view of transistor 100 is shown in accordance with some embodiments. Figure 19A-1 or Figure 19A-2 The cross-sectional view can be viewed from Fig.21 The section AA in (also refer to Fig.15 Section AA in the figure). Figure 19A-1 or Figure 19A-2 Gate contact plugs 88A are also shown in the cross-sectional view of FIG. Fig.21 Outside the cross section shown. Fig.19B The cross-sectional view can be viewed from Fig.21 The cross section BB in the Fig.15 Section BB in the figure).

[0064] Embodiments of the present disclosure have some advantageous features. By selectively forming an etch stop layer (which includes a contact etch stop layer and other etch stop layers) on the feature where the contact is to be formed rather than on the surrounding dielectric layer, the size of the etch stop layer is reduced. Because the etch stop layer can have a higher k value than the nearby interlayer dielectric, reducing the size of the etch stop layer promotes a reduction in parasitic capacitance. In addition, the reduction in the size of the selectively formed etch stop layer creates some space for forming a contact plug and reduces the resistance of the contact plug.

[0065] According to some embodiments, a method includes: forming a gate stack over a semiconductor region; performing an epitaxial process to form a source / drain region next to the gate stack; forming a source / drain contact plug over the source / drain region and electrically coupled to the source / drain region; forming a gate contact plug over the gate stack and electrically coupled to the gate stack; selectively forming a first inhibitor film on a dielectric layer near a conductive feature, wherein the conductive feature is selected from the group consisting of a source / drain region, a source / drain contact plug, and a gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon; and removing the first inhibitor film.

[0066] In an embodiment, the conductive feature includes a source / drain region, and wherein the first inhibitor film includes a portion on the shallow trench isolation near the source / drain region. In an embodiment, the structure further includes: selectively forming a second inhibitor film on the second dielectric layer near the source / drain contact plug; selectively depositing a second etch stop layer on the source / drain contact plug; and removing the second inhibitor film. In an embodiment, the second etch stop layer also includes a portion located directly above the gate stack and in contact with the gate stack. In an embodiment, the structure further includes: recessing the gate stack to form a recess; and forming a hard mask in the recess, wherein the first inhibitor film includes a portion located directly above the hard mask and in contact with the hard mask.

[0067] In an embodiment, the first etch stop layer is selectively deposited by soaking the conductive features in a precursor. In an embodiment, the first etch stop layer is selectively deposited using a silane-containing precursor. In an embodiment, the first inhibitor film is removed by a thermal process. In an embodiment, the thermal process is performed using a precursor including hydrogen (H2). In an embodiment, the first inhibitor film includes carbon.

[0068] According to some embodiments, a structure includes: a semiconductor region; a gate stack located above the semiconductor region; a source / drain region located next to the gate stack; a source / drain silicide region located above and in contact with the source / drain region; a shallow trench isolation region located next to the source / drain region; a first contact etch stop layer located on the source / drain region; and an interlayer dielectric located above the first contact etch stop layer, wherein the interlayer dielectric is in physical contact with both the first contact etch stop layer and the shallow trench isolation region. In an embodiment, the structure further includes: a source / drain contact plug located in the interlayer dielectric and the first contact etch stop layer, wherein the source / drain contact plug is in contact with the source / drain silicide region.

[0069] In an embodiment, the structure further comprises: a second contact etch stop layer in contact with a top surface of the source / drain contact plug; and an additional interlayer dielectric located above and in contact with both the second contact etch stop layer and the interlayer dielectric. In an embodiment, the first contact etch stop layer comprises a first portion located directly above a top surface of the source / drain region.

[0070] In an embodiment, the source / drain region includes a downwardly facing surface, and the interlayer dielectric is in physical contact with the downwardly facing surface. In an embodiment, the source / drain region includes a downwardly facing surface, and the first contact etch stop layer includes a second portion in physical contact with the downwardly facing surface. In an embodiment, the entire first contact etch stop layer is physically spaced apart from the shallow trench isolation region.

[0071] According to some embodiments, a structure includes: a semiconductor substrate; a dielectric isolation region located in the semiconductor substrate; a semiconductor fin adjacent to and higher than a top surface of the dielectric isolation region; a gate stack located on the semiconductor fin; a source / drain region coupled to the semiconductor fin and the gate stack; a source / drain silicide region located on the source / drain region; a contact etch stop layer located on the source / drain region and spaced apart from the dielectric isolation region; an interlayer dielectric located on the contact etch stop layer and in contact with the contact etch stop layer, wherein the interlayer dielectric is also in contact with the dielectric isolation region; and a source / drain contact plug located above the source / drain silicide region and in contact with the source / drain silicide region.

[0072] In an embodiment, the interlayer dielectric is also in physical contact with the source / drain regions. In an embodiment, the interlayer dielectric is in physical contact with downward facing surfaces of the source / drain regions and is spaced apart from upward facing surfaces of the source / drain regions.

[0073] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0074] Example

[0075] Example 1. A method for forming a semiconductor structure, comprising: forming a gate stack above a semiconductor region; performing an epitaxial process to form a source / drain region next to the gate stack; forming a source / drain contact plug above the source / drain region and electrically coupled to the source / drain region; forming a gate contact plug above the gate stack and electrically coupled to the gate stack; selectively forming a first inhibitor film on a dielectric layer near a conductive feature, wherein the conductive feature is selected from the group consisting of the source / drain region, the source / drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon; and removing the first inhibitor film.

[0076] Example 2. The method of Example 1, wherein the conductive feature includes the source / drain region, and wherein the first inhibitor film includes a portion on a shallow trench isolation near the source / drain region.

[0077] Example 3. The method according to Example 2 further includes: selectively forming a second inhibitor film on the second dielectric layer near the source / drain contact plug; selectively depositing a second etch stop layer on the source / drain contact plug; and removing the second inhibitor film.

[0078] Example 4. The method of Example 3, wherein the second etch stop layer further includes a portion directly above the gate stack and in contact with the gate stack.

[0079] Example 5. The method according to Example 1 further includes: recessing the gate stack to form a recess; and forming a hard mask in the recess, wherein the first inhibitor film includes a portion located directly above and in contact with the hard mask.

[0080] Example 6. The method of Example 1, wherein the first etch stop layer is selectively deposited by immersing the conductive features in a precursor.

[0081] Example 7. The method of Example 6, wherein the first etch stop layer is selectively deposited using a silane-containing precursor.

[0082] Example 8. The method of Example 1, wherein the first inhibitor film is removed by a thermal process.

[0083] Example 9. The method of Example 8, wherein the thermal process is performed using a precursor comprising hydrogen (H2).

[0084] Example 10. The method of Example 1, wherein the first inhibitor film comprises carbon.

[0085] Example 11. A semiconductor structure comprising: a semiconductor region; a gate stack located above the semiconductor region; a source / drain region located next to the gate stack; a source / drain silicide region located above and in contact with the source / drain region; a shallow trench isolation region located next to the source / drain region; a first contact etch stop layer located on the source / drain region; and an interlayer dielectric located above the first contact etch stop layer, wherein the interlayer dielectric is in physical contact with both the first contact etch stop layer and the shallow trench isolation region.

[0086] Example 12. The semiconductor structure according to Example 11 further includes: a source / drain contact plug located in the interlayer dielectric and the first contact etch stop layer, wherein the source / drain contact plug is in contact with the source / drain silicide region.

[0087] Example 13. The semiconductor structure according to Example 12 further includes: a second contact etch stop layer, which is in contact with the top surface of the source / drain contact plug; and an additional interlayer dielectric, which is located above both the second contact etch stop layer and the interlayer dielectric and is in contact with both the second contact etch stop layer and the interlayer dielectric.

[0088] Example 14. The semiconductor structure of Example 11, wherein the first contact etch stop layer includes a first portion directly above a top surface of the source / drain region.

[0089] Example 15. The semiconductor structure of Example 14, wherein the source / drain regions include a downward-facing surface, and the interlayer dielectric is in physical contact with the downward-facing surface.

[0090] Example 16. The semiconductor structure of Example 14, wherein the source / drain region includes a downward-facing surface, and the first contact etch stop layer includes a second portion in physical contact with the downward-facing surface.

[0091] Example 17. The semiconductor structure of Example 11, wherein the entire first contact etch stop layer is physically separated from the shallow trench isolation region.

[0092] Example 18. A semiconductor structure comprising: a semiconductor substrate; a dielectric isolation region located in the semiconductor substrate; a semiconductor fin adjacent to and higher than a top surface of the dielectric isolation region; a gate stack located on the semiconductor fin; a source / drain region coupled to the semiconductor fin and next to the gate stack; a source / drain silicide region located on the source / drain region; a contact etch stop layer located on the source / drain region and spaced apart from the dielectric isolation region; an interlayer dielectric located on the contact etch stop layer and in contact with the contact etch stop layer, wherein the interlayer dielectric is also in contact with the dielectric isolation region; and a source / drain contact plug located above the source / drain silicide region and in contact with the source / drain silicide region.

[0093] Example 19. The semiconductor structure of Example 18, wherein the interlayer dielectric is also in physical contact with the source / drain regions.

[0094] Example 20. The semiconductor structure of Example 18, wherein the interlayer dielectric is in physical contact with downward-facing surfaces of the source / drain regions and is spaced apart from upward-facing surfaces of the source / drain regions.

Claims

1. A method for forming a semiconductor structure, comprising: forming a gate stack over the semiconductor region; performing an epitaxial process to form source / drain regions next to the gate stack; forming a source / drain contact plug over the source / drain region and electrically coupled to the source / drain region; forming a gate contact plug over the gate stack and electrically coupled to the gate stack; selectively forming a first inhibitor film on the dielectric layer near a conductive feature, wherein the conductive feature is selected from the group consisting of the source / drain region, the source / drain contact plug, and the gate contact plug; selectively depositing a first etch stop layer on the conductive feature, wherein the first inhibitor film prevents the first etch stop layer from being deposited thereon; and The first inhibitor film is removed.

2. The method according to claim 1, wherein: The conductive feature includes the source / drain region, and wherein the first inhibitor film includes a portion on a shallow trench isolation near the source / drain region.

3. The method according to claim 2, further comprising: selectively forming a second inhibitor film on the second dielectric layer near the source / drain contact plug; selectively depositing a second etch stop layer on the source / drain contact plugs; as well as The second inhibitor film is removed.

4. The method according to claim 3, wherein: The second etch stop layer also includes a portion located directly above the gate stack and in contact with the gate stack.

5. The method according to claim 1, further comprising: recessing the gate stack to form a recess; as well as A hard mask is formed in the recess, wherein the first inhibitor film includes a portion located directly above and in contact with the hard mask.

6. The method according to claim 1, wherein: The first etch stop layer is selectively deposited by immersing the conductive features in a precursor.

7. The method according to claim 6, wherein: The first etch stop layer is selectively deposited using a silane-containing precursor.

8. The method according to claim 1, wherein: The first inhibitor film is removed by a thermal process.

9. A semiconductor structure comprising: Semiconductor region; A gate stack located above the semiconductor region; a source / drain region located next to the gate stack; a source / drain silicide region located above and in contact with the source / drain region; A shallow trench isolation region located next to the source / drain region; A first contact etch stop layer, located on the source / drain region; as well as An interlayer dielectric is located on the first contact etch stop layer, wherein the interlayer dielectric is in physical contact with both the first contact etch stop layer and the shallow trench isolation region.

10. A semiconductor structure comprising: Semiconductor substrate; a dielectric isolation region located in the semiconductor substrate; a semiconductor fin adjacent to and taller than a top surface of the dielectric isolation region; A gate stack located on the semiconductor fin; a source / drain region coupled to the semiconductor fin and adjacent to the gate stack; a source / drain silicide region, located on the source / drain region; a contact etch stop layer on the source / drain region and spaced apart from the dielectric isolation region; an interlayer dielectric located on the contact etch stop layer and in contact with the contact etch stop layer, wherein the interlayer dielectric is also in contact with the dielectric isolation region; as well as The source / drain contact plug is located on the source / drain silicide region and contacts the source / drain silicide region.

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