N-type semiconductor device, semiconductor device and manufacturing method thereof, chip and electronic equipment

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an N-type semiconductor device, a semiconductor device and a manufacturing method thereof, a chip and electronic equipment, and the manufacturing method of the N-type semiconductor device comprises the steps: providing a substrate with a gate structure; performing multiple pre-amorphization injection on the substrate at two sides of the gate structure; wherein, except for the last time of pre-amorphization injection, low-temperature annealing treatment is carried out after each time of pre-amorphization injection; and performing source and drain injection on the substrate at two sides of the gate structure after the last pre-amorphization injection to form a source electrode and a drain electrode. According to the technical scheme, multiple times of pre-amorphization injection is carried out on the substrate on the two sides of the gate structure, and in the subsequent annealing process, the volume of the substrate in the source-drain region expands when the substrate is converted from an amorphous state to a crystalline state to generate a stress effect on a channel, so that the tensile stress of the channel is improved, and the electron mobility can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to an N-type semiconductor device, a semiconductor device and a manufacturing method thereof, a chip and an electronic device. Background Art

[0002] In the past, the semiconductor industry has continuously reduced the size of MOS devices in proportion to improve device performance and reduce device costs. However, when traditional silicon devices approach their physical limits, especially below 65nm, serious short channel effects will occur, the tunneling current of the device gate oxide layer will be large, and the polysilicon gate resistance will increase. Therefore, the traditional method of reducing feature size to improve device performance will be limited by both cost and technology.

[0003] Stress Memorization Technique (SMT) is a process method that mainly improves the carrier mobility of the device channel and thus improves the device performance. SMT technology mainly uses silicon nitride with tensile stress to act on N-type semiconductor devices to transfer stress to the channel region of the semiconductor device, so that the channel region forms a stress structure that is conducive to increasing electron mobility, that is, a tensile stress structure. This stress structure in the channel region has a memory effect, that is, the stress will still remain after the silicon nitride is removed. However, this process is relatively complicated, and the existing SMT technology is more concerned with the improvement of the tensile stress of the channel by the polysilicon gate, and rarely considers the research on the stress improvement of the channel by the source and drain region. Summary of the invention

[0004] In order to solve the problems in the related art, the embodiments of the present disclosure provide an N-type semiconductor device, a semiconductor device and a manufacturing method thereof, a chip and an electronic device.

[0005] In a first aspect, the present disclosure provides a method for manufacturing an N-type semiconductor device, including:

[0006] providing a substrate having a gate structure formed thereon;

[0007] Performing multiple pre-amorphous implantation (PAI) implantations on the substrate at both sides of the gate structure; wherein, except for the last pre-amorphous implantation, a low-temperature annealing treatment is performed after each pre-amorphous implantation;

[0008] After the last pre-amorphization implantation, source and drain implantation is performed on the substrate at both sides of the gate structure to form a source and a drain;

[0009] The depth of the last pre-amorphization implantation is greater than the depth of the previous pre-amorphization implantation; and the depth of the source and drain implantation is not greater than the depth of the last pre-amorphization implantation.

[0010] In one embodiment of the present disclosure, the pre-amorphization implanted ions are germanium ions, silicon ions or indium ions.

[0011] In one embodiment of the present disclosure, the process parameters of the low temperature annealing treatment include an annealing temperature of 500-650° C. and an annealing time of 10-30 min.

[0012] In one embodiment of the present disclosure, it also includes:

[0013] Performing lightly doped drain implantation on the substrate at both sides of the gate structure;

[0014] Wherein, the lightly doped drain implantation is performed after the first pre-amorphization implantation and before the first low-temperature annealing treatment.

[0015] In one embodiment of the present disclosure, the doping ions of the lightly doped drain implantation include one or both of BF2 and phosphorus.

[0016] In one embodiment of the present disclosure, the depth of the lightly doped drain implantation is not greater than the depth of the first pre-amorphization implantation.

[0017] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a substrate, and an NMOS region and a PMOS region formed on the substrate; the NMOS region and the PMOS region are respectively formed with a gate structure, a source and a drain; wherein the source and the drain of the NMOS region are obtained by any of the manufacturing methods described above;

[0018] The manufacturing method further comprises:

[0019] forming a stress memory layer on the surfaces of the NMOS region and the PMOS region;

[0020] Ion doping is performed on the stress memory layer corresponding to the PMOS region, and then a spike annealing process is performed on the substrate.

[0021] In one embodiment of the present disclosure, the doping ions of the ion doping include germanium ions, silicon ions, indium ions or arsenic ions.

[0022] In a third aspect, an embodiment of the present disclosure provides an N-type semiconductor device manufactured by the method for manufacturing an N-type semiconductor device described in any one of the first aspects.

[0023] In a fourth aspect, an embodiment of the present disclosure provides a semiconductor device manufactured using the semiconductor device manufacturing method described in any one of the second aspects.

[0024] In a fifth aspect, a chip is provided in an embodiment of the present disclosure, comprising the N-type semiconductor device described in the third aspect or the semiconductor device described in the fourth aspect.

[0025] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, comprising the N-type semiconductor device described in the third aspect or the semiconductor device described in the fourth aspect.

[0026] The technical effects provided by the embodiments of the present disclosure may include the following beneficial effects:

[0027] According to the technical solution provided by the embodiment of the present disclosure, a method for manufacturing an N-type semiconductor device includes: providing a substrate formed with a gate structure; performing multiple pre-amorphization injections on the substrate on both sides of the gate structure; wherein, except for the last pre-amorphization injection, a low-temperature annealing treatment is performed after each pre-amorphization injection; performing source and drain injections on the substrate on both sides of the gate structure after the last pre-amorphization injection to form a source and a drain; wherein the depth of the last pre-amorphization injection is greater than the depth of the previous pre-amorphization injection; and the depth of the source and drain injection is not greater than the depth of the last pre-amorphization injection. The above technical solution utilizes multiple pre-amorphization injections on the substrate on both sides of the gate structure. In the subsequent annealing process, the substrate in the source and drain regions undergoes volume expansion when it changes from an amorphous state to a crystalline state, which produces stress on the channel, thereby increasing the tensile stress of the channel, and thus being able to improve the electron mobility.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings.

[0030] Figure 1 A flow chart showing a method for manufacturing an N-type semiconductor device according to an embodiment of the present disclosure is shown.

[0031] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 A schematic diagram showing steps of manufacturing an N-type semiconductor device according to an embodiment of the present disclosure is shown.

[0032] Figure 8 A schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0034] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, behaviors, components, parts, or a combination thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof exist or are added.

[0035] It should also be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] As mentioned above, the existing SMT technology focuses more on improving the tensile stress of the channel by the polysilicon gate, and rarely considers the stress enhancement of the channel by the source and drain region positions.

[0037] In view of the above defects, the present disclosure provides a method for manufacturing an N-type semiconductor device, comprising: providing a substrate formed with a gate structure; performing multiple pre-amorphization injections on the substrate on both sides of the gate structure; wherein, except for the last pre-amorphization injection, a low-temperature annealing treatment is performed after each pre-amorphization injection; after the last pre-amorphization injection, source and drain injections are performed on the substrate on both sides of the gate structure to form a source and a drain. The above technical solution utilizes multiple pre-amorphization injections on the substrate on both sides of the gate structure, and in the subsequent annealing process, the stress of the substrate in the source and drain regions is retained when the amorphization to crystallization transitions, thereby increasing the tensile stress of the source and drain regions on the channel and improving the electron mobility.

[0038] Figure 1 A flow chart showing a method for manufacturing an N-type semiconductor device according to an embodiment of the present disclosure is shown.

[0039] like Figure 1As shown, the manufacturing method of an N-type semiconductor device includes steps S1 to S5. Step S1 is to provide a substrate with a gate structure formed thereon; steps S2 to S4 are to perform multiple PAI injections (i.e., pre-amorphization injections), and except for the last PAI injection, a low-temperature annealing treatment is performed after each PAI injection; in the disclosed method, multiple PAI injections are performed on the substrate on both sides of the gate structure; after the last PAI injection in step S4, the S / D injection (i.e., source-drain injection) of step S5 is performed; in the disclosed method, source-drain injections are performed on the substrate on both sides of the gate structure to form a source and a drain. In the present disclosure, only three PAI injections are used as an example for schematic illustration. It can be understood that, as needed, before the last PAI injection, a third PAI injection or more PAI injections can be performed, and the present disclosure does not limit this. In addition, each PAI injection can also use the same or different process parameters, which can be flexibly adjusted by those skilled in the art.

[0040] like Figure 1 and Figure 2 As shown, step S1 is first performed to provide a substrate with a gate structure. In the disclosed method, an insulating structure 101 is formed in the substrate 100, such as a shallow trench isolation structure (STI) to provide an electrical isolation function. The material of the substrate 100 may include semiconductor materials such as single crystal silicon, polycrystalline silicon, amorphous silicon, germanium, silicon germanium or gallium arsenide. The material of the insulating structure 101 may be a dielectric material, such as silicon dioxide. The gate structure is formed on the substrate 100, and the gate structure includes a gate layer 102. The gate layer 102 includes a gate dielectric layer 102a, a gate material layer 102b and a hard mask 102c from bottom to top. The gate dielectric layer 102a may include silicon dioxide, silicon nitride or a high dielectric constant (high-k) material. The gate material layer 102b may include a conductive material such as polycrystalline silicon, a metal material or a metal silicide. The gate layer 102 may be manufactured by forming a gate stack on the substrate 100 . The gate stack includes a gate dielectric layer, a gate material layer, and a hard mask from bottom to top. The gate stack is then patterned to obtain the gate layer 102 .

[0041] The gate structure may further include a gate spacer 103, which is disposed around the sidewall of the gate layer 102 to protect the gate layer 102 during the subsequent PAI injection process. The material of the gate spacer 103 may include oxide and / or nitride, such as silicon dioxide, silicon nitride, silicon oxyammonium, or silicon carbide nitride. The gate spacer 103 may be a single-layer structure, such as a single-layer silicon oxide or silicon nitride, or a stacked structure, such as forming a silicon oxide layer on the sidewall of the gate layer 102, and then forming a silicon nitride layer on the sidewall of the silicon oxide layer.

[0042] Perform step S2, such as Figure 1 and Figure 3 As shown, the insulating structure 101 in the substrate 100 is omitted in the figure, and the substrate on both sides of the gate structure is subjected to the first PAI injection 310, and the injection depth is recorded as d1 to form a first injection area 210. The dotted line portion in the figure indicates that the injected ions may diffuse laterally in the substrate. The injected ions can be germanium ions, silicon ions or indium ions, the ion injection dose range can be 3E14-5E14, the energy can be 10-25k, the tilt angle is 0°, the rotation angle is 0° and the number of rotations is 0 times. Then the first low-temperature annealing treatment is performed. During the annealing process, the volume expansion of the substrate in the first injection area 210 when it changes from an amorphous state to a crystalline state produces stress on the channel, thereby increasing the tensile stress of the channel and thereby increasing the electron mobility. The process parameters of the first low-temperature annealing treatment include an annealing temperature of 500-650°C and an annealing time of 10-30min.

[0043] like Figure 4 As shown, after the first PAI injection 310 and before the first low-temperature annealing treatment, LDD injection 311 may be performed on the substrate on both sides of the gate structure to form an LDD region 211. The first PAI injection 310 before the LDD injection 311 can avoid the punch-through effect caused by subsequent ion injection. The doping ions of the LDD injection 311 include one or both of BF2 and phosphorus. The injection depth of the LDD injection 311 is recorded as d2, and d2 is not greater than the depth d1 of the first PAI injection 310, that is, the LDD injection 311 is performed inside the first injection region 210, in order to avoid the range end defect problem caused by subsequent annealing.

[0044] Next, a sidewall spacer 104 may be formed around the sidewall of the gate sidewall 103 to accurately locate the subsequent source and drain injection positions. The material of the sidewall spacer 104 may include oxides and / or nitrides, such as silicon dioxide, silicon nitride, silicon oxyammonia, or silicon carbide nitride. The formation of the sidewall spacer 104 may be performed after step S2 or after step S3. In some cases, if the thickness of the gate sidewall 103 is sufficient to prevent leakage current, the sidewall spacer 104 may be omitted, and the present disclosure does not limit this. In the present disclosure, the subsequent steps S3 to S5 are schematically illustrated by taking the formation of the sidewall spacer 104 as an example.

[0045] Step S3 is performed. The present disclosure is described based on LDD injection as an example. Figure 1 and Figure 5 As shown, a second PAI injection 320 is performed on the substrate on both sides of the gate structure, and the injection depth is recorded as d3 to form a second injection area 220. In the disclosed method, the process parameters of the second PAI injection 320 are the same as those of the first PAI injection 310, that is, the injected ions, ion injection dose, energy, tilt angle, rotation angle and number of rotations are the same, and the injection depth d3 is also the same as d1. Then a second low-temperature annealing treatment is performed. During the annealing process, the volume expansion of the substrate in the second injection area 220 when it changes from an amorphous state to a crystalline state produces stress on the channel, thereby increasing the tensile stress of the channel and thereby increasing the electron mobility. The process parameters of the second low-temperature annealing treatment include an annealing temperature of 500-650°C and an annealing time of 10-30min.

[0046] Proceed to step S4, such as Figure 1 and Figure 6 As shown, the substrate on both sides of the gate structure is subjected to a final PAI injection 330, and the injection depth is recorded as d4 to form a third injection region 230. The injection depth d4 of the final PAI injection 330 is greater than the injection depth d1 of the first PAI injection 310 and the injection depth d3 of the second PAI injection 320, and the purpose is to form a heavily doped source and drain region, reduce the contact resistance of this region, and regulate the device threshold voltage.

[0047] Proceed to step S5, such as Figure 1 , Figure 6 and Figure 7 As shown, source and drain implantation 300 is performed on the substrate on both sides of the gate structure to form source and drain 200. Specifically, N-type impurities, such as arsenic, phosphorus, etc., can be implanted in the third implantation region 230 to form the source and drain. The last PAI implantation 330 before the source and drain implantation 300 can avoid the punch-through effect caused by subsequent ion implantation. The implantation depth of the source and drain implantation is not greater than the depth d4 of the last first PAI implantation 330, that is, the source and drain implantation 300 is performed inside the third implantation region 230, in order to avoid the range end defect problem caused by subsequent annealing.

[0048] Figure 8 A schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure is shown.

[0049] like Figure 8 As shown, the semiconductor device includes a substrate 100, and an NMOS region and a PMOS region formed on the substrate 100; in the formation region of the NMOS region, a P well 112a is formed in the substrate 100; in the formation region of the PMOS region, an N well 112b is formed in the substrate 100. An insulating structure 101 is also formed on the substrate 100, and an active region is defined by the insulating structure 101. The NMOS region and the PMOS region are respectively formed with a gate layer 102, and a gate sidewall 103 is formed on the side of the gate layer 102. After the gate sidewall 103 is formed, LDD injection is performed to form an LDD region. The LDD region of the NMOS is an N-type LDD region 211a, and the LDD region of the PMOS is a P-type LDD region 211b. After the sidewall 104 is formed, source and drain injection is performed to form a source and a drain. Figure 8 In the embodiment, the source and drain are symmetrically arranged. The source and drain of the NMOS region are respectively composed of N+ regions 200a located on both sides of the gate structure. The source and drain of the PMOS region are respectively composed of P+ regions 200b located on both sides of the gate structure.

[0050] In the present disclosure, embodiments provide Figure 8 The method for manufacturing a semiconductor device shown in FIG. 1 , wherein the source and drain of the NMOS region are formed by Figure 1 The manufacturing method of the LDD region, source and drain of the PMOS region obtained by the manufacturing method is referred to the prior art and will not be described in detail here. It should be noted that before the PAI injection, a mask layer is formed on the substrate of the POMS region to avoid damage to the PMOS region.

[0051] Furthermore, the manufacturing method further comprises:

[0052] forming a stress memory layer on the surfaces of the NMOS region and the PMOS region;

[0053] Ion doping is performed on the stress memory layer corresponding to the PMOS region, and then a spike annealing process is performed on the substrate.

[0054] In the disclosed method, the doped ions of the ion doping include germanium ions, silicon ions, indium ions or arsenic ions. In one embodiment, the doped particles are germanium ions, the ion implantation dose range is 4E14-6E14, the energy is 20-35k, the tilt angle is 0°, the rotation angle is 0° and the number of rotations is 0 times.

[0055] After forming the stress memory layer, ion doping is performed on the stress memory layer in the PMOS region. After spike annealing, the stress memory layer transfers the tensile stress to the channel region of the NMOS to improve the electron mobility of the NMOS. At the same time, the tensile stress of the stress memory layer in the PMOS region is eliminated, thereby reducing the tensile stress in the channel region of the PMOS, or even eliminating the tensile stress, so that the hole mobility of the PMOS is not affected.

[0056] Furthermore, a photoresist layer can be formed on the substrate 100, and the metal silicide formation area can be exposed through a mask, exposure, etc. After the metal silicide is formed, the photoresist layer is removed, and then an etch stop layer is formed on the surface of the NMOS region and the PMOS region.

[0057] Based on the same or similar inventive concept, the embodiment of the present disclosure further provides an N-type semiconductor device, using Figure 1 The N-type semiconductor device is manufactured by the manufacturing method.

[0058] As another aspect, an embodiment of the present disclosure further provides a chip, which includes the N-type semiconductor device or semiconductor device described in the above embodiments.

[0059] As another aspect, an embodiment of the present disclosure further provides an electronic device, which includes the N-type semiconductor device or semiconductor device described in the above embodiment.

[0060] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present disclosure is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other.

Claims

1. A method for manufacturing an N-type semiconductor device, characterized in that: include: providing a substrate having a gate structure formed thereon; Performing multiple pre-amorphization implantations on the substrate at both sides of the gate structure; wherein, except for the last pre-amorphization implantation, a low-temperature annealing treatment is performed after each pre-amorphization implantation; After the last pre-amorphization implantation, source and drain implantation is performed on the substrate at both sides of the gate structure to form a source and a drain; The depth of the last pre-amorphization implantation is greater than the depth of the previous pre-amorphization implantation; and the depth of the source and drain implantation is not greater than the depth of the last pre-amorphization implantation.

2. The method for manufacturing an N-type semiconductor device according to claim 1, characterized in that: The ions implanted for pre-amorphization are germanium ions, silicon ions or indium ions.

3. The method for manufacturing an N-type semiconductor device according to claim 1, characterized in that: The process parameters of the low temperature annealing treatment include an annealing temperature of 500-650° C. and an annealing time of 10-30 min.

4. The method for manufacturing an N-type semiconductor device according to claim 1, characterized in that: Also includes: Performing lightly doped drain implantation on the substrate at both sides of the gate structure; Wherein, the lightly doped drain implantation is performed after the first pre-amorphization implantation and before the first low-temperature annealing treatment.

5. The method for manufacturing an N-type semiconductor device according to claim 4, characterized in that: The doping ions of the lightly doped drain implantation include one or both of BF2 and phosphorus.

6. The method for manufacturing an N-type semiconductor device according to claim 4, characterized in that: The depth of the lightly doped drain implantation is not greater than the depth of the first pre-amorphization implantation.

7. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a substrate, and an NMOS region and a PMOS region formed on the substrate; the NMOS region and the PMOS region are respectively formed with a gate structure, a source and a drain; wherein the source and the drain of the NMOS region are obtained by the manufacturing method according to any one of claims 1 to 6; The manufacturing method further comprises: forming a stress memory layer on the surfaces of the NMOS region and the PMOS region; Ion doping is performed on the stress memory layer corresponding to the PMOS region, and then a spike annealing process is performed on the substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The doping ions of the ion doping include germanium ions, silicon ions, indium ions or arsenic ions.

9. An N-type semiconductor device manufactured by the method for manufacturing an N-type semiconductor device according to any one of claims 1 to 6.

10. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 7 to 8.

11. A chip, characterized in that: Includes the N-type semiconductor device according to claim 9 or the semiconductor device according to claim 10.

12. An electronic device, characterized in that: Includes the N-type semiconductor device according to claim 9 or the semiconductor device according to claim 10.

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