Metal connecting line forming process and semiconductor device

Abstract

The invention provides a metal connecting line forming process and a semiconductor device, and the metal connecting line forming process comprises the following steps: providing a substrate which comprises an insulating dielectric layer and a plurality of metal regions to be connected on the insulating dielectric layer; the method comprises the following steps: A, processing a substrate by using plasma to enable the surface of an insulating dielectric layer to be negatively charged; b, generating negatively charged ruthenium atoms by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and depositing a ruthenium metal layer in the metal area to be wired; and the step A and the step B are repeated, and the ruthenium metal layers are stacked to form the ruthenium metal connecting line. According to the metal connecting wire forming process, the ruthenium metal selectively grows on the substrate, the ruthenium metal layer is deposited on the metal area to be connected for multiple times, and compared with a copper metal connecting wire layer, the finally obtained ruthenium metal connecting wire has the advantages of being better in stability, not prone to diffusion, lower in resistance and the like. The metal connecting wire forming process can replace the existing Damascus copper metal connecting wire process.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a metal wiring forming process and a semiconductor device. Background Art

[0002] Since the introduction of semiconductor devices decades ago, the geometry of semiconductor devices has been drastically reduced in size. Modern semiconductor manufacturing equipment can routinely produce devices with critical dimensions (CD) such as 45nm, 32nm, 28nm, 14nm, 7nm, and 3nm. However, with the emergence of processes with smaller feature sizes, a series of problems have also arisen in the back-end metal wiring. For example, in the existing Damascus metal Cu wiring process, the groove must first be formed by photolithography and etching processes. However, during the formation of the groove, the profile of the groove is difficult to control and is prone to deformation. In particular, the overlap position is also prone to offset, which leads to disconnection.

[0003] Furthermore, in the semiconductor manufacturing process, the electrochemical plating (Electro Chemical Plating, ECP) ​​manufacturing process is one of the stages of the metallization manufacturing process, which mainly uses electric current to provide electrons to convert metal ions into metal atoms and deposit metal thin films on a certain interface. With the increase of aspect ratio, the electroplating copper process cannot meet the requirements of good trench filling, resulting in gaps (Seam) and voids (Void) when the trench is filled. In addition, as the line width decreases, the resistance of the copper metal connection also increases, and it cannot meet the requirements of more advanced process nodes.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a metal wiring formation process and a semiconductor device. The metal wiring formation process adopts the selective growth of ruthenium metal on a substrate to obtain ruthenium metal wiring. Compared with the copper metal wiring layer, the ruthenium metal wiring has the characteristics of better stability, less diffusion, lower resistance, etc. This process can replace the existing Damascus copper metal wiring process.

[0006] Specifically, the first aspect of the present invention provides a metal wiring forming process, the forming process comprising the following steps:

[0007] Providing a substrate, the substrate comprising an insulating dielectric layer and a plurality of metal regions to be connected on the insulating dielectric layer;

[0008] Step A: using plasma to treat the substrate so that the surface of the insulating dielectric layer is negatively charged;

[0009] Step B: using a PECVD deposition process to generate negatively charged ruthenium atoms and depositing a ruthenium metal layer in the metal area to be connected;

[0010] Repeat steps A and B, and multiple ruthenium metal layers are stacked to form ruthenium metal wiring.

[0011] According to the first aspect of the present invention, the reaction gas in the plasma treatment process in step A includes at least hydrogen.

[0012] According to the first aspect of the present invention, during the plasma treatment in step A, a positive bias voltage is applied to the substrate.

[0013] According to the first aspect of the present invention, in the PECVD deposition process of step B, a magnetic field parallel to the surface is applied to the surface of the substrate.

[0014] According to the first aspect of the present invention, the precursor used in the deposition process of step B is ruthenium trichloride trihydrate, ruthenium acetylacetonate or ruthenium acetate, and / or,

[0015] The reaction gas in the deposition process of step B is SF 6 .

[0016] According to the first aspect of the present invention, the thickness of the ruthenium metal layer deposited in step B is between 10 angstroms and 20 angstroms.

[0017] According to the first aspect of the present invention, the thickness of the ruthenium metal wiring is between 300 angstroms and 800 angstroms.

[0018] According to the first aspect of the present invention, the formation process further comprises the following steps after the step of forming the ruthenium metal wiring:

[0019] forming an interlayer dielectric covering the ruthenium metal wiring;

[0020] The interlayer dielectric is planarized to form an interlayer dielectric layer.

[0021] A second aspect of the present invention provides a semiconductor device, the semiconductor device comprising at least one metal connection line, the metal connection line being prepared by the metal connection line forming process.

[0022] According to a second aspect of the present invention, the semiconductor device comprises NMOS transistors and PMOS transistors arranged in an array, and the metal wiring comprises source-drain metal wiring and gate metal wiring;

[0023] The source and drain of the NMOS transistor are electrically connected to an external circuit via the source-drain metal wiring;

[0024] The gate of the PMOS transistor is electrically connected to an external control signal through the gate metal connection line.

[0025] The metal wiring formation process of the present invention adopts the selective growth of ruthenium metal on the substrate, and deposits ruthenium metal layers multiple times in the metal area to be wired. The ruthenium metal wiring finally obtained has the characteristics of better stability, less diffusion, lower resistance, etc. compared with the copper metal wiring layer. The metal wiring formation process can replace the existing Damascus copper metal wiring process, which can not only reduce the complex photolithography process and the complex etching process, but also effectively avoid the problem of gaps and voids in the metal wiring layer, and greatly improve the accuracy of metal wiring stacking. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0027] Figure 1 A flowchart of a metal wiring formation process according to an embodiment of the present invention; and

[0028] Figures 2 to 7 It is a schematic diagram of the structure of the substrate after each step in the metal wiring formation process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0030] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0031] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0032] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0033] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0034] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0035] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0036] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0037] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0038] In response to the existing technical problems, the present invention provides a metal wiring formation process and a semiconductor device, the metal wiring formation process comprising the following steps: providing a substrate, the substrate comprising an insulating dielectric layer and a plurality of metal regions to be connected on the insulating dielectric layer; step A: using plasma to treat the substrate so that the surface of the insulating dielectric layer is negatively charged; step B: using a PECVD deposition process to generate negatively charged ruthenium atoms and depositing a ruthenium metal layer in the metal region to be connected; repeating steps A and B, multiple ruthenium metal layers are stacked to form ruthenium metal wiring. The metal wiring formation process of the present invention adopts the selective growth of ruthenium metal on the substrate, and deposits ruthenium metal layers multiple times in the metal region to be connected. The ruthenium metal wiring finally obtained has the characteristics of better stability, less diffusion, lower resistance, etc. compared with the copper metal wiring layer. The metal wiring formation process can replace the existing Damascus copper metal wiring process.

[0039] The metal wiring forming process and the semiconductor device of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments. It can be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0040] Figure 1 The following is a flow chart of a metal wiring forming process according to an embodiment of the present invention. Specifically, the metal wiring forming process includes the following steps:

[0041] Step S100: Provide a substrate, the substrate includes an insulating dielectric layer and a plurality of metal areas to be wired in the insulating dielectric layer. It should be noted that the substrate here is a substrate prepared with a transistor array, and the transistor has a source / drain and a gate. The source and drain are the input and output ends of the current, and the gate is used to control the on and off of the current. The metal connection is used to lead out the source / drain or the gate, and the metal connection of the source / drain is connected to the external circuit to realize the input and output of the current, so that an effective conductive channel can be formed between the source and the drain, thereby controlling the on and off state of the transistor. The metal connection of the gate connects the gate and the external control circuit, transmits the control signal to the gate, and by changing the magnitude and polarity of the gate voltage, the formation, width and carrier concentration of the conductive channel on the surface of the transistor below the gate can be controlled, thereby controlling the magnitude and on and off state of the current between the source and the drain.

[0042] For example, the substrate may be a substrate on which an NMOS transistor array (oval dashed box) and a PMOS transistor array are arranged, the surface of the substrate is an insulating dielectric layer 10, the insulating dielectric layer 10 of semiconductor devices with different structures is different, the insulating dielectric layer 10 may be a silicon oxide layer or a silicon nitride layer, wherein the metal region to be connected includes a metal region 20a to be connected for source and drain of a plurality of NMOS transistors and a metal region 20b to be connected for gate of a plurality of PMOS transistors, see Figure 2In actual use, the source and drain of the NMOS transistor or the gate of the PMOS transistor can be tungsten metal electrodes, that is, the exposed surface of the substrate in step 100 is mainly composed of the insulating dielectric layer 10 and the metal tungsten region.

[0043] On the substrate where metal wiring is to be formed, step S200 is performed. Step S200 includes step A and step B. Step A is to use plasma to treat the substrate so that the surface of the insulating dielectric layer 10 is negatively charged. Figure 3 After the surface of the insulating dielectric layer 10 is negatively charged, step B is performed, that is, a PECVD deposition process is used to generate negatively charged ruthenium atoms and a ruthenium metal layer 31a and a ruthenium metal layer 31b are deposited in the metal region 20a to be connected and the metal region 20b to be connected, respectively. Figure 4 .

[0044] Step S200 can be performed in a plasma enhanced chemical vapor deposition (PECVD) device. Specifically, the substrate of step S100 is loaded onto the reaction chamber carrier of the plasma enhanced chemical vapor deposition device, and the radio frequency power supply is turned on to generate a high-frequency alternating electric field between the electrodes in the reaction chamber. The atoms or molecules in the reaction gas introduced into the reaction chamber are ionized, and the electrons are separated from the atoms or molecules to form free electrons and charged ions. At the same time, some excited atoms, molecules, free radicals and other active particles are also generated, and these particles together constitute a plasma. Preferably, the reaction gas in the plasma treatment process in step A includes at least hydrogen H 2 In step A, H 2 Into the reaction chamber, H 2 The gas dissociates into negatively charged hydrogen atoms and positively charged hydrogen atoms. A positive bias is applied to the substrate. The positive bias on the substrate will attract the negatively charged hydrogen atoms in the hydrogen plasma to move to the surface of the substrate. The negatively charged hydrogen atoms neutralize the positive charges on the surface of the insulating dielectric layer 10, making it saturated and negatively charged. Since the metal area to be connected has good conductivity, after step A, the metal area to be connected is not charged, and the insulating dielectric layer 10 of the substrate is negatively charged.

[0045] In the PECVD deposition process of step B, plasma is achieved by applying voltage to electrodes in a low-pressure gas environment. Preferably, the PECVD pulse cycle mode is used to deposit the ruthenium metal layer. The PECVD pulse cycle mode is to turn the generation of plasma on and off in a pulsed manner at a certain time interval, so that the reaction gas is excited to form plasma and undergo chemical reactions during the pulse, and the generation of plasma is stopped during the pulse interval, allowing the reaction system to have a certain amount of time to adjust and stabilize. In the pulse-on stage, the gas is decomposed into electrons, ions, and free radicals under the action of the electric field excited by the radio frequency source, and chemical reactions occur to generate the initial components and side reactants that form the film, which are adsorbed to the substrate surface in the form of chemical bonds to form crystal nuclei, which grow into islands and then form continuous thin films; in the pulse-off stage, the by-products are detached from the film surface and discharged under the action of the vacuum pump.

[0046] Compared with the continuous plasma mode, the PECVD pulse cycle mode can reduce the continuous bombardment of the substrate by high-energy ions in the plasma, thereby reducing the damage to the substrate. In the present invention, the PECVD pulse cycle mode can keep the insulating dielectric layer 10 in a negatively charged state as much as possible, thereby achieving a higher selective growth of the ruthenium metal layer in step B. At the same time, by adjusting the frequency, duty cycle and other parameters of the pulse during the deposition process of the PECVD pulse cycle mode, the ionization degree of the reaction gas, the density and activity of the plasma can be more accurately controlled, thereby achieving fine adjustment of the growth rate, thickness, composition, structure and other characteristics of the film. The pulse cycle mode can reduce the continuous action time of the plasma and reduce the probability of particle generation, thereby improving the quality of the deposited ruthenium metal layer.

[0047] In the PECVD deposition process of step B, the precursor used can be ruthenium trichloride trihydrate (RuCl 3 ·3H 2 O), ruthenium acetylacetonate or ruthenium acetate, the reaction gas can be sulfur hexafluoride SF 6 .

[0048] When ruthenium trichloride trihydrate is used as a precursor for growing a ruthenium metal layer, the reaction gas is SF 6 When:

[0049]

[0050] In the above reaction, SF 6As a strong oxidant, the ruthenium ions in the ruthenium trichloride trihydrate are prompted to obtain electrons to generate ruthenium elements, and the chlorine element may exist in the form of chlorine gas or chloride ions. In the subsequent ruthenium deposition process, the negatively charged ruthenium element will not be deposited on the surface of the negatively charged insulating dielectric layer 10, but will only be deposited on the uncharged metal area 20a to be connected and the metal area 20b to be connected. When the negative charge on the surface of the insulating dielectric layer 10 is exhausted, step B is terminated.

[0051] Similarly, when ruthenium acetylacetonate is used as a precursor for growing a ruthenium metal layer, the reaction gas is SF 6 When:

[0052]

[0053] At this time, the acetylacetonate ligand (acac) in ruthenium acetylacetonate may react with SF during the reaction. 6 The interaction occurs and the ruthenium center is separated, and the generated ruthenium element is negatively charged due to charge transfer in the reaction system or other factors. The negatively charged ruthenium element is deposited in the uncharged metal area 20a to be connected and the metal area 20b to be connected.

[0054] When ruthenium acetate is used as a precursor for growing a ruthenium metal layer, the reaction gas is SF 6 When:

[0055]

[0056] The acetate ion (OAc) in ruthenium acetate is in SF 6 Under the redox reaction, the ruthenium ions may be separated, and the generated ruthenium element carries a negative charge due to charge transfer and other reasons. The negatively charged ruthenium element is deposited in the uncharged metal area 20a to be connected and the metal area 20b to be connected. Similarly, when the negative charge on the surface of the insulating dielectric layer 10 is exhausted, step B is terminated.

[0057] As described above, the negative charges on the surface of the insulating dielectric layer 10 are consumed during the deposition of ruthenium metal. When the negative charges on the surface of the insulating dielectric layer 10 are completely consumed, it is considered that the ruthenium metal deposition needs to be terminated. Preferably, the thickness of the deposited ruthenium metal layer in a single step B is between 10 angstroms and 20 angstroms, such as the thickness of the deposited ruthenium metal layer is 10 angstroms, 12 angstroms, 15 angstroms, 18 angstroms or 20 angstroms.

[0058] When the negative charge on the surface of the insulating dielectric layer 10 is exhausted, the process of step A needs to be repeated again to make the surface of the insulating dielectric layer 10 carry negative charge. That is, step S300 is performed: step A and step B are repeated, and multiple ruthenium metal layers are stacked to form ruthenium metal wiring. Figure 5In the present invention, the number of times of repeating step A and step B can be between 20 and 50 times, and accordingly, the thickness of the obtained ruthenium metal connection 30a at the metal area 20a to be connected and the ruthenium metal connection 30b at the metal area 20b to be connected is between 300 angstroms and 800 angstroms.

[0059] In order to improve the selective growth of the ruthenium metal layer, in some embodiments, in the PECVD deposition process of step B, a magnetic field parallel to the surface is applied to the surface of the substrate. The above magnetic field can be achieved by adding an inductor coil on the carrier of the reaction chamber of the PECVD equipment. When the substrate is placed on the carrier, a current is passed through the inductor coil to generate a magnetic field. The negatively charged ruthenium atoms are attracted toward the substrate (perpendicular to the substrate) under the action of the magnetic field parallel to the surface of the substrate, thereby increasing the probability of ruthenium metal growing vertically along the metal area to be connected, ensuring the selective growth of the ruthenium metal layer in the direction perpendicular to the substrate (in the height direction). At the same time, the addition of the magnetic field also increases the deposition rate of ruthenium atoms in the metal area to be connected, and improves the electrical properties of the obtained ruthenium metal layer, such as reducing the resistivity of the ruthenium metal layer.

[0060] The metal wiring formation process of the present invention first adopts a selective regional negative charge treatment process to make the surface of the insulating dielectric layer 10 negatively charged, and then deposits a ruthenium metal layer in the metal area without negative charge. By repeating the above steps, a ruthenium metal wiring with a metal wiring thickness is obtained. This process can replace the existing Damascus copper metal wiring process method, which can not only reduce the photolithography and etching process steps, but also effectively avoid the problems of metal wiring gaps and voids, and also greatly improve the accuracy of metal wiring stacking.

[0061] In some other embodiments, the metal wiring forming process further comprises the following steps after the step of forming the ruthenium metal wiring:

[0062] Step S400: forming an interlayer dielectric 40 covering the ruthenium metal wiring. Figure 6 The interlayer dielectric may include one or more layers, and the interlayer dielectric layer may be silicon oxide and / or silicon nitride, such as the interlayer dielectric including a silicon nitride layer and a silicon oxide layer. The interlayer dielectric 40 may be obtained by PECVD or sub-atmospheric pressure chemical vapor deposition (SACVD).

[0063] Step S500: planarize the interlayer dielectric 40 to form an interlayer dielectric layer 40'. Figure 7 The planarization here can adopt the commonly used Chemical Mechanical Polishing (CMP) process, which will not be described in detail here.

[0064] The present invention also provides a semiconductor device, the semiconductor device includes at least one metal connection, and the metal connection is prepared by the above-mentioned metal connection forming process. More specifically, the semiconductor device may include NMOS transistors and PMOS transistors arranged in an array, the metal connection includes source-drain metal connection and gate metal connection, the above-mentioned metal connection are all ruthenium metal connection, the source and drain of the NMOS transistor are electrically connected to the external circuit through the source-drain metal connection; the gate of the PMOS transistor is electrically connected to the external control signal through the gate metal connection. The source-drain metal connection and the gate metal connection of the above-mentioned semiconductor device have fewer gaps (Seam) and voids (Void), smaller resistance, and can meet more advanced process nodes.

[0065] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0066] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A metal wiring forming process, characterized in that: The forming process comprises the following steps: Providing a substrate, the substrate comprising an insulating dielectric layer and a plurality of metal regions to be connected on the insulating dielectric layer; Step A: treating the substrate with plasma to make the surface of the insulating dielectric layer negatively charged; Step B: using a PECVD deposition process to generate negatively charged ruthenium atoms and depositing a ruthenium metal layer in the metal area to be connected; Repeat step A and step B, and multiple ruthenium metal layers are stacked to form ruthenium metal wiring.

2. The metal wiring forming process according to claim 1, characterized in that: The reaction gas in the plasma treatment process in step A at least includes hydrogen.

3. The metal wiring forming process according to claim 1, characterized in that: During the plasma treatment in step A, a positive bias voltage is applied to the substrate.

4. The metal wiring forming process according to claim 1, characterized in that: In the PECVD deposition process of step B, a magnetic field parallel to the surface of the substrate is applied.

5. The metal wiring forming process according to claim 4, characterized in that: The precursor used in the PECVD deposition process of step B is ruthenium trichloride trihydrate, ruthenium acetylacetonate or ruthenium acetate, and / or, The reaction gas in the deposition process of step B is SF6.

6. The metal wiring forming process according to claim 1, characterized in that: The thickness of the ruthenium metal layer deposited in step B is in a range of 10 angstroms to 20 angstroms.

7. The metal wiring forming process according to claim 1, characterized in that: The thickness of the ruthenium metal wiring is between 300 angstroms and 800 angstroms.

8. The metal wiring forming process according to claim 1, characterized in that: The formation process further comprises the following steps after the step of forming the ruthenium metal connection: forming an interlayer dielectric covering the ruthenium metal wiring; The interlayer dielectric is planarized to form an interlayer dielectric layer.

9. A semiconductor device, characterized in that: The semiconductor device comprises at least one metal connection, and the metal connection is prepared by using the metal connection forming process described in any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that The semiconductor device includes NMOS transistors and PMOS transistors arranged in an array, and the metal wiring includes source-drain metal wiring and gate metal wiring; The source and drain of the NMOS transistor are electrically connected to an external circuit via the source-drain metal wiring; The gate of the PMOS transistor is electrically connected to an external control signal through the gate metal connection line.

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