A highly integrated double-layer integrated circuit structure and preparation method

Abstract

The present invention provides a highly integrated double-layer integrated circuit structure and a manufacturing method thereof. The method includes: a first wafer includes an upper substrate and a first isolation layer, a second wafer includes a lower substrate and a second isolation layer, and the first isolation layer and the second isolation layer are bonded together to form an isolation layer; a first through hole penetrating through the upper substrate and the lower substrate is formed, and isolation regions are formed in the first through hole, on the surface of the upper substrate, and on the surface of the lower substrate; devices are formed on the upper substrate and the lower substrate; a second through hole is formed in the isolation region in the first through hole, and a conductive layer is formed in the second through hole for connecting in series the devices located on the upper substrate and the lower substrate. By forming vertically symmetric devices on two bonded wafers and connecting the devices in the upper and lower layers in series by using the penetrating conductive layer, the present invention can save some manufacturing processes, shorten the process flow, and improve the integration degree of the chip.

Description

Technical Field

[0001] The present invention belongs to the field of double-layer integrated circuits, and particularly relates to a high-integration double-layer integrated circuit structure and a manufacturing method thereof. Background Art

[0002] Since the birth of Moore's Law, the number of transistors has doubled every year. As time goes by, the process node has reached 2nm or even 0.3nm, all aiming to increase the number of transistors and improve the operating speed of the chip. After reaching a certain level of growth, it is only possible to increase the number of transistors by changing the structure, but the change in structure will make the process very complex, such as Fin FET and GAA, etc. Summary of the Invention

[0003] The technical problem to be solved by the present invention is: to provide a high-integration double-layer integrated circuit structure and a manufacturing method thereof, which can increase the number of transistors while saving the process flow.

[0004] The technical solution adopted by the present invention to solve the above technical problem is:

[0005] As a first aspect of the present invention, a manufacturing method of a high-integration double-layer integrated circuit structure is provided, which includes the steps of:

[0006] The first wafer includes an upper substrate and a first isolation layer, and the second wafer includes a lower substrate and a second isolation layer. Bond the first isolation layer and the second isolation layer together to form an isolation layer;

[0007] Form a first through hole penetrating the upper substrate and the lower substrate, and form isolation regions in the first through hole, on the surface of the upper substrate, and on the surface of the lower substrate;

[0008] Form devices on the upper substrate and the lower substrate;

[0009] Form a second through hole in the isolation region in the first through hole, and form a conductive layer in the second through hole for connecting in series the devices located on the upper substrate and the lower substrate.

[0010] According to the above method, the formation of the isolation region specifically includes:

[0011] Form an oxide layer and an etch stop layer with a certain thickness on the surfaces of the upper substrate and the lower substrate respectively;

[0012] Form a layer required for exposure, development, and etching on the etch stop layer on one side, and etch the first through hole, which penetrates the upper substrate and the lower substrate and extends to the etch stop layer on the said one side;

[0013] Fill the first through hole with an insulating layer, and the insulating layer and the oxide layers on both sides together constitute the isolation region;

[0014] Annealing is performed to make the insulating layer more densely filled.

[0015] According to the above method, when the device is a MOS transistor, its formation includes:

[0016] Ion implantation is respectively performed on the regions for forming the device on the upper substrate and the lower substrate to form well regions;

[0017] The first annealing is performed to activate the ions in the well regions in the upper substrate and the lower substrate;

[0018] The isolation regions on the surfaces of the upper substrate and the lower substrate are removed to expose the isolation region and the well region in the first through hole, and then a gate oxide layer with a certain thickness is formed on the surfaces of the upper substrate and the lower substrate;

[0019] Polysilicon layers for serving as gates are respectively formed on the surfaces of the gate oxide layers of the upper substrate and the lower substrate, and gate ion doping is performed;

[0020] The second annealing is performed to make the gate ion implantation in the upper and lower polysilicon layers uniform;

[0021] Gates, source electrodes, and drain electrodes are respectively formed on the upper substrate, the lower substrate, and the corresponding polysilicon layers.

[0022] According to the above method, when performing gate ion doping on the upper and lower polysilicon layers respectively, ions of group IV elements are also implanted; the ions of group IV elements in the upper and lower polysilicon layers are implanted uniformly during the second annealing process.

[0023] According to the above method, the formation of the conductive layer specifically includes:

[0024] Etch stop layers and ILD oxide layers are respectively formed on the outer surfaces of the gates, source electrodes, and drain electrodes of the upper substrate and the lower substrate;

[0025] A first metal is formed that passes through the isolation region from the ILD oxide layer on one side to the etch stop layer on the opposite side;

[0026] A second metal communicating with the first metal is formed on the ILD oxide layer on the other side;

[0027] The first metal and the second metal constitute the conductive layer.

[0028] According to the above method, the device is a MOS transistor, a diode, a triode, an IGBT, or a thyristor.

[0029] As the second aspect of the present invention, the present invention provides a highly integrated double-layer integrated circuit structure, including an upper substrate, an isolation layer, and a lower substrate obtained by a bonding process; devices are respectively formed on the upper substrate and the lower substrate, and the positions of the devices on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer;

[0030] The double-layer integrated circuit structure further includes a conductive layer penetrating the upper substrate, the lower substrate and the isolation layer for serially forming devices on the upper substrate and the lower substrate.

[0031] According to the above solution, it further includes an isolation region penetrating the upper substrate and the lower substrate. The conductive layer is formed in the isolation region and is serially connected with the devices.

[0032] The devices are provided with contacts, and the conductive layer is isolated from each contact by an ILD oxide layer.

[0033] According to the above solution, the device is a MOS transistor, including a well region formed in the upper substrate or the lower substrate. A source electrode and a drain electrode are respectively formed in the well region. A gate electrode is formed on the outer surface of the well region, and the gate electrode is located between the source electrode and the drain electrode. The source electrode and the drain electrode are connected through a channel, and the channel is isolated from the gate electrode.

[0034] According to the above solution, a dielectric barrier layer is provided on the outer surface of the device.

[0035] The unexpected beneficial effects of the present invention are as follows:

[0036] 1. In terms of process, first bond the wafers, first form an isolation region penetrating the upper substrate and the lower substrate, then form devices on the upper substrate and the lower substrate, and finally form a conductive layer in the isolation region. The unexpected effect is that during the process of forming the devices, some of the processes for forming the devices can be integrated, saving the process flow and improving the process efficiency. At the same time, in terms of structure, by forming upper and lower symmetric devices on the two bonded wafers and using the penetrating conductive layer to serially connect the upper and lower layer devices, the unexpected effect is that twice as many devices can be integrated on the same area of the chip, greatly improving the integration degree of the chip.

[0037] 2. The isolation region only needs to be etched once to be formed, without being formed separately on the upper substrate and the lower substrate. The annealing after filling the insulating layer also only needs to be carried out once, so that the process is integrated, saving the process flow and improving the process efficiency.

[0038] 3. When forming devices on the upper substrate and the lower substrate, although some processes still need to be completed separately, the annealing process is integrated, further saving the process flow and improving the process efficiency.

[0039] 4. After the gate ion implantation and before the second annealing, additional group-IV element ions are implanted to inhibit the growth rate of grain growth from slowing down, and the grain boundary length is smaller than the reserved value after the second annealing, resulting in a longer current conduction path, so as to prevent the subsequent ion implantation from penetrating the gate to the current channel, thereby avoiding the leakage problem. Description of the Drawings

[0040] Figure 1It is a flowchart of the method according to an embodiment of the present invention.

[0041] Figure 2 It is a schematic structural diagram before the bonding of two wafers.

[0042] Figure 3 It is a schematic structural diagram after the bonding of two wafers.

[0043] Figure 4 It is a schematic structural diagram before the etching of the first through hole.

[0044] Figure 5 It is a schematic structural diagram after the etching of the first through hole and the filling of the insulating layer.

[0045] Figure 6 It is a schematic structural diagram after the removal of the STI etch stop layer.

[0046] Figure 7 It is a schematic structural diagram for ion implantation to form a well region.

[0047] Figure 8 It is a schematic structural diagram after annealing for the formed well region.

[0048] Figure 9 It is a schematic structural diagram after the removal of the isolation regions on the surfaces of the upper and lower substrates.

[0049] Figure 10 It is a schematic structural diagram after the formation of the gate oxide layer.

[0050] Figure 11 It is a schematic structural diagram after the formation of the polysilicon layer and the sacrificial oxide layer.

[0051] Figure 12 It is a schematic structural diagram after the gate ion doping of the upper and lower polysilicon layers.

[0052] Figure 13 It is a schematic structural diagram after the formation of the gate and the surrounding gate oxide layer.

[0053] Figure 14 It is a schematic structural diagram after the first sidewall process and the LDD process.

[0054] Figure 15 It is a schematic structural diagram after the second sidewall process and the source / drain ion implantation process.

[0055] Figure 16 It is a schematic structural diagram after the self-aligned silicide barrier layer process.

[0056] Figure 17 It is a schematic structural diagram after the formation of the ILD oxide layer.

[0057] Figure 18It is a schematic structural diagram after devices are formed on the other side of the wafer.

[0058] Figure 19 It is a schematic structural diagram after metal contacts are formed on the devices.

[0059] Figure 20 It is a schematic structural diagram for preparing to etch the second through-hole.

[0060] Figure 21 It is a schematic structural diagram after the second through-hole is formed.

[0061] Figure 22 It is a schematic structural diagram after the first metal is formed.

[0062] Figure 23 It is a schematic structural diagram after a through-hole communicating with the second through-hole is etched on the other side.

[0063] Figure 24 It is a schematic partial cross-sectional structural diagram of a device according to an embodiment of the present invention.

[0064] In the figure:

[0065] 100 - upper substrate;

[0066] 200 - isolation layer, 201 - first oxide layer, 202 - second oxide layer, 203 - third oxide layer, 204 - fourth oxide layer, 2041 - second through-hole, 205 - gate oxide layer, 206 - sacrificial oxide layer, 207 - ILD oxide layer;

[0067] 300 - lower substrate;

[0068] 401 - well region, 402 - source, 403 - gate, 404 - drain;

[0069] 501 - source contact, 502 - gate contact, 503 - drain contact;

[0070] 600 - conductive layer, 601 - first metal;

[0071] 701 - STI etch stop layer, 702 - etch stop layer;

[0072] 801 - α-C layer, 802 - oxide layer, 803 - BARC, 804 - photoresist, 805 - TiN layer, 806 - SiON layer, 807 - SiCN thin film;

[0073] 900 - polysilicon layer. Detailed implementation manners

[0074] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0075] It should be noted that the illustrations provided in the embodiments of the present invention only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0076] In the present invention, it should also be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be understood as indicating or implying relative importance.

[0077] The present invention provides a method for preparing a highly integrated double-layer integrated circuit structure as Figure 1 shown, which specifically includes:

[0078] S1. Bond two wafers, that is: the first wafer includes an upper substrate and a first isolation layer, and the second wafer includes a lower substrate and a second isolation layer. Bond the first isolation layer and the second isolation layer together to form an isolation layer.

[0079] S2. Form a first through hole penetrating the upper substrate and the lower substrate, and form isolation regions in the first through hole, on the surface of the upper substrate and on the surface of the lower substrate.

[0080] S3. Form devices on the upper substrate and the lower substrate;

[0081] S4. Form a second through hole in the isolation region in the first through hole, and form a conductive layer in the second through hole for connecting in series the devices located on the upper substrate and the lower substrate.

[0082] Meanwhile, the present invention also provides a highly integrated double-layer integrated circuit structure, including an upper substrate, an isolation layer and a lower substrate obtained by a bonding process; devices are respectively formed on the upper substrate and the lower substrate, and the positions of the devices on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer; it also includes a conductive layer penetrating the upper substrate, the lower substrate and the isolation layer for connecting in series the devices formed on the upper substrate and the lower substrate.

[0083] The device described above can be a MOS transistor, diode, triode, IGBT, thyristor, etc. As long as it adopts the idea of the present invention, uses two bonded wafers to form an upper and lower symmetric device, and connects the upper and lower symmetric devices in series through a penetrating conductive layer, it is within the protection scope of the present invention. However, the structural improvement of the device itself is not within the protection scope of the device structure of the present invention.

[0084] Next, the present invention will be further described by taking a MOS transistor as an example.

[0085] Continue as Figure 1 As shown, the present invention provides a preparation method for a highly integrated double-layer integrated circuit structure, which specifically includes the following steps:

[0086] S1. Bond two wafers, that is: the first wafer includes an upper substrate and a first isolation layer, and the second wafer includes a lower substrate and a second isolation layer. Bond the first isolation layer and the second isolation layer together to form an isolation layer.

[0087] As Figure 2 shown, take two single-crystal silicon wafers as the upper substrate 100 and the lower substrate 300, grow a certain thickness of oxide layer on the wafer surface as the first isolation layer and the second isolation layer, that is, the first oxide layer 201 and the second oxide layer 202, and then use the bonding process to bond the two to form a stacked structure of the upper substrate 100, the isolation layer 200 and the lower substrate 300 as shown in Figure 3 ; the isolation layer 200 is formed by bonding the first oxide layer 201 and the second oxide layer 202.

[0088] In this embodiment, the bonding process specifically includes: respectively activating the dangling bonds on the wafer surface by using plasma (N2 plasma can be used), then rinsing the hydrophilic substances on the wafer surface with deionized water, then flipping the two wafers, and annealing the surfaces where the oxide layers are grown face to face at 350 degrees for 120 minutes to form the above-mentioned stacked structure.

[0089] S2. Form a first through hole penetrating the upper substrate and the lower substrate on the stacked structure, and form isolation regions in the first through hole, on the upper substrate surface and on the lower substrate surface. Specifically include:

[0090] As Figure 4As shown, on one side of the stacked structure, a third oxide layer 203 and an STI etch stop layer 701 with a certain thickness are grown; on the other side of the stacked structure, a third oxide layer 203, an STI etch stop layer 701 with a certain thickness, and other layers required for exposure, development, and etching are produced. The other layers sequentially include an α-C (amorphous carbon) layer 801, an oxide layer 802, a BARC (Bottom Anti-Reflective Coating) 803, and a photoresist 804; among them, the photoresists 804 are arranged at intervals, and the distance is determined according to the first through-hole to be provided, that is: the position where the first through-hole needs to be opened is not coated with photoresist.

[0091] Etch from the other side of the stacked structure (i.e., the side coated with photoresist) to the STI etch stop layer 701 on one side. In this embodiment, the STI etch stop layer 701 is SiN, and then an insulating layer, that is, a fourth oxide layer 204, is filled, mainly to repair the damage to the substrate caused by etching, and then CMP (Chemical Mechanical Polishing process, a process of precisely grinding and polishing the surface of a silicon wafer by combining chemistry and mechanics) is used to grind it flat to form a structure as shown in Figure 5 . Annealing is performed to make the TEOS (tetraethyl orthosilicate) filled in the insulating layer more dense.

[0092] Use the WET process (wet process) to remove the STI etch stop layers 701 on both sides respectively, and phosphoric acid can be used for corrosion. The third oxide layer 203 and the fourth oxide layer 204 on both sides of the stacked structure together form the isolation region, as shown in Figure 6 . Both the third oxide layer 203 and the fourth oxide layer 204 are SiO2.

[0093] It should be noted that the above growth and WET process are completed on both sides respectively, the etching only needs to be completed on one side, and the annealing only needs to be performed once. Therefore, the annealing process is integrated.

[0094] S3. Form devices on the upper substrate and the lower substrate. Specifically in this embodiment, the MOS transistors are formed in the regions between adjacent fourth oxide layers 204 in Figure 6 . It should be noted that this embodiment only takes a part of the upper substrate and the lower substrate as an example. In an actual wafer, it is not necessary to have a fourth oxide layer 204 between every two devices, and the fourth oxide layer 204 only needs to be provided at the places where connection is required.

[0095] S3 specifically includes:

[0096] S301. Perform ion implantation on the regions of the upper substrate 100 and the lower substrate 300 used to form the devices respectively to form well regions 401, as shown in Figure 7 .

[0097] Among them, the parts that do not require ion implantation need to be blocked with photoresist 804, and then the PW region is exposed and developed. The two sides of the wafer are ion implanted respectively using the ion implantation process to form PW (P-type well). The implanted ions are mainly B and BF, and a total of four implantations are required, with B implanted three times and BF implanted once. The junction depth of BF implantation is relatively shallow to form a channel region and adjust the threshold voltage, thus forming a structure as shown in Figure 7 .

[0098] S302. Remove the photoresist 804, and then perform the first annealing to activate the ions in the well regions 401 of the upper substrate and the lower substrate and push them to fixed positions to meet the depth required by the device. The annealing temperature can be 1050 degrees Celsius and the time can be 5 s, obtaining a structure as shown in Figure 8 .

[0099] S303. As shown in Figure 9 and Figure 10 , remove the isolation regions on the surfaces of the upper substrate 100 and the lower substrate 300 to expose the isolation region in the first through hole, i.e., the fourth oxide layer 204 and the well region 401, and then reform a gate oxide layer 205 with a certain thickness on the surfaces of the upper substrate 100 and the lower substrate 100.

[0100] In this embodiment, the originally grown third oxide layer 203 is removed using the WET process. Here, the mask of a low-voltage device is used to open the regions where the gate oxide layer needs to be regrown, and the regions that do not need to be removed are covered with PR. Here, the WET process can use DHF (a mixture of HF, H2O2, and H2O) + SPM (a mixture of H2SO4, H2O2, and H2O). Then, a gate oxide layer 205 with a certain thickness is grown using the RTP process (Rapid Thermal Processing) and the ISSG process (In Situ Steam Generation). Generally, the thickness of the gate oxide layer of a low-voltage device is 22 A.

[0101] S304. As shown in Figure 11 , polysilicon layers 900 used as gates are respectively formed on the surfaces of the upper substrate 100 and the lower substrate 300, and a sacrificial oxide layer 206 is formed on the outer surface of the polysilicon layer 900.

[0102] In this embodiment, polysilicon layers with a certain thickness are grown on both sides of the wafer using the furnace tube process, which are used as the gates of MOS, and then a sacrificial oxide layer 206 is grown on the polysilicon layer using the furnace tube process.

[0103] S305. Gate ion doping is performed on the upper and lower polysilicon layers respectively, as shown in Figure 12As shown. Then perform the second annealing.

[0104] It should be noted that: in order to reduce the on-resistance of the gate, general manufacturing processes will perform ion doping on the polysilicon layer. Generally, nitrogen group elements are used for N-type semiconductors, and boron group elements are used for P-type semiconductors. After ion implantation, annealing is performed to make the ion implantation uniform, thereby reducing the gate resistance value and increasing the component speed.

[0105] However, the annealing here actually brings adverse defects: 1. Since the annealing process (>600 °C) will cause the gate silicon grains to grow again, and at the same time increase the grain boundary length and it is difficult to control the degree. The increase in grain boundaries will cause subsequent ion implantation, such as lightly doped drain, to directly penetrate the gate to the current channel, resulting in the gate being unable to function and leading to a leakage problem.

[0106] Therefore, the present invention makes the following improvements: after gate ion implantation and before the annealing process, additional group IV elements (carbon, silicon, germanium, etc.) ions are implanted to inhibit the growth expansion speed of the grains, and the grain boundary length after the annealing process is smaller than the reserved one, resulting in a longer current flow path, so as to prevent subsequent ion implantation from penetrating the gate to the current channel, thereby not causing a leakage problem.

[0107] Similarly, in this step, the annealing processes of the upper substrate 100 and the lower substrate 300 are also integrated, saving the process.

[0108] S306. Form gates, source electrodes, and drain electrodes on the upper substrate 100, the lower substrate 300, and the corresponding polysilicon layers 900 respectively, and form an etch stop layer 702 on the outer surface. Specifically include:

[0109] First, deposit different thin films on one side of the wafer, sequentially deposit a certain thickness of SiN layer, oxide layer, amorphous carbon layer, SiON layer, oxide layer, BARC layer, then coat photoresist 804, and perform exposure and development of polysilicon; then perform a polysilicon etching process, perform multiple etching processes + WET processes; then perform a polysilicon ROX (recessed oxidation) process, use a furnace tube process to oxidize the sides of the polysilicon to grow an oxide layer of a certain thickness, and then use phosphoric acid to remove the SiN on the top of the polysilicon to obtain as Figure 13 the structure shown, that is, the gate 403 (i.e., the original polysilicon layer 900) and the surrounding gate oxide layer 205 have been formed.

[0110] As Figure 14As shown, the first sidewall process and the LDD process are carried out: First, an oxide layer and a SiN layer with a certain thickness are deposited in sequence. Then, the oxide layer and the SiN layer on the side of the polysilicon are formed by using the self-alignment process. Then, the photomask of NLDD is coated, followed by exposure and development. Then, ion implantation of LDD IMP is carried out, and Ge, C, B, N, and P are implanted to a certain depth in sequence. The implantation of B here mainly plays a role in preventing source-drain punchthrough. The ion junction depth is deeper than the channel to prevent source-drain punchthrough.

[0111] As Figure 15 shown, first remove the photoresist 804, and then enter the second sidewall process and the ion implantation process of the source / drain. Specifically, first deposit an oxide layer and a SiN layer with a certain thickness in sequence. Then, use the self-alignment process to form the second sidewall process, that is, the oxide layer and the SiN layer on the side of the polysilicon. Then, coat the photomask of NMOS S / D, followed by exposure and development, and then carry out ion implantation. When carrying out ion implantation, P, Ge, P, AS, and F need to be implanted to a certain depth in sequence. The source / drain needs to be heavily doped, and its junction depth is about the same as the depth of the channel.

[0112] As Figure 16 shown, first remove the photoresist, and then enter the self-aligned silicide blocking layer process: First, deposit an oxide layer and a SiN layer with a certain thickness in sequence. Then, use the photomask of the SAB layer for exposure and development, and then etch to open the area where NiSi needs to be formed, and the area where NiSi does not need to be formed is covered. Then, use the Siconi process to pre-clean the oxide layer on the surface of the wafer, with a thickness of about 60A. Then deposit the NiPt alloy about 120A, and then deposit the covering layer TiN, 50A. Then, through the first RTP process, the process temperature is 290°C and lasts for 30s to form the high-resistance metal silicide Ni2PtSi. Then, through the second RTP, the low-resistance NIPTSi2 is formed, and then the Ni in the area where NIPTSi2 is not formed is removed, thus forming the structure as Figure 16 shown.

[0113] As Figure 17 shown, deposit a certain thickness of SiN, about 300A, as the etch stop layer 702. Then deposit the ILD (Inter-Layer Dielectric, the dielectric layer between different metal layers) oxide layer 4260A. After polishing by the CMP process, the remaining thickness is 2100A. Then continue to deposit TEOS with a thickness of 600A. Finally, the total thickness of the ILD oxide layer 207 is 2700A.

[0114] Then flip the wafer and repeat the process flow of S306 on the other side to obtain the structure as Figure 18The structure described above. It should be noted that the process where the devices on the back side are the same as those on the front side is given here. If the devices on the back side are different, the process needs to be adjusted accordingly based on the specific devices.

[0115] After completion, the ions implanted in the previous process need to be heat-treated at a certain temperature to activate the ions, enabling the ions to move within a certain depth and be fixed.

[0116] At this time, the same devices are formed on both the front and back sides of the wafer.

[0117] S307. Metal contacts serving as connection devices are respectively formed on the gate, source, and drain.

[0118] Connect the metal layer to the source, drain, and gate of the MOS device, enabling the front and back sides of the wafer to be connected. As the metal contacts serving as connection devices are not the focus of the present invention, the specific process flow will not be listed in detail. The finally formed structure is as Figure 19 shown, obtaining a source contact 501, a gate contact 502, and a drain contact 503.

[0119] S4. A second via is etched in the isolation region (i.e., the fourth oxide layer 204) within the first via, and a conductive layer is formed in the second via for connecting the devices on the upper substrate and the lower substrate in series. Specifically, it includes:

[0120] S401. Form a first metal that passes through the isolation region from the ILD oxide layer on one side to the etch stop layer on the opposite side. Specifically, starting from the ILD oxide layer on one side, sequentially pass through the etch stop layer and the isolation region, and etch all the way to the etch stop layer on the opposite side, and form the first metal in the etched hole. Similarly, various layers required for etching need to be coated, and then exposed, developed, and etched.

[0121] Specifically, a TiN layer 805, a SiON layer 806, an oxide layer, and a BARC layer with a certain thickness are sequentially deposited, a via photoresist is coated, exposed, developed, and then via trench hard mask etching is performed to obtain a structure as Figure 20 shown.

[0122] Then, an ODL layer, an SHB layer, and a photoresist with a certain thickness are sequentially coated, and then via channel exposure and development are performed, and via and channel synchronous etching is carried out to obtain a second via 2041. The specific structure is as Figure 21 shown.

[0123] Immediately afterwards, a certain thickness of Ti / TiN is deposited using the PVD process, and then the first metal 601 is deposited using the CVD process, as Figure 22 shown. Among them, W is selected for the via and the channel, and other metals such as Al and Cu can also be selected.

[0124] S402. Form a second metal connected to the first metal on the ILD oxide layer on the other side. Specifically, etch the ILD oxide layer on the opposite side until the first metal is exposed, and form a second metal in the etched hole.

[0125] After finally depositing a layer of SiCN thin film 807, flip the wafer and perform the via process: sequentially deposit a TiN layer 805, a SiON layer, an oxide layer, and a BARC layer with a certain thickness, coat the via photoresist, and then expose and develop. Then perform via hard mask etching and ILD oxide layer etching. SiN is used as the etch stop layer. Here, in order to better connect the second metal and reduce the resistance value, it is necessary to increase the OE amount of etching to etch all of the SiN. After etching, perform the WET process to clean the via, and obtain a structure as Figure 23 shown.

[0126] Deposit a certain thickness of TI / TIN using the PVD process, and then deposit the second metal using the CVD process. Deposit a SiCN thin film 807 with a certain thickness to obtain the final structure as Figure 24 shown, where the conductive layer 600 is composed of the first metal 601 and the second metal.

[0127] Figure 24 As shown is a high-integration double-layer integrated circuit structure provided by an embodiment of the present invention, including an upper substrate 100, an isolation layer 200, and a lower substrate 300 obtained by a bonding process; MOS transistors are respectively formed on the upper substrate 100 and the lower substrate 300, and the positions of the MOS transistors on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer 200. The double-layer MOS transistor device further includes a conductive layer 600 passing through the upper substrate 100, the lower substrate 300, and the isolation layer 200, which is used to serially form the MOS transistors on the upper substrate 100 and the lower substrate 300. Among them, the conductive layer 600 is composed of the first metal 601 and the second metal integrated together. The SiCN thin film 807 serves as a dielectric barrier layer.

[0128] Among them, Figure 24 Only partial cross-sectional views are given. Actually, on the wafer, there are several conductive layers 600, which are set according to the area of the wafer and the size of the device. The conductive layers 600 are spaced and arranged at positions where electrical connection is required. It should be noted that the conductive layer 600 forms a structure that is wider at the top and narrower at the bottom due to natural etching, and this specific structure is not required. Generally speaking, the conductive layer 600 does not require a specific structure as long as it can play the role of electrical connection and facilitate the process implementation. The structures of the MOS transistors themselves can be the same or different, as long as their positions on the upper substrate and the lower substrate are symmetrical. The MOS transistors can also be replaced with other devices and it is equally applicable.

[0129] In this embodiment, the MOS transistor includes a well region 401 formed in the upper substrate or the lower substrate. A source electrode 402 and a drain electrode 404 are respectively formed in the well region 401. An isolation region and a gate electrode 403 are formed on the outer surface of the well region 401, and the gate electrode 403 is located between the source electrode 402 and the drain electrode 404. The source electrode 402 and the drain electrode 404 are connected through a channel, and the channel is isolated from the gate electrode 502.

[0130] Further, the source electrode 402, the gate electrode 403, and the drain electrode 404 are respectively connected with a source contact 501, a gate contact 502, and a drain contact 503. The source contact 501, the gate contact 502, and the drain contact 503 are isolated by an ILD oxide layer, usually SiO2.

[0131] Through the above process flow, the above-mentioned back-to-back double-layer device structure can be formed. These two layers of devices can be connected in series through a via structure, and then applied through the wiring process of the subsequent complex metal interconnection layer. Since the metal interconnection layer is not the core technology of the present invention, the subsequent process will not be introduced here. The above structures can all adopt the traditional logic MOS process to double the number of MOS in the device without changing the chip area.

[0132] When replacing the MOS transistor with other devices, only the above process needs to be adjusted adaptively according to the actual situation.

[0133] In summary, through a high-integration double-layer integrated circuit device and a preparation method provided by the present invention, two wafers are first bonded to obtain upper and lower substrates, and then upper and lower symmetric devices are formed on the two bonded wafers. The devices in the upper and lower layers are connected in series by a penetrating conductive layer. Unexpectedly, it is possible to integrate twice as many devices on a chip of the same area, greatly improving the integration of the chip, and saving some process steps (such as annealing) and improving the efficiency of the process.

[0134] It should be noted that according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0135] The magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0136] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A method for preparing a highly integrated double-layer integrated circuit structure, characterized in that: The steps include: The first wafer includes an upper substrate and a first isolation layer, and the second wafer includes a lower substrate and a second isolation layer. Bond the first isolation layer and the second isolation layer together to form an isolation layer. Form a first through-hole penetrating the upper substrate and the lower substrate, and form isolation regions in the first through-hole, on the surface of the upper substrate, and on the surface of the lower substrate. Form devices on the upper substrate and the lower substrate. Form a second through-hole in the isolation region within the first through-hole, and form a conductive layer in the second through-hole for connecting in series the devices located on the upper substrate and the lower substrate.

2. The manufacturing method of the highly integrated double-layer integrated circuit structure according to claim 1, wherein: The formation of the isolation region specifically includes: Form an oxide layer and an etch stop layer with a certain thickness on the surfaces of the upper substrate and the lower substrate respectively. Form a layer required for exposure, development, and etching on the etch stop layer on one side, and etch the first through-hole. The first through-hole penetrates the upper substrate and the lower substrate and extends to the etch stop layer on the said one side. Fill the first through-hole with an insulating layer, and the insulating layer and the oxide layers on both sides together constitute the isolation region. Anneal to make the filling of the insulating layer denser.

3. The manufacturing method of the highly integrated double-layer integrated circuit structure according to claim 1, characterized in that: When the device is a MOS transistor, its formation includes: Perform ion implantation on the regions on the upper substrate and the lower substrate for forming the device respectively to form well regions. Perform the first annealing to activate the ions in the well regions in the upper substrate and the lower substrate. Remove the isolation regions on the surfaces of the upper substrate and the lower substrate to expose the isolation region and the well regions in the first through-hole, and then form a gate oxide layer with a certain thickness on the surfaces of the upper substrate and the lower substrate. Form polysilicon layers for serving as gates on the surfaces of the gate oxide layers of the upper substrate and the lower substrate respectively, and perform gate ion doping. Perform the second annealing to make the gate ion implantation in the upper and lower polysilicon layers uniform. Form gates, source electrodes, and drain electrodes on the upper substrate, the lower substrate, and the corresponding polysilicon layers respectively.

4. The manufacturing method of the highly integrated double-layer integrated circuit structure according to claim 3, characterized in that: When performing gate ion doping on the upper and lower polysilicon layers respectively, ions of group IV elements are also implanted; the ions of group IV elements in the upper and lower polysilicon layers are implanted uniformly during the second annealing process.

5. The method for manufacturing a highly integrated double-layer integrated circuit structure according to claim 3, characterized in that: The formation of the conductive layer specifically includes: Form an etch stop layer and an ILD oxide layer on the outer surfaces of the gates, source electrodes, and drain electrodes of the upper substrate and the lower substrate respectively. Form a first metal that penetrates the ILD oxide layer on one side through the isolation region to the etch stop layer on the opposite side. Form a second metal connected to the first metal on the ILD oxide layer on the other side. The first metal and the second metal constitute the conductive layer.

6. The manufacturing method of the highly integrated double-layer integrated circuit structure according to claim 1 or 2, characterized in that: The said device is a MOS transistor, a diode, a triode, an IGBT, or a thyristor.

7. A highly integrated double-layer integrated circuit structure, characterized in that: Prepared by the preparation method of the highly integrated double-layer integrated circuit structure according to any one of claims 1 to 6; This double-layer integrated circuit structure includes an upper substrate, an isolation layer, and a lower substrate obtained by a bonding process; devices are respectively formed on the upper substrate and the lower substrate, and the positions of the devices on the upper substrate and the lower substrate are mirror-symmetrical with respect to the isolation layer. This double-layer integrated circuit structure further includes a conductive layer penetrating the upper substrate, the lower substrate, and the isolation layer for connecting in series the devices formed on the upper substrate and the lower substrate.

8. The highly integrated double-layer integrated circuit structure according to claim 7, characterized in that: It further includes an isolation region penetrating the upper substrate and the lower substrate, and the conductive layer is formed in the isolation region and is connected in series with the devices. The said device is provided with contacts, and the conductive layer and each contact are isolated by an ILD oxide layer.

9. The highly integrated double-layer integrated circuit structure according to claim 7, characterized in that: The device is a MOS transistor, including a well region formed in an upper substrate or a lower substrate, a source electrode and a drain electrode are respectively formed in the well region, a gate electrode is formed on the outer surface of the well region, and the gate electrode is located between the source electrode and the drain electrode. The source electrode and the drain electrode are connected through a channel, and the channel is isolated from the gate electrode.

10. The highly integrated double-layer integrated circuit structure according to claim 7 or 8, characterized in that: A dielectric barrier layer is provided on the outer surface of the device.

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