Area-efficient fully depleted semiconductor-on-insulator structure with hybrid threshold voltage transistor

Abstract

The invention relates to an area-efficient fully depleted semiconductor-on-insulator structure with hybrid threshold voltage transistors. The invention discloses a fully depleted semiconductor-on-insulator structure, which comprises a buried N-well, a P-well region and an N-well region, wherein the buried N-well is positioned in a substrate and below the P-well region and the N-well region; an insulator layer on the substrate, and a hybrid threshold voltage transistor on the insulator layer and over at least one of the well regions. The N-well may be connected to receive a positive bias voltage, where any of the NFETs and any of the PFETs located above are FBB LVT / SLVT NFETs and RBB RVT / HVT PFETs, respectively. The P-well may be connected to receive another positive bias voltage that is less than the positive bias voltage on the N-well, with any NFET and any PFET located above being an FBB RVT / HVT NFET and an RBB LVT / SLVT PFET, respectively. Additionally or alternatively, the P-well may be connected to receive a negative bias voltage, where any of the NFETs and any of the PFETs located above are RBB RVT / HVT NFETs and FBB LVT / SLVT PFETs, respectively.

Description

Technical Field

[0001] The present disclosure relates to a fully depleted semiconductor-on-insulator structure, and more particularly, to embodiments of an area efficient fully depleted semiconductor-on-insulator structure including a hybrid threshold voltage transistor. Background Art

[0002] Currently available fully depleted semiconductor-on-insulator (e.g., fully depleted silicon-on-insulator (FDSOI)) chip structures may include both conventional well regions and flipped well regions. These well regions are physically separated, typically each including a P-type well region laterally surrounded by an N-type well region (N-well) and aligned above a buried N-well. In the flipped well region, a P-channel field effect transistor (PFET) is located on an insulator layer and above the P-well, and an N-channel field effect transistor (NFET) is located on an insulator layer and above the N-well. In this case, both the PFET and the NFET are low threshold voltage (LVT) or ultra-low threshold voltage (SLVT) FETs that are only forward back biased (FBB) to avoid forward biasing of the PN junction between the P-well and the adjacent N-well. In the conventional well region, the PFET is located on an insulator layer and above the N-well, and the NFET is located on an insulator layer and above the P-well. In this case, both PFET and NFET are normal threshold voltage (RVT) or high threshold voltage (HVT) FETs, which are only reverse back biased (RBB) to avoid forward bias of the PN junction between the P well and the adjacent N well. In this fully depleted semiconductor-on-insulator chip structure, the physical separation between the normal well region and the flipped well region, especially the physical separation between its buried N well, increases the chip area consumption. In addition, the restriction on back bias reduces design flexibility. Summary of the invention

[0003] Embodiments of an area-efficient fully depleted semiconductor-on-insulator structure with mixed threshold voltage transistors and both forward and reverse back bias options are disclosed herein. The structure may include: an insulator layer located on a semiconductor substrate; and a plurality of well regions located in the semiconductor substrate and adjacent to the insulator layer. The well regions may include: an N-well; and a P-well laterally surrounded by the N-well. The structure may also include: an additional N-well (also referred to herein as a buried N-well) located in the semiconductor substrate and below the plurality of well regions. The structure may also include: a P-channel and an N-channel field effect transistor located on the insulator layer and above at least one of the plurality of well regions. In the structure, the N-well may be electrically connected to receive a first bias voltage, and the P-well may be electrically connected to receive a second bias voltage lower than the first bias voltage.

[0004] In some embodiments, the structure may include: an insulator layer located on a semiconductor substrate; and a plurality of well regions located in the semiconductor substrate and adjacent to the insulator layer. The well regions may include: an N-well; and a P-well laterally surrounded by the N-well. The structure may also include an additional N-well located in the semiconductor substrate and below the plurality of well regions. The structure may also include: a plurality of rows of field effect transistors located on the insulator layer. The rows may include a row of P-channel field effect transistors and a row of N-channel field effect transistors located above each well region. In the structure, the N-well may be electrically connected to receive a first bias voltage, and the P-well may be electrically connected to receive a second bias voltage lower than the first bias voltage.

[0005] In some embodiments, the structure may include: an insulator layer located on a semiconductor substrate; and a plurality of well regions located in the semiconductor substrate and adjacent to the insulator layer. The plurality of well regions may include alternating N-wells and P-wells. In addition, at least one of the well regions (e.g., the N-well and / or the P-well) includes an extension extending laterally from the well region into an adjacent well region of opposite conductivity. The structure may also include: an additional N-well located in the semiconductor substrate and below the plurality of well regions. The structure may also include: a plurality of rows of N-channel field effect transistors and P-channel field effect transistors located on the insulator layer and above the N-well and the P-well, respectively. In addition, given the extension, a row of N-channel field effect transistors includes at least one N-channel field effect transistor located on the insulator layer and above the P-type extension of the P-well; and / or a row of P-channel field effect transistors includes at least one P-channel field effect transistor located on the insulator layer and above the N-type extension of the N-well. In this structure, the N-well and any N-type extensions thereof are electrically connected to receive a first bias voltage; and the P-well and any P-type extensions thereof are electrically connected to receive a second bias voltage lower than the first bias voltage.

[0006] It should be noted that all aspects, examples and features of the disclosed embodiments mentioned in the above summary of the invention can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary of the invention, can be combined to form an embodiment not specifically described herein. The details of one or more embodiments are set forth in the drawings and the following description. Other features, objects and advantages will be apparent from the specification and drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure may be better understood by reference to the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0008] Figure 1 is a cross-sectional view illustrating a disclosed embodiment of a semiconductor-on-insulator structure;

[0009] Figure 2 can be combined with Figure 1 Schematic diagram of the NAND gate in the structure;

[0010] Figure 3 can be combined with Figure 1 Schematic diagram of the NOR gate in the structure;

[0011] Figure 4 It is shown Figure 1 diagrams of examples of novel arrangements of structures; and

[0012] Figure 5 and 6 It is shown Figure 1 FIG. 5 is a diagram of alternative examples of layouts of structures. DETAILED DESCRIPTION

[0013] As described above, currently available fully depleted semiconductor-on-insulator (e.g., FDSOI) chip structures may include both conventional well regions and flipped well regions. In the flipped well region, PFETs are formed on an insulator layer and above the P-well, so that they are LVT or SLVT PFETs, and NFETs are formed on an insulator layer and above the N-well, so that they are LVT or SLVT NFETs. Those skilled in the art will recognize that whether a FET is a SLVT or LVT FET, or whether a FET is a RVT or HVT FET will depend on the design (e.g., device size, etc.) and process specifications (e.g., dopant concentration, etc.). It should be understood that the LVT / SLVT and RVT / HVT specified in the following description and figures refer to LVT or SLVT FETs and RVT or HVT FETs, respectively. In any case, in the flipped well region, the P-well is laterally surrounded by the N-well, and both the P-well and the N-well are formed above the same buried N-well. In the conventional well region, the PFETs are formed on an insulator layer and above the N-well, so that they are RVT / HVT PFETs, and the NFETs are formed on an insulator layer and above the P-well, so that they are RVT / HVT NFETs. The P-well is again laterally surrounded by the N-well, and both the P-well and the N-well are formed above the same buried N-well (the buried N-well is physically separated from the buried N-well of the conventional well region, specifically referred to as isolation). Those skilled in the art will recognize that in a fully depleted semiconductor-on-insulator process technology platform (e.g., an FDSOI process technology platform), the FET can be forward back biased (FBB) or reverse back biased (RBB) by applying a specific bias voltage to the well region below the FET. FBB refers to applying a gate bias voltage to the well region to reduce the VT of the FET, thereby increasing the switching speed. For PFETs, FBB is achieved by applying a negative bias voltage, while for NFETs, FBB is achieved by applying a positive bias voltage. RBB refers to applying a gate bias voltage to the well region below the FET to increase the VT of the FET, thereby reducing the switching speed. For PFET, RBB is achieved by applying a positive bias voltage, while for NFET, RBB is achieved by applying a negative bias voltage.

[0014] As described above, in currently available semiconductor chip structures on insulators, this back bias is limited by the layout, in particular by the PN junction between the P-well and the adjacent N-well (on the side and below) in both the conventional well region and the flipped well region. If the P-well is biased by a positive bias voltage, and the adjacent N-well is biased by a negative bias voltage, the PN junction will be forward biased (i.e., conductive), thereby shorting the devices to each other and to the bottom of the substrate. Therefore, the P-well can only be biased by a P-well voltage (VPW) or a negative bias voltage of 0.0 volts (V), and the N-well can only be biased to an N-well voltage (VNW) or a positive bias voltage of 0.0V. In the flipped well region, a VPW or negative bias voltage of 0.0V to the P-well below the PFET and a VNW or positive bias voltage of 0.0V to the N-well below the NFET will cause the PFET and NFET to be ZB or FBB. In the conventional well region, a VPW or negative bias voltage of 0.0V to the P-well under the NFET and a VNW or positive bias voltage of 0.0V to the N-well under the PFET will cause the PFET and NFET to be ZB or RBB. In such a chip structure, the physical separation of the conventional well region and the flipped well region, especially the physical separation between its buried N-well, increases the chip area consumption. In addition, the restriction on back bias reduces the design flexibility.

[0015] In view of the above, embodiments of an area-efficient fully depleted semiconductor-on-insulator structure (e.g., an area-efficient FDSOI structure) with hybrid threshold voltage transistors and both forward and reverse back bias options are disclosed herein. The structure may include a buried N-well located in a substrate and below P-type and N-type well regions, an insulator layer located on the substrate, and hybrid threshold voltage transistors (e.g., at least LVT / SLVT FETs and RVT / HVT FETs) located on the insulator layer and above at least one well region. In the structure, the N-well may be electrically connected to receive a positive bias voltage, so any NFETs and PFETs located on the insulator layer and above the N-well will be FBB LVT / SLVT NFETs and RBB RVT / HVT PFETs, respectively. Optionally, the structure may include a NAND gate above the N-well, wherein the series-connected FBB LVT / SLVT NFETs are electrically connected to the parallel-connected RBB RVT / HVT PFETs to achieve optimal performance. In this structure, the P-well can be electrically connected to receive a positive bias voltage that is less than the positive bias voltage on the N-well, so any NFET and any PFET located on the insulator layer and above the P-well will be a FBB RVT / HVT NFET and a RBB LVT / SLVT PFET, respectively. Additionally or alternatively, the P-well can be electrically connected to receive a negative bias voltage, so any NFET and any PFET located on the insulator layer and above the P-well will be a RBBRVT / HVT NFET and a FBB LVT / SLVT PFET, respectively. In either case, the reverse bias of the PN junction between the P-well and the N-well in the semiconductor substrate is maintained. Optionally, the structure can include a NOR gate located above the P-well, wherein the series-connected FBB LVT / SLVT PFETs are electrically connected to the parallel-connected RBB RVT / HVT NFETs to achieve optimal performance.

[0016] More specifically, refer to Figure 1 Embodiments of a semiconductor-on-insulator structure 100 (hereinafter structure 100) such as a fully depleted semiconductor-on-insulator structure (e.g., a fully depleted silicon-on-insulator (FDSOI) structure) are disclosed herein. The structure 100 may include a semiconductor substrate 101. The semiconductor substrate 101 may be, for example, a single crystal silicon substrate or a substrate of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.). The semiconductor substrate 101 may have a bottom surface and a top surface opposite to the bottom surface.

[0017] The semiconductor substrate 101 may also include a plurality of well regions 113, 112a, and 112b located within the semiconductor substrate 101 and adjacent to the top surface of the semiconductor substrate 101. For the purposes of this disclosure, a well region refers to a region of semiconductor material that is doped (e.g., via a dopant implantation process or any other suitable doping process) to have a specific conductivity type. The well region may, for example, include one or more P-type well regions (P-wells) 112a, 112b located at an upper portion of the semiconductor substrate 101 (e.g., at the top surface of the semiconductor substrate 101) and an N-type well region (N-well) 113 that laterally surrounds each P-well 112a, 112.

[0018] The semiconductor substrate 101 may also include a buried N-well 111 located below the plurality of well regions 112a, 112b, and 113 and above the lower portion of the semiconductor substrate 101 (e.g., a distance from the bottom surface of the semiconductor substrate 101). Each P-well 112a, 112b may specifically have all bottom and side boundaries immediately adjacent to the N-type semiconductor material of the N-well and the buried N-well so as to be electrically isolated from the lower portion of the semiconductor substrate 101 below, as long as the PN junction diode formed between the P-well and the adjacent N-well and the buried N-well remains reverse biased. Those skilled in the art will recognize that a reverse biased diode does not conduct due to a negative voltage on the anode (P-type region) and a positive voltage on the cathode (N-type region), while a forward biased diode conducts due to a positive voltage on the anode and a negative voltage on the cathode.

[0019] For purposes of illustration, structure 100 is described and shown in the accompanying drawings as including two P-wells 112a and 112b located within semiconductor substrate 101. It should be understood that the description and drawings are not intended to be limiting. The inclusion of two P-wells 112a and 112b is to illustrate that, due to P-well isolation, different bias conditions can be optionally used on different P-wells, as discussed in more detail below. Alternatively, structure 100 can include only a single P-well, multiple P-wells electrically connected to receive the same bias voltage, multiple P-wells electrically connected to receive different bias voltages (as shown in the figure), etc.

[0020] The structure 100 may also include semiconductor-on-insulator regions (e.g., SOI regions). Each semiconductor-on-insulator region may include an insulator layer 102 located on the top surface of the semiconductor substrate 101. Therefore, within the semiconductor substrate 101, all well regions (e.g., P-wells 112a and 112b and N-well 113) will be adjacent to the insulator layer 102. The insulator layer 102 may be, for example, a thin silicon dioxide layer or a relatively thin layer of any other suitable insulator material. Each semiconductor-on-insulator region may include a thin semiconductor layer 106 located on the insulator layer 102. The semiconductor layer 106 may be, for example, a single crystal silicon layer or a layer of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.).

[0021] In each semiconductor-on-insulator region, the semiconductor layer 106 may further include an isolation structure 105. The isolation structure 105 may, for example, be a shallow trench isolation (STI) structure including a trench that extends vertically through the semiconductor layer 106 to or through the insulator layer 102, filled with one or more layers of isolation material (e.g., silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable isolation material). Alternatively, the isolation structure 105 may be any other suitable type of isolation structure (e.g., a diffusion-destroying structure). In any case, the isolation structure 105 may, for example, define the boundaries of the front-end-of-line (FEOL) device region and provide isolation between the FEOL device regions. The FEOL device region may, for example, include an active device region 110 for transistors (e.g., field effect transistors (FETs)), including P-type transistors (e.g., P-channel field effect transistors (PFETs) 152, 162, and / or 172, as discussed below) and N-type transistors (e.g., N-channel field effect transistors (NFETs) 151, 161, and / or 171, as discussed below).

[0022] Each FET may further include a channel region (C) located between a source region and a drain region (S / D) in the semiconductor layer 106 within its active device region 110. In the PFETs 152, 162, and / or 172, the source / drain regions may have a relatively high conductivity level of P-type conductivity (e.g., may be a P+ source / drain region), and the channel region may be intrinsic (i.e., undoped) or may have a relatively low conductivity level of N-type conductivity (e.g., may be an N-channel region). In the NFETs 151, 161, and / or 171, the source / drain regions may have a relatively high conductivity level of N-type conductivity (e.g., may be an N+ source / drain region), and the channel region may be intrinsic (i.e., undoped) or may have a relatively low conductivity level of P-type conductivity (e.g., may be a P-channel region).

[0023] Each FET may also include a main gate (also referred to herein as a front gate) adjacent to the active device region at the channel region (e.g., located above and immediately adjacent to the active device region). Those skilled in the art will recognize that in a field effect transistor (FET), a gate (also referred to as a gate structure) may include a gate dielectric layer (including one or more layers of gate dielectric material) adjacent to the channel region and a gate conductor layer (including one or more layers of gate conductor material) located on the gate dielectric layer. In each transistor, the main gate may include at least a relatively thin gate dielectric layer adjacent to the top surface of the semiconductor layer 106 at the channel region and a gate conductor layer located on the gate dielectric layer. The main gate may be any of a gate-first polysilicon gate structure, a gate-first high-K metal gate (HKMG) structure, a gate-last HKMG structure (also referred to as a replacement metal gate (RMG) structure), or any other suitable type of gate structure. Optionally, the main gate of the PFET may include a different gate material than the main gate of the NFET and may therefore have a different work function. Gate sidewall spacers may be positioned laterally adjacent to sidewalls of the main gate (eg, to electrically isolate the gate structure from adjacent S / D regions).

[0024] Each FET may also include a secondary gate (also referred to herein as a back gate) adjacent to the active device region 110 (e.g., located below and immediately adjacent to the active device region) opposite to the main gate. The secondary gate may include the insulator layer 102 and an adjacent portion of the underlying P-well 112a or 112b or N-well 113.

[0025] The structure 100 may also include body regions (also referred to as hybrid regions). These regions may not have an insulator layer 102, but may include one or more P-type well contact regions 114a, 114b (also referred to herein as Ptap) located on the semiconductor substrate 101 and adjacent to each P-well 112a, 112b and one or more N-type well contact regions 115 (also referred to herein as Ntap) located on the semiconductor substrate 101 and adjacent to the N-well 113. The Ptap 114a, 114b and the Ntap 115 are electrically isolated from the active device region 110 of any FET (e.g., 151-152, 161-162, 171-172) by the isolation structure 105. The Ptap 114a-114b and the Ntap 115 may, for example, include an epitaxially grown single crystalline semiconductor layer (e.g., an epitaxially grown silicon layer or an epitaxially grown layer of any other suitable semiconductor material) located on the top surface of the semiconductor substrate 101 and adjacent to the P-wells 112a and 112b and the N-well 113, respectively. Each Ptap 114a-114b may be doped (e.g., in-situ doped or subsequently implanted) to have P-type conductivity, optionally at a higher conductivity level than the underlying P-wells 112a and 112b. Each Ntap 115 may be doped (e.g., in-situ doped or subsequently implanted) to have N-type conductivity, optionally at a higher conductivity level than the underlying N-well 113. Optionally, the Ptap and / or Ntap may also include a silicide layer (not shown) thereon.

[0026] Generally, a fully depleted semiconductor-on-insulator structure (e.g., a FDSOI structure) including a semiconductor-on-insulator region having a semiconductor-on-insulator PFET and / or NFET and a body region having a well tap to a P-well and / or N-well in a substrate is well known in the art and can have various configurations. Therefore, details of the FETs, wells, and well taps, and processing techniques for forming them (e.g., conventional FDSOI processing techniques) have been omitted from the specification and drawings to allow the reader to focus on the salient aspects of the disclosed embodiments as discussed in more detail below (e.g., relating to the placement, shape, and biasing of the P-well and / or N-well within a semiconductor substrate, below the PFET and / or NFET, and above the same buried layer; relating to circuits formed thereon, etc.).

[0027] More specifically, in the structure 100, the N-well 113 may be electrically connected (via Ntap 115) to receive a first bias voltage (VNW). VNW may be a positive bias voltage. For example, VNW may be lower than, equal to, or higher than a positive power supply voltage (VDD) of the structure 100. Each P-well may be electrically connected to receive a second bias voltage that is less than the first bias voltage. For example, in some embodiments, the P-well 112a may be electrically connected (via Ptap 114a) to receive a second bias voltage (VPW1), specifically a second positive bias voltage at a voltage level between 0.0V and VNW (i.e., 0.0V<VPW1<VNW). Since VPW1 is less than VNW, the PN junction between the P-well 112a and the N-well 113 and the buried N-well 111 remains reverse biased. In some embodiments, the P-well 112 b can be electrically connected (via Ptap 114 b) to receive a second bias voltage (VPW2), specifically a negative bias voltage (i.e., VPW2 ≤ 0.0 V). Since VPW2 is negative, the PN junction between the P-well 112 b and the N-well 113 and the buried N-well 111 remains reverse biased.

[0028] In some embodiments, the structure 100 may include a first mixed threshold voltage region 150 including at least one NFET 151 and at least one PFET 152 located on the insulator layer 102 and aligned above the N-well 113 (which is electrically connected to receive VNW, specifically a positive bias voltage, as described above). Any NFET 151 above the N-well 113 is a LVT / SLVTNFFET, which is forward back biased (FBB) due to the VNW (which is positive) on the N-well 113. Any PFET 152 above the N-well 113 is a RVT / HVT PFET, which is reverse back biased (RBB) again due to the VNW (which is positive) on the N-well 113. In other words, the NFET 151 and the PFET 152 not only have mixed threshold voltages (i.e., LVT / SLVT and RVT / HVT, respectively), but also have different types of back biases (i.e., FBB and RBB, respectively).

[0029] Additionally or alternatively, the structure 100 may include a second mixed threshold voltage region 160 including at least one NFET 161 and at least one PFET 162 located on the insulator layer 102 and aligned above the P-well 112a (which, as described above, is electrically connected to receive VPW1, specifically a positive bias voltage at a voltage level lower than VNW). Any NFET 161 above the P-well 112a is a RVT / HVT NFET that is FBBed due to VPW1 (which is positive) on the P-well 112a. Any PFET 162 above the P-well 112a is a LVT / SLVT PFET that is RBBed due to VPW1 (which is positive) on the P-well 112a. In other words, the NFET 161 and the PFET 162 not only have mixed threshold voltages (i.e., RVT / HVT NFETs and LVT / SLVT PFETs), but also have different types of back biases (i.e., FBB NFETs and RBB PFETs).

[0030] Additionally or alternatively, the structure 100 may include a third mixed threshold voltage region 170 including at least one NFET 171 and at least one PFET 172 located on the insulator layer 102 and aligned above the P-well 112 b (which is electrically connected to receive VPW2, specifically a negative bias voltage, as described above). Any NFET 171 above the P-well 112 b is a RVT / HVTNFFET, which is RBBed due to VPW2 (which is negative) on the P-well 112 b. Any PFET 172 above the P-well 112 b is a LVT / SLVTPFET, which is FBBed due to VPW2 (which is negative) on the P-well 112 b. In other words, the NFET 171 and the PFET 172 not only have mixed threshold voltages (i.e., RVT / HVT NFET and LVT / SLVT PFET), but also have different types of back biases (i.e., RBB NFET and FBB PFET).

[0031] The structure 100 may be area efficient by providing NFETs and PFETs with mixed threshold voltages and different types of back bias conditions over the same undamaged buried N-well 111. In addition, the structure 100 may include one or more circuits including such NFETs and PFETs with mixed threshold voltages and different types of back bias conditions to achieve optimal performance.

[0032] refer to Figure 2, NAND gate 200 is an example of a circuit that can be incorporated into structure 100. As shown, NAND gate 200 may include a first subdivision having a plurality (e.g., two or more) of PFETs connected in parallel (according to a conventional NAND gate truth table) connected between a positive power supply voltage (VDD) and an output node 290. NAND gate 200 may also include a second subdivision having a plurality (two or more) of NFETs connected in series electrically connected between output node 290 and ground. The gate of each PFET may receive a different input A, B, etc. The gates of the NFETs may receive the same input, respectively. The operation of the first subdivision in response to the input combined with the operation of the second subdivision in response to the input results in a digital output signal at output node 290. Therefore, ideally, any operational delay of the first subdivision will be equal to the operational delay of the second subdivision to achieve optimal performance. However, due to the parallel connection between the PFETs in the first subdivision and the series connection between the NFETs in the second subdivision, the operational delay of the first subdivision will be less than the operational delay of the second subdivision.

[0033] In a conventional FDSOI structure, the NAND gate will be located on a conventional well or flipped well. Therefore, it will have all FBB LVT / SLVT PFETs and NFETs or all RBB RVT / HVT PFETs and NFETs. Therefore, back biasing will not reduce the delay difference. In addition, if the NAND gate has a relatively large number of stacked FETs, it may not operate reliably at lower voltages. However, combined with Figure 1 refer to Figure 2 In the disclosed embodiment, the NAND gate 200 can be formed on the insulator layer 102 in the first hybrid threshold voltage region 150 above the N-well 113 (which is connected to receive VNW, a positive bias voltage). In this case, the parallel-connected PFET can be PFET 152 (which is a RBB RVT / HVT PFET as described above), and the series-connected NFET can be NFET 151 (which is a FBB LVT / SLVT NFET as shown above). By incorporating the parallel-connected RBB RVT / HVTPFET 152 and the series-connected FBB LVT / SLVT NFET 151 into the NAND gate 200, the operation delay of the first division is increased and the operation delay of the second division is reduced. That is, the operation delays of the two divisions of the NAND gate 200 can be balanced for the desired performance level. In addition, even if the NAND gate 200 has a relatively large number of stacked FETs, it will operate reliably at a lower voltage.

[0034] refer to Figure 3, NOR gate 300 is another example of a circuit that can be incorporated into structure 100. As shown, NOR gate 300 may include a first subdivision having a plurality (e.g., two or more) of PFETs connected in series between a positive power supply voltage (VDD) and an output node 390. NOR gate 300 may also include a second subdivision having a plurality (two or more) of NFETs connected in parallel electrically connected between output node 390 and ground. The gate of each PFET may receive a different input A, B, etc. The gates of the NFETs may receive the same input, respectively. The operation of the first subdivision in response to the input combined with the operation of the second subdivision in response to the input results in a digital output signal at output node 390 (according to a conventional NOR gate truth table). Therefore, ideally, any operational delay of the first subdivision will be equal to the operational delay of the second subdivision to achieve optimal performance. However, due to the series connection between the PFETs in the first subdivision and the parallel connection between the NFETs in the second subdivision, the operational delay of the first subdivision will be greater than the operational delay of the second subdivision.

[0035] In a conventional FDSOI structure, the NOR gate will be located on a conventional well or flipped well. Therefore, it will have all FBB LVT / SLVT PFETs and NFETs or all RBB RVT / HVT PFETs and NFETs. Therefore, back biasing will not reduce the delay difference. In addition, if the NOR gate has a relatively large number of stacked FETs, it may not operate reliably at lower voltages. However, combined with Figure 1 refer to Figure 3 In the disclosed embodiment, the NOR gate 300 may be formed on the insulator layer 102 in the third hybrid threshold voltage region 170 above the P-well 112b (which is connected to receive VPW2, a negative bias voltage). In this case, the series-connected PFET may be the PFET 172 (which is a FBB LVT / SLVT PFET as described above), and the parallel-connected NFET may be the NFET 171 (which is a RBB RVT / HVT NFET as shown above). By incorporating the series-connected FBB LVT / SLVT PFET 172 and the parallel-connected RBB RVT / HVT NFET 171 into the NOR gate 300, the operation delay of the first division is reduced and the operation delay of the second division is increased. That is, the operation delays of the two divisions of the NOR gate 300 may be balanced to achieve optimal performance. In addition, even if the NOR gate 200 has a relatively large number of stacked FETs, it will operate reliably at a lower voltage.

[0036] Figure 4 It is shown that it can be used Figure 1FIG. 4 is a diagram of an example of a novel layout 400 of well regions and FETs of the structure 100. As shown in the layout 400, the structure may include a plurality of well regions located within a semiconductor substrate, the well regions including an N-well 113 for a first hybrid threshold voltage region 150 and P-wells 112a, 112b for a second hybrid threshold voltage region 160 and / or a third hybrid threshold voltage region 170, which are laterally surrounded by the N-well 113. The P-wells 112a, 112b may be elongated, substantially rectangular regions that are laterally positioned between similar elongated portions of the N-well 113. The structure may also include a buried N-well 111 located in the semiconductor substrate and below the plurality of well regions 112a, 112b, 113. The structure may also include, for example, two rows of FETs located on an insulator layer and above each P-well and above a portion of an N-well adjacent to the P-well or located between the P-wells. The two rows of FETs above may include a row of PFETs and a row of NFETs. For example, for the first hybrid threshold voltage region 150, a row of NFETs 151 and a row of PFETs 152 may be over an N-well 113 biased by VNW. Optionally, at least some of the NFETs 151 and PFETs 152 may be electrically connected to form a NAND gate 200. Additionally or alternatively, for the second hybrid threshold voltage region 160, a row of NFETs 161 and a row of PFETs 162 may be over a P-well 112a biased by VPW1 (e.g., 0.0V<VPW1<VNW). Additionally or alternatively, for the third hybrid threshold voltage region 170, a row of NFETs 171 and a row of PFETs 172 may be over a P-well 112b biased by VPW2 (e.g., VPW2<0.0V<VNW). Optionally, at least some of the NFETs 171 and PFETs 172 may be electrically connected to form a NOR gate 300. Thus, in such a layout 400, there are alternating rows of PFETs and NFETs. It should be understood that in order to avoid clutter in the figure and allow the reader to focus on the significant aspects of the structure related to the well region and the FETs above the well region, Figure 4 The example layout is not further shown as described above and Figure 1 All components of the structure 100 shown in FIG.

[0037] Those skilled in the art will recognize that in a typical FDSOI chip structure layout, multiple rows of FETs will be located on an insulator layer and aligned above each well region, and multiple rows of FETs located above a given well region will have the same type of conductivity. For example, in a flipped well configuration, multiple rows of NFETs will be located on an insulator layer and only above the N well, and multiple rows of PFETs will be located on an insulator layer and only above the P well; while in a conventional well configuration, multiple rows of NFETs will be located on an insulator layer and only above the P well, and multiple rows of PFETs will be located on an insulator layer and only above the N well. Therefore, there will usually be alternating pairs of PFET rows and pairs of NFET rows.

[0038] In the disclosed embodiment, instead of laying out the structure 100 in a completely new way with alternating single rows of PFETs and NFETs (e.g., as Figure 4 400), the conventional standard primitive layout may be modified to include one or more well extensions 580, 680, such as Figure 5 and 6 Example layouts 500 and 600 are shown.

[0039] More specifically, Figure 5 and 6are diagrams showing example layouts 500 and 600. As shown in these example layouts 500, 600, the structure 100 may include a plurality of well regions within a semiconductor substrate. These well regions may include an N-well 513, 613 and one or more P-wells 512, 612 that are laterally surrounded by the N-well 513, 613. The P-well 512, 612 may be an elongated substantially rectangular region that is laterally positioned between similar elongated portions of the N-well 513, 613. The structure may also include a buried N-well 511, 611 located in the semiconductor substrate and below the plurality of well regions 512-513, 612-613. The structure may also include two rows of FETs located on an insulator layer, above each P-well 512 and above a portion of an N-well 513 adjacent to the P-well or located between the P-wells. Typically, the rows of FETs located above each P-well 512, 612 will have the same type of conductivity, and the rows of FETs located above the N-well will have a different type of conductivity than the rows of FETs located above the P-well 512, 612. For example, in some embodiments, rows of NFETs 581, 681 may be located above the N-well 513, 613, and rows of PFETs 582, 682 may be located above the P-well 512, 612. In this case, the standard cell region 501 will include a row of one or more NFETs 581, 681 located on the N-well 513, 613 and a row of one or more PFETs 582, 682 located above the immediately adjacent P-well 512, 612. However, to implement any of the hybrid threshold voltage regions 150, 160, or 170 of the structure 100, as described above, one or more of the well regions may include well extensions 580, 680 that extend laterally from one well region into an immediately adjacent well region to form a modified primitive region 502, 602 that is laterally positioned between the transition regions 503, 603. It should be understood that the well extension will have the same type of conductivity as the well from which it extends, and will have a different type of conductivity than the adjacent well region to which it extends.

[0040] For example, referring specifically to Figure 5In the example layout 500 of FIG. 5 , the N-well extension 580 of the N-well 513 may extend laterally partially into the adjacent P-well 512, so that the modified cell region 502 includes one or more NFETs 151 formed simultaneously and in the same row as the NFETs 581 in the adjacent standard cell region 501 above the N-well 513, and one or more PFETs 152 formed simultaneously and in the same row as the PFETs 582 in the adjacent standard cell region 501 but above the N-well extension 580 and opposite to the P-well 512. The N-well extension 580 may be tapped (i.e., may have an Ntap thereon) so as to be electrically connected to receive the same bias voltage (i.e., VNW) used to bias the N-well 513 itself. Thus, the first hybrid threshold voltage region 150 may include one or more NFETs 151 located within a row of NFETs 581 formed on the N-well 513, and may also include one or more PFETs 152 located within a row of PFETs 582 but formed above the N-well extension 580. As discussed in more detail above, in the first hybrid threshold voltage region 150, the NAND gate 200 may include both the RBB RVT / HVT PFET 152 and the FBB LVT / SLVT NFET 151 to achieve optimal performance.

[0041] In addition, for example, specifically referring to Figure 6In the example layout 600 of FIG. 600 , the P-well extension 680 of the P-well 612 may extend laterally partially into a portion of the adjacent N-well 613, so that the modified cell region 602 includes one or more PFETs 162 or 172 formed simultaneously and in the same row as the PFET 682 in the adjacent standard cell region 601 above the P-well 612, and one or more NFETs 161 or 171 formed simultaneously and in the same row as the NFET 681 in the adjacent standard cell region 601, but above the P-well extension 680 and opposite to being located above the N-well 613. The P-well extension 680 may be tapped (i.e., may have a Ptap thereon) so as to be electrically connected to receive the same bias voltage (VPW) as the P-well 612. It should be understood that, as discussed in detail above, the NFETs 161 and 171 and the PFETs 162 and 172 may be simply distinguished by the P-well bias voltage (VPW) employed. In some embodiments, VPW may be equal to VPW1, which is a positive bias voltage less than VNW, to achieve the above-mentioned second hybrid threshold voltage region 160. Alternatively, VPW may also be equal to VPW2, which is a negative bias voltage, to achieve the above-mentioned third hybrid threshold voltage region 170. In either case, the modified primitive region 502, 602 includes a hybrid threshold voltage region 160, 170, which includes one or more PFETs 162, 172 (which are located in a row of PFETs 682 formed on the P-well 612) and one or more NFETs 161, 171 (which are located in a row of NFETs 681 but formed above the P-well extension 680). As discussed in more detail above, the second hybrid threshold voltage region 160 will include the RBB LVT / SLVT PFET 162 and the FBB RVT / HVT NFET 161, and the third hybrid threshold voltage region 170 will include the RBB RVT / HVT NFET 171 and the FBB LVT / SLVT PFET 172. Additionally, in the third hybrid threshold voltage region 170, the NOR gate 300 may include both the RBB RVT / HVT NFET 171 and the FBB LVT / SLVT PFET 172 to achieve optimal performance.

[0042] It should be understood that in the above structures and methods, semiconductor materials refer to materials whose conductive properties can be changed by doping with impurities. Such semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining III-group elements such as aluminum (Al), gallium (Ga) or indium (In) with V-group elements such as nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as non-intrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, non-intrinsic silicon is more conductive than intrinsic silicon; non-intrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. In addition, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with Group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with Group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity, and doped with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels depend on the relative concentration levels of (one or more) dopants in a given semiconductor region. In addition, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, its conductivity is higher (lower resistance) than the other semiconductor region or layer; and when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, its conductivity is lower (higher resistance) than the other semiconductor region or layer.

[0043] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having either or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0044] It should be understood that the terms used herein are used to describe the disclosed structures and methods and are not intended to be limiting. For example, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. In addition, as used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the features, wholes, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or groups thereof. In addition, as used herein, when oriented and shown in the figures, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "below", "under", "underlying", "above", "overlying", "parallel", "vertical", etc. are intended to describe relative positions (unless otherwise specified), and terms such as "touching", "direct contact", "adjacent", "directly adjacent", "immediately adjacent", etc. are intended to indicate that at least one element is in physical contact with another element (no other elements separate the elements). The term "laterally" is used herein to describe the relative position of elements and, more specifically, to indicate that one element is to the side of another element, rather than above or below the other element, when the elements are oriented and shown in the figures. For example, an element positioned laterally adjacent to another element will be to the side of the other element, an element positioned laterally next to another element will be directly to the side of the other element, and an element laterally surrounding another element will be adjacent to and bordering the outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed.

[0045] The description of the various disclosed embodiments is given for the purpose of illustration, but is not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications or technical improvements to technologies found on the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: an insulator layer disposed on the semiconductor substrate; a plurality of well regions located in the semiconductor substrate and adjacent to the insulator layer, and comprising: N-well; A P-well laterally surrounded by the N-well; an additional N-well located in the semiconductor substrate and below the plurality of well regions; and P-channel and N-channel field effect transistors located on the insulator layer and above at least one of the plurality of well regions, The N-well is electrically connected to receive a first bias voltage, and the P-well is electrically connected to receive a second bias voltage lower than the first bias voltage.

2. The structure according to claim 1, in, The first bias voltage is a positive bias voltage, wherein the P-channel and N-channel field effect transistors are located on the insulator layer and above the N-well, wherein each P-channel field effect transistor located on the N-well is one of a normal threshold voltage transistor and a high threshold voltage transistor that is reverse back biased by the positive bias voltage, and Each N-channel field effect transistor located on the N-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is forward back biased by the positive bias voltage.

3. The structure according to claim 2, wherein: The P-channel and N-channel field effect transistors include a plurality of parallel-connected P-channel field effect transistors and a plurality of serially connected N-channel field effect transistors that are electrically connected and form a NAND gate.

4. The structure according to claim 1, in, The first bias voltage is a first positive bias voltage, and the second bias voltage is a second positive bias voltage smaller than the first positive bias voltage. wherein the P-channel and N-channel field effect transistors are located on the insulator layer and above the P-well, wherein each P-channel field effect transistor located on the P-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is reverse back biased by the second positive bias voltage, and Each N-channel field effect transistor located above the P-well is one of a normal threshold voltage transistor and a high threshold voltage transistor that is forward back biased by the second positive bias voltage.

5. The structure according to claim 1, in, The first bias voltage is a positive bias voltage, the second bias voltage is a negative bias voltage, wherein the P-channel and N-channel field effect transistors are located on the insulator layer and above the P-well, wherein each P-channel field effect transistor located on the P-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is forward back biased by the negative bias voltage, and Each N-channel field effect transistor located on the P-well is one of a normal threshold voltage transistor and a high threshold voltage transistor which is reverse back biased by the negative bias voltage.

6. The structure according to claim 5, wherein: The P-channel and N-channel field effect transistors include a plurality of N-channel field effect transistors connected in parallel and a plurality of P-channel field effect transistors connected in series that are electrically connected and form a NOR gate.

7. The structure according to claim 1, in, The plurality of well regions include a plurality of P wells laterally surrounded by the N well, The structure further comprises a plurality of groups of P-channel and N-channel field effect transistors located on the insulator layer and above each of the plurality of well regions, and The P-well is electrically connected to receive the same second bias voltage.

8. The structure according to claim 1, in, The plurality of well regions include a plurality of P wells laterally surrounded by the N well, The structure further comprises a plurality of groups of P-channel and N-channel field effect transistors located on the insulator layer and above each of the plurality of well regions, and The P-well is electrically connected to receive at least two different second bias voltages.

9. A structure comprising: an insulator layer disposed on the semiconductor substrate; a plurality of well regions located in the semiconductor substrate and adjacent to the insulator layer, and comprising: N-well; A P-well laterally surrounded by the N-well; an additional N-well located in the semiconductor substrate and below the plurality of well regions; and a plurality of rows of field effect transistors located on the insulator layer and including a row of P-channel field effect transistors and a row of N-channel field effect transistors located above each well region, wherein the N-well is electrically connected to receive a first bias voltage, and The P-well is electrically connected to receive a second bias voltage lower than the first bias voltage.

10. The structure according to claim 9, in, The first bias voltage is a positive bias voltage, wherein each P-channel field effect transistor located above the N-well is one of a normal threshold voltage transistor and a high threshold voltage transistor that is reverse back biased by the positive bias voltage, and Each N-channel field effect transistor located above the N-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is forward back biased by the positive bias voltage.

11. The structure according to claim 10, wherein: Over the N-well, the P-channel and N-channel field effect transistors include a plurality of parallel-connected P-channel field effect transistors and a plurality of serially-connected N-channel field effect transistors that are electrically connected and form a NAND gate.

12. The structure according to claim 9, in, The first bias voltage is a first positive bias voltage, and the second bias voltage is a second positive bias voltage smaller than the first positive bias voltage. wherein each P-channel field effect transistor located above the P-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is reverse back biased by the second positive bias voltage, and Each N-channel field effect transistor located above the P-well is one of a normal threshold voltage transistor and a high threshold voltage transistor that is forward back biased by the second positive bias voltage.

13. The structure according to claim 9, in, The first bias voltage is a positive bias voltage, the second bias voltage is a negative bias voltage, wherein each P-channel field effect transistor located above the P-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is forward back biased by the negative bias voltage, and Each N-channel field effect transistor located above the P-well is one of a normal threshold voltage transistor and a high threshold voltage transistor which is reverse back biased by the negative bias voltage.

14. The structure according to claim 13, wherein: Over the P-well, the P-channel and N-channel field effect transistors include a plurality of parallel-connected N-channel field effect transistors and a plurality of serially-connected P-channel field effect transistors that are electrically connected and form a NOR gate.

15. A structure comprising: an insulator layer disposed on the semiconductor substrate; a plurality of well regions located in the semiconductor substrate and adjacent to the insulator layer, wherein the plurality of well regions include alternating N-wells and P-wells, and wherein at least one well region of the plurality of well regions includes an extension extending laterally into an adjacent well region; an additional N-well located in the semiconductor substrate and below the plurality of well regions; and a plurality of rows of N-channel field effect transistors and P-channel field effect transistors located on the insulator layer and above the N-well and the P-well, respectively; Among them, at least one of the following: a row of N-channel field effect transistors including at least one N-channel field effect transistor located on the insulator layer and above the P-type extension of the P-well; and a row of P-channel field effect transistors including at least one P-channel field effect transistor located on the insulator layer and above the N-type extension of the N-well, wherein the N-well and any N-type extension thereof are electrically connected to receive a first bias voltage; and The P-well and any P-type extensions thereof are electrically connected to receive a second bias voltage lower than the first bias voltage.

16. The structure according to claim 15, wherein: The first bias voltage is a positive bias voltage, wherein each P-channel field effect transistor located above the N-type extension is one of a conventional threshold voltage transistor and a high threshold voltage transistor that is reverse back biased by the positive bias voltage, and each N-channel field effect transistor located above the N-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is forward back biased by the positive bias voltage.

17. The structure of claim 16, further comprising: a plurality of P-channel field effect transistors connected in parallel and located above the N-type extension; and, a plurality of serially connected N-channel field effect transistors located above the N-well, wherein the plurality of parallel-connected P-channel field effect transistors and the plurality of serially connected N-channel field effect transistors are electrically connected and form a NAND gate.

18. The structure of claim 15, wherein: The first bias voltage is a first positive bias voltage, and the second bias voltage is a second positive bias voltage lower than the first positive bias voltage, wherein each P-channel field effect transistor located above the P-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is reverse back biased by the second positive bias voltage, and each N-channel field effect transistor located above the P-type extension is one of a conventional threshold voltage transistor and a high threshold voltage transistor that is forward back biased by the second positive bias voltage.

19. The structure of claim 15, wherein: The first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage, wherein each P-channel field effect transistor located above the P-well is one of a low threshold voltage transistor and an ultra-low threshold voltage transistor that is forward back biased by the negative bias voltage, and each N-channel field effect transistor located above the P-type extension is one of a conventional threshold voltage transistor and a high threshold voltage transistor that is reverse back biased by the negative bias voltage.

20. The structure of claim 19, further comprising: a plurality of N-channel field effect transistors connected in parallel and located above the P-type extension; and, a plurality of P-channel field effect transistors connected in series above the P-well, wherein the plurality of N-channel field effect transistors connected in parallel and the plurality of P-channel field effect transistors connected in series are electrically connected and form a NOR gate.

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