Wafer structure and manufacturing method thereof

Abstract

The invention discloses a wafer structure and a manufacturing method thereof. The wafer structure comprises a bare chip array, wherein the bare chip array is formed by arranging a plurality of bare chip arrays; the included angle between the length direction of the set doping structure in at least one bare chip and the length direction of the set doping structure in the bare chip adjacent to the bare chip is a first set included angle, and the first set included angle is larger than 0 degree and smaller than or equal to 90 degrees; the length direction of the set doping structure is the direction where the longest edge in the set doping structure is located. The invention provides a wafer structure and a manufacturing method thereof. The problem of warping of the wafer structure in the manufacturing process can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer structure and a manufacturing method thereof. Background Art

[0002] Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is an important semiconductor device. It is composed of a metal layer, an oxide layer, and a semiconductor material, and controls the on and off of current through the electric field effect. This device has the advantages of high input resistance, low noise, low power consumption, and easy integration, and is widely used in electronic devices.

[0003] However, in the process of manufacturing multiple transistors, the injection of set ions into the wafer structure causes the warping of the wafer structure to increase dramatically. The highly warped wafer structure can easily get stuck in some machines, causing problems such as inability to pass goods or even the wafer structure getting stuck and broken. Summary of the invention

[0004] The present invention provides a wafer structure and a manufacturing method thereof, which can improve the warping problem of the wafer structure generated during the manufacturing process.

[0005] According to one aspect of the present invention, a wafer structure is provided, the wafer structure comprising:

[0006] A bare chip array is composed of a plurality of bare chips arranged in an array;

[0007] The angle between the length direction of the set doping structure in at least one of the bare chips and the length direction of the set doping structure in the bare chip adjacent thereto is a first set angle, wherein the first set angle is greater than 0° and less than or equal to 90°, and the length direction of the set doping structure is the direction of the longest side of the set doping structure.

[0008] Optionally, an angle between a length direction of the set doping structure in any of the bare chips and a length direction of the set doping structure in any of the adjacent bare chips is the first set angle.

[0009] Optionally, the first set angle is equal to 90°.

[0010] Optionally, each of the set doping structures in each of the bare chips includes a first set doping substructure and a second set doping substructure;

[0011] In the same set doping structure, the angle between the length direction of the first set doping substructure and the length direction of the second set doping substructure is the second set angle, wherein the second set angle is greater than 0° and less than or equal to 90°, the length direction of the first set doping substructure is the direction of the longest side of the first set doping substructure, and the length direction of the second set doping substructure is the direction of the longest side of the second set doping substructure.

[0012] Optionally, the second set angle is equal to 90°.

[0013] Optionally, in a bare chip row, each of the first set doping substructures is arranged along a first direction;

[0014] In the bare chip row, each of the second set doping substructures is arranged along a second direction, and an angle between the first direction and the second direction is the second set angle.

[0015] Optionally, each of the bare chips includes a substrate and an epitaxial layer located on one side of the substrate;

[0016] A plurality of set doping structures in the bare chip are located in the epitaxial layer;

[0017] The doping structure is set to be a trench gate;

[0018] Each of the bare chips further includes a gate pad;

[0019] In the same bare chip, the gate pad is electrically connected to each of the set doping structures.

[0020] Optionally, a vertical projection of the gate pad on the substrate is an axisymmetric figure;

[0021] The lengths of the set doping structures on both sides of the symmetry axis of the axisymmetric figure are equal.

[0022] Optionally, each of the bare chips further includes a field limiting ring;

[0023] The field limiting ring completely surrounds each of the set doping structures in the bare chip where the field limiting ring is located.

[0024] Optionally, the material of the substrate and the material of the epitaxial layer both include silicon carbide.

[0025] According to another aspect of the present invention, a method for manufacturing a wafer structure is provided, and the method manufactures the wafer structure provided by any embodiment of the present invention;

[0026] The production method comprises:

[0027] A bare chip array is manufactured, wherein the bare chip array is composed of a plurality of bare chip arrays; the angle between the length direction of a set doping structure in at least one of the bare chips and the length direction of the set doping structure in the bare chip adjacent thereto is a first set angle, wherein the first set angle is greater than 0° and less than or equal to 90°, and the length direction of the set doping structure is the direction of the longest side of the set doping structure.

[0028] The present embodiment provides a wafer structure, which includes a bare chip array, and the bare chip array is composed of a plurality of bare chip arrays. In the bare chip array, there is at least one bare chip whose length direction of the set doping structure and the length direction of the set doping structure in the adjacent bare chip are greater than 0° and less than or equal to 90°. That is, the length directions of the set doping structures of the bare chips in the wafer structure provided by the present embodiment are not exactly the same, thereby avoiding the problem of severe warping of the wafer structure caused by the stress concentration of the wafer structure in the same direction when making multiple set doping structures. In the wafer structure provided by the present embodiment, the length directions of the set doping structures in at least two bare chips are different. In this way, when making multiple set doping structures, the wafer structure can bear stress in two different directions, thereby improving the warping problem of the wafer structure during the manufacturing process.

[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a schematic diagram of a top view of a wafer structure provided according to an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of a top view of another wafer structure provided according to an embodiment of the present invention;

[0033] Figure 3 is a schematic diagram of a top view of another wafer structure provided according to an embodiment of the present invention;

[0034] Figure 4 is a schematic structural diagram of a bare chip provided according to an embodiment of the present invention;

[0035] Figure 5 is a schematic diagram of a top view of another wafer structure provided according to an embodiment of the present invention;

[0036] Figure 6 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention;

[0037] Figure 7 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention;

[0038] Figure 8 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention;

[0039] Fig. 9 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention;

[0040] Fig.10 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention;

[0041] Fig.11 It is a flow chart of a method for manufacturing a wafer structure provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Figure 1is a schematic diagram of a top view of a wafer structure provided according to an embodiment of the present invention, Figure 2 is a schematic diagram of a top view of another wafer structure provided according to an embodiment of the present invention. Figure 3 is a schematic diagram of a top view of another wafer structure provided according to an embodiment of the present invention. Figure 4 is a schematic diagram of the structure of a bare chip provided according to an embodiment of the present invention, with reference to Figure 1-Figure 4 The wafer structure 100 provided in this embodiment includes a bare chip array composed of a plurality of bare chips 110 arranged in an array; and a plurality of transistor bare chips 110 arranged in an array. The angle between the length direction of the set doping structure 113 in at least one bare chip 110 and the length direction of the set doping structure 113 in the bare chip 110 adjacent thereto is a first set angle, wherein the first set angle is greater than 0° and less than or equal to 90°, and the length direction of the set doping structure 113 is the direction of the longest side of the set doping structure 113.

[0045] Among them, reference Figure 4 , the bare chip 110 includes a substrate 111, an epitaxial layer 112 located on one side of the substrate 111, and a plurality of set doping structures 113 located in the epitaxial layer 112. The substrates 111 of each bare chip 110 may be connected as a whole, and the epitaxial layers 112 of each bare chip 110 may also be connected as a whole. The bare chip 110 refers to an unpackaged chip. The wafer structure in this embodiment refers to a structure that has not been cut. In each bare chip 110, the arrangement direction of the plurality of set doping structures 113 may intersect with the length direction of the set doping structure 113. The set doping structure 113 may be a structure in which a set type of ions is doped in a set region of the epitaxial layer 112, and the set doping structure 113 may extend from the surface of the epitaxial layer 112 away from the substrate 111 to the inside of the epitaxial layer 112, and the set type of ions may be P-type ions or N-type ions. The P-type ions may be at least one of B, Al, Ga, and In, and the N-type ions may be at least one of P, As, and Sb ions, etc. Each bare chip 110 further includes a gate trench, an insulating layer and a trench gate located in the gate trench, and the doping structure 113 may be a trench gate.

[0046] The angle between the length direction of the set doping structure 113 in at least one bare chip 110 and the length direction of the set doping structure 113 in the adjacent bare chip 110 is the first set angle, which may be: in at least one bare chip row 210, or in at least one bare chip column 220, or in at least one bare chip row 210 and at least one bare chip column 220, the angle between the length direction of the set doping structure 113 in at least one bare chip 110 and the length direction of the set doping structure 113 in the adjacent bare chip 110 is the first set angle. The bare chip row 210 in the bare chip array may include at least two bare chips 110, and the bare chip column 220 also includes at least two bare chips 110. The bare chip row 210 is composed of the bare chips 110 in the same row of the bare chip array, and the bare chip column 220 is composed of the bare chips 110 in the same column of the bare chip array.

[0047] Continue to refer Figure 1 , a bare chip array 220 ( Figure 1 The third column in the figure includes a first bare chip 101 and a second bare chip 102, the length direction of the doping structure 113 in the first bare chip 101 is set to be a first direction X, the length direction of the doping structure 113 in the second bare chip 102 is set to be a second direction Y, and the angle between the first direction X and the second direction Y is equal to the first set angle. The first set angle in this embodiment can be specifically 90°, 85°, 80°, 75°, 70°, 65°, 60° or 45°, etc. When the doping structure 113 is set to be a trench gate, the length direction of the doping structure 113 is set to be the same direction as the length direction of the gate trench.

[0048] In the bare chip array, at least two bare chips 110 have different length directions of the doping structures 113. For example, Figure 1 In each bare chip row 210, the length direction of the set doping structure 113 of each bare chip 110 is the same, but in each bare chip column 220, the length direction of the set doping structure 113 of each bare chip 110 and the length direction of the set doping structure 113 of the adjacent bare chip 110 form an angle of the first set angle. Figure 2 , a bare chip 110 (may be referred to as Figure 2 In the bare chip row 210 and bare chip column 220 where the first bare chip in the bare chip row 210 is located, the length directions of the set doping structures 113 in each bare chip 110 are the same, but in other bare chip rows 210 and bare chip columns 220, there is at least one bare chip 110 whose length direction and the length direction of the set doping structure 113 in the adjacent bare chip 110 have an angle that is the first set angle. Figure 3The angle between the length direction of the set doping structure 113 in each bare chip 110 and the length direction of the set doping structure 113 in the adjacent bare chip 110 is a first set angle.

[0049] If the length directions of the set doping structures 113 of each bare chip 110 in the wafer structure 100 are consistent, then when the set type of ions are injected into the set area, the wafer structure 100 will warp in the first direction X or in the second direction Y. However, in this embodiment, the length direction of the set doping structure 113 in at least one bare chip 110 and the length direction of the set doping structure 113 in the adjacent bare chip 110 are set to have an angle greater than 0° and less than or equal to 90°, that is, in the wafer structure 100, the length directions of the set doping structures 113 of at least two bare chips 110 are different. This arrangement allows the wafer structure 100 to bear stress in both the first direction X and the second direction Y, thereby avoiding stress concentration in the same direction to cause severe warping of the wafer structure 100.

[0050] It should be noted that each bare chip 110 in this embodiment further includes other doped regions, interlayer insulating layers, active layers, etc. The first direction X may be a row direction, and the second direction Y may be a column direction.

[0051] The present embodiment provides a wafer structure, which includes a bare chip array, and the bare chip array is composed of a plurality of bare chip arrays. In the bare chip array, there is at least one bare chip whose length direction of the set doping structure and the length direction of the set doping structure in the adjacent bare chip are greater than 0° and less than or equal to 90°. That is, the length directions of the set doping structures of the bare chips in the wafer structure provided by the present embodiment are not exactly the same, thereby avoiding the problem of severe warping of the wafer structure caused by the stress concentration of the wafer structure in the same direction when making multiple set doping structures. In the wafer structure provided by the present embodiment, the length directions of the set doping structures in at least two bare chips are different. In this way, when making multiple set doping structures, the wafer structure can bear stress in two different directions, thereby improving the warping problem of the wafer structure during the manufacturing process.

[0052] Optional, Figure 5 is a schematic diagram of a top view of another wafer structure provided according to an embodiment of the present invention, referring to Figure 3 and Figure 5The angle between the length direction of the set doping structure 113 in any bare chip 110 and the length direction of the set doping structure 113 in any adjacent bare chip 110 is the first set angle. This arrangement allows the length direction angles of the set doping structures 113 in any two adjacent bare chips 110 to be the first set angle, so that when manufacturing multiple set doping structures 113, the wafer structure 100 can bear stress in both the first direction X and the second direction Y, and the stress in the first direction X is not much different from the stress in the second direction Y, further improving the warping problem of the wafer structure 100 generated during the manufacturing process.

[0053] Optional, continue to refer to Figure 1-Figure 3 The first set angle is equal to 90°. With this setting, when manufacturing multiple set doping structures 113, the wafer structure 100 can bear stress in both the first direction X and the second direction Y, and the stress of the wafer structure 100 in the first direction X and the stress in the second direction Y can be made basically equal, which can further improve the warping problem of the wafer structure 100 generated during the manufacturing process.

[0054] Optional, Figure 6 is a schematic diagram of another wafer structure provided according to an embodiment of the present invention, with reference to Figure 6 , each set doping structure 113 in each bare chip 110 includes a first set doping substructure 114 and a second set doping substructure 115; in the same set doping structure 113, the angle between the length direction of the first set doping substructure 114 and the length direction of the second set doping substructure 115 is a second set angle, wherein the second set angle is greater than 0° and less than or equal to 90°, the length direction of the first set doping substructure is the direction of the longest side in the first set doping substructure, and the length direction of the second set doping substructure is the direction of the longest side in the second set doping substructure.

[0055] Specifically, the widths of the first doping substructures 114 may be equal, and the widths of the second doping substructures 115 may also be equal. In the same doping structure 113 , the length of the first doping substructure 114 may be equal to the length of the second doping substructure 115 .

[0056] When the doping structure 113 includes the first doping substructure 114 and the second doping substructure 115 , the length direction of the doping structure 113 includes two directions, one direction is the length direction of the first doping substructure 114 , and the other direction is the length direction of the second doping substructure 115 .

[0057] In the same set doping structure 113, the length of the first set doping substructure 114 and the length of the second set doping substructure 115 are set to extend in two different directions, so that the bare chip has stress in both the first direction X and the second direction Y, so that when manufacturing multiple set doping structures 113, the wafer structure 100 bears stress in both the first direction X and the second direction Y, further improving the warping problem of the wafer structure 100 generated during the manufacturing process.

[0058] Optional, continue to refer to Figure 6 , and the second set angle is equal to 90°. With this arrangement, when manufacturing multiple set doping structures 113, the wafer structure 100 bears stress in both the first direction X and the second direction Y, and the stress borne by the wafer structure 100 in the first direction X is basically consistent with the stress borne in the second direction Y, thereby further improving or even eliminating the warping problem of the wafer structure 100 generated during the manufacturing process.

[0059] Optional, continue to refer to Figure 6 In the bare chip row 210, each first set doping substructure 114 is arranged along the first direction X; in the bare chip column 220, each second set doping substructure 115 is arranged along the second direction Y, and the angle between the first direction X and the second direction Y is the second set angle.

[0060] Specifically, in the wafer structure 100, the arrangement directions of the first set doping substructures 114 in all the bare chips 110 are the same, and the arrangement directions of the second set doping substructures 115 in all the bare chips 110 are the same. Each set doping structure 113 in each bare chip 110 is set to include the first set doping substructure 114 and the second set doping substructure 115, and the angle between the length direction of the first set doping substructure 114 and the length direction of the second set doping substructure 115 is the second set angle, so that each bare chip 110 can bear stress in the first direction X and the second direction Y. Therefore, the arrangement directions of the set doping structures 113 in each bare chip 110 can be set to be the same, which can not only improve the warping problem of the wafer structure 100 generated during the manufacturing process, but also eliminate the need to consider the arrangement directions of each set doping structure 113 too much during the manufacturing process of the wafer structure 100, thereby improving the manufacturing efficiency of the wafer structure 100.

[0061] Optional, Figure 7 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention, Figure 8 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention, Fig. 9 is a structural schematic diagram of another wafer structure provided according to an embodiment of the present invention, Fig.10 is a schematic diagram of another wafer structure provided according to an embodiment of the present invention, with reference to Figure 7-10 , the doping structure 113 is set to be a trench gate; each bare chip 110 also includes a gate pad 120; in the same bare chip 110, the gate pad 120 is electrically connected to each set doping structure 113.

[0062] Specifically, the gate pad 120 has a conductive function, and the gate pad 120 is used to transmit an electrical signal to the trench gate. The shape of the vertical projection of the gate pad 120 on the substrate includes a first rectangle and a second rectangle, and the first rectangle is integrally connected to the second rectangle. The first rectangle can be a square, and the second rectangle can be a rectangle. The length of the first rectangle is less than the length of the second rectangle, and the width of the first rectangle is greater than the width of the second rectangle.

[0063] Optional, continue to refer to Figure 7-10 The vertical projection of the gate pad 120 on the substrate is an axially symmetrical figure; the lengths of the set doping structures 113 on both sides of the symmetry axis of the axially symmetrical figure are equal. This arrangement can make the impedances of the set doping structures 113 on both sides of the gate pad 120 the same, thereby further improving the reliability of the bare chip 110.

[0064] Specifically, the bare chip 110 may include four sides, and the symmetry axis of the axisymmetric figure may coincide with the center line of any side of the bare chip 110, or the symmetry axis of the axisymmetric figure may coincide with the diagonal line of the bare chip 110. The symmetry axis of the axisymmetric figure may be perpendicular to the length direction of the doping structure 113 (see Figure 7-Figure 9 ), the symmetry axis of the axially symmetrical pattern may be at an angle of 45° with the length direction of the first set doping substructure 114, and at an angle of 45° with the length direction of the second set doping substructure 115 (refer to Fig.10 ).

[0065] Optional, continue to refer to Figure 1-Figure 3 ,as well as Figure 5-Figure 10 As shown in any of the figures, each bare chip 110 further includes a field limiting ring 130, and the field limiting ring 130 completely surrounds each set doping structure 113 in the bare chip where the field limiting ring 130 is located.

[0066] Specifically, the field limiting ring 130 is used to protect the bare chip from being broken down by high voltage.

[0067] Optionally, the material of the substrate and the material of the epitaxial layer both include silicon carbide.

[0068] Specifically, silicon carbide material has the characteristics of large bandgap, strong critical breakdown electric field, high thermal conductivity, high temperature resistance and excellent heat dissipation performance. The bare chip in the wafer structure made of silicon carbide material works in a high temperature environment without the need for additional heat dissipation devices.

[0069] This embodiment also provides a method for manufacturing a wafer structure, and the manufacturing method can manufacture the wafer structure provided by any embodiment of the present invention. Fig.11 is a schematic diagram of a process for manufacturing a wafer structure according to an embodiment of the present invention, with reference to Fig.11 The method for manufacturing the wafer structure provided in this embodiment includes the following steps:

[0070] S110, providing a substrate.

[0071] S120. Fabricate a bare chip array on one side of the substrate, wherein the bare chip array is composed of a plurality of bare chip arrays; an angle between a length direction of a set doping structure in at least one bare chip and a length direction of a set doping structure in an adjacent bare chip is a first set angle, wherein the first set angle is greater than 0° and less than or equal to 90°, and the length direction of the set doping structure is the direction of the longest side of the set doping structure.

[0072] The manufacturing method of the wafer structure provided in this embodiment has corresponding beneficial effects with the wafer structure provided in any embodiment of the present invention. For technical details not elaborated in this embodiment, please refer to the wafer structure provided in any embodiment of the present invention.

[0073] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0074] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A wafer structure, characterized in that: include: A bare chip array is composed of a plurality of bare chips arranged in an array; The angle between the length direction of the set doping structure in at least one of the bare chips and the length direction of the set doping structure in the bare chip adjacent thereto is a first set angle, wherein the first set angle is greater than 0° and less than or equal to 90°, and the length direction of the set doping structure is the direction of the longest side of the set doping structure.

2. The wafer structure according to claim 1, characterized in that: The angle between the length direction of the set doping structure in any of the bare chips and the length direction of the set doping structure in any of the adjacent bare chips is the first set angle.

3. The wafer structure according to claim 1, characterized in that: The first set angle is equal to 90°.

4. The wafer structure according to claim 1, characterized in that: Each of the set doping structures in each of the bare chips includes a first set doping substructure and a second set doping substructure; In the same set doping structure, the angle between the length direction of the first set doping substructure and the length direction of the second set doping substructure is the second set angle, wherein the second set angle is greater than 0° and less than or equal to 90°, the length direction of the first set doping substructure is the direction of the longest side of the first set doping substructure, and the length direction of the second set doping substructure is the direction of the longest side of the second set doping substructure.

5. The wafer structure according to claim 4, characterized in that: The second set angle is equal to 90°.

6. The wafer structure according to claim 4, characterized in that: In a bare chip row, each of the first set doping substructures is arranged along a first direction; In the bare chip row, each of the second set doping substructures is arranged along a second direction, and an angle between the first direction and the second direction is the second set angle.

7. The wafer structure according to any one of claims 1 to 6, characterized in that: Each of the bare chips comprises a substrate and an epitaxial layer located on one side of the substrate; A plurality of set doping structures in the bare chip are located in the epitaxial layer; The doping structure is set to be a trench gate; Each of the bare chips further includes a gate pad; In the same bare chip, the gate pad is electrically connected to each of the set doping structures.

8. The wafer structure according to claim 7, characterized in that: The vertical projection of the gate pad on the substrate is an axisymmetric figure; The lengths of the set doping structures on both sides of the symmetry axis of the axisymmetric figure are equal.

9. The wafer structure according to claim 1, characterized in that: Each of the bare chips also includes a field limiting ring; The field limiting ring completely surrounds each of the set doping structures in the bare chip where the field limiting ring is located.

10. The wafer structure according to claim 7, characterized in that: The material of the substrate and the material of the epitaxial layer both include silicon carbide.

11. A method for manufacturing a wafer structure, characterized in that: Used to manufacture the wafer structure according to any one of claims 1 to 10; The production method comprises: A bare chip array is manufactured, wherein the bare chip array is composed of a plurality of bare chip arrays; the angle between the length direction of a set doping structure in at least one of the bare chips and the length direction of the set doping structure in the bare chip adjacent thereto is a first set angle, wherein the first set angle is greater than 0° and less than or equal to 90°, and the length direction of the set doping structure is the direction of the longest side of the set doping structure.

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