Display panel and method of manufacturing the same

Abstract

A display panel and a method of manufacturing the same are provided. The display panel includes: a base layer; a pixel defining film disposed on the base layer and having a light emitting opening; a partition wall including a first partition wall layer disposed on the pixel defining film and a second partition wall layer disposed on the first partition wall layer, in which a partition wall opening is defined in the partition wall to overlap the light emitting opening; and a light emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall, in which at least a portion of the light emitting element is disposed inside the partition wall opening, in which a first inner surface of the first partition wall layer and a second inner surface of the second partition wall layer are aligned with each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0134158, filed on October 10, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display panel and a method of manufacturing the display panel, and more particularly, to a display panel having improved display quality. Background Art

[0004] Display devices such as televisions, monitors, smart phones, and tablet personal computers (PCs) that provide images to users may include display panels that display images. As display panels, various display panels have been developed, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separated for each of a plurality of light emitting regions, and the cathode may provide a common voltage to each of the plurality of light emitting regions. Summary of the invention

[0006] Embodiments of the present disclosure provide a display panel and a method of manufacturing the display panel which are provided by forming a light emitting element without using a metal mask and have improved display quality.

[0007] According to an embodiment, a display panel includes a base layer, a pixel defining film, a partition wall and a light-emitting element, wherein the pixel defining film is arranged on the base layer, wherein a light-emitting opening is defined in the pixel defining film, the partition wall includes a first partition wall layer arranged on the pixel defining film and a second partition wall layer arranged on the first partition wall layer, wherein a partition wall opening is defined in the partition wall to overlap with the light-emitting opening, the light-emitting element includes an anode, an intermediate layer and a cathode in contact with the partition wall, wherein at least a portion of the light-emitting element is arranged inside the partition wall opening, and a first inner surface of the first partition wall layer and a second inner surface of the second partition wall layer are aligned with each other.

[0008] In an implementation, the second partition wall layer may include an inorganic material.

[0009] In an embodiment, the second partition wall layer may include a layer selected from SiON and SiN x At least one of .

[0010] In an embodiment, the display panel may further include a plurality of light emitting regions from which light provided from the light emitting element is emitted, wherein the cathodes are disconnected by the partition walls to correspond to the plurality of light emitting regions.

[0011] In an implementation, the display panel may further include a lower encapsulation inorganic pattern covering the light emitting element, wherein the lower encapsulation inorganic pattern may be disposed inside the partition wall opening.

[0012] In an implementation, a side surface of the lower encapsulation inorganic pattern may be in contact with the second inner surface of the second partition wall layer.

[0013] In an embodiment, the display panel may further include an encapsulation organic film disposed on the lower encapsulation inorganic pattern, wherein the encapsulation organic film may cover an upper surface of the second partition wall layer and an upper surface of the lower encapsulation inorganic pattern.

[0014] In an embodiment, the cathode may extend along the first inner surface of the first partition wall layer, and an end portion of the cathode may contact the first partition wall layer.

[0015] In an embodiment, the width of the partition wall opening may be constant along the first partition wall layer and the second partition wall layer.

[0016] According to an embodiment, a method for manufacturing a display panel includes: providing a preliminary display panel in which a base layer, an anode, a pixel defining film, a first preliminary partition wall layer, and a second preliminary partition wall layer are sequentially laminated, forming a third preliminary partition wall layer and a fourth preliminary partition wall layer on the first preliminary partition wall layer and the second preliminary partition wall layer, forming a preliminary partition wall including a tip portion and defining a preliminary partition wall opening by etching the first preliminary partition wall layer to the fourth preliminary partition wall layer, forming a light emitting pattern and a cathode on the anode, forming a preliminary lower encapsulation inorganic pattern on the cathode, and forming a partition wall and a lower encapsulation inorganic pattern by etching the preliminary lower encapsulation inorganic pattern, the third preliminary partition wall layer, and the fourth preliminary partition wall layer.

[0017] In an embodiment, the method may further include etching a portion of the second preliminary partition wall layer corresponding to the anode.

[0018] In an embodiment, forming a preliminary partition wall including a tip portion by etching a first preliminary partition wall layer to a fourth preliminary partition wall layer and defining a preliminary partition wall opening may include: forming a first preliminary partition wall opening by etching the first preliminary partition wall layer, a third preliminary partition wall layer, and a fourth preliminary partition wall layer, and forming a second preliminary partition wall opening by etching the first preliminary partition wall layer to the third preliminary partition wall layer.

[0019] In an embodiment, the second preliminary partition wall opening may include a first region defined by the inner surface of the first preliminary partition wall layer, the inner surface of the second preliminary partition wall layer, and the inner surface of the third preliminary partition wall layer, and a second region defined by the inner surface of the fourth preliminary partition wall layer, and a width of the second region may be smaller than a width of the first region.

[0020] In an implementation, the etched fourth preliminary partition wall layer may define a tip portion.

[0021] In an embodiment, forming the light emitting pattern and the cathode on the anode may include forming a first dummy pattern including the same material as the light emitting pattern and a second dummy pattern including the same material as the cathode on the preliminary partition wall.

[0022] In an embodiment, forming the preliminary lower encapsulation inorganic pattern on the cathode may include forming a lower encapsulation inorganic layer to cover the cathode and the preliminary partition wall, and etching a portion of the lower encapsulation inorganic layer that does not overlap the anode.

[0023] In an implementation, the method may further include etching the first dummy pattern and the second dummy pattern.

[0024] In an embodiment, forming a partition wall and a lower encapsulation inorganic pattern by etching a preliminary lower encapsulation inorganic pattern, a third preliminary partition wall layer, and a fourth preliminary partition wall layer may include: etching the third preliminary partition wall layer and the fourth preliminary partition wall layer, wherein a first partition wall layer included in the partition wall is formed by the first preliminary partition wall layer, and a second partition wall layer included in the partition wall is formed by the second preliminary partition wall layer.

[0025] In an embodiment, forming a partition wall and a lower encapsulation inorganic pattern by etching a preliminary lower encapsulation inorganic pattern, a third preliminary partition wall layer, and a fourth preliminary partition wall layer may also include: etching a preliminary lower encapsulation inorganic pattern overlapping the third preliminary partition wall layer and the fourth preliminary partition wall layer, wherein a side surface of the lower encapsulation inorganic pattern contacts an inner surface of the second partition wall layer.

[0026] According to an embodiment, a display panel includes a base layer, a pixel defining film, a partition wall, a light-emitting element, and a lower encapsulation inorganic pattern, wherein the pixel defining film is disposed on the base layer, wherein a light-emitting opening is defined in the pixel defining film, the partition wall includes a first partition wall layer disposed on the pixel defining film and a second partition wall layer disposed on the first partition wall layer, wherein a partition wall opening is defined in the partition wall to overlap with the light-emitting opening, the light-emitting element includes an anode, an intermediate layer, and a cathode in contact with the partition wall, wherein at least a portion of the light-emitting element is disposed inside the partition wall opening, the lower encapsulation inorganic pattern covers the light-emitting element and is disposed in the partition wall opening, wherein the lower encapsulation inorganic pattern does not overlap with the partition wall in the thickness direction of the base layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure;

[0029] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0030] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present disclosure;

[0031] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure;

[0032] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present disclosure;

[0033] Figure 5 According to the embodiment of the present disclosure Figure 3 A cross-sectional view of the display panel taken along line II';

[0034] Figure 6 is along Figure 4 A cross-sectional view taken along line II-II'; and

[0035] FIG. 7A to FIG. 7L are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0037] It should be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

[0038] In the specification, the statement that a first component (or region, layer, part, portion, etc.) is "on", "connected to" or "coupled to" a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or means that a third component is interposed therebetween.

[0039] The same reference numerals refer to the same components. In addition, in the accompanying drawings, for the effective description of the technical content, the thickness, ratio and size of the components are exaggerated. The terms used in this article are only for the purpose of describing a specific embodiment, and are not intended to be limited. Unless otherwise clearly indicated in the context, "a", "an", "the" and "at least one" as used herein do not represent the limitation of quantity, and are intended to include both the singular and the plural. Therefore, after mentioning "a" element in the claim, the reference to "the" element includes one element and multiple elements. For example, unless otherwise clearly indicated in the context, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0040] Although the terms "first", "second", etc. may be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0041] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, the term "lower" can include both the orientations of "lower" and "upper", depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "beneath" of the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "below" can include both the orientations of the upper and lower parts.

[0042] It should also be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including” when used in the present specification specify the presence of features, integers, steps, operations, elements or components, or a combination thereof, described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, elements or components, or a combination thereof.

[0043] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0044] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an overly idealized or overly formal meaning.

[0045] Embodiments are described herein with reference to schematically illustrated cross-sectional illustrations as idealized embodiments. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the zones, and are not intended to limit the scope of the claims.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1A is a perspective view of a display device DD according to an embodiment of the present disclosure, and Figure 1B is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0048] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an external billboard. In an embodiment, the display device DD may be a small or medium-sized electronic device such as a personal computer (PC), a notebook computer, a personal digital terminal, a vehicle navigation unit, a game console, a smart phone, a tablet PC, and a camera. However, this is illustrative, and other display devices may be adopted as long as the display device does not deviate from the concept of the present disclosure. Figure 1A and Figure 1B An embodiment in which the display device DD is a smartphone is shown.

[0049] Reference Figure 1A and Figure 1B , an embodiment of the display device DD may display an image IM in a third direction DR3 on a display surface FS parallel to the first direction DR1 and the second direction DR2. The third direction DR3 may be a normal direction of a plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 may be a thickness direction of the display device DD. The image IM may include a still image and a dynamic image. In an embodiment, as Figure 1A As shown in , for example, the image IM may include a monitoring window and an icon. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0050] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each member are defined relative to the direction on which the image IM is displayed. The front surface and the rear surface may face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. Here, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions. In the specification, the phrase "on a plane" or "in a plan view" may mean a state when observed in the third direction DR3.

[0051] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to constitute the exterior of the display device DD.

[0052] The window WP may include an optically transparent insulating material. In an embodiment, for example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. In an embodiment, for example, the transmission area TA may be a region having a visible light transmittance of about 90% or more.

[0053] The frame area BZA may be an area having a relatively lower light transmittance than the light transmittance of the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. However, this is illustrative, and the frame area BZA of the window WP may be omitted. The window WP may include at least one functional layer selected from an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to one embodiment.

[0054] The display module DM may be disposed under the window WP. The display module DM may be a component that basically generates an image IM. The image IM generated by the display module DM is displayed on a display surface IS of the display module DM and is visually recognized by a user from the outside through the transmissive area TA.

[0055] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated based on an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the bezel area BZA and may not be visually recognized from the outside.

[0056] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0057] The housing HAU may include a material having relatively high rigidity. In an embodiment, for example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, metal, or a combination thereof. The housing HAU may stably protect the components of the display device DD accommodated in the internal space from external impacts.

[0058] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0059] Reference Figure 2 , an embodiment of the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to an embodiment of the present disclosure (see Figure 1A ) may further include an anti-reflection member and / or a window member disposed on an upper surface of the protection member, or an input sensor INS disposed on a lower surface of the display panel DP.

[0060] The display panel DP may be a light-emitting display panel. However, this is illustrative, and the present disclosure is not particularly limited thereto. In an embodiment, for example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro light-emitting diodes (LEDs). Hereinafter, for the convenience of description, an embodiment in which the display panel DP is an organic light-emitting display panel will be described in detail.

[0061] The display panel DP may include a base layer BL and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE sequentially arranged on the base layer BL. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. In this specification, the phrase "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B.

[0062] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1B The described display area DA and non-display area NDA may be defined on the base layer BL in the same manner.

[0063] The circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element includes a signal line, a driving circuit of a pixel, or the like.

[0064] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer, and a cathode.

[0065] The thin film encapsulation layer TFE may include a plurality of thin films, at least one selected from the plurality of thin films may be arranged to improve optical efficiency, and at least one selected from the plurality of thin films may be arranged to protect the organic light emitting diode.

[0066] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. In addition, the input sensor INS may include a single layer or multiple layers of insulating layers. The input sensor INS may detect the external input in a capacitive manner. However, this is illustrative, and the present disclosure is not limited thereto. For example, in an embodiment, the input sensor INS may also detect the external input in an electromagnetic induction manner or a pressure sensing manner. In another embodiment of the present disclosure, the input sensor INS may be omitted.

[0067] Figure 3 is a plan view of a display panel DP according to an embodiment of the present disclosure.

[0068] Reference Figure 3 , an embodiment of the display panel DP may include a display area DA and a non-display area NDA around the display area DA. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad part PLD. The display area DA and the non-display area NDA may be distinguished according to whether the pixels PX are provided. The pixels PX may be provided in the display area DA. The drive circuit GDC and the pad part PLD may be arranged in the non-display area NDA.

[0069] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0070] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL may be connected to a corresponding pixel among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel among the pixels PX. The power line PL may be electrically connected to the pixel PX. The control signal line CSL may be connected to the drive circuit GDC to provide a control signal to the drive circuit GDC.

[0071] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate lines GL. The gate driving circuit may also output another control signal to the pixel driving circuit.

[0072] The pad part PLD may be a part to which a flexible circuit board is connected. The pad part PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line among the signal lines SGL. The pixel pad D-PD may be connected to the corresponding pixel PX through the signal line SGL. In addition, any one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0073] In an embodiment, the pad part PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see Figure 2 However, the present disclosure is not limited thereto, and the input pad may be arranged on the input sensor INS (see Figure 2 ) and connected to a circuit board separate from the pixel pad D-PD. Alternatively, the input sensor INS (see Figure 2) may be omitted and the input pad may not be further included.

[0074] Figure 4 is a display panel DP according to an embodiment of the present disclosure (see Figure 2 ) is an enlarged plan view of a portion of the display area DA. Figure 4 shows when the display module DM (see Figure 1B ) of the display surface IS (see Figure 1B ) is a plane of the display module DM when observed, and shows the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0075] Reference Figure 4 In an embodiment, the display area DA may include a first light-emitting area PXA-R, a second light-emitting area PXA-G, and a third light-emitting area PXA-B and a peripheral area NPXA surrounding the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B (hereinafter, for the convenience of explanation, the light-emitting area PXA-R indicates the same features as the first light-emitting area PXA-R; the light-emitting area PXA-G indicates the same features as the second light-emitting area PXA-G; and the light-emitting area PXA-B indicates the same features as the third light-emitting area PXA-B; and they are not particularly distinguished in the description). The first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may respectively correspond to areas from which light provided from the light-emitting element is emitted. The first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may be based on the direction toward the display module DM (see Figure 2 ) is classified by the color of the light emitted externally.

[0076] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may respectively provide first to third color lights having different colors. In an embodiment, for example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not necessarily limited to the above examples.

[0077] Each of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be defined as a region in which the upper surface of the anode is exposed by the light emitting opening, which will be described below. The peripheral region NPXA may set a boundary between the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B, and effectively prevent color mixing between the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B.

[0078] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be provided so that all of them are in plural numbers, and may be repeatedly arranged in the display area DA in a specific arrangement form. In an embodiment, for example, the first light emitting region PXA-R and the third light emitting region PXA-B may be alternately arranged in the first direction DR1 to constitute a "first group". The second light emitting region PXA-G may be arranged in the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" may be provided in plural numbers, and the "first group" and the "second group" may be alternately arranged in the second direction DR2.

[0079] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0080] Figure 4 The arrangement form of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B in the embodiment is shown, but the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be arranged in various forms. Figure 4 As shown in FIG. 1 , the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have Alternatively, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may also have a stripe arrangement or a diamond arrangement. Layout form.

[0081] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have various shapes on a plane. In an embodiment, for example, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a shape such as a polygonal shape, a circular shape, or an elliptical shape. Figure 4 An embodiment is shown in which each of the first light emitting region PXA-R and the third light emitting region PXA-B has a quadrangular shape (or a diamond shape) and the second light emitting region PXA-G has an octagonal shape on a plane.

[0082] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same shape as each other on a plane, or may have shapes at least partially different from each other. Figure 4An embodiment is shown in which the first and third light emitting regions PXA-R and PXA-B have the same shape as each other on a plane and the second light emitting region PXA-G has a shape different from those of the first and third light emitting regions PXA-R and PXA-B.

[0083] At least some of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have different areas on a plane. In an embodiment, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light, and may be smaller than the area of ​​the third light emitting region PXA-B emitting blue light. However, the size relationship between the areas of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B based on the color of the emitted light is not limited thereto, and may be selected according to the display module DM (see Figure 2 However, the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may also have the same area as each other on a plane.

[0084] In the embodiment of the present disclosure, the display module DM (see Figure 2 The shapes, areas, arrangements, or the like of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be based on the color of the emitted light or the display module DM (see Figure 2 ) size and configuration to be designed or modified differently, and is not limited to Figure 4 Those shown in .

[0085] Figure 5 According to the embodiment of the present disclosure Figure 3 1-1' is a cross-sectional view of the display panel DP taken along line II'. Figure 5 The same or similar elements shown in FIG. 1 have been used to describe Figure 2 The embodiments shown in the drawings are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter. Figure 5 The display area DA is shown (see Figure 4 ) is an enlarged view of a portion including only one light emitting region PXA, and Figure 5 The light emitting area PXA may correspond to Figure 4 one of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B.

[0086] Reference Figure 5, an embodiment of the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0087] The display panel DP may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, a plurality of signal lines, or the like. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, or the like. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching processes. In this way, semiconductor patterns, conductive patterns, signal lines, and the like included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0088] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0089] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve a coupling force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately laminated in the buffer layer BFL.

[0090] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the present disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 Only a portion of the semiconductor pattern is shown, and the semiconductor pattern may be further arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 4 ). The semiconductor pattern may be arranged in a specific rule across a plurality of light emitting regions PXA-R, PXA-G, and PXA-B. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical properties. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0091] The conductivity of the first region is greater than the conductivity of the second region, and the first region is substantially used as an electrode or a signal line. The second region may substantially correspond to an active portion (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active portion of a transistor, another portion of the semiconductor pattern may be a source or drain of the transistor, and another portion of the semiconductor pattern may be a conductive region.

[0092] The source S, the active portion A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed of a semiconductor pattern is shown. Although not separately shown, the signal transmission region SCL may be connected to the drain D of the transistor TR1 on a plane.

[0093] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be disposed on the buffer layer BFL. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may include an inorganic layer or an organic layer.

[0094] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active portion A, and the drain D of the transistor TR1 and the signal transmission region SCL disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0095] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0096] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 defined through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0097] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, and a partition wall PW.

[0098] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode).

[0099] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through the connection contact hole CNT-3 defined through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including indium tin oxide (ITO) and Ag. In an embodiment, for example, the anode AE ​​may include a layer including ITO (hereinafter referred to as a lower ITO layer), a layer disposed on the lower ITO layer and including Ag (hereinafter referred to as an Ag layer), and a layer disposed on the Ag layer and including ITO (hereinafter referred to as an upper ITO layer).

[0100] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel defining film PDL. A sacrificial opening OP-S may be defined (or provided) in the sacrificial pattern SP, and a portion of the upper surface of the anode AE ​​is exposed through the sacrificial opening OP-S. The sacrificial opening OP-S may overlap with the light emitting opening OP-E, which will be described below.

[0101] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening OP-E may be defined (or provided) in the pixel defining film PDL. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0102] In an embodiment, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to an embodiment, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL in a cross section with the sacrificial pattern SP interposed therebetween, and thus, damage to the anode AE ​​may be effectively prevented in a process of forming the light emitting opening OP-E.

[0103] On a plane (or when viewed in the third direction DR3), the area of ​​the light emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner surface of the pixel defining film PDL defining the light emitting opening OP-E may be closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the present disclosure is not limited thereto, and the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel defining film PDL defining the light emitting opening OP-E (or on the same plane). In such an embodiment, the light emitting area PXA may be regarded as an area of ​​the anode AE ​​that is exposed from the corresponding sacrificial opening OP-S.

[0104] The pixel definition layer PDL may include an inorganic insulating material. In an embodiment, for example, the pixel definition layer PDL may include silicon nitride (SiN x ). The pixel defining film PDL may be disposed between the anode AE ​​and the partition wall PW, and prevents electrical connection between the anode AE ​​and the partition wall PW.

[0105] The light emitting pattern EP may be disposed on the anode AE. The light emitting pattern EP may include a light emitting layer including a light emitting material. The light emitting pattern EP may also include a hole injection layer and a hole transport layer disposed between the anode AE ​​and the light emitting layer, and may also include an electron transport layer and an electron injection layer disposed on the light emitting layer. The light emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0106] The light emitting pattern EP may be formed by a preliminary partition wall PW-I (see Figure 7F ) is patterned by the tip portion defined in the pixel defining film PDL. A detailed description thereof will be given below. The light emitting pattern EP may be disposed inside the sacrificial opening OP-S and the light emitting opening OP-E. However, this is illustrative, and the light emitting pattern EP may be disposed inside at least one of the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL.

[0107] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be formed by a preliminary partition wall PW-I (see Figure 7F ) is patterned according to the tip portion defined in ). A detailed description thereof will be given below. At least a portion of the cathode CE may be disposed in the partition wall opening OP-P. Figure 5 An embodiment in which the cathode CE is disposed inside the light emitting opening OP-E and the partition wall opening OP-P is shown, but the present disclosure is not limited thereto. In an embodiment, for example, the cathode CE may be disposed only inside the partition wall opening OP-P.

[0108] The cathode CE may extend along the first inner surface S-L1 of the first partition wall layer L1, and an end of the cathode CE may contact the first partition wall layer L1. At least a portion of the cathode CE may contact the first inner surface S-L1 of the first partition wall layer L1. Figure 5 An embodiment in which the cathode CE contacts the first inner surface S-L1 of the first partition wall layer L1 and the inner surface of the pixel defining film PDL is shown, but the present disclosure is not limited thereto. In an embodiment, for example, the cathode CE may contact only the first inner surface S-L1 of the first partition wall layer L1.

[0109] The cathode CE may be conductive. For example, the cathode CE may be formed of at least one selected from various conductive materials such as metals, transparent conductive oxides (TCOs), and conductive polymer materials. In an embodiment, for example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0110] In an embodiment of the present disclosure, the display element layer DP-OLED may further include a covering pattern CP. The covering pattern CP may be disposed inside the partition wall opening OP-P or the light emitting opening OP-E and disposed on the cathode CE. The covering pattern CP may be formed by a preliminary partition wall PW-I (see FIG. 1 ) formed in a display panel manufacturing process. Figure 7F ) is patterned according to the tip portion defined in ). A detailed description thereof will be given below. In another embodiment, the covering pattern CP may be omitted.

[0111] The partition wall PW may be disposed on the pixel defining film PDL. A partition wall opening OP-P may be defined in the partition wall PW. The partition wall opening OP-P may correspond to the light emitting opening OP-E and expose at least a portion of the anode AE.

[0112] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition film PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 5 As shown in FIG. 4 , the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2 , but the present disclosure is not limited thereto.

[0113] The first partition wall layer L1 may include a first inner surface S-L1, and the second partition wall layer L2 may include a second inner surface S-L2. The partition wall opening OP-P may be defined by the first inner surface S-L1 of the first partition wall layer L1 and the second inner surface S-L2 of the second partition wall layer L2. The first inner surface S-L1 of the first partition wall layer L1 and the second inner surface S-L2 of the second partition wall layer L2 may be aligned with each other or on the same plane, that is, jointly form the same continuous surface. The width of the partition wall opening OP-P may be continuous or constant along the first partition wall layer L1 and the second partition wall layer L2. That is, the portions of the first partition wall layer L1 and the second partition wall layer L2 may not be recessed compared to their other portions. The partition wall PW may not be undercut and may not include a tip portion.

[0114] The first partition wall layer L1 and the second partition wall layer L2 may include a conductive material. In an embodiment, for example, the conductive material may include a metal, a TCO, or a combination thereof. In an embodiment, for example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO may include ITO, indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide. In an embodiment of the present disclosure, the second partition wall layer L2 may include an inorganic material. In an embodiment, for example, the second partition wall layer L2 may include a material selected from silicon oxynitride (SiON) and silicon nitride (SiN x ) at least one of.

[0115] Figure 5 An embodiment in which each of the first inner surface S-L1 and the second inner surface S-L2 is perpendicular to the upper surface of the pixel defining film PDL is shown, but the present disclosure is not limited thereto. In an embodiment, for example, the partition wall PW may have a tapered shape or an inverse tapered shape in cross section.

[0116] The partition wall PW may receive a driving voltage, and thus, the cathode CE may be electrically connected to the partition wall PW to receive the driving voltage.

[0117] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0118] The lower encapsulation inorganic pattern LIL may correspond to the light emitting opening OP-E. The lower encapsulation inorganic pattern LIL may be disposed on the cathode CE and may cover the light emitting element ED. The lower encapsulation inorganic pattern LIL may be formed inside the partition wall opening OP-P. In an embodiment, for example, the lower encapsulation inorganic pattern LIL may not be formed on the partition wall PW, but may be formed inside the partition wall opening OP-P. An end of the lower encapsulation inorganic pattern LIL may contact the second inner surface S-L2 of the second partition wall layer L2. That is, on a plane, the lower encapsulation inorganic pattern LIL may not overlap with the partition wall PW in a third direction DR3 which may be a thickness direction of the base layer BL.

[0119] According to an embodiment of the present disclosure, since the lower encapsulation inorganic pattern LIL is in direct contact and connection with the second partition wall layer L2 containing an inorganic material, the connection force of the lower encapsulation inorganic pattern LIL can be improved. In this embodiment, the lower encapsulation inorganic pattern LIL may not be disposed on the partition wall PW. Therefore, the sealing ability of the lower encapsulation inorganic pattern LIL for protecting the display element layer DP-OLED can be improved, and pixel defects (black spots, pixel shrinkage, or the like) caused by foreign matter introduced from the side surface of the lower encapsulation inorganic pattern LIL formed on the partition wall PW can be reduced or eliminated. In this embodiment, in the process of etching the lower encapsulation inorganic pattern LIL, the wet etching area is increased, and thus the mass production rate (or manufacturing efficiency) of the display panel DP can be improved.

[0120] The encapsulation organic film OL may be disposed on the lower encapsulation inorganic pattern LIL. The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The encapsulation organic film OL may cover the upper surface U-L2 of the second partition wall layer L2 and the upper surface U-LIL of the lower encapsulation inorganic pattern LIL. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL.

[0121] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0122] Figure 5 An embodiment in which the thin film encapsulation layer TFE includes a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the thin film encapsulation layer TFE may further include an inorganic pattern disposed between the lower encapsulation inorganic pattern LIL and the encapsulation organic film OL. In another embodiment, the thin film encapsulation layer TFE may not include the encapsulation organic film OL.

[0123] Figure 6 is along Figure 4 A cross-sectional view taken along line II-II'. Figure 6 is an enlarged view showing a portion including a first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B, and the above reference Figure 5 The features described for a light emitting region PXA can be applied similarly to Figure 6 The first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B.

[0124] Reference Figure 6, an embodiment of the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, and a partition wall PW.

[0125] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 (hereinafter, for the convenience of explanation, the light-emitting element EDn and the nth light-emitting element EDn indicate the same features and they are not particularly distinguished in the description, and n is 1, 2, or 3). The first light-emitting element ED1 may include a first anode AE1, a first light-emitting pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be provided as a plurality of patterns (or defined by a plurality of patterns). In an embodiment, the first light-emitting pattern EP1 may provide (or emit) red light, the second light-emitting pattern EP2 may provide green light, and the third light-emitting pattern EP3 may provide blue light.

[0126] A first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E may be defined in the pixel defining film PDL. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0127] In an embodiment, the first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first light emitting opening OP1-E. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second light emitting opening OP2-E. The third light emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed by the third light emitting opening OP3-E.

[0128] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be arranged on upper surfaces of the first anode AE1, the second anode AE2, and the third anode AE3, respectively. A first sacrificial opening OP1-S, a second sacrificial opening OP2-S, and a third sacrificial opening OP3-S respectively overlapping the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3.

[0129] In an embodiment, a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P, which overlap with the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the partition wall PW. The inner surface of the first partition wall layer L1 and the inner surface of the second partition wall layer L2 of each of the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P may be aligned with each other or on the same plane. That is, portions of the first partition wall layer L1 and the second partition wall layer L2 may not be recessed compared to other portions thereof. The partition wall PW may not be undercut and may not include a tip portion.

[0130] The first light emitting pattern EP1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P and the first light emitting opening OP1-E, the second light emitting pattern EP2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P and the second light emitting opening OP2-E, and the third light emitting pattern EP3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P and the third light emitting opening OP3-E. The first cathode CE1, the second cathode CE2, and the third cathode CE3 may be disconnected from each other by the partition wall PW to correspond to the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B.

[0131] In an embodiment, the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 and the first cathode CE1, the second cathode CE2, and the third cathode CE3 may be formed by a preliminary partition wall PW-I (see Figure 7F) are physically separated from each other and can therefore be formed inside the first sacrificial opening OP1-S, the second sacrificial opening OP2-S and the third sacrificial opening OP3-S, the first light-emitting opening OP1-E, the second light-emitting opening OP2-E and the third light-emitting opening OP3-E, or the first partition wall opening OP1-P, the second partition wall opening OP2-P and the third partition wall opening OP3-P, respectively.

[0132] According to an embodiment of the present disclosure, a plurality of first light emission patterns EP1 may be formed by a preliminary partition wall PW-I (see Figure 7F ) is patterned and deposited in units of pixels. That is, the first light emission patterns EP1 may be commonly formed using an open mask, but may be easily divided in units of pixels by the partition walls PW.

[0133] In the case where the first light emitting pattern EP1 is patterned using a fine metal mask (FMM), it may be desirable to provide a support spacer protruding from a conductive partition wall to support the FMM. In this case, since the FMM is separated from the base surface on which patterning is performed by the height of the partition wall and the support spacer, the implementation of high resolution may be limited. In this case, since the fine metal mask is in contact with the support spacer, foreign matter may remain on the support spacer after the patterning process of the first light emitting pattern EP1, and the support spacer may be damaged by stamping of the mask. Therefore, a defective display panel may be formed.

[0134] According to an embodiment, the preliminary partition wall PW-I (see Figure 7F ) can easily perform physical separation between the light emitting elements ED1, ED2, and ED3. Therefore, current leakage or driving error between the adjacent light emitting regions PXA-R, PXA-G, and PXA-B can be effectively prevented, and each of the light emitting elements ED1, ED2, and ED3 can be independently driven.

[0135] In this embodiment, since there is no need to use the display area DA (see Figure 1B ) is patterned with a plurality of first light emitting patterns EP1 without using a mask that contacts the internal components inside the display panel DP, thereby reducing the defect rate, and thus a display panel DP with improved process reliability can be provided. Since patterning can be performed even without providing a separate supporting spacer protruding from the partition wall PW, the areas of the light emitting regions PXA-R, PXA-G, and PXA-B can be miniaturized, and thus a display panel DP with high resolution can be provided.

[0136] In this embodiment, when manufacturing a large-area display panel DP, a display panel DP can be provided in which process costs can be reduced due to the omission of production of a large-area mask, and process reliability can be improved due to the display panel DP being unaffected by defects that may occur in the large-area mask. The description of the plurality of first light emitting patterns EP1 can be similarly applied to the plurality of second light emitting patterns EP2 and the third light emitting pattern EP3.

[0137] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1 , LIL2 , and LIL3 , an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0138] In an embodiment, the lower encapsulation inorganic patterns LIL1, LIL2, and LIL3 may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2, and a third lower encapsulation inorganic pattern LIL3. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may overlap with the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively. The first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3 may be provided in the form of patterns spaced apart from each other.

[0139] The first lower encapsulation inorganic pattern LIL1 may cover the first light emitting element ED1. The first lower encapsulation inorganic pattern LIL1 may be formed inside the first partition wall opening OP1-P. In an embodiment, for example, the first lower encapsulation inorganic pattern LIL1 may not be formed on the partition wall PW corresponding to the first light emitting element ED1, but may be formed inside the first partition wall opening OP1-P. An end portion (or side surface) of the first lower encapsulation inorganic pattern LIL1 may be aligned with a second inner surface S-L2 (see Figure 5 )touch.

[0140] The second lower encapsulation inorganic pattern LIL2 may cover the second light emitting element ED2. The second lower encapsulation inorganic pattern LIL2 may be formed inside the second partition wall opening OP2-P. In an embodiment, for example, the second lower encapsulation inorganic pattern LIL2 may not be formed on the partition wall PW corresponding to the second light emitting element ED2, but may be formed inside the second partition wall opening OP2-P. The end (or side surface) of the second lower encapsulation inorganic pattern LIL2 may be aligned with the second inner surface S-L2 (see Figure 5 )touch.

[0141] The third lower encapsulation inorganic pattern LIL3 may cover the third light emitting element ED3. The third lower encapsulation inorganic pattern LIL3 may be formed inside the third partition wall opening OP3-P. In an embodiment, for example, the third lower encapsulation inorganic pattern LIL3 may not be formed on the partition wall PW corresponding to the third light emitting element ED3, but may be formed inside the third partition wall opening OP3-P. An end portion (or side surface) of the third lower encapsulation inorganic pattern LIL3 may be aligned with the second inner surface S-L2 (see Figure 5 )touch.

[0142] The encapsulation organic film OL may be disposed on the first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3. The encapsulation organic film OL may cover the first lower encapsulation inorganic pattern LIL1, the second lower encapsulation inorganic pattern LIL2, and the third lower encapsulation inorganic pattern LIL3. In an embodiment, for example, the encapsulation organic film OL may cover the upper surface U-L2 of the second partition wall layer L2 and the upper surface U-LIL1 of the first lower encapsulation inorganic pattern LIL1, the upper surface U-LIL2 of the second lower encapsulation inorganic pattern LIL2, and the upper surface U-LIL3 of the third lower encapsulation inorganic pattern LIL3.

[0143] FIG. 7A to FIG. 7L are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to an embodiment of the present disclosure. FIG. 7A to FIG. 7L The same or similar elements shown in FIG. 1 have been used to describe Figures 1A to 6 The embodiments shown in the drawings are denoted by the same reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0144] The following will refer to FIG. 7A to FIG. 7L An embodiment of a method of forming one light emitting element ED and a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL covering the light emitting element ED is described. FIG. 7A to FIG. 7L The display panel DP formed may correspond to Figure 5 display panel DP.

[0145] Reference Fig. 7A , an embodiment of the method of manufacturing a display panel may include an operation of providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in the embodiment may include a base layer BL, a circuit element layer DP-CL, an anode AE, a sacrificial layer SP-I, a pixel defining film PDL, a first preliminary partition wall layer L1-I, and a second preliminary partition wall layer L2-I.

[0146] The circuit element layer DP-CL can be formed by a general method of manufacturing circuit elements, wherein an insulating layer, a semiconductor layer and a conductive layer are formed by a coating method or a deposition method, and the insulating layer, the semiconductor layer and the conductive layer are selectively patterned by photolithography and etching processes to form a semiconductor pattern, a conductive pattern, a signal line or the like.

[0147] The anode AE ​​and the sacrificial layer SP-I may be formed by the same patterning process. A pixel defining layer PDL may be disposed on the base layer BL. The pixel defining layer PDL may cover the anode AE ​​and the sacrificial layer SP-I.

[0148] A first preliminary partition wall layer L1-I may be provided on the pixel defining film PDL. The first preliminary partition wall layer L1-I may be formed by a process of depositing a conductive material on the pixel defining film PDL. A second preliminary partition wall layer L2-I may be provided on the first preliminary partition wall layer L1-I. The second preliminary partition wall layer L2-I may be formed by a process of depositing a conductive material on the first preliminary partition wall layer L1-I.

[0149] In an embodiment, the first preliminary partition wall layer L1-1 and the second preliminary partition wall layer L2-1 may include a conductive material. In an embodiment, for example, the conductive material may include a metal, a TCO, or a combination thereof. In an embodiment, for example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO may include ITO, IZO, zinc oxide, indium oxide, indium gallium oxide, IGZO, or aluminum zinc oxide.

[0150] In an embodiment of the present disclosure, the second preliminary partition wall layer L2-I may include an inorganic material. In an embodiment, for example, the second preliminary partition wall layer L2-I may include a material selected from silicon oxynitride (SiON) and silicon nitride (SiN x However, the materials of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are not limited thereto.

[0151] Afterwards, refer to Figure 7B , an embodiment of the method of manufacturing a display panel may further include an operation of forming a first photoresist layer PR1 on the second preliminary partition wall layer L2-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the second preliminary partition wall layer L2-I and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first optical opening OP-PR1 overlapping the anode AE ​​may be formed in the first photoresist layer PR1.

[0152] Afterwards, refer to Figure 7C, an embodiment of the method for manufacturing a display panel may further include an operation of etching a portion of the second preliminary partition wall layer L2-I corresponding to the anode AE. In the operation of etching the second preliminary partition wall layer L2-I, the second preliminary partition wall layer L2-I may be dry-etched using the first photoresist layer PR1 as a mask. Therefore, a portion of the second preliminary partition wall layer L2-I overlapping with the first optical opening OP-PR1 may be removed. That is, an opening OP overlapping with the first optical opening OP-PR1 may be formed in the second preliminary partition wall layer L2-I.

[0153] Reference Fig.7D , an embodiment of the method for manufacturing a display panel may further include removing the first photoresist layer PR1 (see Figure 7C ), after which an operation is performed to form a third preliminary partition wall layer L3-I and a fourth preliminary partition wall layer L4-I on the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I.

[0154] A third preliminary partition wall layer L3-I may be formed on the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I. A fourth preliminary partition wall layer L4-I may be formed on the third preliminary partition wall layer L3-I. The third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I may be formed by a process of depositing a conductive material. The third preliminary partition wall layer L3-I may include the same material as the first preliminary partition wall layer L1-I, and the fourth preliminary partition wall layer L4-I may include a material having an etching rate lower than that of the first preliminary partition wall layer L1-I and the third preliminary partition wall layer L3-I. However, this is illustrative, and the materials of the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I are not limited to the above examples.

[0155] Reference Fig. 7E and Figure 7F , an embodiment of the method for manufacturing a display panel may further include an operation of forming a preliminary partition wall PW-I including a tip portion and defining a preliminary partition wall opening (or a second preliminary partition wall opening) OP-PI2 by etching the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, the third preliminary partition wall layer L3-I, and the fourth preliminary partition wall layer L4-I. The operation of forming the preliminary partition wall PW-I may include an operation of forming a first preliminary partition wall opening OP-PI1 by etching the first preliminary partition wall layer L1-I, the third preliminary partition wall layer L3-I, and the fourth preliminary partition wall layer L4-I, and an operation of forming a second preliminary partition wall opening OP-PI2 by etching the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I.

[0156] First, if Fig. 7EAs shown in, an embodiment of a method for manufacturing a display panel may include an operation of forming a second photoresist layer PR2 on a fourth preliminary partition wall layer L4-I. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the fourth preliminary partition wall layer L4-I and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a second optical opening OP-PR2 overlapping the anode AE ​​may be formed in the second photoresist layer PR2.

[0157] The operation of forming the first preliminary partition wall opening OP-PI1 by etching the first preliminary partition wall layer L1-I, the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I may include an operation of dry etching (hereinafter referred to as primary dry etching) the first preliminary partition wall layer L1-I, the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I using the second photoresist layer PR2 as a mask. The first preliminary partition wall opening OP-PI1 may be formed by etching the first preliminary partition wall layer L1-I, the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I portions overlapping with the second photo opening OP-PR2.

[0158] The primary dry etching process according to the embodiment may be performed in an etching environment in which the etching selection ratios between the first preliminary partition wall layer L1-I, the third preliminary partition wall layer L3-I, and the fourth preliminary partition wall layer L4-I are substantially the same as each other. Therefore, the inner surface S-L1-I1 of the first preliminary partition wall layer L1-I, the inner surface S-L3-I1 of the third preliminary partition wall layer L3-I, and the inner surface S-L4-I1 of the fourth preliminary partition wall layer L4-I defining the first preliminary partition wall opening OP-PI1 may be substantially aligned with each other or on the same plane.

[0159] Afterwards, refer to Figure 7F, the operation of forming the second preliminary partition wall opening OP-PI2 by etching the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I and the third preliminary partition wall layer L3-I may include the operation of wet etching (hereinafter referred to as secondary wet etching) the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I and the third preliminary partition wall layer L3-I using the second photoresist layer PR2 as a mask. The second preliminary partition wall opening OP-PI2 may be formed by etching the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I and the third preliminary partition wall layer L3-I overlapping the second photo opening OP-PR2. The second preliminary partition wall opening OP-PI2 may be referred to as the preliminary partition wall opening OP-PI2. The first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I after the secondary wet etching process may form a preliminary partition wall PW-I.

[0160] The secondary wet etching process in the embodiment can be performed in an environment where the etching selectivity ratio of the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I and the third preliminary partition wall layer L3-I to the fourth preliminary partition wall layer L4-I is high. Therefore, the inner surface S-L1-I2, S-L2-I2, S-L3-I2 and S-L4-I2 of the preliminary partition wall PW-I defining the second preliminary partition wall opening OP-PI2 may have an undercut shape in cross section. In detail, since the etching rates of the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I and the third preliminary partition wall layer L3-I relative to the etching solution are greater than the etching rate of the fourth preliminary partition wall layer L4-I, the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I and the third preliminary partition wall layer L3-I may be mainly etched. Therefore, compared with the inner surface S-L4-I2 of the fourth preliminary partition wall layer L4-I, the inner surface S-L1-I2 of the first preliminary partition wall layer L1-I, the inner surface S-L2-I2 of the second preliminary partition wall layer L2-I, and the inner surface S-L3-I2 of the third preliminary partition wall layer L3-I may be further recessed inward (or toward the center of the corresponding second preliminary partition wall opening OP-PI2). A tip portion may be formed in the preliminary partition wall PW-I by a portion of the fourth preliminary partition wall layer L4-I that further protrudes from the first preliminary partition wall layer L1-I, the second preliminary partition wall layer L2-I, and the third preliminary partition wall layer L3-I. The etched fourth preliminary partition wall layer L4-I may include a tip portion.

[0161] The second preliminary partition wall opening OP-PI2 may include a first region A1 and a second region A2 sequentially formed in the thickness direction (i.e., the third direction DR3). The first region A1 may be defined by the inner surface S-L1-I2 of the first preliminary partition wall layer L1-I, the inner surface S-L2-I2 of the second preliminary partition wall layer L2-I, and the inner surface S-L3-I2 of the third preliminary partition wall layer L3-I, and the second region A2 may be defined by the inner surface S-L4-I2 of the fourth preliminary partition wall layer L4-I. The width of the second region A2 in one direction may be smaller than the width of the first region A1 in the one direction.

[0162] In an embodiment, Fig. 7E and Figure 7F The operation of forming the second preliminary partition wall opening OP-PI2 may include simultaneously forming the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B (see Figure 6 ) of the first partition wall opening OP1-P, the second partition wall opening OP2-P and the third partition wall opening OP3-P (see Figure 6 However, the present disclosure is not limited to the above example, and in an embodiment, an operation of forming only the first partition wall opening OP1-P corresponding to the first light emitting region PXA-R may be included. In an embodiment, for example, the first partition wall opening OP1-P corresponding to the first light emitting region PXA-R may be formed, and the first light emitting element ED1 may be formed by a subsequent process (see Figure 6 ), and then the second partition wall opening OP2-P corresponding to the second light emitting region PXA-G may be formed. In this embodiment, the second light emitting element ED2 (see Figure 6 ), and a third partition wall opening OP3-P corresponding to the third light emitting region PXA-B may be formed.

[0163] Afterwards, refer to Figure 7G , an embodiment of the method of manufacturing a display panel may further include an operation of etching a pixel definition film PDL and an operation of etching a sacrificial layer SP-I (see Figure 7F ). The process of etching the pixel defining film PDL may be performed by a dry etching method using the second photoresist layer PR2 and the fourth preliminary partition wall layer L4-I as a mask. A light emitting opening OP-E corresponding to the second preliminary partition wall opening OP-PI2 may be formed in the pixel defining film PDL.

[0164] The process of etching the sacrificial layer SP-I may be performed by a wet etching method using the second photoresist layer PR2 and the fourth preliminary partition wall layer L4-I as a mask. A sacrificial opening OP-S overlapping the light emitting opening OP-E may be formed in the sacrificial pattern SP formed by etching the sacrificial layer SP-I. At least a portion of the anode AE ​​may be exposed from the sacrificial pattern SP and the pixel defining film PDL through the sacrificial opening OP-S and the light emitting opening OP-E.

[0165] The process of etching the sacrificial layer SP-I may be performed in an environment in which the etching selectivity ratio between the sacrificial layer SP-I and the anode AE ​​is high, and thus the anode AE ​​may be effectively prevented from being etched together. That is, the sacrificial layer SP-I having an etching rate greater than that of the anode AE ​​is disposed between the pixel defining film PDL and the anode AE, and thus the anode AE ​​may be effectively prevented from being etched together and damaged during the etching process.

[0166] Reference Figure 7H , an embodiment of the method for manufacturing a display panel may further include removing the second photoresist layer PR2 (see Figure 7F ) and then forming a light emitting pattern EP and a cathode CE on the anode AE. The operation of forming the light emitting pattern EP and the cathode CE on the anode AE ​​may include forming a first dummy pattern D1 including a material identical to that of the light emitting pattern EP and a second dummy pattern D2 including a material identical to that of the cathode CE on the preliminary partition wall PW-I.

[0167] First, refer to Figure 7H , the operation of forming the light emitting pattern EP and the cathode CE may be performed by a deposition process. In an implementation, the operation of forming the light emitting pattern EP may include a thermal evaporation process, and the operation of forming the cathode CE may include a sputtering process.

[0168] The light emitting pattern EP may be formed on the anode AE. In the operation of forming the light emitting pattern EP, the light emitting patterns EP may be separated from each other by the tip portions formed in the preliminary partition wall PW-I, and may be disposed inside the light emitting opening OP-E and the sacrificial opening OP-S. However, this is illustrative, and the light emitting pattern EP may be disposed on the light emitting opening OP-E, the sacrificial opening OP-S, or the preliminary partition wall opening OP-PI2.

[0169] In the operation of forming the light emitting pattern EP, a first dummy pattern D1 spaced apart from the light emitting pattern EP may be formed together on the preliminary partition wall PW-I. The first dummy pattern D1 may include an organic material. In an embodiment, for example, the first dummy pattern D1 may include the same material as that of the light emitting pattern EP. The first dummy pattern D1 may be formed synchronously with the light emitting pattern EP through the same process, and may be formed separately from the light emitting pattern EP by the undercut shape of the preliminary partition wall PW-I.

[0170] The cathode CE may be formed on the light emitting pattern EP. In the operation of forming the cathode CE, the cathode CE may be separated from each other by a tip portion formed in the preliminary partition wall PW-I, and may be disposed inside the light emitting opening OP-E and the preliminary partition wall opening OP-PI2. However, this is illustrative, and the cathode CE may be disposed inside the preliminary partition wall opening OP-PI2. The cathode CE may be provided at an input angle higher than that of the light emitting pattern EP, and the cathode CE may be formed to contact the inner surface S-L1-I2 of the first preliminary partition wall layer L1-I. The anode AE, the light emitting pattern EP, and the cathode CE may constitute a light emitting element ED.

[0171] In the operation of forming the cathode CE, a second dummy pattern D2 spaced apart from the cathode CE may be formed together on the preliminary partition wall PW-I. The second dummy pattern D2 may include a conductive material. In an embodiment, for example, the second dummy pattern D2 may include the same material as that of the cathode CE. The second dummy pattern D2 may be formed synchronously with the cathode CE through the same process, and may be formed separately from the cathode CE by the undercut shape of the preliminary partition wall PW-I.

[0172] The first dummy pattern D1 and the second dummy pattern D2 may be sequentially stacked in the third direction DR3 on the upper surface of the preliminary partition wall PW-1. The first dummy pattern D1 and the second dummy pattern D2 may form a dummy pattern DMP.

[0173] In an embodiment of the present disclosure, the method for manufacturing a display panel may further include an operation of forming a covering pattern CP. The operation of forming the covering pattern CP may include a thermal evaporation process. The covering pattern CP may be formed on the cathode CE. In the operation of forming the covering pattern CP, the covering patterns CP may be separated from each other by a tip portion formed in the preliminary partition wall PW-I and disposed inside the preliminary partition wall opening OP-PI2 or the light emitting opening OP-E.

[0174] In the operation of forming the covering pattern CP, a third dummy pattern D3 spaced apart from the covering pattern CP may be formed together on the preliminary partition wall PW-I. The third dummy pattern D3 may include a conductive material. In an embodiment, for example, the third dummy pattern D3 may include the same material as that of the covering pattern CP. The third dummy pattern D3 may be formed synchronously with the covering pattern CP through the same process, and may be formed separately from the covering pattern CP by the undercut shape of the preliminary partition wall PW-I. In this case, the dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3.

[0175] Reference FIG. 7H to FIG. 7I , an embodiment of the method of manufacturing a display panel may further include an operation of forming a preliminary lower encapsulation inorganic pattern LIL-I on the cathode CE. The operation of forming the preliminary lower encapsulation inorganic pattern LIL-I on the cathode CE may include an operation of forming a lower encapsulation inorganic layer LILL covering the cathode CE and the preliminary partition wall PW-I and an operation of etching a portion of the lower encapsulation inorganic layer LILL that does not overlap with the anode AE. Hereinafter, reference will be made to Figure 7H The operation of forming the lower encapsulation inorganic layer LILL will be described, and reference will be made to Fig.7I The operation of etching a portion of the lower encapsulation inorganic layer LILL that does not overlap with the anode AE ​​will be described.

[0176] First, refer to Figure 7H The operation of forming the lower encapsulation inorganic layer LILL covering the cathode CE and the preliminary partition wall PW-I may include a deposition process. In an embodiment, the lower encapsulation inorganic layer LILL may be formed by a chemical vapor deposition (CVD) process. The lower encapsulation inorganic layer LILL may be formed to cover the cathode CE and the preliminary partition wall PW-I.

[0177] Afterwards, refer to Fig.7I , an embodiment of the method of manufacturing a display panel may further include an operation of forming a third photoresist layer PR3. In the operation of forming the third photoresist layer PR3, the third photoresist layer PR3 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the third photoresist layer PR3 may be formed into a pattern shape corresponding to the light emitting opening OP-E.

[0178] In the operation of etching the portion of the lower encapsulation inorganic layer LILL that does not overlap with the anode AE, the lower encapsulation inorganic layer LILL may be dry-etched using the third photoresist layer PR3 as a mask. The lower encapsulation inorganic layer LILL may be patterned in such a manner that the portion of the lower encapsulation inorganic layer LILL that does not overlap with the anode AE ​​is removed. The preliminary lower encapsulation inorganic pattern LIL-I that overlaps with the anode AE ​​may be formed by the patterned lower encapsulation inorganic layer LILL.

[0179] Afterwards, refer to Figure 7J , an embodiment of the method of manufacturing a display panel may further include removing the dummy pattern DMP (see Fig.7I The operation of removing the dummy pattern DMP may include wet etching the first dummy pattern D1 formed on the preliminary partition wall PW-I (see Fig.7I ), the second dummy pattern D2 (see Fig.7I ) and the third dummy pattern D3 (see FIG. 71 ). The area where the dummy pattern DMP is removed may be defined as a dummy area DMA. That is, the dummy area DMA may be formed between the preliminary partition wall PW-1 and the preliminary lower encapsulation inorganic pattern LIL-1 in cross section.

[0180] After forming the preliminary lower encapsulation inorganic pattern LIL-I, operations of forming preliminary partition wall openings OP-PI2 or light emitting openings OP-E corresponding to light emitting areas emitting light having different colors in the preliminary partition wall PW-I and the pixel definition film PDL, operations of forming light emitting elements ED providing light having different colors, and operations of forming the preliminary lower encapsulation inorganic pattern LIL-I covering the light emitting elements ED providing light having different colors may be further performed. In an embodiment, for example, in forming the first anode AE1 (see Figure 6 ) after the preliminary lower package inorganic pattern LIL-I corresponding to the second anode AE2 (see Figure 6 ) corresponding to the preliminary partition wall opening OP-PI2, the second light-emitting opening OP2-E (see Figure 6 ), the second light emitting element ED2 (see Figure 6 ) and a preliminary lower encapsulation inorganic pattern LIL-I. In addition, after forming the preliminary lower encapsulation inorganic pattern LIL-I corresponding to the second anode AE2, a third anode AE3 (see Figure 6 ) corresponding to the preliminary partition wall opening OP-PI2, the third light-emitting opening OP3-E (see Figure 6 ), the third light emitting element ED3 (see Figure 6 ) and preliminary lower package inorganic pattern LIL-I. Therefore, it is possible to form Figure 6 The first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3 corresponding to the multiple light-emitting areas PXA-R, PXA-G and PXA-B shown in the figure, and the preliminary lower encapsulation inorganic pattern LIL-I corresponding to the first light-emitting element ED1, the second light-emitting element ED2 and the third light-emitting element ED3.

[0181] Afterwards, refer to Figure 7K , an embodiment of the method of manufacturing a display panel may further include etching a preliminary lower encapsulation inorganic pattern LIL-I (see Figure 7J), the third preliminary partition wall layer L3-I (see Figure 7J ) and the fourth preliminary partition wall layer L4-I (see Figure 7J ) is used to form the partition wall PW and the lower package inorganic pattern LIL.

[0182] The operation of forming the partition wall PW and the lower encapsulation inorganic pattern LIL by etching the preliminary lower encapsulation inorganic pattern LIL-I, the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I may include the operation of etching the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I, and the operation of forming the first partition wall layer L1 through the first preliminary partition wall layer L1-I and forming the second partition wall layer L2 through the second preliminary partition wall layer L2-I.

[0183] The operation of etching the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I may be performed by a dry etching process and a wet etching process. The third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I subjected to the etching process may be removed. The remaining first preliminary partition wall layer L1-I may form a first partition wall layer L1, and the second preliminary partition wall layer L2-I may form a second partition wall layer L2. The first partition wall layer L1 and the second partition wall layer L2 may form a partition wall PW. Since the fourth preliminary partition wall layer L4-I including the tip portion is removed, the partition wall PW may not be undercut and may not include the tip portion.

[0184] In addition, the operation of forming a partition wall PW and a lower encapsulation inorganic pattern LIL by etching a preliminary lower encapsulation inorganic pattern LIL-I, a third preliminary partition wall layer L3-I, and a fourth preliminary partition wall layer L4-I may include an operation of etching the preliminary lower encapsulation inorganic pattern LIL-I overlapping with the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I, and an operation of forming a lower encapsulation inorganic pattern LIL whose end is in contact with the second inner surface S-L2 of the second partition wall layer L2.

[0185] The operation of etching the preliminary lower encapsulation inorganic pattern LIL-I overlapping the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I may be performed by the same process as the above-mentioned operation of simultaneously etching the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I. In an embodiment, for example, the operation of etching the preliminary lower encapsulation inorganic pattern LIL-I may be performed by a dry etching process and a wet etching process. The portion of the preliminary lower encapsulation inorganic pattern LIL-I subjected to the etching process may be removed. The portion of the preliminary lower encapsulation inorganic pattern LIL-I formed on the preliminary partition wall PW-I and the portion of the preliminary lower encapsulation inorganic pattern LIL-I overlapping the inner surface of the third preliminary partition wall layer L3-I and the fourth preliminary partition wall layer L4-I may be removed. The remaining preliminary lower encapsulation inorganic pattern LIL-I may form a lower encapsulation inorganic pattern LIL, and the end of the lower encapsulation inorganic pattern LIL may contact the inner surface S-L2 of the second partition wall layer L2.

[0186] Afterwards, refer to Figure 7L , an embodiment of the method for manufacturing a display panel may further include completing the operation of the display panel DP by forming an encapsulation organic film OL and an upper encapsulation inorganic film UIL. The encapsulation organic film OL may be formed by applying an organic material by an inkjet method, but the present disclosure is not limited thereto. The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The encapsulation organic film OL may cover the upper surface U-L2 of the second partition wall layer L2 and the upper surface U-LIL of the lower encapsulation inorganic pattern LIL. Thereafter, the upper encapsulation inorganic film UIL may be formed by depositing an inorganic material. Therefore, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0187] According to an embodiment of the present disclosure, as described above, the lower encapsulation inorganic pattern is in direct contact and connection with the second partition wall layer including an inorganic material, and thus the connection force of the lower encapsulation inorganic pattern can be improved. In this embodiment, the lower encapsulation inorganic pattern may not be disposed on the partition wall. Therefore, the sealing ability of the lower encapsulation inorganic pattern for protecting the display element layer can be improved, and pixel defects (black spots, pixel shrinkage, and the like) caused by foreign matter introduced from the side surface of the lower encapsulation inorganic pattern formed on the partition wall can be reduced or eliminated. In this embodiment, in the process of etching the lower encapsulation inorganic pattern, the wet etching area is increased, and thus the mass production rate of the display panel can be improved.

[0188] The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0189] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display panel, comprising: Base layer; A pixel defining film, the pixel defining film being disposed on the base layer, wherein a light emitting opening is defined in the pixel defining film; a partition wall including a first partition wall layer disposed on the pixel definition film and a second partition wall layer disposed on the first partition wall layer, wherein a partition wall opening is defined in the partition wall to overlap the light emitting opening; and a light emitting element, the light emitting element comprising an anode, an intermediate layer, and a cathode in contact with the partition wall, wherein at least a portion of the light emitting element is disposed inside the partition wall opening, The first inner surface of the first partition wall layer and the second inner surface of the second partition wall layer are aligned with each other.

2. The display panel according to claim 1, wherein: The second partition wall layer includes an inorganic material.

3. The display panel according to claim 1, wherein: The second partition wall layer includes a material selected from SiON and SiN x At least one of .

4. The display panel according to claim 1, further comprising: a plurality of light emitting regions from which light provided from the light emitting element is emitted, The cathode is disconnected by the partition wall to correspond to the plurality of light emitting regions.

5. The display panel according to claim 1, further comprising: a lower package inorganic pattern, wherein the lower package inorganic pattern covers the light emitting element, Wherein, the lower package inorganic pattern is arranged inside the partition wall opening.

6. The display panel according to claim 5, wherein: A side surface of the lower encapsulation inorganic pattern contacts the second inner surface of the second partition wall layer.

7. The display panel according to claim 5, further comprising: an encapsulation organic film, wherein the encapsulation organic film is disposed on the lower encapsulation inorganic pattern, The encapsulation organic film covers an upper surface of the second partition wall layer and an upper surface of the lower encapsulation inorganic pattern.

8. The display panel according to claim 1, wherein: The cathode extends along the first inner surface of the first partition wall layer, and An end portion of the cathode contacts the first partition wall layer.

9. The display panel according to claim 1, wherein: A width of the partition wall opening is constant along the first partition wall layer and the second partition wall layer.

10. A method for manufacturing a display panel, the method comprising: providing a preliminary display panel in which a base layer, an anode, a pixel defining film, a first preliminary partition wall layer, and a second preliminary partition wall layer are sequentially laminated; forming a third preliminary partition wall layer and a fourth preliminary partition wall layer on the first preliminary partition wall layer and the second preliminary partition wall layer; forming a preliminary partition wall including a tip portion and defining a preliminary partition wall opening by etching the first preliminary partition wall layer to the fourth preliminary partition wall layer; forming a light emitting pattern and a cathode on the anode; forming a preliminary lower encapsulation inorganic pattern on the cathode; as well as A partition wall and a lower encapsulation inorganic pattern are formed by etching the preliminary lower encapsulation inorganic pattern, the third preliminary partition wall layer, and the fourth preliminary partition wall layer.

11. The method for manufacturing a display panel according to claim 10, further comprising: A portion of the second preliminary partition wall layer corresponding to the anode is etched.

12. The method for manufacturing a display panel according to claim 10, wherein: Forming the preliminary partition wall including the tip portion by etching the first preliminary partition wall layer to the fourth preliminary partition wall layer and defining the preliminary partition wall opening includes: forming a first preliminary partition wall opening by etching the first preliminary partition wall layer, the third preliminary partition wall layer, and the fourth preliminary partition wall layer; and A second preliminary partition wall opening is formed by etching the first preliminary partition wall layer to the third preliminary partition wall layer.

13. The method for manufacturing a display panel according to claim 12, wherein: The second preliminary partition wall opening comprises: a first region defined by an inner surface of the first preliminary partition wall layer, an inner surface of the second preliminary partition wall layer, and an inner surface of the third preliminary partition wall layer; and a second region defined by an inner surface of the fourth preliminary partition wall layer, and The width of the second region is smaller than the width of the first region.

14. The method for manufacturing a display panel according to claim 10, wherein: The etched fourth preliminary partition wall layer defines the tip portion.

15. The method for manufacturing a display panel according to claim 10, wherein: Forming the light emitting pattern and the cathode on the anode includes: A first dummy pattern and a second dummy pattern are formed on the preliminary partition wall, the first dummy pattern including the same material as that of the light emitting pattern, and the second dummy pattern including the same material as that of the cathode.

16. The method for manufacturing a display panel according to claim 15, wherein: Forming the preliminary lower encapsulation inorganic pattern on the cathode comprises: forming a lower encapsulation inorganic layer to cover the cathode and the preliminary partition wall; and A portion of the lower encapsulation inorganic layer not overlapping the anode is etched.

17. The method for manufacturing a display panel according to claim 15, further comprising: The first dummy pattern and the second dummy pattern are etched.

18. The method for manufacturing a display panel according to claim 10, wherein: Forming the partition wall and the lower encapsulation inorganic pattern by etching the preliminary lower encapsulation inorganic pattern, the third preliminary partition wall layer, and the fourth preliminary partition wall layer includes: etching the third preliminary partition wall layer and the fourth preliminary partition wall layer, The first partition wall layer included in the partition wall is formed by the first preliminary partition wall layer, and the second partition wall layer included in the partition wall is formed by the second preliminary partition wall layer.

19. The method for manufacturing a display panel according to claim 18, wherein: Forming the partition wall and the lower encapsulation inorganic pattern by etching the preliminary lower encapsulation inorganic pattern, the third preliminary partition wall layer, and the fourth preliminary partition wall layer further comprises: etching the preliminary lower encapsulation inorganic pattern overlapping the third preliminary partition wall layer and the fourth preliminary partition wall layer, Wherein, a side surface of the lower encapsulation inorganic pattern contacts an inner surface of the second partition wall layer.

20. A display panel, comprising: Base layer; A pixel defining film, the pixel defining film being disposed on the base layer, wherein a light emitting opening is defined in the pixel defining film; a partition wall, the partition wall comprising a first partition wall layer disposed on the pixel definition film and a second partition wall layer disposed on the first partition wall layer, wherein a partition wall opening is defined in the partition wall to overlap with the light emitting opening; a light emitting element, the light emitting element comprising an anode, an intermediate layer, and a cathode in contact with the partition wall, wherein at least a portion of the light emitting element is disposed inside the partition wall opening; and a lower encapsulation inorganic pattern, the lower encapsulation inorganic pattern covering the light emitting element and disposed in the partition wall opening, The lower encapsulation inorganic pattern does not overlap with the partition wall in a thickness direction of the base layer.

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