Self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization and preparation method thereof

Abstract

The application discloses a self-rectifying ferroelectric memristor based on ferroelectric out-of-plane polarization and a preparation method thereof. The memristor is vertically structured from top to bottom as an upper electrode layer, a ferroelectric layer and a semiconductor layer. The ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization. The out-of-plane polarization direction of the ferroelectric layer is perpendicular to the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface at the same time. Two contact surfaces form an asymmetric potential barrier. The out-of-plane polarization state of the ferroelectric layer is changed by an external voltage, thereby changing the potential barrier height of the two contact surfaces and the carrier transport characteristics of the semiconductor layer, and further achieving the regulation function of the conductive state of the memristor. The on-current of the memristor is measured by a peripheral circuit as a storage value. The application realizes the switching of high resistance and low resistance and the rectification characteristic by using the change of the contact potential barrier of the ferroelectric layer and the silicon interface in the polarization reversal process. The memristor has simple structure, is easy to integrate and has low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of ferroelectric memory technology, specifically relating to a self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization and its preparation method. Background Technology

[0002] With the rapid development of new technologies such as artificial intelligence and big data, the market demands increasingly higher performance from storage hardware. However, the huge demand for high-throughput data processing in current data-driven new technologies and scenarios highlights the shortcomings of silicon-based storage. Memristors, considered the fourth basic element in circuitry, store information by adjusting their resistance state. They possess non-linear resistive characteristics and can retain information even when power is off. Therefore, memristors can meet the needs of next-generation high-density information storage and high-performance computing, while also enabling non-volatile state logic operations and neuromorphic computing functions, integrating information storage and computation into a single device. Ferroelectric memristors utilize reversible ferroelectric domains in a ferroelectric thin film layer for storage. By applying an external electric field, the polarization of the ferroelectric domains can be reversed, thereby changing the state of the storage medium layer. Ferroelectric memories offer advantages such as high speed, low power consumption, and high storage density, which have led to widespread attention and rapid development in recent years. One of the main obstacles in the development of memristor storage arrays is the so-called latent current, which causes crosstalk interference between adjacent storage cells and increases overall circuit power consumption, severely affecting the operation of memristor cross-arrays. The unique nonlinearity and self-rectification characteristics of self-rectifying devices make them an effective solution because they do not require additional hardware overhead. Summary of the Invention

[0003] To address the leakage current phenomenon that occurs in memristors in large-scale arrays, this invention provides a self-rectified ferroelectric memristor with high rectification ratio and high nonlinearity, and its fabrication method.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides a self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization, wherein the self-rectified ferroelectric memristor has a vertical structure from top to bottom consisting of an upper electrode layer, a ferroelectric layer, and a semiconductor layer; a lower electrode layer is led out from the semiconductor layer; the ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization; and the contact barrier between the ferroelectric layer and the semiconductor layer needs to be greater than the contact barrier between the ferroelectric layer and the upper electrode layer.

[0006] Furthermore, the out-of-plane polarization direction of the ferroelectric layer is perpendicular to both the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface. The two contact surfaces form an asymmetric potential barrier. By applying an external voltage, the out-of-plane polarization state of the ferroelectric layer will be changed, thereby changing the potential barrier height of the two contact surfaces and changing the carrier transport characteristics of the semiconductor layer, thus achieving the function of regulating the conductance state of the memristor.

[0007] Furthermore, the self-rectified ferroelectric memristor also includes an insulating layer for device isolation and / or substrate.

[0008] Furthermore, the electrode structure of the self-rectified ferroelectric memristor is a sandwich structure, consisting of an upper electrode-ferroelectric layer and a semiconductor layer-lower electrode; the electrode material is any one of gold, platinum, titanium, silver, copper, aluminum, indium tin oxide, heavily doped semiconductor or gallium indium alloy.

[0009] Furthermore, the material of the ferroelectric layer is two-dimensional CuInP2S6 or α-In2Se3.

[0010] Furthermore, the semiconductor layer is a doped material mainly composed of boron, germanium, silicon, gray tin, antimony, selenium, or tellurium crystals.

[0011] Secondly, the present invention provides a method for fabricating a single device of a self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization, including fabricating an interface structure between a ferroelectric layer and a semiconductor layer, and fabricating electrodes that are in contact with the ferroelectric layer and the semiconductor layer respectively; the specific steps are as follows:

[0012] S1, an insulating layer is formed on the semiconductor layer, and the insulating layer is patterned and removed to prepare a contact window between the semiconductor layer and the ferroelectric layer;

[0013] S2, ferroelectric material is transferred onto the contact window using a wet or dry method to form a ferroelectric layer;

[0014] S3, an upper electrode layer is prepared on the ferroelectric layer using patterning and deposition processes;

[0015] S4, the lower electrode layer is prepared by patterning and deposition processes or by coating gallium indium alloy on the semiconductor layer.

[0016] Furthermore, the semiconductor layer is silicon, the insulating layer is silicon oxide, the ferroelectric layer is copper indium phosphorus sulfide, and the upper electrode layer is gold.

[0017] Thirdly, the present invention provides a method for arraying self-rectified ferroelectric memristors based on ferroelectric out-of-plane polarization, comprising the following steps:

[0018] S1, Discrete semiconductor layers are fabricated on a semiconductor / insulator using patterning and deep silicon etching techniques;

[0019] S2, an inert insulating layer is formed by filling the space between discrete semiconductor layers with insulating material using patterning and deposition processes;

[0020] S3, transfer ferroelectric layer material onto the surface of an insulating layer / semiconductor or prepare a ferroelectric layer using a deposition method;

[0021] S4, an upper electrode layer is prepared on the ferroelectric layer using patterning and deposition processes;

[0022] S5, the lower electrode layer is led out in the non-overlapping region of the semiconductor layer to form a device array.

[0023] Furthermore, in S1, the semiconductor is silicon, the insulator is silicon oxide, and the semiconductor / insulator is implemented using an SOI silicon wafer; the inert insulating layer is aluminum oxide, the ferroelectric layer is copper indium phosphorus sulfide, and the upper electrode layer is gold.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] The self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization provided by this invention has a high rectification ratio, meaning it can effectively prevent reverse current, thereby reducing energy consumption and improving computational accuracy. Secondly, its high nonlinearity ensures significant differences in conductance across different voltage ranges, facilitating low-power storage and computation. Furthermore, the vector-matrix multiplication achieved using its high nonlinearity feature features high quantization bits, which is crucial for the multi-bit precision requirements of vector-matrix multiplication and can significantly improve the computational accuracy and model performance of neural networks. Therefore, this device has unique advantages in hardware implementation of deep learning and AI computing tasks, making it an important candidate for building efficient, low-power computing accelerators. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is the implementation scheme of the self-rectified ferroelectric memristor provided in Embodiment 1 of the present invention;

[0028] Figure 2 This is the implementation scheme of the self-rectified ferroelectric memristor provided in Embodiment 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of a 9*9 array structure of a self-rectified ferroelectric memristor provided in Embodiment 2 of the present invention;

[0030] Figure 4 Cyclic volt-ampere curve of a self-rectified ferroelectric memristor based on gold / copper indium phosphorus sulfide / silicon is provided for an embodiment of the present invention;

[0031] Figure 5 A current holding characteristic curve of a self-rectified ferroelectric memristor based on gold / copper indium phosphorus sulfide / silicon / gallium indium alloy / copper is provided for an embodiment of the present invention.

[0032] Figure 6 A schematic diagram of a memristor array with matrix multiplication acceleration function is provided for an embodiment of the present invention;

[0033] In the diagram: 1. Semiconductor layer; 2. Insulating layer; 3. Inert insulating layer; 4. Ferroelectric layer; 5. Top electrode layer. Detailed Implementation

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0036] This invention provides a self-rectified ferroelectric memristor based on out-of-plane ferroelectric polarization. The self-rectified ferroelectric memristor has a vertical structure consisting of an upper electrode layer, a ferroelectric layer, and a semiconductor layer from top to bottom. A lower electrode layer is led out from the semiconductor layer. The ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization. The contact barrier between the ferroelectric layer and the semiconductor layer needs to be greater than the contact barrier between the ferroelectric layer and the upper electrode layer.

[0037] The out-of-plane polarization direction of the ferroelectric layer is perpendicular to both the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface. These interfaces form an asymmetric potential barrier. Applying an external voltage alters the out-of-plane polarization state of the ferroelectric layer, thereby changing the barrier height at the two contact surfaces and simultaneously altering the carrier transport characteristics of the semiconductor layer. This allows for the control of the memristor's conductance state. The self-rectified ferroelectric memristor provided by this invention features a high rectification ratio, high nonlinearity, and low power consumption. It also exhibits large-scale scalability and can be used in the hardware implementation of memory cells and in-memory computing acceleration units in memory arrays.

[0038] Furthermore, the ferroelectric layer is made of ferroelectric semiconductors such as two-dimensional CuInP2S6 and α-In2Se3, which have out-of-plane ferroelectric polarization.

[0039] Furthermore, the semiconductor layer is a doped material mainly composed of boron, germanium, silicon, gray tin, antimony, selenium, or tellurium crystals.

[0040] Furthermore, the electrode structure of the self-rectified ferroelectric memristor is a sandwich structure, consisting of an upper electrode-ferroelectric layer and a semiconductor layer-lower electrode; the electrode material is any one of gold, platinum, titanium, silver, copper, aluminum, indium tin oxide, heavily doped semiconductor or gallium indium alloy.

[0041] Furthermore, the self-rectified ferroelectric memristor also includes an insulating layer for device isolation and / or substrate.

[0042] Furthermore, the insulating layer is made of any one of silicon dioxide, aluminum oxide, zirconium oxide, hafnium silicon oxide, titanium oxide, silicon nitride, or aluminum nitride.

[0043] Example 1

[0044] The structure of the self-rectified ferroelectric memristor in this embodiment is as follows: Figure 1 As shown. Semiconductor layer 1 is silicon, insulating layer 2 is silicon oxide, ferroelectric layer 4 is copper indium phosphorus sulfide (CIPS), and top electrode layer 5 is gold.

[0045] The fabrication of a single self-rectified ferroelectric memristor includes fabricating the interface structure between the ferroelectric layer and the semiconductor layer, and fabricating electrodes that contact the ferroelectric layer and the semiconductor layer respectively; the specific steps are as follows:

[0046] (1) An insulating layer 2 with a thickness of 100 nm is formed on the semiconductor layer 1. A window pattern is made on the insulating layer 2 using ultraviolet lithography. The insulating layer 2 is etched clean using BOE solution to expose the silicon in the window pattern.

[0047] (2) Use PDMS to transfer CIPS to the edge region of the window graphic to form ferroelectric layer 4;

[0048] (3) The upper electrode pattern is fabricated using photolithography. Electron beam evaporation or thermal evaporation is used to first grow a chromium adhesion layer with a thickness of about 5~10nm, and then grow a gold layer with a thickness of about 40~80nm as the upper electrode layer 5.

[0049] (4) After cleaning the bottom of semiconductor layer 1 with BOE solution, the lower electrode layer is fabricated to complete the fabrication of a single self-rectified ferroelectric memristor in this embodiment.

[0050] Furthermore, in step (1), semiconductor layer 1 is an n-type lightly doped silicon, preferably with a resistivity of 2~4 Ω·cm.

[0051] Furthermore, the window sizes formed by the photolithography in step (1) are 3um, 5um, and 10um, which correspond to the lateral dimensions of the subsequent devices.

[0052] Furthermore, the thickness of the copper indium phosphorus sulfur transferred in step (2) is between 10 nm and 100 nm.

[0053] Furthermore, the lower electrode layer in step (4) is fabricated by sputtering, atomic layer deposition, or evaporation; the thickness of the lower electrode layer is tens to hundreds of nanometers. Alternatively, a gallium-indium alloy can be uniformly coated at the bottom of semiconductor layer 1 as the lower electrode layer.

[0054] Example 2

[0055] The structure of the self-rectified ferroelectric memristor in this embodiment is as follows: Figure 2 As shown. Semiconductor layer 1 is silicon, insulating layer 2 is silicon oxide, and semiconductor layer 1 and insulating layer 2 are implemented using SOI silicon wafer. Inert insulating layer 3 is aluminum oxide, ferroelectric layer 4 is copper indium phosphorus sulfide (CIPS), and top electrode layer 5 is gold.

[0056] The fabrication process for the array of the self-rectified ferroelectric memristor is as follows:

[0057] (1) An array pattern of semiconductor layers is fabricated on an SOI silicon wafer using ultraviolet lithography and etched using deep silicon etching. In this embodiment, the array pattern of semiconductor layers is the bit line pattern in a crossbar structure.

[0058] (2) Alumina is deposited between the array patterns using atomic layer deposition technology, and excess alumina on the silicon material surface is completely etched away using alumina etching solution to form an inert insulating layer 3.

[0059] (3) CIPS was grown on the silicon surface as a ferroelectric layer 4 using a vacuum chemical vapor transport system;

[0060] (4) Use photolithography to create an array pattern of the upper electrode layer; in this embodiment, the array pattern of the upper electrode layer is the word line pattern in the crossbar structure; using electron beam evaporation or thermal evaporation technology, first grow a chromium adhesion layer with a thickness of about 5~10nm, and then grow a gold layer with a thickness of about 40~80nm as the upper electrode layer 5.

[0061] (5) The lower electrode layer is led out in the non-overlapping region of semiconductor layer 1 to complete the fabrication of the device array in this embodiment. Figure 3 This is a schematic diagram of a 9x9 array structure of a self-rectified ferroelectric memristor.

[0062] Furthermore, in step (1), the etching depth of the deep silicon etching needs to reach the insulating layer 2 to achieve electrical isolation between subsequent devices.

[0063] In this invention, the electrode patterning process includes masking, photolithography, laser direct writing, electron beam exposure, and nanoimprinting; the electrode deposition process employs vacuum resistance thermal evaporation deposition, electron beam deposition, or magnetron sputtering; the ferroelectric material fabrication process employs physical vapor deposition, chemical vapor deposition, epitaxial growth, solution method, or sol-gel method; the ferroelectric material transfer process employs wet transfer or dry transfer; and the semiconductor fabrication process employs physical vapor deposition, chemical vapor deposition, or epitaxial growth.

[0064] The specific method for using the self-rectified ferroelectric memristor proposed in this invention is as follows:

[0065] A read / write voltage is applied to the upper electrode, and the lower electrode is grounded.

[0066] In a specific embodiment of the present invention, such as Figure 4 This is a cyclic volt-ampere curve of a self-rectified ferroelectric memristor based on gold / copper indium phosphorus sulfide / silicon. The horizontal axis represents voltage, and the vertical axis represents current. The voltage scan ranges from 0V to 4V. Before reaching 4V, at approximately 2.7V, the self-rectified ferroelectric memristor achieves a stable low-resistance state through a SET process. During the voltage scan from 0V to -3V, it returns to a high-resistance state through a RESET process and maintains a stable resistance value. Furthermore, comparing the current at 2V, 1V, and -2V reveals that the memristor exhibits approximately 10... 2 nonlinearity and 10 3 The rectification ratio is high. The SET voltage of this invention is stable within 2V, and the RESET voltage is stable within -3V. The self-rectified ferroelectric memristor of this invention has high stability and a high degree of overlap of each IV curve.

[0067] like Figure 5 This is a current-holding characteristic curve of a self-rectified ferroelectric memristor based on a gold / copper-indium-phosphorus-sulfur / silicon / gallium-indium alloy / copper structure, where the horizontal axis represents time and the vertical axis represents current. The switching ratio between the high-resistance and low-resistance states is 10. 3 And the duration is relatively long. When the ferroelectric memristor is under the action of the read voltage, the low-resistivity current of the ferroelectric memristor (approximately 10) -10 A) Can be maintained for over 1000 seconds with high resistive current (approximately 10). -13 A) It can also last for more than 1000 seconds, and the duration can be further extended. This demonstrates that the self-rectified ferroelectric memristor of the present invention has good switching and holding characteristics.

[0068] This invention also provides a memristor array with matrix multiplication acceleration function. The memristor implements matrix-vector multiplication using Kirchhoff's laws. Where N is the number of rows, such as Figure 6 As shown, each node of the interconnect has a memristor, V iFor the voltage applied in the i-th row, G ij Let I be the memristor conductance value in the i-th row and j-th column. j This is the product of the conductance matrix and the voltage vector. This value is converted into a voltage by a transimpedance amplifier, which is then the result of one calculation. Specifically, matrix-vector multiplication using a self-rectified memristor requires preprocessing of the input. V i A quantization process is required to obtain x[i-1]. Then, a voltage input is applied based on the data of each bit: half the read voltage is input for 0, and the full read voltage is input for 1. This calculation method fully utilizes the high nonlinearity of the memristor, enabling high-precision matrix-vector multiplication.

[0069] The above description is merely a preferred embodiment of one or more embodiments of this specification and is not intended to limit the scope of one or more embodiments of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the protection scope of one or more embodiments of this specification.

Claims

1. A self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization, characterized in that, The self-rectified ferroelectric memristor has a vertical structure from top to bottom consisting of an upper electrode layer, a ferroelectric layer, and a semiconductor layer; a lower electrode layer is led out from the semiconductor layer; the ferroelectric layer is a ferroelectric semiconductor with out-of-plane ferroelectric polarization; the contact barrier between the ferroelectric layer and the semiconductor layer needs to be greater than the contact barrier between the ferroelectric layer and the upper electrode layer; the ferroelectric layer is copper indium phosphorus sulfide; The out-of-plane polarization direction of the ferroelectric layer is perpendicular to both the upper electrode layer / ferroelectric layer interface and the ferroelectric layer / semiconductor layer interface. The two contact surfaces form an asymmetric potential barrier. By applying an external voltage, the out-of-plane polarization state of the ferroelectric layer will be changed, thereby changing the potential barrier height of the two contact surfaces and changing the carrier transport characteristics of the semiconductor layer, thus achieving the function of regulating the conductance state of the memristor.

2. The self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that, The self-rectified ferroelectric memristor also includes an insulating layer for device isolation and / or substrate.

3. The self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that, The electrode structure of the self-rectified ferroelectric memristor is a sandwich structure, and the electrode material is any one of gold, platinum, titanium, silver, copper, aluminum, indium tin oxide, heavily doped semiconductor, or gallium indium alloy.

4. The self-rectified ferroelectric memristor based on ferroelectric out-of-plane polarization according to claim 1, characterized in that, The semiconductor layer is a doped material mainly composed of boron, germanium, silicon, gray tin, antimony, selenium, or tellurium crystals.

5. A method for fabricating a single device of the self-rectified ferroelectric memristor according to any one of claims 1-4, characterized in that, This includes preparing the interface structure between the ferroelectric layer and the semiconductor layer, and preparing electrodes that are in contact with the ferroelectric layer and the semiconductor layer, respectively; the specific steps are as follows: S1, an insulating layer is formed on the semiconductor layer, and the insulating layer is patterned and removed to prepare a contact window between the semiconductor layer and the ferroelectric layer; S2, ferroelectric material is transferred onto the contact window using a wet or dry method to form a ferroelectric layer; S3, an upper electrode layer is prepared on the ferroelectric layer using patterning and deposition processes; S4, the lower electrode layer is prepared by patterning and deposition processes or by coating gallium indium alloy on the semiconductor layer.

6. The preparation method according to claim 5, characterized in that, The semiconductor layer is silicon, the insulating layer is silicon oxide, and the upper electrode layer is gold.

7. A method for fabricating an array of self-rectified ferroelectric memristors according to any one of claims 1-4, characterized in that, Includes the following steps: S1, a discrete semiconductor layer is fabricated on a semiconductor / insulator using patterning and deep silicon etching techniques; the array pattern of the semiconductor layer is a bitline pattern in a crossbar structure; S2, an inert insulating layer is formed by filling the space between discrete semiconductor layers with insulating material using patterning and deposition processes; S3, transfer ferroelectric layer material onto the surface of an insulating layer / semiconductor or prepare a ferroelectric layer using a deposition method; S4, an upper electrode layer is fabricated on the ferroelectric layer using patterning and deposition processes; the array pattern of the upper electrode layer is a word line pattern in a crossbar structure; S5, the lower electrode layer is led out in the semiconductor layer to form a device array.

8. The preparation method according to claim 7, characterized in that, The semiconductor in S1 is silicon, the insulator is silicon oxide, and the semiconductor / insulator is implemented using an SOI silicon wafer; the inert insulating layer is aluminum oxide, and the upper electrode layer is gold.

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