Memory access method, device and system

Abstract

A memory access method, device and system, relating to the technical field of communications, the method comprising: after a first network card receives a first message carrying a first conversion virtual address sent by a second network card, querying a first translation table according to the first conversion virtual address to obtain a first physical address, and accessing the first physical address. Wherein the length of the first conversion virtual address is different from that of a process virtual address in a first node where the first network card is located. The problem that the memory access mode is relatively single can be solved. The method and the device are used for physical address access.

Description

Storage access method, device and system Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a memory access method, device, and system. Background Art

[0002] With the development of communication technology, distributed systems have been widely used. Distributed systems include multiple nodes that can share memory.

[0003] For example, in a distributed system, a first node shares the memory of the first node with a second node. The second network card of the second node can access the physical address of the first node based on the process virtual address (i.e., access the storage location with the physical address). For example, the second network card of the second node can send a message to the first network card of the first node, where the message carries the process virtual address corresponding to a physical address in the first node. After receiving the message, the first network card can query the translation table based on the process virtual address carried in the message to obtain the physical address; thereafter, the first network card can access the physical address.

[0004] However, currently the second node can only access the physical address based on the process virtual address. Therefore, the memory access method of the second node is relatively simple.

[0005] Summary of the Invention

[0006] This application provides a memory access method, device, and system that can solve the problem of a relatively single memory access method. The technical solution is as follows:

[0007] In a first aspect, the present application provides a memory access method, the method comprising: after a first network interface card receives a first message carrying a first translated virtual address from a second network interface card, querying a first translation table based on the first translated virtual address to obtain a first physical address, and performing memory access on the first physical address. The length of the first translated virtual address is different from the length of a process virtual address in a first node where the first network interface card is located.

[0008] The first translation virtual address and the first process virtual address corresponding to the first physical address have different lengths. Both the first translation virtual address and the first process virtual address are virtual addresses used to refer to the first physical address. The first translation virtual address will replace the first process virtual address and correspond to the first physical address. The second node can specify the first translation virtual address that needs to be accessed to the first node, so that the first node accesses the first physical address corresponding to the first translation virtual address according to the first translation virtual address. Optionally, the length of the first translation virtual address can be smaller than the first process virtual address. Therefore, it can be regarded as compressing the first process virtual address into the first translation virtual address.

[0009] The first translation table may include at least one level of tables, that is, the number of levels of the first translation table may be 1 or an integer greater than 1. Each level of the first translation table may include an index and an entry, and the entry corresponding to the index may be queried based on the index. The first conversion virtual address may include at least one level bit corresponding to the at least one level table, and an in-page offset excluding the at least one level bit. The index of each level table includes the level bit corresponding to the level table, and the at least one level table will be queried in sequence. By querying the level table based on the level bit corresponding to any level table, an entry may be obtained. The last level table is queried based on the level bit corresponding to the last level table, and the entry obtained includes the page frame number (PFN) of the storage page where the first physical address is located. When the first translation table includes multiple levels of tables, the i-th level table is queried based on the level bit corresponding to the i-th level table, and the entry obtained includes the identifier of the i+1-th level table, where i≥1. The first physical address may be determined based on the above-mentioned in-page offset and PFN, and the storage location with the first physical address is located within the storage page.

[0010] In the solution provided by the embodiment of the present application, the message sent by the second network card of the second node to the first network card of the first node carries a first translation virtual address, the length of which is different from the length of the process virtual address. Furthermore, the first network card can query the first translation table based on the first translation virtual address to obtain the first physical address and access the first physical address. It can be seen that the second node can access the physical address in the first node based on the translation virtual address that is different from the process virtual address, thereby enriching the ways in which the second node can access the physical address in the first node.

[0011] Optionally, the length of the first conversion virtual address is less than the length of the process virtual address. For example, the addressing method of the first conversion virtual address may be: an addressing method that obtains the shortest conversion virtual address among multiple addressing methods. In this case, the length of the conversion virtual address can be made as short as possible, further reducing the physical address and the conversion virtual address. It can be understood that the length of the first conversion virtual address may also be greater than the length of the process virtual address in the first node where the first network card is located, and the addressing method of the first conversion virtual address may not be an addressing method that obtains the shortest conversion virtual address among the multiple addressing methods, and this application does not limit this.

[0012] The number of levels of the translation table is positively correlated with the length of the virtual address that the translation table is used to translate. When the length of the first conversion virtual address is smaller than the length of the process virtual address to a certain extent, the number of levels of the first translation table can be smaller than the number of levels of the second translation table used to translate the first process virtual address into the first physical address. This can improve the efficiency of querying the translation table. It is understandable that when the length of the first conversion virtual address is smaller than the length of the process virtual address, the number of levels of the first translation table can also be equal to the number of levels of the second translation table, and this embodiment of the present application does not limit this.

[0013] The first physical address may belong to hardware such as memory or heterogeneous hardware in the first node. The first physical address belonging to memory means that the first physical address is the address of a storage location in the memory. The first physical address belonging to heterogeneous hardware means that the first physical address is the address of a storage location in the heterogeneous hardware. Heterogeneous hardware and memory are two different pieces of hardware in the first node, and the heterogeneous hardware is connected to the first network interface card. The heterogeneous hardware may be any type of hardware in the first node other than memory. For example, the heterogeneous hardware may be external memory (such as a solid state disk (SSD)) in the first storage of the first node; or the heterogeneous hardware may be hardware used for storage in the first processor of the first node; or the heterogeneous hardware may be any type of processor (PU), such as the first processor (which may be a central processing unit (CPU)), a graphics processing unit (GPU), or a data processing unit (DPU).

[0014] Furthermore, the first translation table can be implemented in a variety of ways, two of which are taken as examples below.

[0015] (1) In a first implementation of the first translation table, assuming that the first physical address belongs to the memory in the first node, the first translation table includes: a first-level table and multiple second-level tables. When the first network card queries the first translation table according to the first translation virtual address to obtain the first physical address, it can first query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables and information about the second-level bits in the first translation virtual address; then, the first network card determines the second-level bits and the page offset in the first translation virtual address according to the information about the second-level bits, and the page offset is determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits; finally, the first network card determines the second-level table according to the identifier of the second-level table, queries the second-level table according to the second-level bits, obtains a page frame number in the memory, and determines the first physical address according to the page frame number and the page offset.

[0016] (2) In a second implementation of the first translation table, the first physical address belongs to heterogeneous hardware (different from memory) in the first node. The first translation table includes: a first-level table and multiple second-level tables. When the first network card queries the first translation table according to the first translation virtual address to obtain the first physical address, it can first query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables and the information of the second-level bits in the first translation virtual address; then, the first network card determines the second-level bits, the page offset and the heterogeneous hardware in the first translation virtual address according to the information of the second-level bits, the page offset is determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits, and the value of the second-level bits is used to identify the heterogeneous hardware; the first network card can also determine the second-level table according to the identifier of the second-level table, query the second-level table according to the second-level bits to obtain a page frame number in the heterogeneous hardware, and determine the first physical address in the heterogeneous hardware according to the page frame number and the page offset. When the first network card accesses the first physical address, it can replace the first converted virtual address carried by the first message with the first physical address to obtain a second message, and forward the second message to the heterogeneous hardware, so that the heterogeneous hardware accesses the first physical address based on the second message.

[0017] Optionally, the first node where the first network card is located further includes a first processor, and the method further includes: receiving information of the first translation table sent by the first processor.

[0018] Optionally, the first translation table is used to translate multiple conversion virtual addresses into multiple physical addresses one by one; the multiple physical addresses include: at least two physical addresses whose corresponding process virtual addresses belong to different processes; the conversion virtual addresses used to translate the at least two physical addresses in the multiple conversion virtual addresses are different from each other.

[0019] Furthermore, the first message may also carry target permission information, and accordingly, the above-mentioned first request may also carry the target permission information. Before accessing the first physical address, the first network card may query the protection table based on the target permission information to verify the target permission information and determine whether the target permission information has been verified. In this way, the security of memory access can be improved through the target permission information. The first network card can query the protection table and query the first translation table in parallel. The first network card does not need to query the protection table first, and query the first translation table after determining that the target permission information has been verified. In this way, the efficiency of memory access is further improved.

[0020] In a second aspect, the present application provides a memory access method, the method comprising: a first processor in a first node assigns a first conversion virtual address to a first physical address, the length of the first conversion virtual address being different from the length of the process virtual address in the first node; thereafter, the first processor sends the first conversion virtual address to the second processor in the second node, and sends information of a first translation table to the first network card in the first node, the first translation table being used to translate the first conversion virtual address into the first physical address; wherein the second processor is used to send a first request carrying the first conversion virtual address to the second network card in the second node, and the second network card is used to send a first message carrying the first conversion virtual address to the first network card based on the first request; the first network card is used to query the first translation table according to the first conversion virtual address carried in the first message to obtain the first physical address, and access the first physical address.

[0021] Optionally, the first processor may allocate the first translated virtual address to the first physical address after registering the process virtual address corresponding to the first physical address.

[0022] In a third aspect, the present application provides a memory access method, comprising: a second processor in a second node sends a first request to a second network card in the second node, the first request carrying a first conversion virtual address; wherein the second network card is used to send a first message carrying the first conversion virtual address to the first network card in the first node based on the first request; the first network card is used to query a first translation table according to the first conversion virtual address, obtain a first physical address, and access the first physical address; the length of the first conversion virtual address is different from the length of the process virtual address in the first node.

[0023] Optionally, the method further includes: receiving, by a second processor, the first translated virtual address sent by the first processor in the first node.

[0024] In a fourth aspect, the present application provides a memory access device, the memory access device belonging to a first network card, the memory access device comprising: a first receiving module, a first query module, and a memory access module. The first receiving module is configured to receive a first message carrying a first translation virtual address sent by a second network card; the first query module is configured to query a first translation table based on the first translation virtual address to obtain a first physical address, wherein the length of the first translation virtual address is different from the length of the process virtual address in the first node where the first network card is located; and the memory access module is configured to access the first physical address.

[0025] In the solution provided by the embodiment of the present application, the message sent by the second network card of the second node to the first network card of the first node carries a first translation virtual address, the length of which is different from the length of the process virtual address. Furthermore, the first network card can query the first translation table based on the first translation virtual address to obtain the first physical address and access the first physical address. It can be seen that the second node can access the physical address in the first node based on the translation virtual address that is different from the process virtual address, thereby enriching the ways in which the second node can access the physical address in the first node.

[0026] Optionally, the length of the first conversion virtual address is less than the length of the process virtual address. For example, the addressing method of the first conversion virtual address may be: an addressing method that obtains the shortest conversion virtual address among multiple addressing methods. In this case, the length of the conversion virtual address can be made as short as possible, further reducing the physical address and the conversion virtual address. It can be understood that the length of the first conversion virtual address may also be greater than the length of the process virtual address in the first node where the first network card is located, and the addressing method of the first conversion virtual address may not be an addressing method that obtains the shortest conversion virtual address among the multiple addressing methods, and this application does not limit this.

[0027] The number of levels of the translation table is positively correlated with the length of the virtual address that the translation table is used to translate. When the length of the first conversion virtual address is smaller than the length of the process virtual address to a certain extent, the number of levels of the first translation table can be smaller than the number of levels of the second translation table used to translate the first process virtual address into the first physical address. This can improve the efficiency of querying the translation table. It is understandable that when the length of the first conversion virtual address is smaller than the length of the process virtual address, the number of levels of the first translation table can also be equal to the number of levels of the second translation table, and this embodiment of the present application does not limit this.

[0028] The first physical address may belong to hardware such as memory or heterogeneous hardware in the first node.

[0029] Furthermore, the first translation table can be implemented in a variety of ways, two of which are taken as examples below.

[0030] (1) In a first implementation of the first translation table, assuming that the first physical address belongs to the memory in the first node, the first translation table includes: a first-level table and multiple second-level tables, and the first query module is used to: query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables and information about the second-level bits in the first translation virtual address; determine the second-level bits and the page offset in the first translation virtual address according to the information about the second-level bits, the page offset being determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits; determine the second-level table according to the identifier of the second-level table; query the second-level table according to the second-level bits to obtain a page frame number in the memory; and determine the first physical address according to the page frame number and the page offset.

[0031] (2) In a second implementation of the first translation table, the first physical address belongs to heterogeneous hardware (different from memory) in the first node. Based on the first implementation of the first translation table, in the second implementation of the first translation table, the value of the second-level bit is used to identify the heterogeneous hardware, and the PFN in the second-level table is the PFN of the heterogeneous hardware.

[0032] For example, the first translation table includes: a first-level table and multiple second-level tables, the first query module is used to: query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables, and information about the second-level bits in the first translation virtual address; determine the second-level bits, the page offset, and the heterogeneous hardware in the first translation virtual address according to the information about the second-level bits, the page offset being determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits, and the value of the second-level bits being used to identify the heterogeneous hardware; determine the second-level table according to the identifier of the second-level table; query the second-level table according to the second-level bits to obtain a page frame number in the heterogeneous hardware; determine the first physical address in the heterogeneous hardware according to the page frame number and the page offset; the memory access module is used to: replace the first translation virtual address carried by the first message with the first physical address to obtain a second message; and forward the second message to the heterogeneous hardware so that the heterogeneous hardware accesses the first physical address based on the second message.

[0033] Optionally, the first node where the first network card is located further includes a first processor, and the memory access device further includes: a second receiving module, configured to receive information of the first translation table sent by the first processor.

[0034] Optionally, the first translation table is used to translate multiple conversion virtual addresses into multiple physical addresses one by one; the multiple physical addresses include: at least two physical addresses whose corresponding process virtual addresses belong to different processes; the conversion virtual addresses used to translate the at least two physical addresses in the multiple conversion virtual addresses are different from each other.

[0035] Furthermore, the first message may also carry target permission information, and accordingly, the above-mentioned first request may also carry the target permission information. Before accessing the first physical address, the first network card may query the protection table based on the target permission information to verify the target permission information and determine whether the target permission information has been verified. In this way, the security of memory access can be improved through the target permission information. The first network card can query the protection table and query the first translation table in parallel. The first network card does not need to query the protection table first, and query the first translation table after determining that the target permission information has been verified. In this way, the efficiency of memory access is further improved.

[0036] In a fifth aspect, the present application provides a memory access device, the memory access device belonging to a first processor in a first node, the memory access device comprising: an allocation module, a first sending module, and a second sending module. The allocation module is configured to allocate a first translation virtual address to a first physical address, wherein the length of the first translation virtual address is different from the length of the process virtual address in the first node; the first sending module is configured to send the first translation virtual address to a second processor in a second node; and the second sending module is configured to send information of a first translation table to a first network card in the first node, wherein the first translation table is configured to translate the first translation virtual address into the first physical address.

[0037] The second processor is used to send a first request carrying the first conversion virtual address to the second network card in the second node; the second network card is used to send a first message carrying the first conversion virtual address to the first network card based on the first request; the first network card is used to query the first translation table according to the first conversion virtual address carried in the first message to obtain the first physical address, and access the first physical address.

[0038] Optionally, the allocation module is configured to allocate the first converted virtual address to the first physical address after registering the process virtual address corresponding to the first physical address.

[0039] In the sixth aspect, the present application provides a memory access device, which belongs to a second processor in a second node, and the memory access device includes: a sending module for sending a first request to a second network card in the second node, wherein the first request carries a first conversion virtual address; wherein the second network card is used to send a first message carrying the first conversion virtual address to the first network card in the first node based on the first request; the first network card is used to query a first translation table according to the first conversion virtual address, obtain a first physical address, and access the first physical address; the length of the first conversion virtual address is different from the length of the process virtual address in the first node.

[0040] Optionally, the memory access device further includes: a receiving module, configured to receive the first converted virtual address sent by the first processor in the first node.

[0041] In the seventh aspect, the present application provides a memory access node, which is a first node, and the memory access node includes a first network card and a first processor; the first processor is used to communicate with other nodes outside the first node through the first network card; the first network card includes the memory access device described in any design in the fourth aspect.

[0042] Optionally, the first processor includes the memory access device described in any design of the fifth aspect.

[0043] In the eighth aspect, the present application provides a memory access node, which is a second node, and the memory access node includes a second network card and a second processor; the second processor is used to communicate with other nodes outside the second node through the second network card, and the second processor includes the memory access device described in any design in the sixth aspect.

[0044] In a ninth aspect, the present application provides a memory access method, the method comprising: after a first node receives a first message carrying a first translated virtual address from a second node, querying a first translation table based on the first translated virtual address to obtain a first physical address, and accessing the first physical address. The length of the first translated virtual address is different from the length of the virtual address of a process in the first node where the first network interface card is located.

[0045] Optionally, before receiving the first message carrying the first conversion virtual address sent by the second node, the first node can also assign the first conversion virtual address to the first physical address, and send the first conversion virtual address and information configuring the first translation table to the second node.

[0046] Optionally, the first node may allocate the first translated virtual address to the first physical address after registering the process virtual address corresponding to the first physical address.

[0047] Optionally, the length of the first conversion virtual address is less than the length of the process virtual address. For example, the addressing method of the first conversion virtual address may be: an addressing method that obtains the shortest conversion virtual address among multiple addressing methods. In this case, the length of the conversion virtual address can be made as short as possible, further reducing the physical address and the conversion virtual address. It can be understood that the length of the first conversion virtual address may also be greater than the length of the process virtual address in the first node, and the addressing method of the first conversion virtual address may not be an addressing method that obtains the shortest conversion virtual address among the multiple addressing methods, and this application does not limit this.

[0048] The number of levels of the translation table is positively correlated with the length of the virtual address that the translation table is used to translate. When the length of the first conversion virtual address is smaller than the length of the process virtual address to a certain extent, the number of levels of the first translation table can be smaller than the number of levels of the second translation table used to translate the first process virtual address into the first physical address. This can improve the efficiency of querying the translation table. It is understandable that when the length of the first conversion virtual address is smaller than the length of the process virtual address, the number of levels of the first translation table can also be equal to the number of levels of the second translation table, and this embodiment of the present application does not limit this.

[0049] The first physical address may belong to hardware such as memory or heterogeneous hardware in the first node.

[0050] Furthermore, the first translation table can be implemented in a variety of ways, two of which are taken as examples below.

[0051] (1) In a first possible implementation of the first translation table, assuming that the first physical address belongs to the memory in the first node, the first translation table includes: a first-level table and multiple second-level tables. When the first node queries the first translation table according to the first conversion virtual address to obtain the first physical address, it can first query the first-level table according to the first-level bits in the first conversion virtual address to obtain the identifier of a second-level table in the multiple second-level tables, and information about the second-level bits in the first conversion virtual address; then, the first node determines the second-level bits and the page offset in the first conversion virtual address according to the information about the second-level bits, and the page offset is determined according to the bits in the first conversion virtual address other than the first-level bits and the second-level bits; finally, the first node determines the second-level table according to the identifier of the second-level table, queries the second-level table according to the second-level bits, obtains a page frame number in the memory, and determines the first physical address according to the page frame number and the page offset.

[0052] (2) In a second implementation of the first translation table, the first physical address belongs to heterogeneous hardware (different from memory) in the first node. The first translation table includes: a first-level table and multiple second-level tables. When the first node queries the first translation table according to the first translation virtual address to obtain the first physical address, it can first query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables and the information of the second-level bits in the first translation virtual address; then, the first node determines the second-level bits, the page offset and the heterogeneous hardware in the first translation virtual address according to the information of the second-level bits, the page offset is determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits, and the value of the second-level bits is used to identify the heterogeneous hardware; the first node can also determine the second-level table according to the identifier of the second-level table, query the second-level table according to the second-level bits to obtain a page frame number in the heterogeneous hardware, and determine the first physical address in the heterogeneous hardware according to the page frame number and the page offset. When the first node accesses the first physical address, it can replace the first converted virtual address carried by the first message with the first physical address to obtain a second message, and transmit the second message to the heterogeneous hardware so that the heterogeneous hardware accesses the first physical address based on the second message.

[0053] Optionally, the first translation table is used to translate multiple conversion virtual addresses into multiple physical addresses one by one; the multiple physical addresses include: at least two physical addresses whose corresponding process virtual addresses belong to different processes; the conversion virtual addresses used to translate the at least two physical addresses in the multiple conversion virtual addresses are different from each other.

[0054] Furthermore, the first message may also carry target authority information, and accordingly, the above-mentioned first request may also carry the target authority information. Before accessing the first physical address, the first node may query the protection table based on the target authority information to verify the target authority information and determine whether the target authority information has been verified. In this way, the security of memory access can be improved through the target authority information. The first node can query the protection table and query the first translation table in parallel. The first node does not need to query the protection table first, and query the first translation table after determining that the target authority information has been verified. In this way, the efficiency of memory access is further improved.

[0055] In the tenth aspect, the present application provides a memory access method, which includes: a second node sends a first message carrying a first conversion virtual address to a first node; wherein the first node is used to query a first translation table according to the first conversion virtual address, obtain a first physical address, and access the first physical address; the length of the first conversion virtual address is different from the length of the process virtual address in the first node.

[0056] Optionally, before sending the first message to the first node, the second node may further receive the first converted virtual address sent by the first node.

[0057] In an eleventh aspect, the present application provides a memory access system, comprising a first node and a second node;

[0058] The first node includes: a first network card and a first processor, the first network card is used to execute the memory access method described in any design of the first aspect, and the first processor is used to execute the memory access method described in any design of the second aspect; the second node includes: a second network card and a second processor, the second processor is used to execute the memory access method described in any design of the third aspect;

[0059] Alternatively, the first node is used to execute the memory access method described in any design of the ninth aspect, and the second node is used to execute the memory access method described in any design of the tenth aspect.

[0060] In the twelfth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is run on a computer, it is used to implement the memory access method described in any one of the designs of the first aspect, the second aspect, the third aspect, the ninth aspect and the tenth aspect.

[0061] In a thirteenth aspect, the present application provides a computer program product comprising instructions, which, when running on a computer, is used to implement the memory access method described in any one of the first, second, third, ninth and tenth aspects.

[0062] The effects of the fourth to thirteenth aspects can refer to the effects of the corresponding schemes in the first to third aspects, and this application will not go into details here. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG1 is a schematic diagram of the structure of a memory access node provided in an embodiment of the present application;

[0064] FIG2 is a schematic diagram of the structure of another memory access node provided in an embodiment of the present application;

[0065] FIG3 is a schematic diagram of the architecture of another memory access node provided in an embodiment of the present application;

[0066] FIG4 is a schematic diagram of communication between a first node and a second node provided in an embodiment of the present application;

[0067] FIG5 is a schematic diagram of another communication between a first node and a second node provided in an embodiment of the present application;

[0068] FIG6 is a schematic diagram of a translation table query process provided in an embodiment of the present application;

[0069] FIG7 is a flowchart of a memory access method provided in an embodiment of the present application;

[0070] FIG8 is a schematic diagram of a query process of a first translation table provided in an embodiment of the present application;

[0071] FIG9 is a schematic diagram of a correspondence relationship between virtual address spaces provided in an embodiment of the present application;

[0072] FIG10 is a schematic diagram of a process of executing a memory access method by a memory access node provided in an embodiment of the present application;

[0073] FIG11 is a flowchart of another memory access method provided in an embodiment of the present application;

[0074] FIG12 is a schematic structural diagram of a memory access device provided in an embodiment of the present application;

[0075] FIG13 is a schematic structural diagram of another memory access device provided in an embodiment of the present application;

[0076] FIG14 is a schematic structural diagram of another memory access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] In order to make the principles, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0078] The present invention provides a memory access system. The memory access system can be any system including multiple memory access nodes, such as a distributed system. A node can be a device or a part of a device. The device can be a mobile phone, a computer, a gateway, a router, a server, or a server cluster.

[0079] For example, FIG1 is a schematic structural diagram of a memory access node provided in an embodiment of the present application. As shown in FIG1 , the memory access node includes: a processor 101 and a network interface card (NIC) 102 connected to each other. The processor 101 is used to call a program to execute a corresponding method or implement a corresponding function. The NIC 102 is used to communicate with the NICs in other memory access nodes under the control of the processor 101. For example, the NICs 102 can communicate with each other through messages. Communication between the NICs 102 can adopt any protocol, such as the Infiniband (IB) protocol, the IB remote direct memory access (RDMA) protocol, the unified bus (UB) protocol, etc. The NICs 102 do not need to communicate through the processor, thereby reducing redundant input / output (I / O) stacks, improving communication efficiency between NICs, and improving processor performance.

[0080] Optionally, as shown in FIG2 , based on the memory access node shown in FIG1 , the memory access node may further include a memory 103. Memory 103 is used to store programs. Processor 101 is connected to memory 103 and is used to communicate with other nodes outside the memory access node via a network interface card (NIC). The program invoked by processor 101 may be stored on processor 101 or memory 103. Network interface card 102 may also be connected to memory 103 and may be capable of accessing physical addresses in memory 103. For example, NIC 102 may access the physical addresses based on messages sent by other NICs.

[0081] Furthermore, the architecture of the memory access node can be shown in FIG3 , which includes a software portion 201 and a hardware portion 202. The software portion 201, also known as a software stack, includes a process 2010, a software framework 2011, and a network card driver (NIC driver) 2012. The software framework 2011 can be any software framework, such as the Open Fabrics Enterprise Distribution (OFED) software framework or the Unified Memory Development Kit (UMDK) software framework.

[0082] Hardware 202 includes a network card 2021 and a processor, or a network card 2021, a processor, and memory. FIG3 illustrates an example of a hardware component including a network card 2021 and memory 2022. Software 201 includes a program for running on the processor. When the program runs on the processor, the processor controls the network card.

[0083] For example, the portion of software 201 used to control the network card can be software framework 2011 or network card driver 2012. When the portion used to control the network card can be software framework 2011, software framework 2011 can generate instructions for controlling the network card and transmit the instructions to network card 2021 via network card driver 2012. When the portion used to control the network card is network card driver 2012, network card driver 2012 can generate instructions for controlling the network card and transmit the instructions to network card 2021. It is understood that software 201 can also include processes running on software framework 2011, and these processes can also control the network card.

[0084] As described above, network cards in memory access nodes can communicate with each other via messages. For example, the multiple memory access nodes in a memory access system may include a first node and a second node. Taking the memory access node structure shown in Figure 1 as an example, as shown in Figure 4, the first node includes a first processor and a first network card, and the second node includes a second processor and a second network card. It can be seen that the first and second processors are processors in two different nodes, and the first and second network cards are network cards in two different nodes. It is understandable that the first node may also include a first memory, and the second node may also include a second memory; the first and second memories are not shown in Figure 4. Continuing with Figure 4, the second processor can control the second network card to send a message to the first network card. The first network card can process the message. Taking the memory access node structure shown in Figure 3 as an example, as shown in Figure 5, a second process running on the second processor in the second node can invoke a second software framework to control the second network card through the second network card driver to send a message to the first network card in the first node. The first network card can process the message. In the above process, the second node sends a message to the first node. Therefore, the first node is a target-side node and the second node is an initiator-side node.

[0085] Furthermore, the rise of artificial intelligence (AI) and big data services has led to an increase in data volumes, and the "central processing unit (CPU)-centric" model has evolved into a "memory-centric" model. Network cards can now share memory in the storage by transmitting messages. For example, a message sent by the second network card to the first network card is used to access the physical address of the memory in the first storage:

[0086] In this scenario, the first processor configures a protection table (PT) and multiple translation tables (TT) (also known as page tables) on the first network card. The protection table records the correspondence between verification information and the base address of the translation table. The translation table is used to translate the process virtual address into a physical address. The message sent by the second network card to the first network card can carry the process virtual address and verification information of the physical address in the memory. After receiving the message, the first network card can query the protection table based on the verification information carried by the message to obtain the translation table base address corresponding to the verification information, and find the corresponding translation table based on the translation table base address. Afterwards, the first network card can query the translation table based on the process virtual address carried by the message to obtain the physical address, and then access the physical address (access the storage location with the physical address). It can be seen that the second network card can access the memory of the first memory through the first network card, and the data in the memory of the first memory does not need to be moved to the memory of the second memory of the second node. In this way, the communication overhead of data movement is reduced through the flow of computing power.

[0087] However, the length of a process virtual address is usually long (usually including 64 bits or 32 bits, etc., which is much larger than the length of a physical address), and the number of levels in the translation table is positively correlated with the length of the process virtual address. Therefore, the translation table used to translate the process virtual address into the physical address usually needs to include a multi-level table (usually the translation table includes a three-level table or a four-level table), such as a radix tree multi-level page table. In this way, when the first network card queries the translation table according to the process virtual address, it needs to query the multi-level table in sequence, resulting in low efficiency of the first network card in querying the translation table, affecting the first network card's processing efficiency of the message, and high communication delay (also known as the end-to-end (E2E) delay) between the first network card and the second network card.

[0088] In related technologies, in order to reduce the number of levels of translation tables, the following solutions can be adopted:

[0089] The protection table not only records the translation table base address corresponding to the verification information, but also records the virtual address base address corresponding to the verification information. The translation table is not used to translate the process virtual address into a physical address, but is used to translate the offset of the process virtual address relative to the virtual address base address into a physical address. After the first network card queries the protection table based on the verification information carried by the message, it can obtain the translation table base address and virtual address base address corresponding to the verification information; thereafter, the first network card can determine the offset of the process virtual address carried by the message relative to the virtual address base address, and query the translation table corresponding to the translation table base address based on the offset to obtain the above-mentioned physical address. In this way, since the length of the offset is shorter than the length of the process virtual address, the number of levels of the translation table can be reduced to a certain extent.

[0090] For example, referring to Figure 6, assume that the message sent by the second network card to the first network card carries: verification information 1 and the process virtual address, and all bits in the offset of the process virtual address 1 relative to the virtual address base B1 can be divided into: first-level index A1, second-level index A2, third-level index A3, fourth-level index A4, and in-page offset. Then, the first network card can query the protection table based on the verification information 1 to obtain the virtual address base B1 corresponding to the verification information 1 and the base address B21 of the first-level table in the translation table. Afterwards, the first network card can determine the offset of the process virtual address 1 relative to the virtual address base B1 based on the process virtual address 1 and the virtual address base B1, and query the first-level table with the base address B21 based on the first-level index A1 in the offset to obtain the base address B22 of the second-level table. Next, the first network card can query the second-level table with base address B22 based on the second-level index A2 in the offset and obtain the base address B23 of the third-level table. Based on the third-level index A3 in the offset, it can query the third-level table with base address B23 and obtain the base address B24 of the fourth-level table. Based on the fourth-level index A4 in the offset, it can query the fourth-level table with base address B24 and obtain PFN C1. Finally, the first network card can obtain the physical address based on PFN C1 and the page offset in the offset.

[0091] However, the translation table used to translate the offset of a process's virtual address relative to the virtual address base into a physical address still requires a large number of levels (e.g., four levels in the example shown in Figure 6 ). This still results in low efficiency in querying the translation table by the first network card, impacting its packet processing efficiency. Furthermore, currently, the second node can only access the physical address in the first node based on the process's virtual address, resulting in a relatively simple memory access method for the second node.

[0092] Embodiments of the present application provide a memory access method that involves fewer levels of translation tables, thereby improving the efficiency of a first network interface card in querying the translation table and the efficiency of the first network interface card in processing packets. Furthermore, in this memory access method, a second node can access a physical address in the first node based on a translated virtual address that differs from a process virtual address, thereby enriching the second node's memory access methods.

[0093] For example, FIG7 is a flowchart of a memory access method provided in an embodiment of the present application. The method is performed by a memory access system provided in an embodiment of the present application. The memory access system includes a first node and a second node. The first node includes a first network card and a first processor, and the second node includes a second network card and a second processor. In the embodiment of the present application, memory access at a first physical address is used as an example. Memory access at other physical addresses different from the first physical address can refer to the memory access at the first physical address. The embodiment of the present application will not be described in detail here.

[0094] As shown in FIG7 , the memory access method includes the following operations.

[0095] S701: A first processor registers a first process virtual address, where the first process virtual address corresponds to a first physical address.

[0096] A first process (such as an application process) is running on the first processor. The first process can specify the first process virtual address that needs to be registered in the process virtual address space according to business needs; thereafter, the software framework running on the first processor can complete the registration of the first process virtual address under the call of the first process.

[0097] After the first process virtual address is registered, the first process virtual address has a corresponding first physical address. Unregistered virtual addresses in the process virtual address space do not have corresponding physical addresses. The first processor may also record information used to translate the first process virtual address into the first physical address in the second translation table.

[0098] The first physical address may belong to a first memory in the first node, that is, the first physical address may be the physical address of a storage location in the first memory. For example, the first physical address may be the physical address of a storage location in a memory in the first memory. The memory may include a double data rate synchronous dynamic random access memory (DDR), etc.

[0099] S702: The first processor allocates a first translated virtual address to the first physical address, where the length of the first translated virtual address is smaller than the length of the virtual address of the process in the first node.

[0100] The software framework running on the first processor may allocate a first translated virtual address to the first physical address after the first process virtual address is registered, so that the second node can subsequently access the first physical address based on the first translated virtual address.

[0101] The first translation virtual address is different from the first process virtual address in length. Both the first translation virtual address and the first process virtual address are virtual addresses used to refer to the first physical address. In subsequent operations, the first translation virtual address will replace the first process virtual address and correspond to the first physical address. The second node can specify the first translation virtual address that needs to be accessed to the first node, so that the first node can access the first physical address corresponding to the first translation virtual address according to the first translation virtual address. Optionally, the length of the first translation virtual address can be smaller than the first process virtual address. Therefore, it can be regarded as compressing the first process virtual address into the first translation virtual address.

[0102] The first processor allocates different translation virtual addresses to different physical addresses. The first processor may allocate corresponding translation virtual addresses according to different physical addresses.

[0103] Typically, the address space of a physical address is small, while the process virtual address space is large (some process virtual addresses in the process virtual address space will not be registered). Therefore, the length of the physical address is short, while the length of the process virtual address is long, and the length difference between the physical address and the process virtual address is large. In the embodiment of the present application, the first processor only allocates a converted virtual address to the physical address corresponding to the registered process virtual address. In this way, the length of the converted virtual address allocated to the physical address can be smaller than the length of the process virtual address, so that the address space of the converted virtual address can match the address space of the physical address as much as possible, and the length difference between the physical address and the converted virtual address is small.

[0104] Furthermore, according to the idea of ​​allocating the conversion virtual address described above, the conversion virtual address can have multiple addressing modes, and the lengths of the conversion virtual addresses obtained by using different addressing modes are different. In the embodiment of the present application, the first conversion virtual address is taken as an example using the addressing mode that obtains the shortest conversion virtual address among the multiple addressing modes. In this case, the length of the conversion virtual address can be made as short as possible, further reducing the length difference between the physical address and the conversion virtual address.

[0105] After allocating the first translated virtual address to the first physical address, the first processor may further record the relationship between the first physical address and the first translated virtual address.

[0106] S703: The first processor sends the first translated virtual address to the second processor.

[0107] When registering the first process virtual address, the first process on the first processor may further specify a second process corresponding to the first process virtual address. The second process is used to access the first physical address corresponding to the first process virtual address. The second process runs on the second processor of the second node. After allocating the first translated virtual address, the software framework running on the first processor may further send the first translated virtual address to the second processor, so that the second process running on the second processor can obtain the first translated virtual address.

[0108] The first converted virtual address can be transmitted between the first processor and the second processor via a secure channel. Information (including the first converted virtual address) transmitted between the first processor and the second processor can be transmitted in the form of serialized data.

[0109] S704: The first processor sends information of a first translation table to the first network card, where the first translation table is used to translate the first converted virtual address into a first physical address.

[0110] After assigning the first translated virtual address to the first physical address, the software framework running on the first processor can further configure, based on the first physical address and the first translated virtual address, information of a first translation table for translating the first translated virtual address into the first physical address to the first network interface card, so that the first network interface card can subsequently translate the first translated virtual address into the first physical address according to the first translation table. For example, the software framework running on the first processor can send the information of the first translation table to the first network interface card via a network interface card driver, wherein the network interface card driver is configured to format the information of the first translation table into a format recognizable by the first network interface card.

[0111] The first translation table may include at least one level table, that is, the number of levels of the first translation table may be 1 or an integer greater than 1. Each level table of the first translation table includes: an index and an entry, and the entry corresponding to the index can be queried according to the index. The first conversion virtual address includes: at least one level bit corresponding to the at least one level table, and an in-page offset excluding the at least one level bit. The index of each level table includes the level bit corresponding to the level table, and the at least one level table will be queried in sequence. By querying the level table according to the level bit corresponding to any level table, an entry can be obtained. Among them, the last level table is queried according to the level bit corresponding to the last level table, and the entry obtained includes the PFN of the storage page where the first physical address is located; when the first translation table includes multiple levels of tables, the i-th level table is queried according to the level bit corresponding to the i-th level table, and the entry obtained includes the identifier of the i+1-th level table, i≥1. The first physical address can be determined according to the above-mentioned in-page offset and PFN, and the storage location with the first physical address is located within the storage page.

[0112] The first translation table may or may not be stored on the first network card. When the first translation table includes multiple levels of tables, some tables may be stored on the first network card, while other tables may not be stored on the first network card. For tables in the first translation table stored on the first network card, the information about these tables sent by the first processor to the first network card may be the tables themselves. For tables in the first translation table not stored on the first network card, the information about these tables sent by the first processor to the first network card may be the storage addresses of these tables. The first network card may store the information about the first translation table in at least one register.

[0113] The number of levels of the translation table is positively correlated with the length of the virtual address that the translation table is used to translate. When the length of the first conversion virtual address is smaller than the length of the process virtual address (such as the first process virtual address) to a certain extent, the number of levels of the first translation table can be smaller than the number of levels of the second translation table used to translate the first process virtual address into the first physical address. The index length of the i-th level table in the first translation table can be the same as the index length of the i-th level table in the second translation table, and the index length of the i-th level table in the first translation table can also be different from the index length of the i-th level table in the second translation table, i≥1. For example, the number of levels of the first translation table is 1 and the number of levels of the second translation table is 4, then the number of levels of the first translation table is 3 less than the number of levels of the second translation table. It can be understood that, when the length of the first conversion virtual address is smaller than the length of the process virtual address, the number of levels of the first translation table can also be equal to the number of levels of the second translation table, and the embodiments of the present application do not limit this.

[0114] In this application, the registration of the first process virtual address corresponding to the first physical address and the allocation of the first conversion virtual address to the first physical address are taken as examples. It can be understood that the first process can register a process virtual address subspace (belonging to the process virtual address space) at a time, and the process virtual address subspace includes multiple process virtual addresses, and the process virtual address corresponding to the first physical address is one of the multiple process virtual addresses. Accordingly, the first processor can allocate a conversion virtual address subspace to the physical address subspace corresponding to the process virtual address subspace in S702. The conversion virtual address subspace includes: a conversion virtual address allocated to the physical address corresponding to each process virtual address in the process virtual address subspace. In S703, the first processor can send each conversion virtual address in the conversion virtual address subspace to the second processor. The first translation table in S704 can be used to translate each conversion virtual address in the conversion virtual address subspace into a physical address.

[0115] S705: The second processor sends a first request to the second network card, where the first request carries a first converted virtual address.

[0116] Since the first processor sent the first translated virtual address to the second process running on the second processor in S703, the second process can access the first translated virtual address as needed (which can be understood as accessing the first physical address corresponding to the first translated virtual address). When the second process needs to access the first translated virtual address, the software framework running on the second processor can generate a first request carrying the first translated virtual address and send the first request to the second network card. For example, the software framework running on the second processor can send the first request to the second network card via the network card driver running on the second processor.

[0117] Optionally, when the second process needs to access memory, it can specify the first translated virtual address, so that the second processor generates the first request based on the first translated virtual address. Alternatively, when the first processor sends the first translated virtual address to the second processor, it can also carry the first process virtual address; when the second process needs to access data memory, it can specify the first process virtual address, and the second processor can determine the first translated virtual address based on the first process virtual address, and then generate the first request based on the first translated virtual address.

[0118] S706: The second network card sends a first message carrying the first translated virtual address to the first network card based on the first request.

[0119] After receiving the first request, the second network interface card may write the first request into a request queue and, based on the requests in the request queue, encapsulate messages for transmission to the first network interface card. The queue may be referred to as a work queue, and the first request added to the queue may be referred to as a work queue element (WQE). Based on the first request, the second network interface card may encapsulate a first message carrying the first translated virtual address and send the first message to the first network interface card.

[0120] In an embodiment of the present application, a communication connection is established between the first network card and the second network card. The second network card can transmit the first message to the first network card through the communication connection. During this process, the first message will not pass through the first processor.

[0121] In addition to carrying the first conversion virtual address carried in the first request, the first message may also carry other information, which is not limited in this embodiment of the present application.

[0122] S707: The first network card searches the first translation table according to the first converted virtual address carried in the first message to obtain a first physical address.

[0123] After receiving the first message, the first network card can parse the first message and extract the first translated virtual address carried in the first message. After obtaining the first translated virtual address, the first network card can query a first translation table based on the first translated virtual address to obtain a first physical address obtained by translating the first translated virtual address. The first network card can query the first translation table using a linear table lookup. The first network card can include a message engine, and the first network card can use the message engine to parse the first message and extract the first translated virtual address, and obtain the first physical address based on the first translated virtual address.

[0124] S708: The first network card accesses the first physical address.

[0125] The first network card performs memory access on the first physical address, that is, the first network card performs memory access on the storage location having the first physical address. After determining the first physical address, the first network card can determine the target storage location having the first physical address based on the first physical address, and then perform memory access (access or store) on the target storage location.

[0126] When the first message is used to access the target storage location, the first network card can read the data stored in the target storage location and send the data to the second network card. The second network card can then send the data to the second processor so that the second process in the second processor can obtain the data.

[0127] When the first message is used to store data in the target storage location, the first request carries not only the first translated virtual address but also the data to be stored. The first network card can then write the data to the target storage location. Subsequently, the first network card can send a store response to the second network card indicating that the data has been written to the target storage location, so that the second network card can transmit the store response to the second processor, allowing the second process on the second processor to determine that the data has been successfully stored based on the store response.

[0128] In summary, in the memory access method provided in the embodiment of the present application, the message sent by the second network card of the second node to the first network card of the first node carries a first conversion virtual address, and the length of the first conversion virtual address is different from the length of the process virtual address. In addition, the first network card can query the first translation table based on the first conversion virtual address to obtain the first physical address and access the first physical address. It can be seen that the second node can access the physical address in the first node based on the conversion virtual address that is different from the process virtual address, thereby enriching the way in which the second node accesses the physical address in the first node.

[0129] In the above embodiment, the length of the first converted virtual address is smaller than the length of the process virtual address. It can be understood that the length of the first converted virtual address can also be larger than the length of the process virtual address, and the embodiment of the present application does not limit this.

[0130] In addition, when the length of the first conversion virtual address sent by the second network card to the first network card is less than the length of the virtual address, the number of levels of the first translation table used to translate the first physical address according to the first conversion virtual address in this application can be less than the number of levels of the second translation table used to translate the physical address according to the process virtual address (such as the first physical address translated according to the first process virtual address). In this way, in the process of the first network card querying the first translation table to obtain the first physical address according to the first conversion virtual address, the first network card needs to query fewer tables, so the speed at which the first network card translates the first conversion virtual address into the first physical address is faster, which can improve the processing efficiency of the first network card for the message. For example, in this application, the speed at which the first network card translates the first conversion virtual address into the first physical address is 36 percent higher than the speed at which the first network card translates the first process virtual address into the first physical address.

[0131] In addition, the process to which the process virtual address in this application belongs can be a virtual machine process, for example, both the first process and the second process described above can be virtual machine processes. When the process to which the process virtual address belongs is a virtual machine process, the speed at which the first network interface card translates the first conversion virtual address into the first physical address is increased by 78 percent compared to the speed at which the first network interface card translates the first process virtual address into the first physical address.

[0132] In the above embodiment, the first physical address belongs to the memory in the first node as an example. It can be understood that the first physical address may not belong to the memory, but to the heterogeneous hardware in the first node. The first physical address belongs to the heterogeneous hardware, which means that the first physical address is the address of a storage location in the heterogeneous hardware. Heterogeneous hardware and memory are two different hardware in the first node, and the heterogeneous hardware is connected to the first network card. Heterogeneous hardware can be any hardware other than memory in the first node. For example, the heterogeneous hardware can be external memory (such as SSD, etc.) in the first memory of the first node; or, the heterogeneous hardware can be hardware for storage in the first processor of the first node; or, the heterogeneous hardware can also be any PU, such as the first processor (which can be a CPU), GPU, DPU, etc.

[0133] Furthermore, the first translation table can be implemented in a variety of ways, two of which are taken as examples below.

[0134] (1) In the first implementation of the first translation table, as shown in FIG8 , assuming that the first physical address belongs to the memory in the first node, the first translation table includes: a first-level table and multiple second-level tables, and FIG8 shows only one second-level table. The index of the first-level table is the first-level bit in the conversion virtual address, and the entry corresponding to the index of the first-level table includes: the identifier of the second-level table (such as the base address of the second-level table), and the information of the second-level bit in the conversion virtual address; the index of the second-level table is the second-level bit in the conversion virtual address, and the entry corresponding to the index of the second-level table includes: the page frame number (PFN). Both the first-level table and the second-level table may include one or more table entries, which is not limited in the embodiment of the present application. The position of the first-level bit in the conversion virtual address may also be specified by the first processor, and the information of the first-level bit may be carried in the information of the first translation table, and the information of the first-level bit may also be stored in a register by the first network card.

[0135] Taking the example of a first translation table used to translate a first translation virtual address into a first physical address, the first-level bits in the first translation virtual address correspond in the first-level table to: an identifier of a second-level table and information about the second-level bits in the first translation virtual address; the bits indicated by this information are the second-level bits in the first translation virtual address. The second-level bits in the first translation virtual address correspond to a PFN in the second-level table. The first physical address can be determined based on the PFN and the page offset, where the page offset is determined based on the bits in the first translation virtual address other than the first-level bits and the second-level bits. For example, if the first-level bits, second-level bits, and third-level bits are arranged consecutively and in sequence in the bits of the first translation virtual address, then the value of the third-level bit is the page offset. Optionally, the first-level bits and second-level bits in the bits of the first translation virtual address may be discontinuous.

[0136] It is understandable that the implementation of the first translation table may also differ from the implementation shown in FIG8 . For example, the first translation table may include a first-level table or a third-level table. When the first translation table includes the first-level table and the second-level table, the entry corresponding to the index in the first-level table in the first translation table may also not include information about the second-level bits in the converted virtual address. In this case, the position of the second-level bits may also be specified by the first processor, the information about the second-level bits may also be carried in the information in the first translation table, and the information about the second-level bits may also be stored in a register by the first network interface card.

[0137] When the first translation table is shown in FIG8 , when the first network interface card queries the first translation table based on the first translation virtual address, it can first query the first-level table in the first translation table based on the first-level bits in the first translation virtual address to obtain an identifier of a second-level table in the first translation table and information about the second-level bits in the first translation virtual address. The first network interface card can then determine the second-level bits and the page offset in the first translation virtual address based on the information about the second-level bits in the first translation virtual address, and determine a second-level table based on the identifier of the second-level table. The page offset is determined by the first network interface card based on bits in the first translation virtual address other than the first-level bits and the second-level bits. After determining the second-level bits, the page offset, and the second-level table in the first translation virtual address, the first network interface card can query the second-level table based on the second-level bits in the first translation virtual address to obtain a PFN in memory, and determine the first physical address in memory based on the PFN and the page offset. For example, the first network card may first find the storage page corresponding to the PFN in the memory, and then find the first physical address in the storage page according to the offset in the page.

[0138] In this case, when the first network card accesses the first physical address in S708 , it may directly determine the storage location having the first physical address in the memory according to the first physical address, and access the storage location.

[0139] Optionally, when the first translation table includes a first-level table and multiple second-level tables, the sizes of the storage pages corresponding to the PFNs recorded in each second-level table may be the same, or the sizes of the storage pages corresponding to the PFNs recorded in at least two second-level tables may be different. For example, the sizes of the storage pages corresponding to the PFNs recorded in these second-level tables may include multiple sizes such as 4 kilobytes, 64 kilobytes, 1 megabyte, 8 megabytes, 16 megabytes, 128 megabytes, 516 megabytes, and 1 gigabyte (e.g., 16 sizes). When the sizes of the storage pages corresponding to the PFNs recorded in at least two second-level tables are different, the multiple second-level tables may also include second-level tables that record the same size of storage pages corresponding to the PFNs.

[0140] The number of second-level bits indicated by the second-level bit information recorded in the second-level table can be negatively correlated with the size of the storage page corresponding to the PFN recorded in the second-level table, and positively correlated with the number of table entries in the second-level table (that is, the number of PFNs recorded in the second-level table).

[0141] For example, assuming the first translated virtual address includes bit 0 to bit 63, a total of 64 bits, the first-level bits may be the upper three bits in the first translated virtual address, and the first-level table may be as shown in Table 1.

[0142] Table 1

[0143]

[0144] For another example, assuming the first translated virtual address includes bit 0 to bit 47, a total of 48 bits, the first-level bits may be the upper three bits in the first translated virtual address, and the first-level table may be as shown in Table 2.

[0145] Table 2

[0146]

[0147] In Tables 1 and 2, the index of the first-level table is the first-level bit. The entry corresponding to the index in the first-level table includes: the identifier of the second-level table, the number of entries in the second-level table, the size of the storage page corresponding to the PFN in the second-level table, and the second-level bit information (the starting second-level bit and the ending second-level bit). The entry in the first-level table may include 8 bytes. It is understood that the entry corresponding to the index in the first-level table may not include the number of entries in the second-level table or the size of the storage page corresponding to the PFN in the second-level table, and the entry in the first-level table may not include 8 bytes, for example, the entry may include 5 bytes.

[0148] In addition, the index of the second-level table is a second-level bit, and the entry corresponding to the index in the second-level table may include a PFN, and the entry may further include flag information of the PFN.

[0149] Assume that after registering each process virtual address subspace, the first processor allocates a translation virtual address subspace (which may be referred to as a segmented translation virtual address space) to the physical address subspace corresponding to the process virtual address subspace. The translation virtual address subspace may correspond to an entry in the first-level table and a second-level table. The entry is used to indicate the second-level table, which is used to record the PFN of each physical address in the physical address subspace. The first processor may allocate the translation virtual address subspace based on the size of the physical address subspace and the size of each storage page.

[0150] (2) In a second implementation of the first translation table, the first physical address belongs to heterogeneous hardware (different from memory) in the first node. Based on the first implementation of the first translation table, in the second implementation of the first translation table, the value of the second-level bit is used to identify the heterogeneous hardware, and the PFN in the second-level table is the PFN of the heterogeneous hardware.

[0151] When the first network card queries the first translation table based on the first translation virtual address, it can first query the first-level table based on the first-level bits in the first translation virtual address to obtain the identifier of a second-level table among multiple second-level tables, as well as information about the second-level bits in the first translation virtual address. Then, based on the information about the second-level bits, the first network card can determine the second-level bits, the page offset, and the heterogeneous hardware in the first translation virtual address. The page offset is determined based on the bits in the first translation virtual address other than the first-level bits and the second-level bits, and the value of the second-level bits is used to identify the heterogeneous hardware. The first network card can also determine the second-level table based on the identifier of the second-level table, and query the second-level table based on the second-level bits to obtain a page frame number in the heterogeneous hardware. Finally, the first network card can determine the first physical address in the heterogeneous hardware based on the page frame number and the page offset.

[0152] In this case, when the first network interface card accesses the first physical address in S708, the heterogeneous hardware may access the first physical address. For example, the first network interface card may replace the first translated virtual address carried in the first message with the first physical address to obtain a second message. The first network interface card may then forward the second message to the heterogeneous hardware, so that the heterogeneous hardware accesses the first physical address based on the second message.

[0153] Usually, when the second node accesses the heterogeneous hardware in the first node, the first processor of the first node needs to participate. For example, after the second network card of the second node transmits the first message to the first network card, the first network card will report the first message to the first processor, and then the first processor will analyze the first message to determine the heterogeneous hardware to be accessed; after that, the first processor will instruct the first network card to access the heterogeneous hardware. In the embodiment of the present application, after receiving the first message, the first network card can determine the first physical address according to the first translation table, and then send the second message to the heterogeneous hardware based on the first physical address, so that the heterogeneous hardware can access the first physical address. The first processor does not need to participate in this process, thereby improving the memory access efficiency of the heterogeneous hardware and improving business performance.

[0154] In the embodiment of the present application, the first translation table is used to translate the conversion virtual address into a physical address in memory or heterogeneous hardware as an example. It is understandable that the first translation table can also be used to translate a part of the conversion virtual address into a physical address in memory, and to translate another part of the conversion virtual address into a physical address in heterogeneous hardware. In this case, the first network card queries the first-level table based on the first-level bits in the conversion virtual address, and not only obtains the identifier of a second-level table in multiple second-level tables, and the information of the second-level bits in the conversion virtual address, but also obtains a flag information. The flag information is used to indicate whether the physical address to which the first translation table is used to translate the conversion virtual address belongs to memory or heterogeneous hardware. Afterwards, when the flag information is used to indicate that the physical address to which the first translation table is used to translate the conversion virtual address belongs to memory, the first network card can continue to query the second-level table with reference to the first implementable method of the above-mentioned first translation table to determine the first physical address. When the flag information is used to indicate that the physical address into which the conversion virtual address is translated by the first translation table belongs to heterogeneous hardware, the first network card can continue to query the second-level table with reference to the second implementable method of the above-mentioned first translation table to determine the first physical address, and send a second message to the heterogeneous hardware based on the first physical address.

[0155] Furthermore, in the above embodiments, the functions of a processor (a first processor or a second processor) are implemented by a software framework running on the processor. For example, the functions of the first processor are implemented by a software framework running on the first processor, and the functions of the second processor are implemented by a software framework running on the second processor. It is understood that the functions of the above-mentioned processors may not be implemented by a software framework. For example, the functions of the processors may be implemented by a network card driver.

[0156] In the above embodiment, the conversion virtual address (first conversion virtual address) is allocated by the first processor and transmitted to the second processor, and the information of the first translation table is sent by the first processor to the first network card as an example. It is understandable that the conversion virtual address (first conversion virtual address) may not be allocated by the first processor and transmitted to the second processor, and the information of the first translation table may not be sent by the first processor to the first network card. For example, the conversion virtual address (first conversion virtual address) can be configured on the second processor by the staff, and the information of the first translation table can also be configured on the first network card by the staff. In this case, the above embodiment may not include S701 to S704.

[0157] In addition, the first processor may further adjust and update the first translation table so that the first translation table is used to update the first physical address obtained by translating the first converted virtual address.

[0158] For example, the first processor can send information about an updated first translation table to the first network card, and the first network card can update the first translation table based on the information about the updated first translation table, so that the first physical address obtained by translating the first conversion virtual address in the first translation table is updated. After the first translation table is updated, if the first network card receives a message carrying the first conversion virtual address sent by the second network card, the first network card can query the updated first translation table based on the first conversion virtual address, obtain the updated first physical address, and access the updated first physical address. In this way, it is possible to achieve flexible adjustment of the first physical address accessed by the first network card based on the first conversion virtual address, so that the second device can interweave access to multiple physical addresses based on the first conversion virtual address. For example, the first physical address can be flexibly switched between the physical addresses in DDR and SSD.

[0159] In the embodiments of this application, the first network card updates the first translation table based on information about the updated first translation table sent by the first processor. It is understood that the first network card may also update the first translation table based on other information. For example, the first network card may update the first translation table based on instructions input by a staff member; or, in another example, the first network card may independently update the first translation table based on a certain algorithm.

[0160] In the above embodiment, the first translation table is used to translate the first conversion virtual address into the first physical address as an example. It can be understood that the first translation table can be used to translate multiple conversion virtual addresses into multiple physical addresses one by one; the multiple conversion virtual addresses include the above first conversion virtual address, and the multiple physical addresses include the above first physical address.

[0161] Optionally, the multiple physical addresses include: at least two physical addresses whose corresponding process virtual addresses belong to different processes; and the converted virtual addresses used to translate the at least two physical addresses in the multiple converted virtual addresses are different from each other.

[0162] In other words, the first processor is used to allocate a translation virtual address to the physical address corresponding to the process virtual address of each process in a translation virtual address space. It can be seen that the translation virtual address space is an operating system (OS)-level virtual address space, and the first processor can uniformly allocate a translation virtual address to the physical address corresponding to each process virtual address in the translation virtual address space. When the above-mentioned first physical address is a physical address in the memory, the translation virtual address can be called a unified memory address (UMA). In this way, the physical addresses corresponding to the process virtual addresses of different processes are allocated different translation virtual addresses, and the physical addresses corresponding to the process virtual addresses of the same process are also allocated different translation virtual addresses. Therefore, any two translation virtual addresses allocated by the first processor are different.

[0163] 9 , it is assumed that the process virtual address space of the first processor includes virtual address space A of process 1 and virtual address space B of process 2. Process 1 can register a process virtual address in virtual address space A, and process 2 can register a virtual address in virtual address space B.

[0164] The virtual addresses of each process in virtual address space A are different from each other, and the virtual addresses of each process in virtual address space B are different from each other, but the virtual address of a process in virtual address space A and the virtual address of a process in virtual address space B are the same.

[0165] The physical addresses corresponding to the virtual addresses of each process registered in virtual address space A are different from each other, the physical addresses corresponding to the virtual addresses of each process registered in virtual address space B are different from each other, and the physical addresses corresponding to the virtual addresses of the processes registered in virtual address space A and the virtual addresses of the processes registered in virtual address space B are different.

[0166] The first processor can allocate translation virtual addresses in the translation virtual address space to the physical addresses corresponding to the process virtual addresses in virtual address spaces A and B. As shown in FIG9 , assuming that a 1GB (1GB = 1024MB, 1MB = 1024KB, 1KB = 1024 bytes) process virtual address is registered in virtual address space A and a 2GB process virtual address is registered in virtual address space B, then the first processor can allocate 3GB of translation virtual addresses in the translation virtual address space. This 3GB of translation virtual addresses includes: a 1GB translation virtual address allocated to the physical address corresponding to the 1GB process virtual address in virtual address space A, and a 2GB translation virtual address allocated to the physical address corresponding to the 2GB process virtual address in virtual address space B.

[0167] The 3G translation virtual addresses are different from each other and can be continuous or discontinuous. FIG9 takes the case where the 1G translation virtual address is continuous, the 2G translation virtual address is continuous, and the 1G translation virtual address and the 2G translation virtual address are discontinuous as an example. The 1G translation virtual address and the 2G translation virtual address are separated by a 3G translation virtual address.

[0168] In addition, the first processor can also reclaim at least part of the allocated converted virtual addresses. When reclaiming the converted virtual addresses, the first processor needs to instruct the first network card to delete the information used to translate the converted virtual addresses into physical addresses in the first translation table. The first processor can also instruct the second processor to delete the converted virtual addresses.

[0169] Optionally, when allocating the conversion virtual address, the first processor can adopt a buddy algorithm to allocate the conversion virtual address in the conversion virtual address space, and manage the conversion virtual address space according to the address space of a fixed length (e.g., 1 megabyte) to reduce the fragmentation of the conversion virtual address space as much as possible. For example, when allocating the conversion virtual address, the first processor can allocate the address space of this fixed length at each time. When reclaiming the conversion virtual address, the first processor can reclaim the address space of this fixed length at each time. Of course, the first processor can also adopt other algorithms different from the buddy algorithm to allocate the conversion virtual address, and the embodiments of the present application do not limit this.

[0170] Furthermore, the first message may also carry target permission information, and accordingly, the first request may also carry the target permission information. Before accessing the first physical address, the first network card may query the protection table based on the target permission information to verify the target permission information and determine whether the target permission information has been verified. In this way, the security of memory access can be improved by using the target permission information.

[0171] At least part of the target permission information may be information specified by the first process running on the first processor. If the at least part of the information is part of the target permission information, then the other part of the information may be generated by the software framework running on the first processor when it is called by the first process to allocate the first translation virtual address.

[0172] When the first processor sends the first translated virtual address to the second processor, the target permission information can also be sent to the second processor. When the first processor sends the first translation table information to the first network card, the protection table information can also be sent to the first network card.

[0173] There are various ways to implement the target permission information.

[0174] For example, the target permission information includes: a token identity document (token ID), a token, an identifier of the storage page where the first physical address is located (such as a base address), the size of the storage page, and memory access permission (RW) information. Among them, the information other than the token identifier in the target permission information can be specified by the first process running on the first processor, and the token identifier can be specified by the software framework running on the first processor. The index of the protection table can be the token identifier, and the entries corresponding to the index can include: the token, the identifier of the storage page where the first physical address is located, the size of the storage page, and RW information.

[0175] When the first network card queries the protection table based on the target permission information to verify the target permission information, it can query the entry corresponding to the token identifier in the protection table based on the token identifier carried by the first message. The first network card can also compare the token in the entry with the token carried by the first message; compare the identifier of the storage page in the entry with the identifier of the storage page carried by the first message; compare the size of the storage page in the entry with the size of the storage page carried by the first message; and compare the RW information in the entry with the RW information carried by the first message. When the results of these comparisons are the same, the first network card can determine that the target permission information has been verified. If the results of at least one of these comparisons are different, then the first network card can determine that the target permission information has not been verified.

[0176] Furthermore, when the above-mentioned multiple physical addresses include: at least two physical addresses whose corresponding process virtual addresses belong to different processes, and the conversion virtual addresses used to translate the at least two physical addresses in the above-mentioned multiple conversion virtual addresses are different from each other, any two conversion virtual addresses assigned by the first processor are different. In this case, the first translation table can be used to translate any conversion virtual address assigned by the first processor into a physical address, so the first network card querying the protection table and querying the first translation table can be performed in parallel. The first network card does not need to query the protection table first, and only needs to query the first translation table after confirming that the target permission information has been verified. In this way, the efficiency of memory access is further improved.

[0177] In the above content, the above-mentioned multiple physical addresses include: at least two physical addresses of which the corresponding process virtual addresses belong to different processes; and the conversion virtual addresses used to translate the at least two physical addresses are different from each other. It is understandable that the conversion virtual addresses used to translate the at least two physical addresses can also be the same. In this case, the protection table not only records the permission information, but also records the identifier of the first translation table corresponding to the permission information (such as the base address). After the target permission information is verified, the first network card can determine the first translation table according to the identifier of the first translation table corresponding to the target permission information, and then query the first translation table according to the first conversion virtual address.

[0178] The following is an example to illustrate the method provided in the embodiment of the present application.

[0179] For example, the first node includes a software component and a hardware component. As shown in FIG10 , the software component includes a first process, a software framework, and a network card driver, and the hardware component includes a first network card, a first memory (only the memory in the first memory is shown in FIG10 ), and a first processor (the first processor is not shown in FIG10 ).

[0180] The software part in the first node runs on the first processor to implement the functions of the first processor. FIG10 takes the translation address management module in the software framework in the software part as an example to implement the functions of the first processor.

[0181] A first network card is connected to a first memory. A first-level table in a first translation table is stored on the first network card. A second-level table and a protection table in the first translation table are also stored in the first memory. The first network card includes registers 1, 2, and 3. Register 1 is used to record the storage address of the protection table; register 2 is used to record the storage address of the first-level table in the first translation table; and register 3 is used to record information about first-level bits in a converted virtual address.

[0182] The translation address management module can allocate a first translation virtual address to the first physical address when the first process registers the process virtual address corresponding to the first physical address, and configure the register and the first-level table in the first network card, as well as the protection table and the second-level table in the memory according to the first translation virtual address and the first physical address.

[0183] The first network card also includes a message engine. The message engine can receive the first message sent by the second network card and parse the first message to obtain the first conversion virtual address and target verification information. The message engine can also query the protection table based on the target verification information and the storage address recorded by register 1 to verify the target verification information. At the same time, the message engine can also query the first-level table in the first translation table based on the first conversion virtual address, the storage address recorded by register 2, and the first-level bit information recorded by register 3 to obtain a second-level table identifier and second-level bit information. Thereafter, the message engine can also query the second-level table based on the first conversion virtual address, the identifier of the second-level table, and the second-level bit information to obtain a PFN, and then determine the first physical address based on the PFN and the page offset in the first conversion virtual address. Finally, after the target verification information is verified, the message engine can access the first physical address.

[0184] Continuing with FIG10 , the second node also includes a software component and a hardware component. The software component includes a second process, a software framework, and a network card driver. The software component in the second node runs on a second processor and is used to implement the functions of the second processor. The hardware component of the second node includes a second network card, a second memory, and a second processor (the second memory and second processor are not shown in FIG10 ). The second network card includes a work queue and a message engine.

[0185] The translation address management module in the first node is further configured to send the first translation virtual address to the second processor in the second node, so that the second process running on the second processor can obtain the first translation virtual address. In the second node, the second process can call the software framework to generate a first request, and the software framework can transmit the first request to the work queue in the second network card through the network card driver; the software framework can also write to the doorbell (DB) register (not shown in FIG10 ) in the second network card to trigger the message engine of the second network card to take the first request from the work queue, encapsulate the first message according to the first request, and transmit the first message to the first network card.

[0186] In addition, the method provided by the embodiment of the present application may also include an initialization phase, and the first node is used to perform initialization operations in the initialization phase. For example, the initialization operation may include at least some of the following operations: the first processor in the first node determines the conversion virtual address space; the first processor determines the location for recording the relationship between the first physical address and the first conversion virtual address, and ensures that the relationship recorded at the location is empty; the first processor allocates the storage location of the first translation table and the protection table; the first processor configures the various registers in the first network card; the first processor configures the initialized first translation table (empty table) and the initialized protection table (empty table). These operations may be performed sequentially or not, and the embodiment of the present application does not limit this.

[0187] As can be seen from the above description, an embodiment of the present application provides a memory access method in which a second node can send a first message carrying a first translated virtual address to a first node. After receiving the first message, the first node can query a first translation table based on the first translated virtual address to obtain a first physical address, and then access the first physical address.

[0188] Optionally, before the second node sends the first message to the first node, the first node may further assign a first translated virtual address to the first physical address and send the first translated virtual address, along with information about locally configuring the first translation table, to the second node. Accordingly, the second node receives the first translated virtual address sent by the first node. The second node may send the first message to the first node based on the first translated virtual address sent by the first node.

[0189] Optionally, the first node may allocate a first translated virtual address to the first physical address after registering the process virtual address corresponding to the first physical address.

[0190] Optionally, the first message also carries target authority information. After receiving the first message, the first node can also query the protection table based on the target authority information to verify the target authority information; wherein, querying the protection table and querying the first translation table are performed in parallel; the first node can access the first physical address when the target authority information is verified.

[0191] As shown in FIG11 , the memory access method may include:

[0192] S1101. A first node registers a process virtual address corresponding to a first physical address.

[0193] S1102: The first node allocates a first converted virtual address to the first physical address.

[0194] S1103: The first node sends a first converted virtual address to the second node.

[0195] S1104: The first node locally configures information of a first translation table.

[0196] S1105: The second node sends a first message carrying the first translated virtual address and target authority information to the first node according to the first translated virtual address sent by the first node.

[0197] S1106: The first node concurrently queries the first translation table according to the first converted virtual address to obtain the first physical address, and queries the protection table according to the target permission information to verify the target permission information.

[0198] S1107: When the target authority information is verified, the first node accesses the first physical address.

[0199] The memory access method provided in the embodiment of the present application is introduced above. The memory access device provided in the embodiment of the present application will be introduced below in combination with the above memory access method.

[0200] For example, FIG12 is a schematic structural diagram of a memory access device provided in an embodiment of the present application. The memory access device may belong to a first network card in a first node. As shown in FIG12 , the memory access device includes:

[0201] The first receiving module 1201 is configured to receive a first message carrying a first translated virtual address sent by the second network card. The operations performed by the first receiving module 1201 may refer to the contents related to the first network card in S706 in the above embodiment.

[0202] A first query module 1202 is configured to query a first translation table based on the first translated virtual address to obtain a first physical address, where the length of the first translated virtual address is different from the length of the virtual address of the process in the first node where the first network interface card is located. For the operations performed by the first query module 1202, reference may be made to the contents related to the first network interface card in S707 of the aforementioned embodiment.

[0203] The memory access module 1203 is configured to access the first physical address. The operations performed by the memory access module 1203 may refer to the contents related to the first network card in S708 in the above embodiment.

[0204] In the solution provided by the embodiment of the present application, the message sent by the second network card of the second node to the first network card of the first node carries a first translation virtual address, the length of which is different from the length of the process virtual address. Furthermore, the first network card can query the first translation table based on the first translation virtual address to obtain the first physical address and access the first physical address. It can be seen that the second node can access the physical address in the first node based on the translation virtual address that is different from the process virtual address, thereby enriching the ways in which the second node can access the physical address in the first node.

[0205] Optionally, the length of the first conversion virtual address is less than the length of the process virtual address. For example, the addressing method of the first conversion virtual address may be: an addressing method that obtains the shortest conversion virtual address among multiple addressing methods. In this case, the length of the conversion virtual address can be made as short as possible, further reducing the physical address and the conversion virtual address. It can be understood that the length of the first conversion virtual address may also be greater than the length of the process virtual address in the first node where the first network card is located, and the addressing method of the first conversion virtual address may not be an addressing method that obtains the shortest conversion virtual address among the multiple addressing methods, and this application does not limit this.

[0206] The number of levels of the translation table is positively correlated with the length of the virtual address that the translation table is used to translate. When the length of the first conversion virtual address is smaller than the length of the process virtual address to a certain extent, the number of levels of the first translation table can be smaller than the number of levels of the second translation table used to translate the first process virtual address into the first physical address. This can improve the efficiency of querying the translation table. It is understandable that when the length of the first conversion virtual address is smaller than the length of the process virtual address, the number of levels of the first translation table can also be equal to the number of levels of the second translation table, and this embodiment of the present application does not limit this.

[0207] The first physical address may belong to hardware such as memory or heterogeneous hardware in the first node.

[0208] Furthermore, the first translation table can be implemented in a variety of ways, two of which are taken as examples below.

[0209] (1) In a first implementation of the first translation table, assuming that the first physical address belongs to the memory in the first node, the first translation table includes: a first-level table and multiple second-level tables, and the first query module is used to: query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables and information about the second-level bits in the first translation virtual address; determine the second-level bits and the page offset in the first translation virtual address according to the information about the second-level bits, the page offset being determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits; determine the second-level table according to the identifier of the second-level table; query the second-level table according to the second-level bits to obtain a page frame number in the memory; and determine the first physical address according to the page frame number and the page offset.

[0210] (2) In a second implementation of the first translation table, the first physical address belongs to heterogeneous hardware (different from memory) in the first node. Based on the first implementation of the first translation table, in the second implementation of the first translation table, the value of the second-level bit is used to identify the heterogeneous hardware, and the PFN in the second-level table is the PFN of the heterogeneous hardware.

[0211] For example, the first translation table includes: a first-level table and multiple second-level tables, the first query module is used to: query the first-level table according to the first-level bits in the first translation virtual address to obtain the identifier of a second-level table in the multiple second-level tables, and information about the second-level bits in the first translation virtual address; determine the second-level bits, the page offset, and the heterogeneous hardware in the first translation virtual address according to the information about the second-level bits, the page offset being determined according to the bits in the first translation virtual address other than the first-level bits and the second-level bits, and the value of the second-level bits being used to identify the heterogeneous hardware; determine the second-level table according to the identifier of the second-level table; query the second-level table according to the second-level bits to obtain a page frame number in the heterogeneous hardware; determine the first physical address in the heterogeneous hardware according to the page frame number and the page offset; the memory access module is used to: replace the first translation virtual address carried by the first message with the first physical address to obtain a second message; and forward the second message to the heterogeneous hardware so that the heterogeneous hardware accesses the first physical address based on the second message.

[0212] Optionally, the first node where the first network card is located further includes a first processor, and the memory access device further includes: a second receiving module (not shown in the drawings) configured to receive information about the first translation table sent by the first processor. The operations performed by the second receiving module may refer to the contents related to the first network card in S704.

[0213] Optionally, the first translation table is used to translate multiple conversion virtual addresses into multiple physical addresses one by one; the multiple physical addresses include: at least two physical addresses whose corresponding process virtual addresses belong to different processes; the conversion virtual addresses used to translate the at least two physical addresses in the multiple conversion virtual addresses are different from each other.

[0214] Furthermore, the first message may also carry target permission information, and accordingly, the above-mentioned first request may also carry the target permission information. Before accessing the first physical address, the first network card may query the protection table based on the target permission information to verify the target permission information and determine whether the target permission information has been verified. In this way, the security of memory access can be improved through the target permission information. The first network card can query the protection table and query the first translation table in parallel. The first network card does not need to query the protection table first, and query the first translation table after determining that the target permission information has been verified. In this way, the efficiency of memory access is further improved.

[0215] As another example, FIG13 is a schematic structural diagram of a memory access device provided in an embodiment of the present application. The memory access device may belong to a first processor in a first node. As shown in FIG13 , the memory access device includes:

[0216] The allocation module 1301 is configured to allocate a first translated virtual address to the first physical address, wherein the length of the first translated virtual address is different from the length of the process virtual address in the first node. For the operations performed by the allocation module 1301, reference may be made to the contents related to the first processor in S702.

[0217] The first sending module 1302 is configured to send the first translated virtual address to the second processor in the second node. For the operations performed by the first sending module 1302 , reference may be made to the contents related to the first processor in S703 .

[0218] The second sending module 1303 is used to send information of the first translation table to the first network card in the first node, and the first translation table is used to translate the first conversion virtual address into the first physical address; the operation performed by the second sending module 1303 can refer to the content related to the first processor in S704.

[0219] The second processor is used to send a first request carrying the first conversion virtual address to the second network card in the second node; the second network card is used to send a first message carrying the first conversion virtual address to the first network card based on the first request; the first network card is used to query the first translation table according to the first conversion virtual address carried in the first message to obtain the first physical address, and access the first physical address.

[0220] Optionally, the allocation module is configured to allocate the first converted virtual address to the first physical address after registering the process virtual address corresponding to the first physical address.

[0221] As another example, FIG14 is a schematic structural diagram of a memory access device provided in an embodiment of the present application. The memory access device may belong to a second processor in a second node. As shown in FIG14 , the memory access device includes:

[0222] A sending module 1401 is configured to send a first request to a second network interface card in the second node, the first request carrying a first translated virtual address. For operations performed by the sending module 1401, reference may be made to the second processor-related content in S705. The second network interface card is configured to send a first message carrying the first translated virtual address to the first network interface card in the first node based on the first request. The first network interface card is configured to query a first translation table based on the first translated virtual address to obtain a first physical address, and to access the first physical address. The length of the first translated virtual address is different from the length of the process virtual address in the first node.

[0223] Optionally, the memory access device further includes a receiving module (not shown in the drawings) configured to receive the first translated virtual address sent by the first processor in the first node. The operations performed by the receiving module may refer to the contents related to the second processor in S703.

[0224] An embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is run on a computer, it is used to implement any memory access method provided in the embodiments of the present application and executed by the first network card, the second network card, the first processor, the second processor, the first node or the second node.

[0225] An embodiment of the present application provides a computer program product comprising instructions, which, when running on a computer, is used to implement any memory access method provided in the embodiments of the present application and executed by a first network card, a second network card, a first processor, a second processor, a first node, or a second node.

[0226] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium (e.g., a solid-state hard disk).

[0227] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" refers to one or more, and "a plurality" refers to two or more, unless otherwise expressly defined.

[0228] The various embodiments provided in the embodiments of this application (such as various method embodiments, method embodiments and device embodiments) can refer to each other. The various actions described in the method embodiments provided in the embodiments of this application do not necessarily represent a sequential order. The execution order of each action can be appropriately adjusted as needed, and the actions can also be increased or decreased accordingly according to the situation. Any person skilled in the art who can easily think of a method of change within the technical scope disclosed in this application should be included in the scope of protection of this application, so it will not be repeated here.

[0229] In the corresponding embodiments provided in this application, it should be understood that the disclosed structures can be implemented through other configurations. For example, the embodiments described above are merely illustrative.

[0230] The above are merely optional embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A memory access method, characterized in that: The method is performed by a first network card, and includes: receiving a first message carrying a first converted virtual address sent by the second network card; querying a first translation table according to the first translated virtual address to obtain a first physical address, wherein a length of the first translated virtual address is different from a length of a virtual address of a process in a first node where the first network card is located; Access the first physical address.

2. The method according to claim 1, characterized in that The length of the first translation virtual address is smaller than the length of the process virtual address.

3. The method according to claim 2, characterized in that The addressing mode of the first conversion virtual address is: an addressing mode that obtains the shortest conversion virtual address among multiple addressing modes.

4. The method according to claim 2 or 3, characterized in that The level number of the first translation table is smaller than the level number of the second translation table, and the second translation table is used to translate the process virtual address into a physical address.

5. The method according to any one of claims 1 to 4, characterized in that: The first physical address belongs to the memory of the first node.

6. The method according to claim 5, characterized in that The first translation table includes: a first-level table and multiple second-level tables, and querying the first translation table according to the first converted virtual address to obtain the first physical address includes: querying the first-level table according to the first-level bits in the first translated virtual address to obtain an identifier of a second-level table among the plurality of second-level tables and information about the second-level bits in the first translated virtual address; Determining, based on the information of the second-level bits, the second-level bits and the page offset in the first translation virtual address, wherein the page offset is determined based on the bits in the first translation virtual address other than the first-level bits and the second-level bits; Determining the one second-level table according to an identifier of the one second-level table; querying the second-level table according to the second-level bit to obtain a page frame number in the memory; The first physical address is determined according to the page frame number and the intra-page offset.

7. The method according to any one of claims 1 to 4, characterized in that: The first physical address belongs to heterogeneous hardware in the first node.

8. The method according to claim 7, characterized in that The first translation table includes: a first-level table and multiple second-level tables, and querying the first translation table according to the first converted virtual address to obtain the first physical address includes: querying the first-level table according to the first-level bits in the first translated virtual address to obtain an identifier of a second-level table among the plurality of second-level tables and information about the second-level bits in the first translated virtual address; Determining, based on the information of the second-level bits, the second-level bits, the page offset, and the heterogeneous hardware in the first translation virtual address, wherein the page offset is determined based on bits in the first translation virtual address other than the first-level bits and the second-level bits, and the values ​​of the second-level bits are used to identify the heterogeneous hardware; Determining the one second-level table according to an identifier of the one second-level table; querying the second-level table according to the second-level bit to obtain a page frame number in the heterogeneous hardware; Determining the first physical address in the heterogeneous hardware according to the page frame number and the intra-page offset; Accessing the first physical address includes: Replacing the first translated virtual address carried in the first message with the first physical address to obtain a second message; The second message is forwarded to the heterogeneous hardware, so that the heterogeneous hardware accesses the first physical address based on the second message.

9. The method according to any one of claims 1 to 8, characterized in that: The first node where the first network card is located further includes a first processor, and the method further includes: Receive information about the first translation table sent by the first processor.

10. The method according to any one of claims 1 to 9, characterized in that: The first translation table is used to translate a plurality of conversion virtual addresses into a plurality of physical addresses in a one-to-one correspondence; The plurality of physical addresses include: at least two physical addresses corresponding to process virtual addresses belonging to different processes; The translated virtual addresses used for translating the at least two physical addresses in the multiple translated virtual addresses are different from each other.

11. The method according to claim 10, characterized in that The first message also carries target authority information, and the method further includes: querying a protection table according to the target permission information to verify the target permission information; wherein querying the protection table and querying the first translation table are performed in parallel; Accessing the first physical address includes: When the target authority information is verified, the first physical address is accessed.

12. A memory access method, characterized in that: The method is executed by a first processor in a first node, and the method includes: Allocating a first translated virtual address to the first physical address, wherein a length of the first translated virtual address is different from a length of a process virtual address in the first node; sending the first translated virtual address to a second processor in the second node; Sending information of a first translation table to a first network card in the first node, where the first translation table is used to translate the first converted virtual address into the first physical address; The second processor is used to send a first request carrying the first conversion virtual address to the second network card in the second node; the second network card is used to send a first message carrying the first conversion virtual address to the first network card based on the first request; the first network card is used to query the first translation table according to the first conversion virtual address carried in the first message to obtain the first physical address, and access the first physical address.

13. The method according to claim 12, characterized in that Allocating a first translated virtual address to the first physical address includes: After registering the process virtual address corresponding to the first physical address, the first translated virtual address is allocated to the first physical address.

14. A memory access method, characterized in that: The method is executed by a second processor in a second node, and the method includes: Sending a first request to the second network card in the second node, where the first request carries a first converted virtual address; The second network card is used to send a first message carrying the first conversion virtual address to the first network card in the first node based on the first request; the first network card is used to query a first translation table according to the first conversion virtual address to obtain a first physical address, and to access the first physical address; the length of the first conversion virtual address is different from the length of the process virtual address in the first node.

15. The method according to claim 14, characterized in that The method further comprises: The first translated virtual address sent by the first processor in the first node is received.

16. A memory access device, characterized in that: The memory access device belongs to the first network card, and the memory access device includes: A first receiving module, configured to receive a first message carrying a first converted virtual address sent by the second network card; a first query module, configured to query a first translation table according to the first converted virtual address to obtain a first physical address, wherein a length of the first converted virtual address is different from a length of a process virtual address in a first node where the first network card is located; A memory access module is used to access the first physical address.

17. A memory access device, characterized in that: The memory access device belongs to the first processor in the first node, and the memory access device includes: an allocating module, configured to allocate a first translated virtual address to the first physical address, wherein a length of the first translated virtual address is different from a length of a process virtual address in the first node; A first sending module, configured to send a first converted virtual address to a second processor in a second node; a second sending module, configured to send information of a first translation table to the first network card in the first node, where the first translation table is used to translate the first converted virtual address into the first physical address; The second processor is used to send a first request carrying the first conversion virtual address to the second network card in the second node; the second network card is used to send a first message carrying the first conversion virtual address to the first network card based on the first request; the first network card is used to query the first translation table according to the first conversion virtual address carried in the first message to obtain the first physical address, and access the first physical address.

18. A memory access device, characterized in that: The memory access device belongs to the second processor in the second node, and the memory access device includes: a sending module, configured to send a first request to the second network card in the second node, where the first request carries a first converted virtual address; Among them, the second network card is used to send a first message carrying the first conversion virtual address to the first network card in the first node based on the first request; the first network card is used to query the first translation table according to the first conversion virtual address, obtain the first physical address, and access the first physical address; the length of the first conversion virtual address is different from the length of the process virtual address in the first node.

19. A memory access node, characterized in that: The memory access node is a first node, and the memory access node includes a first network card and a first processor; The first processor is configured to communicate with other nodes other than the first node through the first network card; The first network card includes the memory access device according to claim 16.

20. The memory access node according to claim 19, wherein: The first processor includes the memory access device according to claim 17.

21. A memory access node, characterized in that: The memory access node is a second node, and the memory access node includes a second network card and a second processor; The second processor is used to communicate with other nodes outside the second node through the second network card, and the second processor includes the memory access device according to claim 18.

22. A memory access method, characterized in that: The method is performed by a first node, and includes: receiving a first message carrying a first converted virtual address sent by a second node; querying a first translation table according to the first translated virtual address to obtain a first physical address, wherein a length of the first translated virtual address is different from a length of a virtual address of a process in a first node where the first network card is located; Access the first physical address.

23. The memory access method according to claim 22, wherein: Before receiving the first message carrying the first converted virtual address sent by the second node, the method further includes: Allocating the first translated virtual address to the first physical address; Sending the first translated virtual address to the second node; Configure information of the first translation table.

24. A memory access method, characterized in that: The method is performed by the second node, and includes: Sending a first message carrying a first converted virtual address to the first node; The first node is used to query the first translation table according to the first conversion virtual address to obtain the first physical address and to access the first physical address; the length of the first conversion virtual address is different from the length of the process virtual address in the first node.

25. The method according to claim 24, characterized in that The method further comprises: Receive the first converted virtual address sent by the first node.

26. A memory access system, characterized in that: including a first node and a second node; The first node comprises: a first network card and a first processor, the first network card being configured to execute the memory access method according to any one of claims 1 to 11, and the first processor being configured to execute the memory access method according to claim 12 or 13; the second node comprises: a second network card and a second processor, the second processor being configured to execute the memory access method according to claim 14 or 15; Alternatively, the first node is used to execute the memory access method described in claim 22 or 23, and the second node is used to execute the memory access method described in claim 24 or 25.

27. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which is used to implement the memory access method according to any one of claims 1 to 15 and 22 to 25 when running on a computer.

28. A computer program product comprising instructions, characterized in that When the computer program product is run on a computer, it is used to implement the memory access method described in any one of claims 1 to 15 and 22 to 25.

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