Optical computing system with separated memory system

Abstract

Described herein are embodiments of a photonic computing system that includes one or more processors in communication with a split storage system over one or more optical channels. The split memory system includes a plurality of memory cells arranged on a photonic substrate, the photonic substrate including a photonic network that can be programmed to configure which of the memory cells is accessible by each of the processor (s).

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 395,311, filed on August 4, 2022, entitled “COMPUTE AND MEMORY DISAGGREGATION USING RECONFIGURABLE OPTICAL COMMUNICATION SUBSTRATE,” under 35 U.S.C. §119(e), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of the present disclosure relate to an optical computing system that includes one or more processors in communication with one or more separate memory blocks. Each of the separate memory blocks (multiple) may include multiple memory cells interconnected by a photonic network. Background Art

[0004] The storage unit may be a chip containing an integrated circuit capable of storing data. The storage unit may include a random access memory (RAM) or a read-only memory (ROM). For example, the storage unit may be a dynamic RAM (DRAM) chip, a static RAM (SRAM) chip, a programmable ROM (PROM) chip, or an erasable PROM (EPROM). The processor may use the storage unit to store information. For example, the processor may use a RAM chip to temporarily store information (e.g., software application instructions and / or data). For another example, a ROM chip may store firmware for operating the device. Summary of the invention

[0005] Embodiments of a photonic computing system are described herein that include one or more processors communicating with a separate storage system via one or more optical channels. The separate storage system includes a plurality of storage cells arranged on a photonic substrate, the photonic substrate including a photonic network that can be programmed to configure which of the storage cells can be accessed by each of the processor(s).

[0006] Some embodiments provide a photonic computing system. The photonic computing system includes: at least one processor; at least one optical channel; and at least one photonic substrate, which is separate from the at least one processor, the at least one photonic substrate including a plurality of storage units and at least one photonic network for providing the at least one processor with access to the plurality of storage units, wherein: the at least one photonic network communicates with the at least one processor via the at least one optical channel; and the at least one photonic network is programmable to configure which storage unit among the plurality of storage units in the at least one photonic substrate the at least one processor can access via the at least one optical channel.

[0007] Some embodiments provide a method for using a photonic network to perform parallelized data processing using multiple storage units. The photonic network can be programmed to configure which storage unit of the multiple storage units can be accessed by a first processor and a second processor. The photonic network is programmed to allow access to a first storage unit of the multiple storage units by the first processor and to allow access to a second storage unit of the multiple storage units by the second processor. The method includes: programming the photonic network to allow access to the second storage unit by the first processor and to allow access to the first storage unit by the second processor; performing an operation by the first processor using data stored in the second storage unit to obtain an output; and performing an operation by the second processor using data stored in the first storage unit in parallel with the execution of the first processor.

[0008] Some embodiments provide a photonic network disposed on a photonic substrate. The photonic network is accessible via at least one optical channel. The photonic network includes: a plurality of storage units; at least one configurable optical switch for controlling which storage unit of the plurality of storage units is accessible via the at least one optical channel; and at least one electrical / optical (E / O) transceiver for transmitting data to and from the plurality of storage units via the at least one optical channel.

[0009] Some embodiments provide a method of manufacturing a photonic computing system. The method includes manufacturing the photonic computing system to include: at least one processor; at least one optical channel; and at least one photonic substrate, which is separate from the at least one processor, the at least one photonic substrate including a plurality of memory cells and at least one photonic network for connecting the at least one processor to the plurality of memory cells, wherein: the at least one photonic network communicates with the at least one processor via the at least one optical channel; and the at least one photonic network is programmable to configure which memory cell of the plurality of memory cells in the at least one photonic substrate the at least one processor can access via the at least one optical channel.

[0010] The foregoing is a non-limiting summary. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various aspects and embodiments will be described with reference to the following drawings. It should be understood that the drawings are not necessarily drawn to scale. Items appearing in multiple drawings are indicated by the same or similar reference numerals in all drawings in which they appear.

[0012] Figure 1A is an exemplary photonic computing system according to some embodiments of the technology described herein.

[0013] Figure 1B According to some embodiments of the technology described herein Figure 1AThe first programmed configuration of photonic networks in a photonic computing system.

[0014] Figure 1C According to some embodiments of the technology described herein Figure 1A A second programming configuration of a photonic network in a photonic computing system.

[0015] Figure 2A is a side view of a photonic substrate according to some embodiments of the technology described herein.

[0016] Figure 2B According to some embodiments of the technology described herein Figure 2A Top view of the photonic substrate.

[0017] Figure 2C is a side view of another photonic substrate according to some embodiments of the technology described herein.

[0018] Figure 2D is a side view of another photonic substrate according to some embodiments of the technology described herein.

[0019] Figure 3 is an exemplary processor for a photonic computing system according to some embodiments of the technology described herein.

[0020] Figure 4 An exemplary parallelization paradigm is illustrated that may be used by some embodiments of the techniques described herein.

[0021] Figure 5A Virtualization is illustrated that can be performed by a computing system using some embodiments of the techniques described herein.

[0022] Figure 5B Some embodiments of the technology described herein are illustrated. Figure 5A Reallocation of processors and memory to virtual machines.

[0023] Fig. 6A An exemplary photonic computing system according to some embodiments of the techniques described herein is shown.

[0024] Figure 6B According to some embodiments of the technology described herein, Fig. 6A An exemplary set of connections from the fiber optic attachments of a storage tile to the storage controllers of all storage tiles.

[0025] Figure 6C According to some embodiments of the technology described herein, Fig. 6A Another exemplary set of connections from a fiber optic attachment of another storage tile to the storage controllers of all storage tiles.

[0026] Fig. 7ASome embodiments of the technology described herein are shown FIG. 6A to FIG. 6C An exemplary configuration of a photonic network of storage tiles.

[0027] Figure 7B Some embodiments of the technology described herein are shown FIG. 6A to FIG. 6C Another exemplary configuration of a photonic network of storage tiles 604A-604H.

[0028] Figure 8 Some embodiments of the technology described herein are shown Fig. 6A An exemplary configuration of a photonic computing system in which each processor is designated for a different application.

[0029] Fig. 9 An exemplary photonic computing system is shown in which a set of processors can access multiple separate memory pools according to some embodiments of the technology described herein.

[0030] Fig.10 An exemplary photonic computing system is shown in which the memory of the computer system is expanded by separate groups of memory cells according to some embodiments of the technology described herein.

[0031] Fig.11 is an exemplary process for programming a photonic network according to some embodiments of the technology described herein.

[0032] Fig.12 is an exemplary process for parallelizing the execution of a software application according to some embodiments of the techniques described herein.

[0033] Fig.13 is a block diagram of an illustrative computing system that can be used to implement some embodiments of the techniques described herein. DETAILED DESCRIPTION

[0034] Embodiments of a photonic computing system are described herein that include one or more processors communicating with a separate storage system via one or more optical channels. The separate storage system includes a plurality of storage cells arranged on a photonic substrate, the photonic substrate including a photonic network that can be programmed to configure which of the storage cells can be accessed by each of the processor(s).

[0035] Typically, processors need to make a tradeoff between (1) memory capacity and (2) memory bandwidth / latency and resources (e.g., power and space on the chip). This tradeoff often results in limiting memory capacity to maintain target bandwidth / latency, reduce chip size, and reduce power consumption. Conventional high bandwidth memory (HBM) can provide up to 800 gigabytes per second (GB / s) of memory bandwidth, but consumes a lot of power (e.g., about 6 pJ / bit) and requires a lot of space on the chip. HBM memory cells need to be a few millimeters away from the processor (e.g., the compute die) that accesses the HBM memory cells. Conventional HBM only provides densities of up to 48GB in a memory cell (e.g., a stack of one or more memory dies). Size and spacing constraints limit the number of stacks in a chip to only two stacks, i.e., a total of 96GB of HBM. High-speed double data rate (DDR) memory does not require as much space on the chip as HBM and uses less power than HBM. However, DDR provides lower bandwidth (up to 32GB / s) and worse latency than HBM.

[0036] Limiting the processor to a specific set of high-density memories (e.g., HBM and / or DDR) attached requires communication between processors when executing parallelizable applications. Parallelization often requires multiple processors to access a shared set of data. The data thus needs to be transferred between the memories of multiple processors. This reduces the efficiency of parallel execution and creates data redundancy. When the memory storing the data can be accessed by all processors, the processor access to the data can be more efficient because this eliminates the need to transfer data between different memories. Conventional technology to achieve this function involves establishing a multi-chip package that requires several tape-outs, which increases the complexity of managing a variety of different products. Moreover, the constraints of power and regional resources limit the performance of certain applications. This requires more application-specific chip designs.

[0037] Separating the memory from the processor enables the storage unit to be reconfigured to be connected to different processors, which will allow for more efficient parallelization. However, conventional techniques for separating the memory from the processor are high in power, low in bandwidth, and high in latency. Therefore, conventional separate storage systems are limited to separate disk drives and / or solid-state drives because the high power cost of such storage hardware has exceeded 10 pJ / bit. In addition, conventional separate storage systems provide low bandwidth and high latency, making them unsuitable for executing applications that require high bandwidth and low latency.

[0038] In order to solve the above shortcomings in the storage design for processors, the inventors have developed technologies that use photonics to separate memory from processors in computing systems. These technologies allow the density of memory accessible to processors to be increased without sacrificing storage bandwidth. These technologies arrange separate pools of storage cells on a photonic substrate with a photonic network that can be programmed to configure which storage cells can be accessed by each processor in the processor. The processor communicates with the pool of storage cells via one or more optical channels. These technologies can support storage bandwidths greater than 15 terabytes per second (TB / s).

[0039] Some embodiments include a photonic substrate separate from the processor that includes a plurality of memory cells (e.g., a memory stack) and a programmable photonic network. The photonic network can be programmed to different configurations to change which processors are connected to corresponding memory cells in the memory cells. This allows the computing system to use a paradigm to parallelize the execution of operations without relying on transferring data between different memories. The photonic network can be programmed to reconfigure the connection between the memory cells and the processor, thereby reducing or even eliminating the need to transfer data between the memory cells to parallelize the operation. This allows for more efficient parallelization of operations.

[0040] In some embodiments, the programmable photonic network is able to dynamically reconfigure the amount of storage allocated to the processor. In this way, the photonic network can be programmed according to the application execution requirements. For example, an application that requires more storage for execution can allocate more memory from the storage pool, while an application that requires less storage for execution can allocate less memory from the storage pool. Further, the photonic network increases the amount of storage that can be attached to a processor with high bandwidth (e.g., high-density memory) without being constrained by the size and space limitations of conventional HBM. For example, these technologies no longer require that the HBM storage unit be located within millimeters of the processor (e.g., computing die) that accesses the HBM storage unit.

[0041] Some embodiments allow a processor to communicate with one or more groups of storage units via one or more optical channels (e.g., fiber optic cables). The optical channels allow the processor to be separated from the group (or groups) of storage units. Conventional techniques typically require that the processor be arranged on a chip (e.g., a silicon interposer) with high-density storage units (e.g., HBM units), while some embodiments herein allow the processor to be separated from the chip (s) that includes the group (or groups) of storage units. For example, these techniques allow a processor to be connected to a storage unit housed in a package or chassis that is separate from the processor.

[0042] Some embodiments provide a photonic computing system. The photonic computing system includes one or more processors, one or more optical channels, and a photonic substrate separate from the processor(s). The photonic substrate includes multiple storage units and a photonic network for connecting the processor(s) to the storage units. The photonic network communicates with the processor(s) via the optical channel. The photonic network can be programmed to configure which storage unit(s) of the storage units in the photonic substrate the processor(s) can access via the optical channel.

[0043] Some embodiments provide a photonic computing system. The photonic computing system includes: at least one processor; at least one optical channel (e.g., one or more optical fibers); and at least one photonic substrate (e.g., a photonic interposer) separated from the at least one processor, the at least one photonic substrate including a plurality of storage units (e.g., HBM units, SRAM units, DDRSDRAM units) and at least one photonic network for providing at least one processor with access to the plurality of storage units. The at least one photonic network communicates with the at least one processor via the at least one optical channel. The at least one photonic network can be programmed to configure which storage unit among the plurality of storage units in the at least one photonic substrate the at least one processor can access via the at least one optical channel.

[0044] In some embodiments, at least one processor includes a first processor and a second processor; and the first processor and the second processor are configured to process a data set using a plurality of storage units. In some embodiments, at least one photonic network is programmed to allow access to a first storage unit of the plurality of storage units by the first processor and to allow access to a second storage unit of the plurality of storage units by the second processor; and processing the data set includes: performing an operation by the first processor using data stored in the first storage unit to obtain a first output; and storing the first output in the first storage unit. In some embodiments, after storing the first output in the first storage unit, at least one photonic network is programmed to allow access to the first storage unit by the second processor and to allow access to the second storage unit by the first processor; and processing the data set further includes: performing an operation by the first processor using data stored in the second storage unit to obtain a second output; performing an operation by the second processor using the first output stored in the first storage unit to obtain a first result in parallel with the execution of the first processor; storing the second output in the second storage unit; and outputting the first result from the first storage unit. In some embodiments, at least one photonic network is programmed to allow access to a first storage unit by a first processor and to allow access to a second storage unit by a second processor; and processing a data set stored in multiple storage units of at least one photonic network further includes: performing an operation by the first processor using the data stored in the first storage unit to obtain a third output; performing an operation by the second processor using the second output stored in the second storage unit to obtain a second result in parallel with execution of the first processor; storing the third output in the first storage unit; and outputting the second result from the second storage unit.

[0045] In some embodiments, at least one photonic network includes at least one optical switch, and the at least one optical switch can be configured to connect at least one processor to each of a plurality of memory cells or disconnect at least one processor from each of a plurality of memory cells; and the at least one photonic network can be programmed by configuring the at least one optical switch.

[0046] In some embodiments, at a first time, at least one photonic network is programmed to allow access to a first storage unit among a plurality of storage units by at least one processor through at least one optical channel; and at a second time after the first time, at least one photonic network is programmed to: prohibit access to the first storage unit by at least one processor through at least one optical channel; and allow access to a second storage unit among the plurality of storage units by at least one processor through at least one optical channel.

[0047] In some embodiments, at least one processor includes a first processor and a second processor; the plurality of memory units include a first memory unit and a second memory unit; and at least one photonic network is programmed to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor.

[0048] In some embodiments, the at least one photonic substrate further comprises at least one memory controller configured to program the at least one photonic network. In some embodiments, the at least one processor is configured to program the at least one photonic network.

[0049] In some embodiments, at least one processor includes a plurality of processors, the plurality of processors are organized into a plurality of groups of processors; and at least one photonic network is programmed to allow each of the plurality of groups of processors to access a different subset of storage units of the plurality of storage units through at least one optical channel. In some embodiments, each of the plurality of groups of processors and a corresponding subset of storage units in the plurality of storage units accessible by the plurality of processors form a corresponding virtual processor assigned to a corresponding virtual machine. In some embodiments, at least one processor includes a plurality of processors; at least one optical channel includes a plurality of optical channels; and each of the plurality of processors communicates with at least one photonic network through a corresponding optical channel in the plurality of optical channels. In some embodiments, at least one photonic network includes a plurality of photonic networks; at least one photonic substrate includes a plurality of photonic modules, each of the plurality of photonic modules includes: a corresponding photonic network in the plurality of photonic networks; a subset of storage units in the plurality of storage units; and a storage controller. In some embodiments, each of the plurality of processors is connected to a storage controller of the plurality of photonic modules through a corresponding optical channel in the plurality of optical channels.

[0050] In some embodiments, at least one photonic network is programmed with a configuration to allocate storage units among multiple processors based on storage requirements for execution of multiple software applications, wherein the configuration: allows access to a first group of storage units among the multiple storage units by a first processor among the multiple processors that is configured to execute a first software application (e.g., a software application using a machine learning model such as a large language model (LLM), a computer vision model, a software development and testing application, and / or other types of software applications); and allows access to a second group of storage units among the multiple storage units by a second processor among the multiple processors that is configured to execute a second software application (e.g., a software application using a machine learning model such as a large language model (LLM), a computer vision model, a software development and testing application, and / or other types of software applications).

[0051] In some embodiments, at least one photonic substrate comprises a plurality of photonic substrates, each of the plurality of photonic substrates comprising a set of storage units and a corresponding photonic network, wherein: the photonic networks of the plurality of substrates are each programmable to configure which storage unit of the corresponding set of storage units is accessible to at least one processor. In some embodiments, the photonic computing system comprises an optical switch, wherein the optical switch is configurable to provide at least one processor with access to a plurality of storage units distributed across a plurality of the plurality of photonic substrates.

[0052] In some embodiments, at least one photonic substrate includes at least one storage controller; and at least one photonic network includes an optical circuit interconnecting the at least one storage controller with the plurality of storage units. In some embodiments, at least one photonic network includes a plurality of electrical / optical (E / O) transceivers, each of the plurality of E / O transceivers connecting a corresponding storage unit in the plurality of storage units to the optical circuit.

[0053] In some embodiments: at least one photonic substrate includes: at least one storage controller; at least one fiber optic attachment, the at least one fiber optic attachment connected to at least one optical channel; and at least one E / O transceiver; and at least one photonic network includes an optical circuit connecting the at least one storage controller to the at least one fiber optic attachment, wherein the E / O transceiver is configured to convert signals transmitted between the at least one storage controller and the at least one fiber optic attachment. In some embodiments, the at least one photonic network includes a plurality of electrical connections between the at least one storage controller and a plurality of storage units, wherein data signals are transmitted between the at least one storage controller and the plurality of storage units via the plurality of electrical connections.

[0054] Some embodiments provide a photonic network arranged on a photonic substrate. The photonic network is accessible via at least one optical channel. The photonic network includes: a plurality of storage units; at least one configurable optical switch, the at least one configurable optical switch controlling which storage unit of the plurality of storage units is accessible via the at least one optical channel; and at least one electrical / optical (E / O) transceiver, the at least one E / O transceiver for transmitting data to and from the plurality of storage units via the at least one optical channel.

[0055] In some embodiments, at a first time, at least one optical switch is configured to allow access to a first storage unit in the plurality of storage units through at least one optical channel; and at a second time after the first time, at least one optical switch is configured to allow access to a second storage unit in the plurality of storage units through at least one optical channel. In some embodiments, at the second time, at least one optical switch is programmed to prohibit access to the second storage unit through at least one optical channel.

[0056] In some embodiments, the photonic network further comprises a storage controller, wherein the at least one optical switch is configurable by the storage controller. In some embodiments, the photonic network comprises an optical circuit, the optical circuit comprising at least one configurable optical switch. In some embodiments: the at least one E / O transceiver comprises a plurality of E / O transceivers connected to corresponding storage units in the plurality of storage units; and the optical circuit connects the storage controller to the plurality of storage units through the plurality of E / O transceivers. In some embodiments, the photonic network further comprises an optical fiber attachment, wherein: the optical circuit connects the storage controller to the optical fiber attachment through the at least one E / O transceiver.

[0057] Because the technology described herein is not limited to any particular implementation, it can be implemented in any of many ways. The examples of implementation details provided herein are for illustrative purposes only. Also, because the various aspects of the technology described herein are not limited to the use of any particular technology or combination of technologies, the technology disclosed herein can be used alone or in any suitable combination.

[0058] Figure 1A is an exemplary photonic computing system according to some embodiments of the technology described herein. The photonic computing system includes processors 100A, 100B, a photonic substrate 102, and a group of one or more optical channels 112A, 112B, and the respective processors 100A, 100B are connected to the photonic substrate 102 through the optical channels 112A, 112B. The processors 100A, 100B can be configured to access a storage unit 104 arranged on the photonic substrate 102 through the respective groups of optical channels 112A, 112B.

[0059] Each processor in processors 100A, 100B can be any suitable processor. In some embodiments, the processor may include a central processing unit (CPU) including logic circuits for executing instructions. The CPU may be configured to perform arithmetic, logic, and input / output (I / O) operations. In some embodiments, the processor may include a graphics processing unit (GPU). The GPU may be configured to perform graphics processing. For example, the GPU may perform image processing operations. In some embodiments, the processor may include a neural processing unit (NPU), which is configured to perform neural network processing. For example, the NPU may use the weights of a neural network model to process the input to the neural network model to determine the output of the neural network model for the input. In some embodiments, the processor may include an analog processor. For example, the analog processor may be a photon processor. In U.S. Pat. No. 11,218,227, an exemplary photon processor that can be used in some embodiments is described, which is incorporated herein by reference.

[0060] In some embodiments, one or more processors in processors 100A, 100B may be multi-core processors. For example, a processor may have 2, 4, 6, 8, 10, or 12 cores. A multi-core processor may be configured to process multiple sets of instructions simultaneously. In some embodiments, each processor in processors 100A, 100B may be a virtualized processor core (e.g., vCPU).

[0061] like Figure 1A As shown, the processors 100A, 100B include corresponding optical interfaces 110A, 110B, and the processors 100A, 100B can transmit and / or receive data in the form of optical transmission through the optical interfaces 110A, 110B. In some embodiments, each of the optical interfaces 110A, 110B may include an optical fiber attachment for connecting to a group of one or more optical fibers. In some embodiments, (multiple) optical fibers can be vertically attached through the use of vertical grating couplers and lenses. In some embodiments, (multiple) optical fibers can be attached through edge attachments using edge couplers, V-grooves, or attenuation couplers. In some embodiments, (multiple) optical fibers can be plugged and unplugged through the use of pluggable glass modules. The processors 100A, 100B can each transmit and receive optical transmissions through a group of (multiple) optical fibers.

[0062] Figure 1A The photonic computing system includes a photonic substrate 102. The photonic substrate includes storage units 104A, 104B, 104C, 104D, 104E, 104F, 104G, 104H and two photonic networks 108A, 108B. The first group of storage units 104A, 104B, 104C, 104D can be accessed through the photonic network 108A. The second group of storage units 104E, 104F, 104G, 104H can be accessed through the photonic network 108B. Examples of storage units include HBM, DRAM, non-volatile random access memory (NVRAM) and / or NAND flash memory. The photonic substrate 102 also includes electrical / optical (E / O) transceivers 114A, 114B and optical interfaces 110C, 110D. In some embodiments, the photonic substrate 102 includes memory controllers 106A, 106B connected to respective photonic networks 108A, 108B. The memory controllers 106A, 106B may be configured to program the respective photonic networks to select one or more memory cells for connection to each processor to enable read and write operations.

[0063] It should be noted that in some embodiments, a common photonic network across all storage units may be used, rather than Figure 1A. A common storage controller may program the common photonic network. Further, in some embodiments, the photonic substrate 102 may not include the storage controllers 106A, 106B. In such embodiments, a storage controller external to the photonic substrate 102 may program the photonic network(s). One or more of the processors 100A and 100B may act as an external storage controller.

[0064] In some embodiments, the photonic network may include multiple photonic modules. Each photonic module may be uniquely associated with a specific storage unit (or a specific storage unit subgroup), and may be programmed to allow or prohibit access to the storage unit or storage unit subgroup. For example, each photonic module may include one or more programmable photonic switches, one or more programmable photonic switches configured to be connected to or disconnected from a corresponding storage unit or storage unit subgroup. In some embodiments, the photonic modules forming the photonic substrate 102 may be manufactured using micromachining technology (e.g., complementary metal oxide semiconductor (CMOS) micromachining technology). For example, a manufacturing technique based on step and repeat lithography may be used to pattern the photonic modules into multiple copies of the template photonic modules. A detailed description of the photonic modules is provided in U.S. Patent No. 11,036,002, the entire contents of which are incorporated herein by reference.

[0065] In some embodiments, each of the photonic networks 108A, 108B may be a programmable photonic network. Each of the photonic networks 108A, 108B may be programmable to configure which memory cells of the memory cells 104A-104H are accessible by each of the processors 100A, 100B. For example, when the photonic network 108A is programmed to a specific configuration, it may provide the processor 100A with access to one or more of the memory cells 104A, 104B, 104C, 104D, and / or provide the processor 100B with access to one or more of the memory cells 104A, 104B, 104C, 104D. For another example, when the photonic network 108B is programmed into a specific configuration, it can provide the processor 100A with access to one or more of the memory cells 104E, 104F, 104G, 104H, and / or provide the processor 100B with access to one or more of the memory cells 104E, 104F, 104G, 104H. Thus, each of the photonic networks 108A, 108B can be programmed to selectively place the processors 100A, 100B in communication with a corresponding subset of the memory cells 104A-104H.

[0066] In some embodiments, the configuration of each photonic network in the photonic networks 108A, 108B can be dynamic. In this way, the photonic networks 108A, 108B can be programmed multiple times. For example, the photonic networks 108A, 108B can be programmed to provide the processors 100A, 100B to different storage units in the storage units 104A-104H during the execution of instructions. In some embodiments, the photonic networks 108A, 108B can be programmed as part of performing parallelized operations. Exemplary techniques for parallel execution of execution operations are described herein. In some embodiments, the photonic networks 108A, 108B can be programmed to allocate memory to a virtual machine (e.g., a virtual CPU). For example, memory can be allocated to a virtual machine based on the requirements of the application to be executed by the virtual machine.

[0067] like Figure 1A As shown in the example, in some embodiments, the photonic network can interconnect storage units and storage controllers in optical circuits. For example, the photonic network 108A may include optical circuits that interconnect storage units 104A, 104B, 104C, 104D and storage controller 106A. For another example, the photonic network 108B may include optical circuits that interconnect storage units 104E, 104F, 104G, 104H and storage controller 106B. In such an embodiment, each storage unit can be connected to the photonic network via a corresponding E / O transceiver for converting data read and write signals between electrical signals and optical signals. For example, an E / O transceiver can be connected to an optical circuit of the photonic network, and the E / O transceiver can transmit and receive optical signals through the optical circuit. Although Figure 1A The exemplary embodiment of FIG. 1 shows a single E / O transceiver associated with the photonic network, but in some embodiments, the photonic substrate 102 may include multiple E / O transceivers, each E / O transceiver being associated with a storage unit.

[0068] In some embodiments, the photonic network may include optical circuits connecting the storage controller to an optical interface (e.g., a fiber optic attachment) and electrical connections between the storage controller and the storage units. For example, the storage controller 106A may be connected to the fiber optic attachment via an optical circuit and may be connected to the storage units 104A, 104B, 104C, 104D via an electrical connection. The storage controller 106A may transmit data signals (e.g., read and write signals) to and receive data signals from the storage units 104A, 104B, 104C, 104D via the electrical connection. In such an embodiment, the E / O transceiver may convert data signals to / from the storage controller between electrical signals and optical signals. For example, the E / O transceiver 114A may convert data signals to / from the storage controller 106A between electrical signals and optical signals.

[0069] Figure 1B is a first programmed configuration 120A of the photonic network 108A, 108B according to some embodiments of the technology described herein. For example, Figure 1B Configuration 120A may be used to execute one or more instructions by each of processors 100A, 100B. In a first programming configuration 120A, photonic network 108A is programmed to provide processor 100A with access to memory units 140A, 140C, and to provide processor 100B with access to memory units 104B, 104D. Photonic network 108B is programmed to provide processor 100A with access to memory unit 104E, and to provide processor 100B with access to memory units 104F, 104G, 104H. Figure 1B As shown, processor 104A and all memory cells accessible to it in configuration 120A are shaded horizontally. Processor 100B and all memory cells accessible to it in configuration 120A are shaded diagonally.

[0070] Figure 1C is a second programmed configuration 120B of the photonic network 108A, 108B according to some embodiments of the technology described herein. For example, Figure 1C The configuration 120B can be used in Figure 1B The one or more instructions are then executed by each of the processors 100A, 100B in the second programming configuration 120A. In the second programming configuration 120B, the photonic network 108A is programmed to provide the processor 100A with access to the memory cells 104A, 104B, 104C, 104D. The photonic network 108B is programmed to provide the processor 100A with access to the memory cells 104D, 104E and to provide the processor 100B with access to the memory cells 104F, 104G. Figure 1B As shown, processor 104A and all memory cells accessible to it in configuration 120A are shaded horizontally. Processor 100B and all memory cells accessible to it in configuration 120A are shaded diagonally.

[0071] In some embodiments, each photonic network in the photonic networks 108A, 108B includes one or more photonic switches. Each photonic network in the photonic networks 108A, 108B can be programmed by configuring one or more photonic switches of the photonic network. Examples of optical switches that can be included in each photonic network in the photonic networks 108A, 108B include Mach-Zehnder interferometers, optical resonators, multimode interference (MMI) waveguides, arrayed waveguide gratings (AWGs), thermo-optic switches, acousto-optic switches, magneto-optic switches, micro-electromechanical switches (MEMS) optical switches, nonlinear optical switches, liquid crystal switches, piezoelectric beam steering switches, grating switches, dispersion switches, and / or other suitable optical switches. In some embodiments, one or more optical switches of the photonic network can be implemented in an optical circuit. One or more optical switches can be configured to control a path in an optical circuit. In some embodiments, one or more optical switches can be integrated into the photonic substrate 102.

[0072] In an embodiment where the photonic substrate 102 includes storage controllers 106A, 106B, the photonic networks 108A, 108B may be programmed by the respective storage controllers 106A, 106B. The storage controller 106A may be configured to program the photonic network 108A, and the storage controller 106B may be configured to program the photonic network 108B. In some embodiments, each of the storage controllers 106A, 106B may be configured to program the respective photonic network in the photonic network 108A, 108B by configuring one or more switches of the photonic network. The storage controller 106A may be connected to an optical circuit including an optical switch that can be controlled by the storage controller 106A. The storage controller 106A may configure the optical switch in the optical circuit to control which storage unit 104A, 104B, 104C, 104D can be accessed by the processor 100A through the optical circuit. The storage controller 106B may be connected to an optical circuit including an optical switch that can be controlled by the storage controller 106B. The memory controller 106A may configure an optical switch in the optical circuit to control which memory cells among the memory cells 104E, 104F, 104G, 104H can be accessed by the processor 100B through the optical circuit.

[0073] In some embodiments, the photonic networks 108A, 108B may be programmed by the processors 100A, 100B. In some embodiments, the photonic networks 108A, 108B may be programmed by the processors 100A, 100B simultaneously. The optical switches of the photonic networks 108A, 108B may be configured by the processors 100A, 100B to program the photonic networks 108A, 108B. For example, in embodiments where the photonic substrate 102 does not include the storage controllers 106A, 106B, the photonic networks 108A, 108B may be programmed by the processors 100A, 100B. Although in Figure 1A Although not illustrated in the example of FIG. 1 , in some embodiments, the photonic networks 108A, 108B can be programmed by a separate host. For example, the host can be a CPU. For example, the CPU can access the configuration of some or all of the photonic networks in the photonic substrate 102.

[0074] In some embodiments, each of the E / O transceivers 114A, 114B may include an optoelectronic converter such as an optical modulator and an optoelectronic converter such as an optical receiver. The optoelectronic converter may be configured to convert an electrical data signal generated from reading a storage unit (e.g., by a storage controller) into an optical signal that can be transmitted to a processor through an optical channel. The optoelectronic converter may be configured to convert an optical signal received from a processor through an optical channel into an electrical data signal for storing data in a storage unit (e.g., by a storage controller). In some embodiments, the E / O transceiver may include a shim that converts one electronic protocol to another electronic protocol. For example, a shim may convert a signal / protocol used between a storage controller and a processor into one or more SerDes signals. These SerDes signals may then drive a photon transmission (TX) component within a large photon interposer. The conversion may be just a direct analog signal conversion or a more complex data conversion in the digital domain. For example, the bandwidth of each pin of HBM3 is 9.2Gb / s, but the optical link may run at a higher speed (50-100Gb / s per signal). Therefore, multiple HBM3 pin signals can be serialized into a single optical signal, which can then be deserialized at the receiver side.

[0075] In some embodiments, each of the optical interfaces 110A, 110B may provide an interface for a corresponding optical channel 112A, 112B. In some embodiments, the optical channels 112A, 112B each include a set of one or more optical fibers. The optical interfaces 110A, 110B may each include a fiber optic attachment, which may include one or more ports, and a set (multiple) of optical fibers may be connected to an E / O transceiver through the one or more ports. The fiber optic attachment may include a fiber optic coupler (e.g., an out-of-plane coupler or an edge coupler) capable of coupling to an optical channel. The fiber optic coupler may allow the storage controller to communicate with the processor via an optical channel.

[0076] In some embodiments, each of the storage controllers 106A, 106B may each include digital circuits for controlling the input and output of data from the storage cells. In some embodiments, each of the storage controllers 106A, 106B may be configured to control access to corresponding groups of storage cells (e.g., for on-chip SRAM storage cells). For example, the storage controller 106A may read data from the storage cells 104A, 104B, 104C, 104D requested by the processors 100A, 100B, and write data transmitted from the processors 100A, 100B to the storage cells 104A, 104B, 104C, 104D. In some embodiments, the storage controllers 106A, 106B may be integrated storage controllers integrated with corresponding groups of storage cells on the chip. In some embodiments, the storage controllers 106A, 106B may be separate from the storage cells 104A-104H (e.g., for DRAM, NVRAM, and flash memory cells). Further, in some embodiments, the storage controllers 106A, 106B may be integrally fabricated with the photonic substrate 102, the E / O transceivers 114A, 114B, the photonic networks 108A, 108B, and the storage units 104A-104H.

[0077] In some embodiments, each of the storage controllers 106A, 106B may be configured to manage the allocation of storage units to the processors 100A, 100B. For example, the storage controller may be configured to allocate memory to the processor 100A based on the process (e.g., software application) being executed by the processor. The storage controller may be configured to determine the storage resources required for the process and allocate storage units to the processor 100A accordingly. In some embodiments, the storage controllers 106A, 106B may be configured to determine the allocation of storage units to the processors 100A, 100B based on the parallel programming model being used by the process. The storage controllers 106A, 106B may allocate storage units to the processors 100A, 100B according to the parallel programming model to enable parallel execution of the process. The storage controllers 106A, 106B may be configured to program the corresponding photonic networks 108A, 108B based on the determined storage allocation.

[0078] like Figure 1A As shown in the example of, in some embodiments, processors 100A, 100B access storage units 104A-104H through corresponding optical channels 112A, 112B. In some embodiments, optical channels can provide paths for optical transmission. In some embodiments, optical channels can include one or more optical fibers. For example, each of the (multiple) optical fibers can be a strand of glass, plastic, or other suitable material for transmitting light. A plurality of such strands can be bundled into a group of optical fibers (e.g., bundled into a fiber optic cable). In some embodiments, optical channels can transmit data at a rate of at least 1-5, 5-10, 10-15, 15-20, 20-25, or 25-30 terabytes per second (TB / s). For example, an optical channel can transmit data between a processor and a photonic network at a rate of at least 15TB / s. In some embodiments, each optical channel can carry one or more optical signals, for example, by using wavelength division multiplexing or polarization multiplexing schemes to carry one or more optical signals.

[0079] In some embodiments, error correction can be used to allow for higher bandwidth photonic communications. Error correction can be performed on data transmissions to and / or from a storage unit through a photonic network. For example, error correction can be performed using an error correction code (ECC). In some embodiments, a storage controller can be configured to perform error correction on data transmissions to and / or from a storage unit. In some embodiments, processors 100A, 100B can be configured to perform error correction on data received from a storage unit. The use of error correction can allow for higher bandwidth photonic communications, but at the expense of increased latency caused by the performance of the error correction.

[0080] Figure 2A is a side view of a photonic substrate 200 according to some embodiments of the technology described herein. Figure 2B is a top view of the photon substrate 200. Figure 2B As shown, the photonic substrate 200 includes a storage controller 204, a storage stack 206A, a storage stack 206B, a storage stack 206C, and a storage stack 206D. For example, Figure 2A The photonic substrate 200 shown in FIG. 2 may be a reference to Figures 1A to 1C The storage stacks 206A, 206B, 206C, 206D may be Figures 1A to 1C Storage units 104A, 104B, 104C, and 104D.

[0081] like Figure 2A As shown, the optical fiber attachment 202, the E / O transceiver 210, the storage controller 204, the storage stack 206A, and the storage stack are arranged on the photonic substrate 200. The photonic substrate 200 further includes an integrated optical circuit 212, which can form a photonic network (e.g., the photonic network 108A). The optical circuit 212 may include an integrated optical switch, which can be configured to program the photonic network. Figure 2A As shown, optical circuit 212 connects fiber optic attachment 202 to E / O transceiver 210. Thus, optical signals may be transmitted to and from E / O transceiver 210 via optical circuit 212.

[0082] In some embodiments, the E / O transceiver 210 may include the use of wavelength division multiplexing (WDM), in which multiple signals (each at a different optical wavelength) are used to increase the transmission bandwidth in a single optical waveguide or optical fiber. Some embodiments may use dense WDM. In dense WDM, the wavelengths may be spaced apart by a spacing of 100-200GHz. Some embodiments may use sparse WDM. In sparse WDM, the wavelengths may be spaced apart by>10nm. In summary, WDM reduces the number of optical fibers that need to be attached to the photonic substrate 200.

[0083] like Figure 2AAs shown, the photonic substrate includes an electrical connection 214, and electrical signals can be transmitted between the E / O transceiver 210 and the storage controller 204 and between the storage controller 204 and the storage stacks 206A, 206B, 206C, 206D through the electrical connection 214. The electrical connection 214 can be configured to transmit electrical data signals generated from reading and writing the storage stacks 206A, 206B, 206C, 206D. For example, the electrical connection 214 can be used by the storage controller 204 to obtain an electrical data signal from the read data from the storage stacks 206A, 206B, 206C, 206D, and transmit the electrical data signal to the E / O transceiver 210 (e.g., for transmitting a corresponding optical signal to a processor separate from the photonic substrate 200). For another example, electrical connection 214 may be used by storage controller 204 to obtain electrical data signals from E / O transceiver 210 corresponding to optical signals transmitted from an external processor, and transmit the electrical data signals to storage stacks 206A, 206B, 206C, 206D to write data into the memory.

[0084] In some embodiments, each of the storage stacks 206A, 206B, 206C, 206D may include a stack of dies. For example, each of the storage stacks 206A, 206B, 206C, 206D may be a stack of 3 dies, but the number of stacked dies may also be other numbers. The stack of dies may be mounted to the photonic substrate 200. In some embodiments, the stack of dies may form a storage unit. In some embodiments, each of the storage stacks 206A, 206B, 206C, 206D may be any suitable type of memory. For example, each storage stack may be HBM, DDR, DDRAM, SRAM, DDR SDRAM, or other suitable types of memory.

[0085] In some embodiments, the memory controller 204 may be another die mounted to the photonic substrate 200. Figures 1A to 1C As described, the storage controller 204 may be configured to configure the optical switch of the optical circuit 212 to configure which storage stack of the storage stacks 206A, 206B, 206C, 206D can be accessed by the external processor. In some embodiments, the optical circuit 212 may be configured to allow one or more external processors to access a particular storage stack. In some embodiments, the optical circuit 212 may be configured to allow only one external processor to access a particular storage stack at a time.

[0086] exist Figure 2A In the example shown, the communication between the fiber optic attachment 202 and the E / O transceiver 210 is performed photonically, while the communication between the E / O transceiver 210 and the storage stack 206 is performed electrically. In other examples, as described below in conjunction with Figure 2C to Figure 2D As discussed, fiber optic accessories can be photonically coupled to the storage stack, and optical switch modules can be used to route the optical signals.

[0087] Figure 2C 2 is a side view of another photonic substrate 220 according to some embodiments of the technology described herein. Figure 2C As shown, the photonic substrate 220 includes a storage controller 204, storage stacks 206A, 206B. For example, Figure 2C The photonic substrate 220 shown may be a Figures 1A to 1C The photonic substrate 220 may include a portion of the photonic substrate 102 depicted in FIG. 20. The storage stacks 206A, 206B may be storage cells 104A, 104B. The photonic substrate 220 may include Figure 2C Other storage stacks not shown (eg, storage stacks 206C, 206D).

[0088] exist Figure 2C In an exemplary embodiment of the present invention, the photonic substrate 220 includes a photonic network that includes an optical circuit 222 that provides an optical channel for optical transmission to and / or from the storage stacks 206A, 206B. The optical circuit 222 can be connected to the storage stack of the photonic substrate 220. The optical circuit 222 includes optical switch modules 224A, 224B, which can be configured to control which storage stack of the storage stacks 206A, 206B is accessible (e.g., accessed by a processor). The storage controller 204 can be configured to program the photonic network by configuring the optical switch modules 224A, 224B. The optical switch modules 224A, 224B are connected to the corresponding storage stacks 206A, 206B via corresponding electrical connections 230A, 230B. The electrical connections 230A, 230B can, for example, include conductive materials (e.g., metal wiring).

[0089] Figure 2CAn exemplary assembly of an optical module is shown. As shown in the box expanded from the optical module 224A, the optical module 224A includes an optical switch 226. An exemplary optical switch is described herein. The optical module 224A further includes an E / O transceiver 228 for converting between optical signals and electrical signals. When the optical switch 226 is configured to allow access to the storage stack 206A, the E / O transceiver 228 can be configured to convert an optical signal received through the optical circuit 222 (e.g., through an optical fiber attachment) into an electrical signal that can be transmitted through the electrical connection 230A. For example, the E / O transceiver 228 can transmit an optical data signal as an electrical data signal (e.g., for writing data to the storage stack 206A). The E / O transceiver 228 can further be configured to convert an electrical signal received through the electrical connection 230A into an optical signal that can be transmitted through the optical circuit 222. For example, the E / O transceiver 228 may convert electrical data signals obtained from read data from the storage stack 206A into optical data signals transmitted through the optical circuit 222 .

[0090] Figure 2D 2 is a side view of another photonic substrate 230 according to some embodiments of the technology described herein. Figure 2D As shown, the photonic substrate 230 includes storage stacks 206A, 206B. For example, Figure 2D The photonic substrate 230 shown may be a Figures 1A to 1C The photonic substrate 230 may include a portion of the photonic substrate 102 depicted in FIG. 2 . The storage stacks 206A, 206B may be storage cells 104A, 104B. The photonic substrate 230 may include Figure 2D Other storage stacks not shown (eg, storage stacks 206C, 206D).

[0091] exist Figure 2D In an exemplary embodiment of the present invention, the photonic substrate 230 includes a photonic network that includes an optical circuit 222 that provides an optical channel for optical transmission to and / or from the storage stacks 206A, 206B. The optical circuit 222 can be connected to the storage stack of the photonic substrate 220. The optical circuit 222 includes optical switch modules 224A, 224B, which can be configured to control which storage stack of the storage stacks 206A, 206B is accessible (e.g., accessed by a processor). The storage controller 204 can be configured to program the photonic network by configuring the optical switch modules 224A, 224B. The optical switch modules 224A, 224B are connected to the corresponding storage stacks 206A, 206B via corresponding electrical connections 230A, 230B. The electrical connections 230A, 230B can, for example, include conductive materials (e.g., metal wiring).

[0092] like Figure 2DAs shown in the exemplary embodiment of the present invention, the photonic substrate 230 does not include a storage controller. In such an embodiment, the photonic network including the optical circuit 222 can be programmed by an external processor (e.g., an external storage controller or other processor connected to the photonic substrate 230). The external processor can program the photonic network by configuring the optical switches of the optical switch modules 224A, 224B. The external processor can transmit configuration instructions (e.g., transmit the configuration instructions via an optical channel), which are transmitted to the optical switch modules 224A, 224B via the optical circuit 222. For example, the configuration instructions can be included as a prefix and / or suffix of the data read and / or write signals.

[0093] Figure 3 is an exemplary processor 300 of a photonic computing system according to some embodiments of the technology described herein. For example, the processor 300 may be the processor 300 of the photonic computing system described herein. Figures 1A to 1C One of the processors 100A and 100B described above. Figure 3 As shown, processor 300 includes one or more computing cores 302 , static RAM (SRAM) 304 , E / O transceiver 308 , and optional DDR or HBM 306 .

[0094] In some embodiments, the computing core(s) 302 may include one or more CPUs, GPUs, NPUs, photonic processors, and / or other computing cores. The SRAM 304 may be used by the computing core(s) 302 to execute instructions (e.g., as part of executing a software application). For example, the SRAM 304 may store instructions and / or data for execution by the computing core(s) 302.

[0095] In some embodiments, the processor 300 may include DDR and / or HBM 306. For example, the processor 300 may execute data-intensive applications, thereby using DDR and / or HBM 306. For example, the processor 300 may be used to execute applications to train deep learning models and / or use them to perform reasoning. Deep learning models often use a large number of parameters (e.g., millions of weights and / or activations), thereby requiring additional storage capacity for the processor 300. For another example, the processor 300 may be used for graphics processing. Graphics processing may involve processing consecutive frames of thousands of pixels, thereby requiring additional storage capacity.

[0096] Figure 4 An exemplary parallelization paradigm that can be used by some embodiments of the technology described herein is illustrated. For example, Figure 4 The parallelization example can be referenced in this paper Figures 1A to 1C The photonic computing system described uses. Figure 4 In the example, the photonic computing system performs the process fB (f A (x i )), where f A is an application program to be executed by the first processor (eg, processor 100A), and f B is an application program to be executed by the second processor (eg, processor 100B). i represents the i-th data point to be provided as input. Application f A and f B Each application in can include one or more operations.

[0097] Execution of the process begins at stage 402, where input x1 is stored in storage unit 102A, and input x2 is stored in storage unit 102B. In some embodiments, inputs x1 and x2 may be loaded into respective storage units 104A, 104B in parallel. Processor 100A then executes f A (x1) and stores the result in storage unit 104A.

[0098] Next, at stage 404, the photonic network 108A is programmed to provide access to the memory unit 104B to the first processor 100A and to provide access to the memory unit 104A to the second processor 100B. The first processor 100A executes f using the input x2 stored in the memory unit 104B. A (x2) and stores the result in the storage unit 104B. In parallel with the execution of the first processor 100A, the second processor 100B uses the f stored in the storage unit 104A. A (x1) to perform f B (f A (x1)) and stores the result in storage unit 104A.

[0099] Next, at stage 406, the execution f is output from storage unit 104A. B (f A (x1)). Photonic network 108A is programmed to provide processor 104B with access to memory unit 104B, which currently stores the process f executed in stage 404. A Processor 104B executes process f B (f A (x2)) and stores the result in storage unit 104B.

[0100] Next, at stage 408, the execution process f stored in the storage unit 104B is output from the storage unit 104B. B (f AIn some embodiments, a subsequent pair of inputs (eg, x3 and x4) may be loaded into storage units 104A, 104B, and the execution process of stages 402 to 408 may be performed again.

[0101] exist Figure 4 In the parallelization paradigm illustrated by the example of , the execution of two applications is parallelized by programming the photonic network to dynamically configure which processors can access storage units through the photonic network. Therefore, the input and output data for each application executed by the corresponding processor resides in a single storage location (e.g., one or more storage units). Unlike the conventional parallelization paradigm, the act of copying and transferring data between storage locations can be omitted. As a result, no communication is required between storage units. Further, there is no need to allocate memory for data replication. Instead, both storage units are used for the execution of the application. In addition, because there is only a single copy of each input and the result of the (multiple) applications executed using the input, consistency is automatically maintained in the parallelization paradigm.

[0102] Figure 5A The present invention illustrates virtualization that can be performed by a computing system using some embodiments of the techniques described herein. Figure 5A As shown, the virtualization system 500 determines the allocation of processors and corresponding groups of storage units for virtual machines 506A, 506B, 506C. In some embodiments, the virtualization system 500 can be configured to use a virtual machine management software application to allocate processing power and memory to the virtual machines 506A, 506B, 506C. For example, the virtualization system 500 can use VMWare, Citrix Virtual Apps & Desktops, or another suitable virtual machine management software application.

[0103] Figure 5A The allocation can be performed by programming one or more photonic networks to allocate a set of memory cells to a set of processors. This article describes exemplary techniques for programming a photonic network to allocate (multiple) memory cells to (multiple) processors. Figure 5A In the example, (multiple) photonic networks are programmed to: (1) allocate access to storage units 504A, 504B, 504C, 504D, 504E, 504F, 504G, 504H to processors 502A, 502B, 502E, 502F of virtual machine 506A; (2) allocate access to storage units 504I, 504J, 504K, 504L to processors 502C and 502G of virtual machine 506B; (3) allocate access to storage units 504M, 504N, 504O, 504P to processors 502D and 502H of virtual machine 506C.

[0104] In some embodiments, the virtualization system 500 can be configured to assign virtual machines 506A, 506B, 506C to different users. This assignment can allow multiple different users to use virtual machines executed by a shared set of processing and storage resources. By programming the photonic network to grant each of the virtual machines 506A, 506B, 506C access to a set of storage units, the virtual machines can be configured for the respective users. In some embodiments, the photonic network can be dynamically reprogrammed during the execution of the virtual machines 506A, 506B, 506C to reallocate storage resources (e.g., based on changes in the storage requirements of the virtual machines 506A, 506B, 506C).

[0105] Figure 5B Illustrate some embodiments of the technology described herein Figure 5A In some embodiments, the virtualization system 500 can be configured to reallocate resources (e.g., distribute computing resources (e.g., processing power and storage) and / or balance loads between virtual machines 506A, 506B, 506C based on the requirements of the applications being executed by the virtual machines 506A, 506B, 506C).

[0106] In some embodiments, the reallocation may be performed by programming the photonic network(s) to a different configuration. The virtualization system 500 may be configured to determine the reallocation and cause the photonic network(s) to be programmed based on the reallocation. For example, the storage controller(s) associated with the photonic network(s) may program the photonic network(s) to a new configuration based on the reallocation determined by the virtualization system 500. Figure 5B In the allocation, (multiple) photonic networks are programmed to: (1) allocate access to storage units 504A, 504B, 504C, and 504D to processors 502A, 502B, 502E, and 502F of virtual machine 506A; 2) allocate access to storage units 504I and 504J to processor 502G of virtual machine 506B; and (3) allocate access to storage units 504E, 504F, 504G, 504H, 504K, 504L, 504M, 504N, 504O, and 504P to processors 502C, 502D, and 502H of virtual machine 506C.

[0107] Fig. 6A An exemplary photonic computing system 600 is shown according to some embodiments of the techniques described herein. Fig. 6A As shown, the photonic computing system includes processors 602A, 602B, 602C connected to a photonic substrate including a photonic module. Fig. 6AIn the example of , the plurality of photonic modules are storage tiles 604A, 604B, 604C, 604D, 604E, 604F, 604G, 604H. The processors 602A, 602B, 602C are each connected to the photonic substrate via a respective optical channel 606A, 606B, 606C. Each of the optical channels 606A, 606B, 606C is connected to an interface (e.g., an optical fiber attachment) of a respective storage tile. As indicated by the three dots below the processors 602A, 602B, 602C, in some embodiments, the photonic computing system 600 may include additional processors connected to the photonic substrate.

[0108] like Fig. 6A As shown, each of the memory tiles 604A, 604B, 604C, 604D, 604E, 604F, 604G, 604H includes a set of HBM memory cells. Each tile has four HBM memory cells. Each tile can include a photonic network that can be programmed (e.g., by its corresponding memory controller) to configure which processor of the processors 602A, 602B, 602C can access each of its HBM memory cells (e.g., by configuring optical switches).

[0109] Figure 6B An exemplary set of connections 608A from a fiber optic attachment of a storage tile 604A to a storage controller of all storage tiles 604A-604H is shown in accordance with some embodiments of the techniques described herein. For example, the set of connections 608A may be optical connections connected to an E / O transceiver associated with a storage controller (e.g., which are co-located on a storage tile of the storage controller). As another example, the set of connections 608A may be electrical connections from an E / O transceiver of the storage tile 604A to the storage controller. Figure 6B As shown, connection 608A allows processor 602A to communicate with the storage controller of each tile via optical channel 606A. Thus, the photonic network of each storage tile in storage tiles 604A-604H can be programmed (e.g., by the storage controller of the tile) to provide processor 602A with access to the storage unit of the tile.

[0110] Figure 6C An exemplary set of connections 608B is shown from a fiber optic attachment of a storage tile 604C to a storage controller of all storage tiles 604A-604H in accordance with some embodiments of the techniques described herein. For example, the set of connections 608B may be optical connections connected to an E / O transceiver associated with the storage controller (e.g., which are co-located on a storage tile of the storage controller). As another example, the set of connections 608B may be electrical connections from an E / O transceiver of a storage tile 604B to the storage controller. Figure 6CAs shown, connection 608B allows processor 602B to communicate with the storage controller of each tile via optical channel 606B. Thus, the photonic network of each storage tile in storage tiles 604A-604H can be programmed (e.g., by the storage controller of the tile) to provide processor 602A with access to the storage unit of the tile.

[0111] Fig. 7A Some embodiments of the technology described herein are shown FIG. 6A to FIG. 6C An exemplary configuration of a photonic network of storage tiles 604A-604H. Fig. 7A As shown, the photonic network of each storage tile in the storage tiles 604A-604H is programmed to allow access to the HBM storage cells of the tile by the processor 602A. The processor 602A may be configured to Figure 6B Each of the HBM memory cells is accessed by the connections illustrated in FIG.

[0112] Figure 7B Some embodiments of the technology described herein are shown FIG. 6A to FIG. 6C Another exemplary configuration of a photonic network of storage tiles 604A-604H. An exemplary configuration of a photonic network may be Fig. 7A Programming is performed after the configuration of Figure 7B As shown, the photonic network of each storage tile in the storage tiles 604A-604H is programmed to allow access to the HBM storage cells of the tile by the processor 602B. The processor 602B may be configured to Figure 6C , and access each HBM storage unit in the HBM storage unit by using the connection illustrated in . In some embodiments, the processor 602A may no longer access the HBM storage unit. In some embodiments, the processor 602A may access the HBM storage unit simultaneously with the processor 602B.

[0113] Figure 8 Some embodiments of the technology described herein are shown Fig. 6A An exemplary configuration 800 of a photonic computing system, wherein each of processors 602A, 602B, 602C is designated for a different application. Figure 8 As shown in the example of FIG. 8 , processor 602A is configured to execute a large language model (LLM) application 802A, processor 602B is configured to execute a computer vision application 802B, and processor 602C is configured to execute a development and testing application 802C. Figure 8As shown, each of the applications 802A, 802B, 802C is allocated a corresponding set of memory cells from memory tiles 604A-604H. LLM application 802A is allocated two HBM memory cells from tile 604A, three HBM memory cells from tile 604B, one HBM memory cell from tile 604C, three HBM memory cells from tile 604D, one HBM memory cell from tile 604E, three HBM memory cells from tile 604F, no HBM memory cells from tile 604G, and no HBM memory cells from tile 604H. Computer vision model application 802B is allocated one HBM memory cell from tile 604A, one HBM memory cell from tile 604B, three HBM memory cells from tile 604C, one HBM memory cell from tile 604D, no HBM memory cells from tile 604E, one HBM memory cell from tile 604F, one HBM memory cell from tile 604G, and three HBM memory cells from tile 604H. Development and test application 802C is allocated one HBM memory cell from tile 604A, no HBM memory cell from tile 604B, no HBM memory cell from tile 604C, no HBM memory cell from tile 604D, three HBM memory cells from tile 604E, no HBM memory cell from tile 604F, three HBM memory cells from tile 604G, and one HBM memory cell from tile 604H.

[0114] In some embodiments, each of the applications 802A, 802B, 802C may be allocated HBM storage units based on the requirements of the applications 802A, 802B, 802C. For example, the storage units allocated to each application may be determined based on the amount of storage required to execute the application.

[0115] Fig. 9 An exemplary photonic computing system 900 is shown in accordance with some embodiments of the techniques described herein, wherein a set of processors 602A, 602B, 602C is able to access a plurality of separate memory pools 904A, 904B, 904C, 904D, 904E. In some embodiments, each of the memory pools 904A, 904B, 904C, 904D, 904E may be a photonic substrate comprising a plurality of memory tiles (e.g., Fig. 6A). Processors 602A, 602B, 602C may access storage pools 904A-904E through optical circuit switch 902. In some embodiments, optical circuit switch 902 may be configured to set which processor among processors 602A, 602B, 602C can access each storage pool among storage pools 904A-904E. Fig. 9 As shown, each of the processors 602A, 602B, 602C may be connected to the optical circuit switch 902 via a corresponding optical channel. Each of the processors 602A, 602B, 602C may be provided access to storage units from different ones of the storage pools 904A-904E via the optical circuit switch 902.

[0116] Fig.10 An exemplary photonic computing system 1000 is shown in which the storage of a computer system 1002 is expanded by separate groups of storage units 1004A, 1004B, 1004C according to some embodiments of the technology described herein. Fig.10 As shown, the computer system 1002 is connected to each group of storage units 1004A, 1004B, 1004C via a corresponding optical channel. Fig.10 In the example of FIG. 1 , each group of memory cells 1004A, 100B, 1004C includes an HBM library as a memory cell. Fig.10 As indicated, computer system 1002 has 96 GB of local storage. Expanding computer system 1002 by one storage unit has 192 GB of storage. Expanding computer system 1002 by two storage units has 288 GB of storage. Expanding computer system 1002 by three storage units has 384 GB.

[0117] Fig.11 is an exemplary process 1100 for programming a photonic network according to some embodiments of the technology described herein. In some embodiments, process 1100 can be performed using a programmable photonic network that controls which processor in a group of one or more processors can access a storage unit of a storage system separate from the processor(s). For example, process 1100 can be referred to herein as Figures 1A to 1C The photonic computing system described is implemented.

[0118] Process 1100 begins at block 1102, where the system determines a storage allocation indicating which storage units are accessible by each processor in the set (multiple) of processors. In some embodiments, the system can be configured to determine for a virtual CPU (e.g., FIG. 5A to FIG. 5BIn some embodiments, the system may be configured to determine storage allocations based on the requirements of one or more processes (e.g., software application(s)) to be executed by the system. In some embodiments, the system may be configured to determine storage allocations for parallel execution phases of a process (e.g., Figure 4 As an illustrative example, the system may determine a storage allocation that indicates, for each processor in a group (or multiple processors), which storage units are accessible to the processor.

[0119] Next, process 1100 continues to block 1104, where the system determines a configuration of the photonic network based on the storage allocation. In some embodiments, the photonic network may include an optical circuit including one or more configurable optical switches. The system may be configured to determine the configuration of the photonic network by determining the configuration of the one or more optical switches based on the storage allocation. The configuration of the one or more optical switches may configure the photonic network so that each processor in the set (multiple) of processors will have access to the (multiple) storage units indicated by the storage allocation.

[0120] Next, process 1100 continues to block 1106, where the system programs the photonic network to the determined configuration. In some embodiments, the system may be configured to program the photonic network to the configuration by configuring one or more optical switches of the photonic network. The system may be configured to configure one or more optical switches so that the optical circuits of the photonic network enable communication between each processor in the group (multiple) of processors and its assigned (multiple) storage unit. For example, the configuration may allow the group (multiple) of processors to read data from the corresponding assigned (multiple) storage unit and write data to the corresponding assigned (multiple) storage unit.

[0121] Fig.12 is an exemplary process 1200 for parallelizing the execution of a software application according to some embodiments of the techniques described herein. In some embodiments, process 1200 may be referred to herein as Figures 1A to 1C In some embodiments, when two processors are each configured to execute a corresponding application (e.g., one or more operations) to parallelize the execution of the software application (e.g., as described herein with reference to Figure 4 ), process 1200 may be performed.

[0122] In some embodiments, before performing process 1200, input data may be loaded into one or more storage units in the storage unit to be used for executing the software application. The one or more storage units may include a first storage unit and a second storage unit. The first storage unit may have data stored therein. For example, input to be used for executing the software application may be stored in the first storage unit. In some embodiments, the photonic network of the system may be programmed to a specific configuration before performing process 1200. The photonic network may be programmed so that the first processor accesses the first storage unit and the second processor accesses the second storage unit.

[0123] Process 1200 begins at block 1202, where a first processor uses data stored in a first storage unit to perform one or more operations to obtain a first output. In some embodiments, the (multiple) operations may be (multiple) operations performed in response to executing instructions of a software application. For example, the first processor may use one or more values ​​stored in the first storage unit to perform one or more functions. Next, process 1200 continues to block 1204, where the system stores the first output obtained from performing the (multiple) operations at block 1202 in the first storage unit.

[0124] Next, process 1200 continues to block 1206, where the system programs the photonic network to allow access to the second memory unit by the first processor and to allow access to the first memory unit by the second processor. In some embodiments, the system can be configured to program the photonic network as described herein with reference to Fig.11 The process described in the description 1100. For example, the system can configure an optical switch of an optical circuit to program a photonic network.

[0125] Next, process 1200 continues to block 1208, where the first processor uses the data stored in the second storage unit to perform (multiple) operations to obtain a second output. In some embodiments, the first processor can be configured to perform the same (multiple) operations it performed at block 1202, but using the data stored in the second storage unit. For example, the first processor can use (multiple) values ​​stored in the second storage unit to perform one or more functions.

[0126] At block 1210, in parallel with the execution of the first processor at block 1208, the second processor performs (multiple) operations using the first output stored in the first storage unit. In some embodiments, the second processor can be configured to execute another software application using the first output stored in the first storage unit. For example, the output of the (multiple) operations performed by the first processor is further processed by the second processor to generate a final output.

[0127] Next, process 1200 continues to block 1212, where the system stores the second output obtained in block 1208 in the second storage unit. At block 1214, the system outputs the result of the operation(s) performed by the second processor in block 1210 from the first storage unit. The outputted result may be an output corresponding to the input originally stored in the first storage unit.

[0128] Next, process 1200 continues to block 1216, where the system programs the photonic network to allow access to the first storage unit by the first processor and to allow access to the second storage unit by the second processor. Process 1200 then returns to block 1202, where the system processes subsequent input (e.g., more numerical values). Process 1200 can then continue through blocks 1202 to 1216 of process 1200.

[0129] Fig.13 is an exemplary computer system that can be used to implement some embodiments of the technology described herein. Computing device 1300 may include one or more computer hardware processors 1302 and non-transitory computer-readable storage media (e.g., memory 1304 and one or more non-volatile storage devices 1306). (Multiple) processors 1302 can control writing data to (1) memory 1304; and (2) (multiple) non-volatile storage devices 1306 and reading data from (1) memory 1304; and (2) (multiple) non-volatile storage devices 1306. In order to perform any of the functions described herein, (multiple) processors 1302 can execute one or more processor-executable instructions stored in one or more non-transitory computer-readable storage media (e.g., memory 1304), which can act as non-transitory computer-readable storage media that store processor-executable instructions for execution by (multiple) processors 1302.

[0130] The term "program" or "software" is used in this article in a general sense and refers to any type of computer code or processor executable instruction set that can be used to program a computer or other processor (physical or virtual processor) to implement various aspects of the embodiments discussed above. In addition, according to one aspect, one or more computer programs that perform the methods of the disclosure provided herein when executed do not have to reside on a single computer or processor, but can be distributed in a modular manner between different computers or processors to implement various aspects of the disclosure provided herein.

[0131] Processor executable instructions can be in various forms, such as program modules, that are executed by one or more computers or other devices. Generally speaking, program modules include routines, programs, objects, components, data structures, etc. that perform tasks or implement abstract data types. Typically, the functionality of program modules can be combined or distributed.

[0132] Some embodiments provide a photonic computing system. The photonic computing system includes: at least one processor; at least one optical channel; and at least one photonic substrate, which is separate from the at least one processor, the at least one photonic substrate including a plurality of storage units and at least one photonic network for providing the at least one processor with access to the plurality of storage units, wherein: the at least one photonic network communicates with the at least one processor via the at least one optical channel; and the at least one photonic network is programmable to configure which storage unit among the plurality of storage units in the at least one photonic substrate the at least one processor can access via the at least one optical channel.

[0133] In some embodiments, the photonic computing system may include one or more of the following properties:

[0134] a. The at least one processor includes a first processor and a second processor; and the first processor and the second processor are configured to process a data set using a plurality of storage units.

[0135] b. at least one photonic network is programmed to allow access to a first storage unit in the plurality of storage units by a first processor and to allow access to a second storage unit in the plurality of storage units by a second processor; and

[0136] Processing stored data sets includes:

[0137] i. performing an operation by a first processor using data stored in a first storage unit to obtain a first output; and

[0138] ii. Storing the first output in the first storage unit.

[0139] c. after storing the first output in the first storage unit, at least one photonic network is programmed to allow access to the first storage unit by the second processor and to allow access to the second storage unit by the first processor; and processing the stored data set further comprises:

[0140] i. performing an operation by the first processor using the data stored in the second storage unit to obtain a second output;

[0141] ii. In parallel with the execution of the first processor, the second processor uses the data stored in the first memory

[0142] performing an operation on a first output of a storage unit to obtain a first result;

[0143] iii. storing the second output in the second storage unit; and

[0144] iv. Output the first result from the first storage unit.

[0145] d. at least one photonic network is programmed to allow access to the first storage unit by the first processor and to allow access to the second storage unit by the second processor; and processing the data sets stored in the plurality of storage units of the at least one photonic network further comprises:

[0146] i. The first processor performs an operation using the data stored in the first storage unit

[0147] To obtain the third output;

[0148] ii. In parallel with the execution of the first processor, the second processor uses the data stored in the second memory

[0149] performing an operation on a second output of the storage unit to obtain a second result;

[0150] iii. storing the third output in the first storage unit; and

[0151] iv. Output the second result from the second storage unit.

[0152] e. At least one photonic network is programmed to allow access to a subset of the plurality of storage units by at least one processor via at least one optical channel.

[0153] f. At least one optical channel is configured to transmit data at a rate of at least 15 terabytes per second (TB / s) between at least one processor and at least one photonic network.

[0154] g. At least one photonic network includes at least one optical switch that can be configured to connect at least one processor to each of a plurality of memory cells / disconnect at least one processor from each of a plurality of memory cells; and at least one photonic network can be programmed by configuring the at least one optical switch.

[0155] h. At a first time, at least one photonic network is programmed to allow access to a first storage unit in the plurality of storage units by at least one processor via at least one optical channel; and at a second time after the first time, at least one photonic network is programmed to:

[0156] i. prohibiting access to the first storage unit by at least one processor through at least one optical channel; and

[0157] ii. allowing access by at least one processor to a second storage unit of the plurality of storage units through at least one optical channel.

[0158] i. At least one processor includes a first processor and a second processor; a plurality of memory units include a first memory unit and a second memory unit; and at least one photonic network is programmed to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor.

[0159] j. The plurality of memory cells include a plurality of high bandwidth memory (HBM) cells.

[0160] k. The plurality of memory cells comprises a plurality of static random access memory (SRAM) cells.

[0161] 1. The plurality of memory cells include a plurality of double data rate (DDR) synchronous dynamic random access memories (SDRAMs).

[0162] m. The at least one photonic substrate further comprises at least one memory controller configured to program the at least one photonic network.

[0163] n. At least one processor is configured to program at least one photonic network.

[0164] o. The at least one processor comprises a plurality of processors, the plurality of processors being organized into a plurality of groups of processors; and the at least one photonic network being programmed to allow each group of processors in the plurality of groups of processors to access a different subset of storage units in the plurality of storage units through at least one optical channel.

[0165] p. Each group of processors in the plurality of groups of processors and a corresponding subset of storage units in the plurality of storage units accessible by the group of processors form a corresponding virtual processor assigned to a corresponding virtual machine.

[0166] q. The at least one processor comprises a plurality of processors; the at least one optical channel comprises a plurality of optical channels; and each processor in the plurality of processors communicates with the at least one photonic network via a corresponding optical channel in the plurality of optical channels.

[0167] r. At least one photon network comprises a plurality of photon networks; at least one photon substrate comprises a plurality of photon modules, each photon module comprising:

[0168] i. a corresponding photon network among a plurality of photon networks;

[0169] ii. a subgroup of storage units in a plurality of storage units; and

[0170] iii. Storage controller.

[0171] s. Each processor of the plurality of processors is connected to a memory controller of the plurality of photonic modules via a corresponding optical channel of the plurality of optical channels.

[0172] t. at least one photonic network is programmed in a configuration to allocate storage units among the plurality of processors based on storage requirements for execution of the plurality of software applications, wherein the configuration:

[0173] i. allowing access to a first group of storage units in a plurality of storage units by a first processor in a plurality of processors configured to execute a first software application; and

[0174] ii. allowing access to a second group of memory cells in the plurality of memory cells by a second processor in the plurality of processors that is configured to execute a second software application.

[0175] u. The first software application uses a machine learning model.

[0176] v. The machine learning model is a large language model (LLM).

[0177] w. Machine learning models are computer vision models.

[0178] x. The first software application is a software development and testing application.

[0179] y. At least one photon substrate includes a plurality of photon substrates, each of which includes a set of

[0180] A storage unit and a corresponding photonic network, wherein:

[0181] i. The photonic networks of the plurality of substrates are each programmable to configure which memory cells in a corresponding set of memory cells are accessible to at least one processor.

[0182] z. The optical computing system further comprises an optical switch, wherein the optical switch is configurable to provide at least one processor with access to a plurality of memory cells distributed across a plurality of the plurality of photonic substrates.

[0183] aa. At least one photonic substrate includes at least one storage controller; and at least one photonic network includes optical circuits interconnecting the at least one storage controller with a plurality of storage units.

[0184] bb. At least one photonic network includes a plurality of electrical / optical (E / O) transceivers, each E / O transceiver connecting a corresponding storage unit of the plurality of storage units to the optical circuit.

[0185] cc. At least one photonic substrate comprises: at least one storage controller; at least one fiber optic attachment, the at least one fiber optic attachment connected to at least one optical channel; and at least one E / O transceiver; and at least one photonic network comprises an optical circuit connecting the at least one storage controller to the at least one fiber optic attachment, wherein the E / O transceiver is configured to convert signals transmitted between the at least one storage controller and the at least one fiber optic attachment.

[0186] dd. At least one photonic network includes a plurality of electrical connections between at least one storage controller and a plurality of storage units, wherein data signals are transmitted between the at least one storage controller and the plurality of storage units via the plurality of electrical connections.

[0187] Some embodiments provide a method for using a photonic network to perform parallelized data processing using multiple storage units. The photonic network can be programmed to configure which storage unit of the multiple storage units can be accessed by a first processor and a second processor. The photonic network is programmed to allow access to a first storage unit of the multiple storage units by the first processor and to allow access to a second storage unit of the multiple storage units by the second processor. The method includes: programming the photonic network to allow access to the second storage unit by the first processor and to allow access to the first storage unit by the second processor; performing an operation by the first processor using data stored in the second storage unit to obtain an output; and performing an operation by the second processor using data stored in the first storage unit in parallel with the execution of the first processor.

[0188] In some embodiments, the method may include one or more of the following attributes:

[0189] a. The method further includes: programming the photonic network to allow access to the first storage unit by the first processor and to allow access to the second storage unit by the second processor; performing operations by the first processor using data stored in the first storage unit; and performing operations by the second processor using data stored in the second storage unit in parallel with the execution of the first processor.

[0190] b. The method further comprises storing in the second storage unit a result of an operation performed by the first processor using the data stored in the second storage unit.

[0191] Some embodiments provide a photonic network disposed on a photonic substrate. The photonic network is accessible via at least one optical channel. The photonic network includes: a plurality of storage units; at least one configurable optical switch that controls which storage unit of the plurality of storage units is accessible via at least one optical channel; and at least one electrical / optical (E / O) transceiver for transmitting data to and from the plurality of storage units via at least one optical channel.

[0192] In some embodiments, the photonic network may have one or more of the following properties:

[0193] a. At a first time, at least one optical switch is configured to allow access to a first storage unit in the plurality of storage units through at least one optical channel; and at a second time after the first time, at least one optical switch is configured to allow access to a second storage unit in the plurality of storage units through at least one optical channel.

[0194] b. At a second time, at least one optical switch is programmed to disable access to the second storage unit via at least one optical channel.

[0195] c. The photonic network further comprises a storage controller, wherein at least one optical switch can be configured by the storage controller.

[0196] d. The photonic network includes an optical circuit, which includes at least one configurable optical switch.

[0197] e. the at least one E / O transceiver comprises a plurality of E / O transceivers connected to corresponding ones of the plurality of storage units; and the optical circuit connects the storage controller to the plurality of storage units through the plurality of E / O transceivers.

[0198] f. The photonic network includes a fiber optic attachment, wherein: the optical circuit connects the storage controller to the fiber optic attachment through at least one E / O transceiver.

[0199] Some embodiments provide a method of manufacturing a photonic computing system. The method includes manufacturing the photonic computing system to include: at least one processor; at least one optical channel; and at least one photonic substrate, which is separate from the at least one processor, the at least one photonic substrate including a plurality of memory cells and at least one photonic network for connecting the at least one processor to the plurality of memory cells, wherein: the at least one photonic network communicates with the at least one processor via the at least one optical channel; and the at least one photonic network is programmable to configure which memory cell of the plurality of memory cells in the at least one photonic substrate the at least one processor can access via the at least one optical channel.

[0200] Various inventive concepts may be embodied as one or more processes, examples of which have been given. The actions performed as part of each process may be ordered in any suitable manner. Thus, embodiments may be constructed in which the order of execution of the actions differs from the illustrated order, which may include performing some actions simultaneously, even though they are shown as sequential actions in the illustrative embodiments.

[0201] As used herein in the specification and claims, the phrase "at least one" when referring to a list of one or more elements should be understood to refer to at least one element selected from any one or more elements in the list of elements, but does not necessarily include at least one element of each element specifically listed in the list of elements, nor does it exclude any combination of elements in the list of elements. This limitation also allows that elements other than the specifically identified elements referred to by the phrase "at least one" in the list of elements may optionally exist, whether related to or unrelated to the specifically identified elements. Thus, for example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and / or B") may refer to at least one A, optionally including more than one A, without B (and optionally including elements other than B) in one embodiment; in another embodiment, refers to at least one B, optionally including more than one B, without A (and optionally including elements other than A); in yet another embodiment, refers to at least one A, optionally including more than one A, and at least one B, optionally including more than one B (and optionally including other elements); and so on.

[0202] The phrase "and / or" as used herein in the specification and claims should be understood to refer to "either or both" of the combined elements (i.e., elements that exist in a combined manner in some cases and in a dispersed manner in other cases). Multiple elements listed with "and / or" should be interpreted in the same manner, i.e., "one or more" of the combined elements. In addition to the elements specifically identified by the "and / or" clause, other elements may optionally be present, whether or not they are related to the specifically identified elements. Thus, as a non-limiting example, when used in conjunction with an open-ended term such as "including", a reference to "A and / or B" may refer to only A (optionally including elements other than B) in one embodiment; to only B (optionally including elements other than A) in another embodiment; to both A and B (optionally including other elements) in yet another embodiment; and so on.

[0203] The use of ordinal numbers such as "first," "second," "third," etc. in the claims to modify claim elements does not, by itself, imply that one claim element has any priority, importance, or order relative to another claim element, nor does it imply a temporal order in which the actions of the method are performed. Such terms are used only as labels to distinguish one claim element with a particular name from another element with the same name (but this is directed to the use of ordinal numbers). The words and terms used herein are for descriptive purposes and should not be considered restrictive. The use of "comprises," "includes," "has," "contains," "involves," and variations thereof are intended to cover the items listed thereafter and other items.

[0204] Having described in detail several embodiments of the technology described herein, various modifications and improvements will readily occur to those skilled in the art. Such modifications and improvements are intended to fall within the spirit and scope of the present disclosure. Thus, the foregoing description is intended to be exemplary only and is not intended to be limiting. These technologies are limited only by the limitations of the following claims and their equivalents.

Claims

1. A photonic computing system, comprising: at least one processor; at least one optical channel; as well as At least one photonic substrate, the at least one photonic substrate being separate from the at least one processor, the at least one photonic substrate comprising a plurality of storage units and at least one photonic network, the at least one photonic network being configured to provide the at least one processor with access to the plurality of storage units, wherein: The at least one photonic network is in communication with the at least one processor via the at least one optical channel; and The at least one photonic network is programmable to configure which memory cells of the plurality of memory cells in the at least one photonic substrate the at least one processor is able to access via the at least one optical channel.

2. The photonic computing system according to claim 1, wherein: The at least one processor includes a first processor and a second processor; and The first processor and the second processor are configured to process a data set using the plurality of memory cells.

3. A photonic computing system according to claim 2 or any preceding claim, wherein: The at least one photonic network is programmed to allow access to a first storage unit of the plurality of storage units by the first processor and to allow access to a second storage unit of the plurality of storage units by the second processor; and Processing the data set includes: performing, by the first processor, an operation using the data stored in the first storage unit to obtain a first output; as well as The first output is stored in the first storage unit.

4. A photonic computing system according to claim 3 or any preceding claim, wherein: After storing the first output in the first storage unit, the at least one photonic network is programmed to allow access to the first storage unit by the second processor and to allow access to the second storage unit by the first processor; and Processing the data set further comprises: performing, by the first processor, an operation using the data stored in the second storage unit to obtain a second output; In parallel with execution by the first processor, performing, by the second processor, an operation using the first output stored in the first storage unit to obtain a first result; storing the second output in the second storage unit; and The first result is output from the first storage unit.

5. A photonic computing system according to claim 4 or any preceding claim, wherein: The at least one photonic network is programmed to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor; and Processing the data sets stored in the plurality of storage units of the at least one photonic network further comprises: performing, by the first processor, an operation using the data stored in the first storage unit to obtain a third output; In parallel with execution by the first processor, performing, by the second processor, an operation using the second output stored in the second storage unit to obtain a second result; storing the third output in the first storage unit; and The second result is output from the second storage unit.

6. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one photonic network is programmed to allow access by the at least one processor to a subset of the plurality of storage cells via the at least one optical channel.

7. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one optical channel is configured to transmit data between the at least one processor and the at least one photonic network at a rate of at least 15 terabytes per second (TB / s).

8. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one photonic network comprises at least one optical switch configurable to connect or disconnect the at least one processor to or from each of the plurality of memory cells; and The at least one photonic network is programmable by configuring the at least one optical switch.

9. A photonic computing system according to claim 1 or any preceding claim, wherein: At a first time, the at least one photonic network is programmed to allow access by the at least one processor to a first storage unit of the plurality of storage units via the at least one optical channel; and At a second time after the first time, the at least one photonic network is programmed to: disabling access to the first storage unit by the at least one processor through the at least one optical channel; and Access to a second storage unit of the plurality of storage units is permitted by the at least one processor through the at least one optical channel.

10. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one processor includes a first processor and a second processor; The plurality of storage units include a first storage unit and a second storage unit; and The at least one photonic network is programmed to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor.

11. The photonic computing system of claim 1 or any preceding claim, wherein the plurality of storage cells comprises a plurality of high bandwidth memory (HBM) cells.

12. The photonic computing system of claim 1 or any preceding claim, wherein the plurality of storage cells comprises a plurality of static random access memory (SRAM) cells.

13. The photonic computing system of claim 1 or any preceding claim, wherein the plurality of memory cells comprises a plurality of double data rate (DDR) synchronous dynamic random access memory (SDRAM) cells.

14. The photonic computing system of claim 1 or any preceding claim, wherein the at least one photonic substrate further comprises at least one memory controller configured to program the at least one photonic network.

15. The photonic computing system of claim 1 or any preceding claim, wherein the at least one processor is configured to program the at least one photonic network.

16. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one processor includes a plurality of processors, the plurality of processors being organized into a plurality of groups of processors; and The at least one optical network is programmed to allow each of the plurality of groups of processors to access a different subset of the plurality of memory cells via the at least one optical channel.

17. A photonic computing system according to claim 16 or any preceding claim, wherein: Each group of processors in the plurality of groups of processors and a corresponding subset of storage units in the plurality of storage units accessible by the group of processors form a corresponding virtual processor assigned to a corresponding virtual machine.

18. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one processor comprises a plurality of processors; The at least one optical channel comprises a plurality of optical channels; and Each processor of the plurality of processors communicates with the at least one photonic network via a corresponding optical channel of the plurality of optical channels.

19. A photonic computing system according to claim 18 or any preceding claim, wherein: The at least one photonic network comprises a plurality of photonic networks; The at least one photon substrate comprises a plurality of photon modules, each of the plurality of photon modules comprising: a corresponding photonic network among the plurality of photonic networks; a subset of storage cells in the plurality of storage cells; and Storage controller.

20. The photonic computing system of claim 19 or any preceding claim, wherein each processor of the plurality of processors is connected to a memory controller of the plurality of photonic modules via a corresponding optical channel of the plurality of optical channels.

21. The photonic computing system of claim 18 or any preceding claim, wherein the at least one photonic network is programmed into a configuration to allocate storage units among the plurality of processors based on storage requirements for executing a plurality of software applications, wherein the configuration: allowing access to a first group of memory cells in the plurality of memory cells by a first processor in the plurality of processors that is configured to execute a first software application; and Access to a second group of memory cells in the plurality of memory cells is permitted by a second processor in the plurality of processors that is configured to execute a second software application.

22. A photonic computing system according to claim 21 or any preceding claim, wherein the first software application uses a machine learning model.

23. A photonic computing system according to claim 22 or any preceding claim, wherein the machine learning model is a large language model (LLM).

24. A photonic computing system according to claim 22 or any preceding claim, wherein the machine learning model is a computer vision model.

25. The photonic computing system of claim 21 or any preceding claim, wherein the first software application is a software development and testing application.

26. The photonic computing system of claim 1 or any preceding claim, wherein the at least one photonic substrate comprises a plurality of photonic substrates, each of the plurality of photonic substrates comprising a set of storage units and a corresponding photonic network, wherein: The photonic networks of the plurality of substrates are each programmable to configure which memory cells of a corresponding set of memory cells are accessible by the at least one processor.

27. The photonic computing system of claim 26 or any preceding claim, further comprising an optical switch, wherein the optical switch is configurable to provide the at least one processor with access to a plurality of memory cells distributed across a plurality of the plurality of photonic substrates.

28. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one photonic substrate comprises at least one memory controller; and The at least one photonic network includes optical circuits interconnecting the at least one storage controller with the plurality of storage units.

29. A photonic computing system according to claim 28 or any preceding claim, wherein the at least one photonic network comprises a plurality of electrical / optical (E / O) transceivers, each of the plurality of E / O transceivers connecting a corresponding storage unit of the plurality of storage units to the optical circuit.

30. A photonic computing system according to claim 1 or any preceding claim, wherein: The at least one photonic substrate comprises: at least one storage controller; at least one fiber optic accessory connected to the at least one optical channel; and at least one E / O transceiver; and The at least one photonic network includes optical circuits connecting the at least one storage controller to the at least one fiber optic attachment, wherein the E / O transceiver is configured to convert signals transmitted between the at least one storage controller and the at least one fiber optic attachment.

31. A photonic computing system according to claim 30 or any preceding claim, wherein the at least one photonic network includes a plurality of electrical connections between the at least one storage controller and the plurality of storage units, wherein data signals are transmitted between the at least one storage controller and the plurality of storage units via the plurality of electrical connections.

32. A method for parallelizing data processing using a plurality of storage units using a photonic network, the photonic network being programmable to configure which storage unit of the plurality of storage units can be accessed by a first processor and a second processor, the photonic network being programmed to allow access to a first storage unit of the plurality of storage units by the first processor and to allow access to a second storage unit of the plurality of storage units by the second processor, the method comprising: programming the photonic network to allow access to the second memory unit by the first processor and to allow access to the first memory unit by the second processor; performing, by the first processor, an operation using the data stored in the second storage unit to obtain an output; as well as In parallel with execution by the first processor, operations are performed by the second processor using data stored in the first storage unit.

33. The method of claim 32 or any preceding claim, further comprising: programming the photonic network to allow access to the first memory unit by the first processor and to allow access to the second memory unit by the second processor; performing, by the first processor, an operation using the data stored in the first storage unit; In parallel with execution by the first processor, operations are performed by the second processor using data stored in the second storage unit.

34. The method of claim 32 or any preceding claim, further comprising: A result of an operation performed by the first processor using the data stored in the second storage unit is stored in the second storage unit.

35. A photonic network arranged on a photonic substrate, the photonic network being accessible via at least one optical channel, the photonic network comprising: Multiple storage units; at least one configurable optical switch, the at least one configurable optical switch controlling which of the plurality of storage units is accessible via the at least one optical channel; as well as At least one electrical / optical (E / O) transceiver is configured to transmit data to and from the plurality of storage units via the at least one optical channel.

36. A photonic network according to claim 35 or any preceding claim, wherein: At a first time, the at least one optical switch is configured to allow access to a first storage unit of the plurality of storage units through the at least one optical channel; and At a second time after the first time, the at least one optical switch is configured to allow access to a second storage unit of the plurality of storage units through the at least one optical channel.

37. A photonic network according to claim 35 or any preceding claim, wherein: At the second time, the at least one optical switch is programmed to inhibit access to the second storage unit via the at least one optical channel.

38. A photonic network according to claim 35 or any preceding claim, further comprising a storage controller, wherein the at least one optical switch is configurable by the storage controller.

39. A photonic network according to claim 38 or any preceding claim, further comprising an optical circuit comprising the at least one configurable optical switch.

40. A photonic network according to claim 38 or any preceding claim, wherein: The at least one E / O transceiver comprises a plurality of E / O transceivers connected to corresponding ones of the plurality of storage units; and The optical circuit connects the storage controller to the plurality of storage units through the plurality of E / O transceivers.

41. A photonic network according to claim 38 or any preceding claim, further comprising an optical fiber attachment, wherein: The optical circuit connects the storage controller to the fiber optic attachment through the at least one E / O transceiver.

42. A method of manufacturing a photonic computing system, the method comprising manufacturing the photonic computing system to include: at least one processor; at least one optical channel; as well as at least one photonic substrate, the at least one photonic substrate being separate from the at least one processor, the at least one photonic substrate comprising a plurality of memory cells and at least one photonic network, the at least one photonic network being used to connect the at least one processor to the plurality of memory cells, wherein: The at least one photonic network is in communication with the at least one processor via the at least one optical channel; and The at least one photonic network is programmable to configure which memory cells of the plurality of memory cells in the at least one photonic substrate the at least one processor is able to access via the at least one optical channel.

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