Nitride hot atomic layer etch

Abstract

Nitride atomic layer etching is provided that includes generating phosphoric acid in situ on a surface of a silicon nitride layer by reacting a phosphorus-containing reactant with one or more oxidants. Phosphoric acid selectively etches the silicon nitride layer rather than silicon oxide and / or silicon.

Description

Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed PCT application form to which this application claims the benefit or priority is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] Semiconductor manufacturing processes often involve selectively etching one or more materials in a semiconductor substrate. As device dimensions shrink and technology advances, it is challenging to selectively etch a controlled amount of material from a substrate without compromising the structural stability of the device.

[0003] The background description provided here is for the purpose of generally presenting the background of the present disclosure. The work of the currently designated inventors within the scope described in this background section and aspects of the specification that were not determined to be prior art at the time of filing the application are neither explicitly nor implicitly admitted to be prior art against the present disclosure. Summary of the invention

[0004] Atomic layer etching of a silicon nitride layer is provided. The method may include a reaction between a phosphorus-containing reactant, an oxidant, and / or water vapor to generate phosphoric acid in situ on the surface of the silicon nitride layer for use as a dry etching chemical. The phosphoric acid may selectively etch the silicon nitride layer over other adjacent materials, such as silicon or silicon oxide. The substrate temperature may be adjusted to above 100° C. to increase the etching rate of the silicon nitride layer.

[0005] One aspect of the present disclosure relates to a method of treating a silicon nitride layer. The method may include: (a) generating phosphoric acid on a surface of the silicon nitride layer; and (b) treating a portion of the surface of the silicon nitride layer with the phosphoric acid.

[0006] In some embodiments, the method may further include (c): providing water vapor to form one or more monolayers of water molecules on the surface of the silicon nitride layer before (a).

[0007] In some embodiments, the temperature of the surface of the silicon nitride layer may range between about 0° C. and about 100° C., and the pressure of the surface of the silicon nitride layer may range between about 1 Torr and about 100 Torr.

[0008] In some embodiments, the temperature can be about 20°C, and the pressure can be about 10 Torr.

[0009] In some embodiments, generating the phosphoric acid may include: providing a first reactant; providing a second reactant; and reacting the first reactant and the second reactant to form the phosphoric acid. The first reactant may include phosphorus. The first reactant may be selected from the group consisting of phosphine, phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkylphosphine halides, trimethylphosphine, triethylphosphine, tripropylphosphine and / or mixtures thereof. The second reactant may be selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (N2O), nitrogen dioxide (NO2) and / or mixtures thereof.

[0010] In some embodiments, the method may further include: providing water vapor; and adjusting the temperature to no less than about 100° C. before or during providing the water vapor.

[0011] In some embodiments, processing the surface of the silicon nitride layer can include etching a portion of the surface of the silicon nitride layer and generating etching byproducts.

[0012] In some embodiments, the method may further include removing etching byproducts from the surface of the silicon nitride layer by: (i) heating to not less than about 360° C., (ii) heating to between about 100° C. and about 120° C. by reacting with hydrogen fluoride, or (iii) reacting with the hydrogen fluoride. The etching byproducts may include phosphorus or silicon.

[0013] In some embodiments, generating the phosphoric acid may include: co-flowing a first reactant and a second reactant comprising phosphorus. The first reactant may be selected from the group consisting of phosphine, phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkylphosphine halides, trimethylphosphine, triethylphosphine, tripropylphosphine and / or mixtures thereof. The second reactant may be selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (N2O), nitrogen dioxide (NO2) and / or mixtures thereof.

[0014] Another aspect of the present disclosure relates to a method for etching a silicon nitride layer in a reaction chamber. The method may include providing a semiconductor substrate including the silicon nitride layer in the reaction chamber. The method may also include providing a first water vapor to form one or more monolayers of water molecules on the surface of the silicon nitride layer; and providing phosphine to the surface of the silicon nitride layer. The method may also include providing an oxidant to the phosphine to generate phosphoric acid in situ on the silicon nitride layer.

[0015] In some embodiments, the temperature of the surface of the silicon nitride layer can range between about 0° C. and about 100° C., and the pressure of the surface of the silicon nitride layer can range between about 1 Torr and about 100 Torr.

[0016] In some embodiments, the temperature may be about 20° C. and the pressure may be about 10 Torr.

[0017] In some embodiments, the second reactant may be selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (N2O), nitrogen dioxide (NO2) and / or mixtures thereof.

[0018] In some embodiments, the method may further include: providing a second water vapor in the reaction chamber; and adjusting the temperature to no less than about 100° C. before or during providing the water vapor.

[0019] In some embodiments, the method may further include generating etching byproducts comprising silicon or phosphorus; and removing the etching byproducts from the surface of the silicon nitride layer by: (i) heating the etching byproducts to not less than about 360° C., or (ii) heating to between about 100° C. and about 120° C. by reacting with hydrogen fluoride, or (iii) reacting with the hydrogen fluoride. The etching byproducts include orthosilicic acid or phosphorus pentoxide.

[0020] Another aspect of the present disclosure relates to an apparatus for processing a substrate. The apparatus may include: a processing chamber for processing the substrate; a susceptor including one or more heating elements for heating the substrate; a gas distribution unit for delivering one or more gaseous reactants to the substrate; and a controller. The controller is configured to: control the gas distribution unit to control the flow rate and duration of the one or more gaseous reactants and / or vapors, and control the operation of the heating elements to control the temperature of the substrate.

[0021] In some embodiments, the one or more heating elements may be located on the back side of the substrate.

[0022] In some embodiments, the one or more heating elements may include one or more light emitting element (LED) units.

[0023] In some embodiments, the one or more heating elements can be configured to increase the substrate temperature at a rate of up to about 20° C. per second.

[0024] In some embodiments, the susceptor may be spaced a predetermined distance from the substrate.

[0025] In some embodiments, the susceptor may be in direct contact with the substrate.

[0026] In some embodiments, one or more gaseous reactants may include: water vapor; a first reactant selected from the group consisting of phosphine, phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxy phosphine, alkyl phosphine halides, trimethyl phosphine, triethyl phosphine, tripropyl phosphine and / or mixtures thereof; a second reactant selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2) and / or mixtures thereof; or hydrogen fluoride.

[0027] In some embodiments, the substrate can include a silicon nitride layer.

[0028] These and other aspects will be discussed further below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a process flow diagram illustrating thermal atomic layer etching according to some embodiments.

[0030] Figure 2A is a schematic diagram illustrating a reaction chamber for thermal atomic layer etching according to some embodiments.

[0031] Figure 2B is a schematic diagram showing an arrangement of light sources according to some embodiments.

[0032] Figure 2C is another schematic diagram showing an arrangement of light sources according to some embodiments.

[0033] Figure 2D is a schematic diagram showing a cross-sectional depiction of a susceptor according to some embodiments.

[0034] Figure 2E is another schematic diagram showing a cross-sectional depiction of a susceptor according to some embodiments.

[0035] Figure 2F is another schematic diagram showing a cross-sectional depiction of a substrate support, according to some embodiments.

[0036] Figure 3A is a schematic diagram showing a cross-sectional depiction of a feature prior to atomic layer etching, according to some embodiments.

[0037] Figure 3B is a schematic diagram showing a cross-sectional depiction of a feature after atomic layer etching, according to some embodiments.

[0038] Figure 4 It is shown Figure 3A-3BProcess flow diagram for thermal atomic layer etching of the features shown in . DETAILED DESCRIPTION

[0039] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other cases, well-known process operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that this is not intended to limit the disclosed embodiments.

[0040] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "semiconductor substrate", "silicon substrate", "features on a substrate", and "features formed on a substrate" are used interchangeably. It should be understood by those of ordinary skill in the art that the term "features on a substrate" can refer to one or more partially manufactured integrated circuits formed on a silicon wafer during any of the many stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor equipment industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not limited to this. The workpiece can have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various items, such as printed circuit boards, etc.

[0041] In the present disclosure, the terms "depositing" and "forming" are used interchangeably. In addition, the terms "layer" and "film" are used interchangeably. It should be understood by those of ordinary skill in the art that as the feature size in semiconductor devices decreases, "forming" a layer in any of the many stages of integrated circuit manufacturing can refer to "depositing" a thin layer by one of a variety of thin film formation methods, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), hot filament chemical vapor deposition (hot filament CVD), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD).

[0042] Introduction and context

[0043] A method for processing a feature including a silicon nitride layer is provided. The method involves selectively etching the silicon nitride layer in one or more features on a nanoscale substrate. The method involves in situ generation of phosphoric acid on a surface of the silicon nitride layer and then selectively removing at least a portion of the silicon nitride layer. The silicon nitride layer can be formed by various deposition processes (e.g., CVD, PECVD, ALD, or PEALD).

[0044] Semiconductor devices may include 3D-NAND, 2D-NAND, DRAM (random access memory) or logic devices. Semiconductor devices may include one or more partially manufactured integrated circuits and may include patterned or unpatterned stacks of oxide, nitride or carbide layers associated with one or more metal elements or one or more metal layers. The patterned substrate may have "features" such as columns, rods, grooves, through holes or contact holes, which may be characterized as one or more of narrow and / or concave openings, constrictions within features, and high aspect ratios (HAR). As the density of devices on substrates increases and individual feature sizes become smaller and smaller, precise control of the etching process may be critical.

[0045] For example, high-density semiconductor device manufacturing requires an etching process that can reliably remove very small amounts of material from features to meet design rules. The etching process can be designed to provide selectivity relative to other materials that should not be etched. In addition, the etching process can be designed to remove material without directionality. This may be particularly important for small-sized high aspect ratio features that may require directional etching. For high-density semiconductor devices with small-sized high aspect ratio (HAR) features, it may also be important to minimize or prevent the collapse of features during etching.

[0046] Etching processes can include wet etching and dry etching. Wet etching is a liquid-based process that can remove portions of a feature using liquid etching chemicals at a suitable temperature. For example, wet etching can be performed at temperatures ranging from atmospheric temperature to 200-300°C, depending on the material to be removed. Wet etching can be isotropic. Dry etching can use gaseous etching chemicals, such as oxygen plasma. Dry etching may be more suitable for anisotropic etching.

[0047] One aspect of the embodiment relates to a method for removing at least a portion of a silicon nitride layer on a substrate using phosphoric acid generated in situ by a reaction between water vapor, phosphine and / or one or more oxidants. Water vapor can be supplied to form one or more monolayers of water molecules adsorbed on the silicon nitride layer. Alternatively, water vapor can be provided from the atmosphere in the reaction chamber. Phosphine reacts with water to form phosphoric acid in situ. Phosphoric acid can also be generated in situ by hydrated phosphorus oxide (P2O5), which is generated by the reaction of phosphine with one or more oxidants. One or more oxidants can be oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2) and / or mixtures thereof. Subsequently, water vapor can be provided and the substrate temperature can be raised to above 100°C to increase the reactivity of phosphoric acid and the etching rate of the silicon nitride layer.

[0048] Another aspect of the embodiment relates to a method for selectively etching a portion of a silicon nitride layer on a substrate using phosphoric acid generated in situ by reacting phosphine with one or more oxidants. The one or more oxidants can be oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2) and / or mixtures thereof. Phosphoric acid can be uniformly formed on the surface of the silicon nitride layer. Providing water vapor to the phosphoric acid can increase the reactivity of the phosphoric acid and the etching rate of the silicon nitride layer. The substrate temperature can be adjusted to above 100°C to further increase the etching rate of the silicon nitride layer. Phosphoric acid can selectively etch the silicon nitride layer, rather than adjacent materials, such as silicon or silicon oxide.

[0049] Yet another aspect of the embodiment relates to a method for removing one or more etching byproducts generated during etching of a silicon nitride layer. The etching byproducts may include silicon and / or phosphorus and may remain on the surface of the silicon nitride layer. Silicon-containing etching byproducts may be removed by reacting with hydrogen fluoride (HF) at between about 100°C and about 120°C to generate volatile etching byproducts (e.g., silicon tetrafluoride). Phosphorus-containing etching byproducts may be removed by reacting with hydrogen fluoride at above 100°C, or by thermal sublimation at above about 360°C, or above about 375°C, or above about 400°C.

[0050] Yet another aspect of the embodiment relates to a method of etching a silicon nitride layer and subsequently depositing one or more silicon-containing layers on a substrate without breaking the vacuum in a reaction chamber or exposing the substrate to ambient atmosphere. The one or more silicon-containing layers may be deposited by CVD, PECVD, ALD, or PEALD.

[0051] Also provided herein is a device for semiconductor processing, for example, using thermal energy instead of plasma energy or as a supplement to plasma energy to etch a semiconductor substrate. In various embodiments, the device described herein is designed or configured to heat and cool a substrate quickly, and accurately and uniformly control the temperature of the substrate. In some embodiments, the visible light emitted by a light emitting diode (LED) in a pedestal below the substrate is partially used to heat the substrate quickly and accurately control its temperature. The visible light may have a wavelength including between 400nm and 800nm. The pedestal may include various features for realizing substrate temperature control, such as a transparent window, and the transparent window may have a lens for advantageously guiding or focusing the emitted light, a reflective material for advantageously guiding or focusing the emitted light, and a temperature control element that helps control the LED, pedestal, and chamber temperature.

[0052] The apparatus may also thermally isolate or thermally "float" the substrate within the process chamber so that only minimal thermal mass is heated, ideally just the substrate itself, which may allow for faster heating and cooling. The substrate may be rapidly cooled using cooling gases and radiative heat transfer to a heat sink, such as a top plate (or other gas distribution element) above the substrate, or both. In some cases, the apparatus may also include temperature control elements within the process chamber walls, pedestal, and top plate (or other gas distribution element) to enable further temperature control of the substrate and process conditions within the chamber, thereby preventing unnecessary condensation of process gases and vapors.

[0053] The device can also be configured to implement a variety of control loops to accurately control the substrate and chamber temperature (e.g., using a controller configured to execute instructions that cause the device to perform these loops). This can include using a variety of sensors to determine the substrate and chamber temperature as part of an open loop and a feedback control loop. These sensors may include a temperature sensor in a substrate support that contacts the substrate and measures its temperature, as well as a non-contact sensor, such as a photodetector that measures the light output of an LED and a pyrometer configured to measure the temperature of different types of substrates. As described in more detail below, some pyrometers determine the temperature of an object by emitting infrared light or other optical signals to the object and measuring the signal reflected or emitted by the object. However, the temperature of many silicon substrates cannot be measured by some pyrometers because silicon is transparent at various temperatures and various processes, such as doped or low-doped silicon. For example, a low-doped silicon substrate with a temperature below 200°C is transparent to infrared light signals. The pyrometer provided herein is capable of measuring various types of silicon substrates at different temperatures.

[0054] Thermal Atomic Layer Etching

[0055] Figure 1 is a process flow diagram describing a method of performing thermal atomic layer etching on a substrate according to some embodiments. The substrate may include one or more features. The one or more features may include a stack of materials with different chemical compositions. The stack may include alternating layers of materials with different compositions. The one or more features may include material to be etched and material not to be etched. In some embodiments, the material to be removed may be silicon nitride. In some embodiments, the material not to be removed may be silicon oxide or silicon. Examples of applications of thermal atomic layer etching according to some embodiments include features in 2D-NAND, 3D-NAND, DRAM, and logic devices. Although Figure 1 A process for producing phosphoric acid from phosphine is described in Figure 1 It should be understood that any phosphorus-containing reactant described herein can be replaced with phosphine and used to generate phosphoric acid.

[0056] The method begins with providing a substrate in operation 102. A transfer tool can be used to provide the substrate in a reaction chamber. Once the substrate is provided in the reaction chamber, the substrate can be supported on a pedestal. After providing the substrate, an optional cleaning step can be performed. Optional cleaning can remove any oxide layer or unwanted material formed on the feature surface on the substrate. In some embodiments, chlorine (Cl)-based plasma, hydrogen fluoride (HF) vapor cleaning, ammonium fluoride (NH4F) cleaning or treatment using other reducing agents can be used to reduce Si oxides that are not desired to be formed on features or substrates. One or more layers described herein can be formed on the substrate by any suitable process (including but not limited to CVD, PECVD, ALD or PEALD) before operation 102. In some embodiments, one or more layers can be adsorbed on the silicon nitride layer.

[0057] In optional operation 104, water vapor is supplied to the interior of the chamber according to the process recipe. In some embodiments, the controller and switching system can control the flow rate and duration of the water vapor entering the interior of the chamber. In some embodiments, the flow rate and duration of the water vapor can be configured so that the water vapor does not condense on the surface of the silicon nitride layer. For example, about one to about ten monolayers of water molecules can be adsorbed on the surface of the feature. One or more monolayers of water molecules can be configured to uniformly cover the surface of the feature on the substrate or the surface of the silicon nitride layer.

[0058] Temperature and pressure can affect the amount of water molecules adsorbed. For example, the amount of water adsorbed on the surface may be inversely proportional to the temperature and directly proportional to the pressure. During optional operation 104, the substrate temperature may be between about 0°C and 100°C, or between about 10°C and 50°C, or between about 10°C and 30°C, or about 20°C. In some embodiments, the chamber temperature may be substantially the same as the substrate temperature. In some embodiments, the chamber temperature, the temperature of the substrate, the temperature of the silicon nitride layer, and / or the temperature of the water vapor may be configured to be substantially the same as each other. The chamber pressure during operation 104 may be adjusted to between about 1 Torr and 100 Torr, or between about 5 Torr and 50 Torr, or about 10 Torr.

[0059] In operation 106, a phosphorus-containing reactant may be provided. In one example, the phosphorus-containing reactant may be a gaseous reactant. One example may include gaseous phosphine. On the other hand, it should be understood that Figure 1 The process flow in is not limited to phosphine. That being said, according to some embodiments, other phosphorus-containing reactants may also be replaced with phosphine to generate phosphoric acid in situ on the surface of silicon nitride. For example, phosphine, phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkylphosphine halides, trimethylphosphine, triethylphosphine, tripropylphosphine and / or mixtures thereof may be used as phosphorus-containing reactants.

[0060] When water vapor is provided to the surface of the silicon nitride at operation 104, phosphine can react with water to form phosphoric acid (H3PO4) in situ. The reaction of phosphine with water can increase the solubility of phosphine in water and promote the formation of phosphoric acid. In the absence of water molecules adsorbed on the feature surface by providing water vapor, phosphine can still react with water molecules (moisture) in the reaction chamber to form phosphoric acid.

[0061] The amount of phosphoric acid produced by the reaction with water may depend on, for example, the relative amount of water in the chamber atmosphere relative to the amount of phosphine. In some embodiments, a portion of the phosphine may be consumed to react with water in the chamber atmosphere to produce phosphoric acid, while a portion of the phosphine may still remain unreacted on the surface of the feature. For example, depending on the amount of phosphine, excess phosphine may not react with water and may remain unreacted on the surface of the silicon nitride layer. Thus, a mixture of phosphine and phosphoric acid may be present on the surface of the silicon nitride layer. In some embodiments, the substrate temperature and chamber pressure during operation 106 may be substantially the same as operation 104. For example, the substrate temperature in operation 106 may be between about 0°C and 100°C, or between about 0°C and 50°C, or between about 10°C and 30°C, or about 20°C. The chamber pressure in operation 106 may be adjusted to between about 1 Torr and 100 Torr, or between about 5 Torr and 50 Torr, or between about 10 Torr.

[0062] In operation 108, one or more oxidants may be provided to the reaction chamber. The oxidants may react with the phosphine on the surface of the silicon nitride layer, wherein unreacted phosphine remains. The phosphine may be oxidized by the one or more oxidants to form phosphorus oxide (P2O5). The P2O5 may be hydrated by water that may be present on or near the surface of the silicon nitride, thereby generating phosphoric acid in situ. Examples of oxidants include oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (N2O), nitrogen dioxide (NO2), and / or mixtures thereof.

[0063] It should be understood that although operations 106 and 108 may be performed sequentially as described, operations 106 and 108 may be performed simultaneously or substantially simultaneously. In one example, phosphine and ozone (or oxygen or other oxidants) may flow into the chamber interior together through the fluid inlet. Phosphine may react with water (from the reaction chamber atmosphere or water vapor provided to the substrate surface in optional operation 104) to generate phosphoric acid in situ. Simultaneously or substantially simultaneously, unreacted phosphine may be oxidized by the oxidant and hydrated to form phosphoric acid. The substrate temperature and chamber pressure during operation 108 may be maintained substantially the same as the substrate temperature and chamber pressure during operations 104 and / or 106.

[0064] In operation 110, water vapor may be supplied to the reaction chamber. In some embodiments, the flow rate and duration of the water vapor may be configured to avoid condensation of the water vapor on the features. Providing additional water vapor in operation 110 may increase the concentration and / or reactivity of the phosphoric acid. Thus, the etch rate of the silicon nitride layer in operation 110 may be greater than the etch rate in operations 106 and / or 108. The substrate temperature and chamber pressure during operation 110 may be maintained substantially the same as the substrate temperature and chamber pressure in operations 104-108.

[0065] In operation 112, the substrate temperature may be increased to above 100°C, or to between about 100°C and about 180°C, or to between about 120°C and about 180°C. In some embodiments, the substrate temperature may be configured to be increased before operation 112 begins. Increasing the substrate temperature in operation 112 may increase the etching rate of silicon nitride. In operation 112, a faster heating rate may obtain a more uniform nitride etching. For example, the substrate temperature may be configured to be increased at a heating rate of about 20°C / second. Therefore, operation 112 may involve significant etching of the silicon nitride layer. The etching rate of the silicon nitride layer in operation 112 may be significantly greater than the etching rate in other operations. For example, most or substantially all of the etching processes may be performed in operation 112. During the nitride etching in operation 112, one or more etching byproducts may be generated. One or more etching byproducts may contain silicon or phosphorus, which may be non-volatile. The pressure in operation 112 may be configured to range between about 1 Torr and about 100 Torr.

[0066] According to some embodiments, nitride etching can be a dry etching process, which is performed by providing gaseous and / or vapor reactants to the surface of the silicon nitride layer in the feature. The silicon nitride layer is etched by exposing the silicon nitride layer to phosphoric acid generated in situ. Phosphoric acid can be generated in situ by a combination of different reaction pathways. For example, the water vapor in operation 104 can increase the solubility of the phosphine (or other phosphorus-containing reactants) provided in operation 106, and generate phosphoric acid in situ. Phosphoric acid can be generated by hydrated phosphorus oxide (P2O5), which is formed by reacting phosphine (or other phosphorus-containing reactants) with one or more oxidants. Regardless of the approach, the generated phosphoric acid may include gaseous etching chemicals. Therefore, according to some embodiments, phosphoric acid can be uniformly covered and adsorbed on the surface of the feature without providing excessive etching chemicals to local areas on the substrate. This is particularly advantageous for semiconductor devices including high-density, smaller-size features, where uneven, excessive etching chemicals may lead to uneven etching rates, and endanger the structural stability of the feature and increase the probability of device failure.

[0067] At operation 114, one or more etching byproducts may be removed by thermal treatment or a combination of chemical and thermal treatment. In one example, orthosilicic acid (Si(OH)4) may be present on the surface of silicon nitride as an etching byproduct. Si(OH)4 may be non-volatile. Si(OH)4 on the substrate may be heated to above about 100°C, or above 120°C, or between about 100°C and about 120°C, or above 130°C, or above 140°C, or above 150°C, while reacting with hydrogen fluoride (HF) vapor. This combination of chemical and thermal treatment may generate volatile silicon tetrafluoride (SiF4) without substantially reacting with other adjacent materials, such as silicon or silicon oxide (SiO2), because HF does not react with silicon oxide at high temperatures without water. Volatile SiF4 may be removed from the reaction chamber.

[0068] In another example, excess phosphoric acid may remain on the surface of the silicon nitride layer without being completely consumed in operations 106-112. The substrate may be heated to above 100°C to remove any water molecules from the phosphoric acid, thereby leaving P2O5 on the substrate surface. HF vapor may be supplied to P2O5 to form volatile phosphorus-containing byproducts, such as phosphorus pentafluoride (PF5). Alternatively, P2O5 may be removed by sublimation without the aid of HF or other reducing agents. The boiling point of P2O5 may be about 350-360°C. Further heating the substrate with remaining P2O5 to above about 360°C, or above about 375°C, or above about 400°C may sublime the P2O5 from the features, thereby making the features free of P2O5. The sublimation duration may range from about 5 seconds to about 600 seconds.

[0069] After operation 114 is completed, it may be determined whether to further etch the features or substrate including the silicon nitride layer according to the device design. In the case where the silicon nitride layer may require further etching, operations 104-114 (or operations 106-114) may be repeated until the desired etching is obtained. For example, the number of cycles of the nitride atomic layer etching may depend on the size of the feature, such as the depth of the silicon nitride layer in the stack, etc.

[0070] After operation 114, subsequent processes may be optionally performed. For example, after removing etching byproducts from the silicon nitride surface as described herein, one or more silicon-containing layers may be deposited. One or more silicon-containing layers may be formed in a suitable deposition process (e.g., CVD, PECVD, ALD, PEALD, or any other deposition technique). In another example, another substrate may be transferred to a reaction chamber for etching of the silicon nitride layer. It is noteworthy that the reaction chamber may be configured to deposit one or more oxide layers, nitride layers, carbide layers, oxynitride layers, carbon oxide layers, or carbon oxide layers associated with one or more metal elements, or to deposit one or more metal layers, and selectively etch at least a portion of the layer deposited before the selective etching without breaking the vacuum and without exposing the substrate to the surrounding atmosphere.

[0071] Device

[0072] Figure 2A A cross-sectional side view of an exemplary apparatus according to some embodiments is depicted. As described below, the apparatus 200 is capable of quickly and accurately controlling the temperature of a substrate, including performing a thermal etching operation, one example of which is the Prevos 100 manufactured by Lam Research Corporation (Fremont, California). TM Selective etching tool.

[0073] The apparatus 200 includes a processing chamber 202, a pedestal 204 having a plurality of substrate supports 208 configured to support a substrate 218, and a gas distribution unit 210. The processing chamber 202 includes sidewalls 212A, a top 212B, and a bottom 212C that at least partially define a chamber interior 214, which can be considered a plenum volume. As described herein, in some embodiments, it may be desirable to actively control the temperature of the processing chamber walls 212A, the top 212B, and the bottom 212C to prevent undesirable condensation from occurring on their surfaces. Some emerging semiconductor processing operations flow vapors (e.g., water and / or alcohol vapors) onto a substrate, which adsorb onto the substrate, but may also undesirably adsorb onto the interior surfaces of the chamber. This can result in undesirable deposition and etching on the interior surfaces of the chamber, which can damage the chamber surfaces and cause particles to flake onto the substrate, thereby causing substrate defects. In order to reduce and prevent undesirable condensation from occurring on the chamber surfaces, the temperature of the chamber walls, top, and bottom can be maintained at a temperature at which chemicals used in the processing operation will not condense.

[0074] Active temperature control of the chamber surfaces may be achieved by using heaters to heat the chamber walls 212A, top 212B, and bottom 212C. Figure 2AAs shown, chamber heater 216A is located on chamber wall 212A and configured to heat it, chamber heater 216B is located on top 212B and configured to heat it, and chamber heater 216C is located on bottom 212C and configured to heat it. Chamber heaters 216A-216C can be resistive heaters, which are configured to generate heat when current flows through resistive elements. Chamber heaters 216A-216C can also be fluid conduits, and heat transfer fluid can flow through the fluid conduits, such as heating fluid, which can include heated water. In some examples, chamber heaters 216A-216C can be a combination of heating fluid and resistive heaters. The chamber heaters 216A-216C are configured to generate heat to bring the interior surface of each chamber wall 212A, top 212B, and bottom 212C to a desired temperature, which may range between about 40°C and about 400°C, between about 40°C and about 250°C, between about 40°C and about 150°C, including, for example, between about 80°C and about 130°C, or about 90°C, or about 120°C. It has been found that under some conditions, water and alcohol vapors do not condense on surfaces maintained at about 90°C or higher. Although Figure 2A Not shown, but the chamber heaters 216A-216C may include one or more temperature sensors operably coupled to the chamber heaters 216A-216C to monitor the chamber temperature.

[0075] The chamber walls 212A, top 212B, and bottom 212C may also be constructed of various materials that can withstand the chemicals used in the process technology. These chamber materials may include, for example, aluminum, anodized aluminum, aluminum with a polymer (e.g., plastic), metals or metal alloys with yttria coatings, metals or metal alloys with zirconium oxide coatings, and metals or metal alloys with aluminum oxide coatings; in some examples, the coating material may be a mixed or different material combination of layers, such as alternating layers of aluminum oxide and yttria, or alternating layers of aluminum oxide and zirconium oxide. These materials are configured to withstand the chemicals used in the process technology, such as any anhydrous HF, water vapor, methanol, isopropyl alcohol, chlorine, fluorine, nitrogen, hydrogen, helium, and / or mixtures thereof.

[0076] The apparatus 200 may also be configured to perform processing operations under vacuum or near vacuum, such as at a pressure of about 0.1 Torr to about 100 Torr, about 20 Torr to about 200 Torr, about 0.1 Torr to about 10 Torr, or about 10 Torr. The apparatus 200 may include a vacuum pump 284 configured to evacuate the chamber interior 214 to a low pressure, such as a vacuum having a pressure of about 0.1 Torr to about 100 Torr (including about 0.1 Torr to about 10 Torr, about 20 Torr to about 200 Torr, about 0.1 Torr to about 10 Torr, or about 10 Torr).

[0077] Various features of the base 204 will now be discussed. The base 204 includes a heater 222 (at Figure 2A ), which has a plurality of LEDs 224 configured to emit visible light (whose wavelength includes and is between 400nm and 800nm, including 450nm). The heater LEDs emit this visible light to the back side of the substrate, thereby heating the substrate. Visible light with a wavelength of about 400nm to 800nm ​​can quickly and efficiently heat a silicon substrate from ambient temperature (e.g., about 20°C) to a temperature as high as about 600°C because silicon absorbs visible light in this range. In contrast, radiative heating (including infrared light radiation) heating may not be able to efficiently heat silicon to temperatures as high as about 400°C because silicon tends to be transparent to infrared light at temperatures below about 400°C. In addition, radiative heaters that directly heat the top side of the substrate, as in many conventional semiconductor processes, can cause damage or other adverse effects to the top side film. Many "hot plate" heaters that rely on solid-to-solid heat transfer between a substrate and a heated plate (e.g., a susceptor with a heating coil) have relatively slow heating and cooling rates and provide uneven heating, which may be caused by substrate warping and inconsistent contact with the heated plate. For example, it may take several minutes to heat some susceptors to a desired temperature, to heat from a first higher temperature to a second higher temperature, and to cool the susceptor to a lower temperature.

[0078] The multiple LEDs of the heater can be arranged, electrically connected, and electrically controlled in a variety of ways. Each LED can be configured to emit visible blue light and / or visible white light. In certain embodiments, white light (generated using a wavelength range in the visible portion of the EM spectrum) is used. In some semiconductor processing operations, white light can reduce or prevent undesirable film interference. For example, some substrates have backside films that reflect different amounts of different wavelengths of light, thereby causing uneven and potentially inefficient heating. The use of white light can reduce this undesirable reflection variation by averaging the film interference over the wide visible spectrum range provided by white light. In some instances, depending on the material on the back of the substrate, it may be advantageous to use a visible non-white light (e.g., blue light having a wavelength of 450 nm), for example to provide a single or narrowband wavelength that can provide more efficient, more powerful, and more direct heating to some substrates that may have better absorption for narrowband wavelengths than white light.

[0079] A variety of types of LEDs may be employed. Examples include chip-on-board (COB) LEDs or surface mount diode (SMD) LEDs. For SMD LEDs, the LED chip may be fused to a printed circuit board (PCB), which may have multiple electrical contacts that enable control of the individual diodes on the chip. For example, a single SMD chip may have three diodes that may be individually controlled to produce different colors (e.g., red, blue, or green). The size range of SMD LED chips may be, for example, 2.8×2.5 mm, 3.0×3.0 mm, 3.5×2.8 mm, 5.0×5.0 mm, and 5.6×3.0 mm. For COB LEDs, each chip may have more than 3 diodes (e.g., nine, 12, dozens, hundreds, or more) printed on the same PCB. Regardless of the number of diodes, a COB LED chip typically has one circuit and two contacts, thus providing a simple design and efficient single-color applications. The ability and performance of an LED to heat a substrate may be measured by the wattage of heat given off by each LED; these watts of heat may directly contribute to heating the substrate.

[0080] Figure 2B A top view of a substrate heater with a plurality of LEDs is depicted. The substrate heater 222 includes a printed circuit board 226 and a plurality of LEDs 224, some of which are labeled; the depicted plurality includes approximately 1,300 LEDs. External connections 228 are connected via traces to provide power to the plurality of LEDs 224. Figure 2B As shown, the LEDs may be arranged along a plurality of arcs that are radially offset from the center 230 of the substrate heater 222 at different radii; in each arc, the LEDs may be equally spaced from each other. For example, one arc 232 is encircled by a partially shaded dotted shape, includes 16 LEDs 224, and is a portion of a circle of radius R that extends around the center 230. The 16 LEDs 224 may be considered to be equally spaced from each other along the arc 232.

[0081] In some embodiments, the LEDs may also be arranged along a circle around the center of the substrate heater. In some examples, some LEDs may be arranged along a circle, while others may be arranged along an arc. Figure 2C Depicted is a top view of another example of a substrate heater having multiple LEDs. Figure 2C The substrate heater 222 of FIG. 1 includes a printed circuit board 226 and a plurality of LEDs 224, some of which are labeled. Here, the LEDs 224 are arranged along a plurality of circles that are radially offset from a center 230 of the substrate heater 222 at different radii; within each circle, the LEDs may be equally spaced from one another. For example, a circle 234 is encircled by a partially shaded ring, includes 78 LEDs 224, and has a radius R extending around the center 230. The 78 LEDs 224 may be considered to be equally spaced from one another along the circle 234. Figure 2B Compared with the arrangement in Figure 2C The arrangement of LEDs in the substrate provides a more uniform light and heat distribution pattern across the back side of the substrate because Figure 2B Substrate heater 222 in areas containing external connections may provide unheated cold spots on the substrate, particularly because the substrate and heater remain stationary relative to each other during processing; the substrate and substrate heater do not rotate.

[0082] In some embodiments, the plurality of LEDs may include at least about 1,000 LEDs, such as about 1,200, 1,500, 2,000, 3,000, 4,000, 5,000 or more than 6,000. In some instances, each LED may be configured to use about 4 watts or less at 100% power, including about 3 watts at 100% power and about 1 watt at 100% power. The LEDs may be arranged and electrically connected to individually controllable regions to achieve temperature adjustment and fine-tuning across the substrate. In some instances, the LEDs may be grouped into at least 20, for example, independently controllable regions, such as at least about 25, 50, 75, 80, 85, 90, 95 or 100 regions. These regions may enable temperature adjustment in radial and azimuthal (i.e., angular) directions. These regions may be arranged in a defined pattern, such as in a rectangular grid, a hexagonal grid, or other suitable pattern for generating a desired temperature profile. The regions may also have different shapes, such as square, trapezoid, rectangle, triangle, oblong, ellipse, circle, annular (e.g., ring), partial annular (e.g., ring sector), arc, segmental, and a sector centered at the center of the heater and having a radius less than or equal to the total PCB radius of the substrate heater. For example, in FIG. 2 , the LED has 88 regions, which are organized into at least 20 (e.g., 20 or 21) concentric rings. These regions can adjust the temperature at many locations across the substrate to produce a more uniform temperature distribution and a desired temperature curve, such as a temperature around the edge of the substrate that is higher than the temperature at the center of the substrate. Independent control of these regions may also include the ability to control the power output of each region. For example, each region may have at least 15, 20, or 25 adjustable power outputs. In some instances, each region may have one LED, thereby enabling each LED to be individually controlled and adjusted, which may result in a more uniform heating curve on the substrate. Therefore, in some embodiments, each of the multiple LEDs in the substrate heater may be individually controllable.

[0083] In some embodiments, the substrate heater 222 is configured to heat the substrate to a plurality of temperatures and maintain each such temperature for various durations. The substrate heater may be configured to heat the substrate to between about 50°C and 600°C, including any temperature or range between these temperatures. In addition, in some embodiments, the substrate heater 222 is configured to heat the substrate to any temperature within these ranges in, for example, less than about 60 seconds, less than about 45 seconds, less than about 30 seconds, or less than about 15 seconds. In some embodiments, the substrate heater 222 is configured to heat the substrate at one or more heating rates, for example, between at least about 0.1°C / second and at least about 20°C / second.

[0084] The substrate heater can increase the temperature of the substrate by causing the LED to emit visible light at one or more power levels, including at least about 80%, at least about 90%, at least about 95%, or at least about 100% power. In some embodiments, the substrate heater is configured to emit light between 10 W and 4000 W, including at least about 10 W, at least about 30 W, at least about 0.3 kilowatts (kW), at least about 0.5 kW, at least about 2 kW, at least about 3 kW, or at least about 4 kW. The device is configured to provide a power between about 0.1 kW and 9 kW to the base; the power supply source is connected to the substrate heater through the base, but is not shown in the figure. During the temperature rise, the substrate heater can be operated at high power and can be operated at a lower power level (e.g., including between about 5 W and about 0.5 kW) to maintain the temperature of the heated substrate.

[0085] The pedestal may include a reflective material on its inner surface that reflects and directs light emitted by the LEDs to the back side of the substrate supported by the pedestal during operation. In some such embodiments, the substrate heater may include such a reflective material located on the top surface 240 of the PCB 226, such as Figure 2A As shown, a plurality of LEDs 224 are located on the top surface 240. The reflective material may include aluminum, such as polished aluminum, stainless steel, aluminum alloys, nickel alloys, and other protective layers that can prevent metal oxidation and / or enhance reflectivity at specific wavelengths (e.g., reflectivity greater than 99% for specific wavelengths), as well as other durable reflective coatings. Additionally or alternatively, the base 204 may have a bowl 246 in which the substrate heater 222 is at least partially located. The bowl 246 may have an exposed inner surface 248 of a base sidewall 249, on which the reflective material may be located. The reflective material improves the heating efficiency of the substrate heater and reduces undesired heating of the PCB 226 and the base 204 by advantageously directing light back onto the substrate (otherwise the light would be absorbed by the PCB 226 and the base 204).

[0086] In some embodiments, the substrate heater may further include a pedestal cooler that is thermally coupled to the LEDs such that heat generated by the plurality of LEDs can be transferred from the LEDs to the pedestal cooler. The thermal coupling allows heat to be conducted from the plurality of LEDs to the pedestal cooler along one or more heat flow paths between these components. In some instances, the pedestal cooler is in direct contact with one or more elements of the substrate heater, while in other instances, other conductive elements, such as a thermally conductive plate (e.g., comprising metal) are interposed between the substrate heater and the pedestal cooler. Return to Reference Figure 2A , the substrate heater includes a pedestal cooler 236 in direct contact with the bottom of the PCB 226. Heat is configured to flow from the LED to the PCB 226 and to the pedestal cooler 236. The pedestal cooler 236 also includes a plurality of fluid conduits 238 through which a heat transfer fluid (e.g., water) is configured to flow to receive heat and thereby cool the LEDs in the substrate heater 222. The fluid conduits 238 may be connected to a container and pump (not shown) located outside the chamber. In some examples, the pedestal cooler may be configured to flow cooled water (e.g., between about 5°C and 20°C).

[0087] As provided herein, it may be advantageous to actively heat the exterior surfaces of the processing chamber 202. In some instances, it may also be advantageous to heat the exterior surfaces of the susceptor 204 to prevent unwanted condensation and deposition on the exterior surfaces thereof. Figure 2A As shown, the pedestal 204 may further include a pedestal heater 244 inside the pedestal 204, which is configured to heat the outer surface of the pedestal 204, including its side 242A and bottom 242B. The pedestal heater 244 may include one or more heating elements, such as one or more resistive heating elements and a fluid conduit in which the heating fluid is configured to flow. In some examples, the pedestal cooler and the pedestal heater may have fluid conduits that are fluidly connected to each other so that the same heat transfer fluid can flow in both the pedestal cooler and the pedestal heater. In these embodiments, the fluid can be heated to between 50°C and 130°C, including about 90°C and 120°C.

[0088] The pedestal may also include a window to protect the substrate heater including the plurality of LEDs from damage due to exposure to the processing chemicals and pressures used during the processing operation. Figure 2AAs shown, window 250 may be located above substrate heater 222 and may be sealed to sidewall 249 of base 204 to create a gas-filled chamber volume in the base that is isolated from the fluid inside the chamber. The gas-filled chamber volume may also be considered as the interior of bowl 246. The window may be made of one or more materials that are transparent to visible light emitted by the LED (including light with a wavelength in the range of 400nm to 800nm). In some embodiments, the material may be quartz, sapphire, quartz with a sapphire coating, or calcium fluoride (CaF). There may also be no holes or openings in the window. In some embodiments, the heater may have a thickness of about 15 to 30 mm, including about 20 mm and about 25 mm.

[0089] Figure 2D Depicted are various embodiments having additional features. Figure 2A The base. Figure 2D As shown, the window 250 includes a top surface 252 facing the substrate 218 supported by the base 204 and a bottom surface 254 facing the substrate heater 222. In some embodiments, the top surface 252 and the bottom surface 254 can be flat planar surfaces (or substantially flat, for example, within ±10% or 5% of the flatness). In some other examples, the top 252, the bottom 254, or both the top 252 and the bottom 254 can be non-planar surfaces. The non-planarity of these surfaces can be configured to refract and / or guide the light emitted by the LED 224 of the substrate heater 222 to heat the substrate more efficiently and / or effectively. The non-planarity can also be along part or all of the surface. For example, the entire bottom surface can have a convex or concave curvature, and in another example, the outer annular area of ​​the bottom surface can have a convex or concave curvature, while the rest of the surface is flat. In further examples, the surfaces may have multiple but different non-planar portions, such as a conical portion at the center of the surface adjacent to a planar annular portion adjacent to the conical frustum surface at the same or different angles as the conical portion. In some embodiments, the window 250 may have features as a lens array oriented to focus light emitted by one or more LEDs (e.g., each LED).

[0090] Since the window 250 is located above the substrate heater 222, the window 250 is heated by the substrate heater 222, which affects the thermal environment around the substrate. Depending on the one or more materials used for the window 250, such as quartz, the window can retain heat and gradually retain more heat during the process of processing one or more substrates. The heat can be transferred to the substrate by radiation, thereby directly heating the substrate. In some instances, the window causes the temperature to increase by between 50°C and 80°C over the heater temperature. The heat may also produce a temperature gradient across the entire thickness or vertical direction of the window. In some instances, the top surface 252 is 30°C hotter than the bottom surface 254. Therefore, it may be advantageous to adjust and configure the chamber to address and reduce the thermal effects of the window. This may include detecting the temperature of the substrate and adjusting the substrate heater to address the heat retained by the window.

[0091] This may also include various configurations of the base, such as actively cooled windows. Figure 2A and 2D As shown, the window 250 can be offset from the substrate heater 222 by a first distance 256. In some embodiments, the first distance can be between about 2 mm and 50 mm, including between about 5 mm and 40 mm. A cooling fluid, such as an inert gas, can flow between the window 250 and the substrate heater 222 to cool both the window 250 and the substrate heater 222. The base can have one or more inlets and one or more outlets for flowing such gas within a plenum volume or bowl 246 of the base 204. The one or more inlet fluids are connected to a source of inert gas external to the processing chamber 202, which can include a through fluid conduit that can have a path at least partially within the base 204. The one or more outlet fluids are connected to an exhaust device or other environment external to the processing chamber 202, which can also be a through fluid conduit extending within the base. Figure 2E , which depicts a plurality of embodiments having additional features Figure 2D pedestal 204, one or more inlets 251 are located in the sidewall 249 and extend through the inner surface 248; the one or more inlets are also fluidly connected to the inert gas source 272 (e.g., an inert gas source) in part by way of a fluid conduit 255 that passes through the pedestal 204. A single outlet 253 is located in a central region of the substrate heater 222, i.e., not at the exact center but proximate to the center. In some embodiments, the one or more gas inlets and the one or more outlets are switchable so that one or more outlets extend through the sidewall 249 (i.e., they are Figure 2E 251), and the one or more inlets may be a central region of the substrate heater 222 (i.e., Figure 2E253 in the figure). In some embodiments, there may be more than one outlet; in some embodiments, there may be only a single gas inlet. In some embodiments, one or more gas inlets extend through the inner surface 248 of the base sidewall 249 below the LED heater 222, and one or more gas outlets extend through another portion of the base sidewall 249, such as a mounting bracket between the LED heater 222 and the base sidewall 249.

[0092] In some embodiments, the window may be placed in direct thermal contact with the substrate heater, and the pedestal cooler may be configured to cool both the PCB and the window. Figure 2A and Figure 2D As shown, the window 250 can be thermally connected to the sidewall 249 of the base 204 to transfer some of the heat retained in the window 250 to the base 204. The transferred heat can be further transferred out of the base using, for example, a base heater 244, which can flow a fluid heated to, for example, between about 20° C. and 100° C. through the base 204. The heated fluid will be cooler than the temperature of the base 204 thermally connected to the window 250. In some embodiments, the window 250 can have one or more fluid conduits located within the window 250, and a transparent cooling fluid can be configured to flow through the fluid conduits. The fluid can be routed from a fluid source or container outside the chamber through the base to the window.

[0093] like Figure 2A and 2D As shown, the substrate support 208 of the pedestal 204 is configured to support the substrate 218 above and away from the window 250 and the substrate heater 222. In certain embodiments, the temperature of the substrate can be quickly and accurately controlled by thermally floating or thermally isolating the substrate within the chamber. It is desirable to arrange the substrate to heat and cool the minimum thermal mass. The thermal floatation is arranged to arrange the substrate so that it has minimal thermal contact (both direct and radiant) with other objects in the chamber.

[0094] Thus, the pedestal 204 is configured in some embodiments to support a substrate 218 by thermally floating or thermally isolating the substrate within the chamber interior 214. The plurality of substrate supports 208 of the pedestal 204 are configured to support the substrate 218 such that the thermal mass of the substrate 218 is reduced as much as possible to only the thermal mass of the substrate 218. Each substrate support 208 can have a substrate support surface 220 that provides minimal contact with the substrate 218. The number of substrate supports 208 can range from at least 3 to, for example, at least 6 or more. The surface area of ​​the support surface 220 can also be the minimum area required to adequately support the substrate during processing operations (e.g., to support the weight of the substrate and prevent inelastic deformation of the substrate).

[0095] The substrate support is also configured to prevent the substrate from contacting other elements of the pedestal, including the surface of the pedestal and features beneath the substrate. Figure 2A and 2D As seen in FIG. 1 , the substrate support 108 holds the substrate 218 above and offset from the next adjacent surface of the pedestal 204 below the substrate 218, which is the top surface 252 of the window 250 (identified at Figure 2D ). It can be seen from these figures that in addition to the contact with the substrate support, there is a volume or gap below the substrate. Figure 2D As shown, substrate 218 is offset from top surface 252 of window 250 by distance 258. This distance 258 affects the thermal effect caused by window 250 on substrate 218. The greater the distance 258, the less the effect. It has been found that a distance 258 of 2 mm or less results in significant thermal coupling between the window and the substrate; thus, a distance 258 greater than 2 mm is desirable, such as at least about 5 mm, about 10 mm, about 15 mm, about 20 mm, about 30 mm, about 50 mm, or about 100 mm.

[0096] The substrate 218 is also offset from the substrate heater 222 (in some examples, measured from the top surface of the substrate heater 222, which can be the top surface of the LED 224) by a distance 260. The distance 260 affects many aspects of heating the substrate 218. In some embodiments, a distance 260 of between about 10 mm and about 90 mm, between about 5 mm and about 100 mm, such as between about 10 mm and 30 mm, provides a substantially uniform heating pattern and acceptable heating efficiency.

[0097] As described above, the substrate supports 208 are configured to support the substrate 218 above the window. In some embodiments, these substrate supports are stationary and fixed in place; they are not lift pins or support rings. In some embodiments, at least a portion of each substrate support 208 including the support surface 220 can be composed of a material that is transparent to at least the light emitted by the LED 224. The material can be quartz or sapphire in some examples. The light transparency of these substrate supports 208 can enable visible light emitted by the LED 224 of the substrate heater 222 to pass through the substrate support 208 and reach the substrate 218, so that the substrate support 208 does not block the light and the substrate 218 can be heated in the area where it is supported. Compared to a substrate support including a material that is transparent to the visible light portion, this can provide more uniform heating of the substrate 218. In some other embodiments, the substrate support 208 can be composed of an opaque material, such as zirconium dioxide (ZrO2).

[0098] In some embodiments, the pedestal may be configured to directly support the substrate (not shown). The pedestal may be configured with lift pins or other movable support members to position the substrate in a deposition zone in the environment of the substrate. The substrate may move in a vertical direction in the chamber. In some embodiments, the pedestal includes an electrostatic chuck. The electrostatic chuck may be the uppermost portion of the pedestal and may include one or more electrostatic clamping electrodes embedded in the body of the electrostatic chuck. The substrate may be supported on the top surface of the electrostatic chuck. In some embodiments, one or more electrostatic clamping electrodes may be coplanar or substantially coplanar. The electrostatic clamping electrodes may be powered by a DC power supply or a DC clamping voltage (e.g., between about 200V and about 2000V) so that the substrate may be held on the electrostatic chuck by electrostatic attraction. Power to the electrostatic clamping electrodes may be provided by a first wire connected to the electrostatic clamping electrodes. The electrostatic chuck may also include one or more heating elements embedded in the body of the electrostatic chuck. The one or more heating elements may include a resistive heater. In some embodiments, the one or more heating elements are located below the one or more electrostatic clamping electrodes. The one or more heating elements may be configured to heat the substrate to a temperature greater than about 200° C., greater than about 450° C., greater than about 500° C., greater than about 550° C., greater than about 600° C., or greater than about 650° C. The one or more heating elements provide selective temperature control for the substrate. Power to the one or more heating elements may be provided by a second wire connecting the one or more heating elements to a power source.

[0099] In some embodiments, for example Figure 2D , the substrate supports 208 can be disposed closer to the central axis 262 of the window than the outer diameter 264 of the window 250. In some examples, a portion of these substrate supports can extend above and on the window 250.

[0100] In some embodiments, the substrate supports may each include a temperature sensor configured to detect a temperature of a substrate located on a supporting surface of the substrate support. Figure 2F Depicted is a schematic diagram of a device according to the disclosed embodiment. Figure 2A and 2D208 and the substrate support. Here, the support surface 220 of the substrate support 208 and the temperature sensor 266 are marked. In some embodiments, the temperature sensor 166 extends through the support surface 120 so that the temperature sensor 266 is in direct contact with the substrate held by the support surface 220. In some other embodiments, the temperature sensor 266 is located within the substrate support 208 and below the support surface 220. In some embodiments, the temperature sensor 266 is a thermocouple. In some other embodiments, the temperature sensor 266 can be a thermistor, a resistance temperature detector (RTD), and a semiconductor sensor. The wire 268 for the temperature sensor 266 can be routed through the substrate support 208 and can also be routed through the base 204.

[0101] Return to reference Figure 2A In some embodiments, the susceptor is also configured to move vertically. This may include moving the susceptor so that the gap 286 between the face plate 276 of the gas distribution unit 210 and the substrate 218 can be in a range of between about 2 mm and 70 mm. Moving the susceptor vertically may enable active cooling of the substrate and fast cycle times for processing operations, including flowing and flushing gases, because it creates a small volume between the gas distribution unit 210 and the substrate 218. The movement may also create a small process volume between the substrate and the gas distribution unit, which may result in smaller flushing and process volumes, thereby reducing flushing and gas movement times and increasing throughput.

[0102] The gas distribution unit 210 is configured to flow a process gas (which may include liquids and / or gases, such as reactants, modifying molecules, converting molecules, or removing molecules) onto a substrate 218 in the chamber interior 214. In some embodiments, the process gas may include phosphine. In some embodiments, the process gas may include hydrogen fluoride (HF), oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2), or a combination thereof. Figure 2AAs shown, the gas distribution unit 210 includes one or more fluid inlets 270, which are fluidly connected to one or more gas sources 272 and / or one or more vapor sources 274. The gas distribution unit 110 and other units or components that can fluidly contact the process gas can be designed and manufactured to be chemically resistant or chemically inert to the process gas. In some embodiments, the gas pipelines and mixing chambers can be heated to prevent the undesirable condensation of the vapor and gas flowing therein. These pipelines can be heated to at least about 40°C, at least about 80°C, at least about 90°C, at least about 100°C, at least about 120°C, at least about 130°C, or at least about 150°C. The one or more vapor sources may include one or more gas and / or liquid sources that are vaporized. In some embodiments, one or more gas and / or liquid sources include water vapor, alcohol (including but not limited to methanol, ethanol, isopropanol, butanol), phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxy phosphine, alkyl phosphine halides, trimethyl phosphine, triethyl phosphine, tripropyl phosphine and / or mixtures thereof. In some embodiments, one or more gas and / or liquid sources may be provided in the form of a fine spray by an atomizer without heating one or more gas and / or liquid sources to a high temperature. In some embodiments, one or more gas and / or liquid sources may be further diluted by one or more suitable solvents or liquids suitable for atomization. Vaporization may be a direct injection vaporizer, a flow-through vaporizer, or both. In some embodiments, one or more vapor sources and one or more process gases may be configured to operate sequentially or simultaneously. For example, a vapor source (e.g., water vapor) and a process gas (e.g., phosphine) may be supplied sequentially or simultaneously to the interior of the reaction chamber. The gas distribution unit 210 also includes a panel 276, which includes a plurality of through holes 278 that fluidly connect the gas distribution unit 210 to the interior 214 of the chamber. These through holes 278 are fluidly connected to the one or more fluid inlets 270 and also extend through the front surface 277 of the panel 276, which is configured to face the substrate 218. In some embodiments, the gas distribution unit 210 may be considered as a top plate, and in some other embodiments, it may be considered as a showerhead.

[0103] The through holes 278 can be configured in various ways to deliver a uniform gas flow to the substrate. In some embodiments, the through holes can all have the same outer diameter, such as between about 0.03 inches and 0.05 inches, including about 0.04 inches (1.016 mm). The panel through holes can also be arranged throughout the panel to produce a uniform flow out of the panel.

[0104] Return to reference Figure 2A, the gas distribution unit 210 may also include a unit heater 280 that is thermally connected to the panel 276 so that heat can be transferred between the panel 276 and the unit heater 280. The unit heater 280 may include a fluid conduit through which a heat transfer fluid may flow. Similar to the above, the heat transfer fluid may be heated to a temperature range of, for example, about 20° C. to 120° C. In some examples, the unit heater 280 may be used to heat the gas distribution unit 210 to prevent unwanted condensation of vapor and gas; in some such examples, the temperature may be at least about 90° C. or 120° C.

[0105] In some embodiments, the gas distribution unit 210 may include a second unit heater 282 configured to heat the panel 276. The second unit heater 282 may include one or more resistive heating elements, a fluid conduit for heating fluid flow, or both. The use of two heaters 280 and 282 in the gas distribution unit 210 may enable a variety of heat transfer within the gas distribution unit 210. This may include using the first and / or second unit heaters 280 and 282 to heat the panel 276 to provide a temperature controlled chamber, as described above, to reduce or prevent unwanted condensation on components of the gas distribution unit 210.

[0106] The device 200 may also be configured to cool the substrate. The cooling may include flowing a cooling gas onto the substrate, moving the substrate near the panel to allow heat transfer between the substrate and the panel, or both. Actively cooling the substrate may achieve more precise temperature control and faster temperature conversion, which reduces processing time and improves yield. In some embodiments, a first unit heater 280 that allows a heat transfer fluid to flow through a fluid conduit may be used to cool the substrate 218 by transferring the heat transferred from the substrate 218 from the panel 276. Therefore, the substrate 218 may be cooled by arranging it to be adjacent to the panel 276 with a gap 286 that is, for example, less than or equal to 5 mm or 2 mm, so that the heat in the substrate 218 is transferred to the panel 276 by radiation and is transferred from the panel 276 by the heat transfer fluid in the first unit heater 280. The panel 276 may therefore be considered as a heat sink for the substrate 218 to cool the substrate 218.

[0107] In some embodiments, for example, the apparatus 200 may further include a cooling fluid source 273, which may include a cooling fluid (gas or liquid) and a cooler (not shown) configured to cool the cooling fluid to a desired temperature, such as less than or equal to about 90° C., less than or equal to about 70° C., less than or equal to about 50° C., less than or equal to about 20° C., less than or equal to about 10° C., less than or equal to about 0° C., less than or equal to about -50° C., less than or equal to about -100° C., less than or equal to about -150° C., less than or equal to about -190° C., about -200° C., or less than or equal to about -250° C. Apparatus 200 The apparatus 200 includes a conduit for delivering cooling fluid to the one or more fluid inlets 270, and a gas distribution unit 210 configured to flow the cooling fluid onto the substrate. In some embodiments, the fluid may be in a liquid state when flowing to the processing chamber 202, and may become a vapor state when it reaches the interior of the chamber 214, for example, if the interior of the chamber 214 is in a low pressure state, such as described above, for example, between about 0.1 Torr and 10 Torr, or between 0.1 Torr and 100 Torr, or between about 20 Torr and 200 Torr. The cooling fluid may be an inert element, such as nitrogen, argon, or helium. In some instances, the cooling fluid may include or may have only non-inert elements and / or mixtures, such as hydrogen. In certain embodiments, the apparatus may be configured to cool the substrate at one or more cooling rates, such as at least about 5°C / second, at least about 10°C / second, at least about 15°C / second, at least about 20°C / second, at least about 30°C / second, or at least about 40°C / second.

[0108] In some embodiments, the apparatus 200 can actively cool the substrate by moving the substrate close to the panel and flowing a cooling gas onto the substrate. In some instances, active cooling is more effective by flowing a cooling gas when the substrate is in close proximity to the panel. The effectiveness of the cooling gas may also depend on the type of gas used.

[0109] In some embodiments, the apparatus 200 may include a mixing plenum for mixing and / or conditioning the process gas for delivery before reaching the fluid inlet 270. One or more mixing plenum inlet valves may control the introduction of process gas into the mixing plenum. In some other embodiments, the gas distribution unit 210 may include one or more mixing plenums within the gas distribution unit 210. The gas distribution unit 210 may also include an annular flow path fluidly connected to the through hole 278, which may evenly distribute the received fluid to the through hole 278 to provide a uniform flow onto the substrate.

[0110] The apparatus 200 may also include one or more additional non-contact sensors for detecting the temperature of the substrate. For example, such a sensor may include an improved pyrometer. Although conventional pyrometers cannot detect certain substrates within a specific temperature range, the pyrometers described herein overcome these problems. For example, the pyrometer is configured to detect multiple emission ranges to detect multiple types of substrates, such as doped, low-doped, or undoped, at various temperature ranges. This includes configurations for detecting emission ranges of about 0.95 microns to about 1.1 microns, about 1 micron, about 1 to about 4 microns, and / or about 8 to 15 microns. The pyrometer is also configured to detect the temperature of the substrate at a shorter wavelength to distinguish the signal from the thermal noise of the chamber.

[0111] The pyrometer may include an emitter configured to emit an infrared light signal and a detector configured to receive the emission. Figure 2A , the apparatus includes a pyrometer 288 and a detector 290, the pyrometer 288 having an emitter within the pyrometer 288. The pyrometer can be configured to emit a signal on one side (top or bottom) of the substrate and to receive a signal on the other side of the substrate. For example, the emitter can emit a signal on the top of the substrate, while the detector is below the substrate and receives the signal emitted through the substrate and below the substrate. Therefore, the apparatus can have at least one first port 292A on the top of the processing chamber 202, such as port 292A passing through the center of the gas distribution unit 210, and a second port 292B passing through the base 204 and the substrate heater 222. The emitter in the pyrometer 288 can be connected to one of the ports 292A or 292B by a fiber optic connection, such as Figure 2A , and the detector is optically connected to another port, such as Figure 2A The first port 292A may include a port window 294 to seal the first port 292A from chemicals within the chamber interior 214. Figure 2A The second port 292B seen in FIG. 2 extends through the pedestal 204 and the substrate heater so that the emission of the emitter can pass through the substrate, through the window 250, into the second port 292B and to the detector 290 disposed in the second port or optically connected to the second port through another fiber optic connection (not shown). In some other embodiments, the emitter and detector are reversed so that the emitter emits through the second port 292B and the detector detects through the first port 292A.

[0112] The apparatus 200 may also include one or more optical sensors 298 to detect one or more measurements of visible light emitted by the LEDs. In some embodiments, the optical sensors may be one or more photodetectors configured to detect light and / or light intensity emitted by the LEDs of the substrate heater. Figure 2A, a single optical sensor 298 is shown connected to the chamber interior 214 via a fiber optic connection, such that the optical sensor 298 can detect light emitted by the substrate heater 222. The optical sensor 298, as well as additional optical sensors, can be disposed at different locations of the process chamber 202, such as in the top and sides, to detect emitted light at different locations within the process chamber 202. As described below, this can enable measurement and adjustment of the substrate heater, such as adjusting one or more independently controllable LED zones. In some embodiments, there may be multiple optical sensors 298 arranged along a circle or multiple concentric circles to measure multiple LED zones throughout the process chamber 202. In some embodiments, the optical sensor can be disposed within the chamber interior 214.

[0113] In some embodiments, the apparatus described herein may include a controller configured to control various aspects of the apparatus to perform the techniques described herein. Figure 2A , the apparatus 200 includes a controller 231 (which may include one or more physical or logical controllers) that is communicatively connected to and controls some or all of the operations of the processing chamber. The system controller 231 may include one or more memory devices 233 and one or more processors 235. In some embodiments, when performing the disclosed embodiments, the apparatus includes, for example, a switching system operably coupled to the system controller 231 for controlling flow rate and duration, a substrate heating unit, a substrate cooling unit, loading and unloading of the substrate in the chamber, thermal flotation of the substrate, and a process gas unit. For example, the switching system may control the flow rate and duration of water vapor in the chamber so that one or more monolayers of water are controllably adsorbed on the substrate or on the silicon nitride surface. In some embodiments, the apparatus may have a switching time of up to about 500 milliseconds (ms) or up to about 750 ms. The switching time may depend on the flow chemistry, the selected recipe, the reactor architecture, and other factors.

[0114] In some embodiments, the switching system of the apparatus may be coupled to one or more contact or non-contact sensors to monitor substrate temperature, one or more temperature sensors may be operably coupled to a chamber heater to monitor chamber temperature, or coupled to a gas distribution unit to monitor and control the flow rate and duration of one or more gaseous reactants and vapors.

[0115] In some implementations, the controller is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller", which can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the controller can be programmed to control any process disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out tools and other transfer tools and / or load locks connected or docked with a specific system.

[0116] Broadly speaking, a controller can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuit can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0117] In some implementations, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a wafer fab host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a manufacturing operation, check the history of past manufacturing operations, check trends or performance criteria for multiple manufacturing operations, change parameters of a current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0118] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, PVD chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers. In some embodiments, an example system may include a combination of an ALD chamber or module and an ALE chamber or module such that one or more depositions are performed on a substrate followed by one or more etches without breaking the vacuum in the chamber and without exposing the substrate to the surrounding atmosphere.

[0119] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport to transport wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0120] In some embodiments, the apparatus can also be configured to generate plasma and use the plasma for some of the processes in various embodiments. This can include having a plasma source configured to generate plasma inside the chamber, such as capacitively coupled plasma (CCP), inductively coupled plasma (ICP), upper remote plasma, and lower remote plasma.

[0121] The apparatus described herein may be used in a variety of etching techniques including, but not limited to, continuous etching methods and cyclic methods, such as atomic layer etching.

[0122] application

[0123] There are various applications in which etching processes according to the embodiments of the present invention can be used. One application is the selective etching of nitride layers in 3D memory stacks. When manufacturing 3D NAND or other devices, silicon oxide layers and silicon nitride layers can be alternately deposited to form oxide / nitride stacks. Silicon oxide layers and silicon nitride layers can be deposited by any suitable process (e.g., ALD, PEALD, CVD, or PECVD). Silicon oxide / silicon nitride layer stacks can be etched to form high aspect ratio (HAR) structures, wherein trenches are formed between adjacent HAR structures. Figure 3A is a schematic diagram showing a cross-sectional depiction of a feature before atomic layer etching according to some embodiments. The feature on the substrate may be a HAR structure 300, which includes silicon oxide layers 310 and silicon nitride layers 320 alternately stacked on a substrate (i.e., a silicon substrate) 330, wherein a trench 340 is formed between adjacent HAR structures 300. In some embodiments, the height of the HAR structure may be between about 7 μm and about 10 μm. The thickness of each silicon nitride layer may be between about 5 nm and 40 nm.

[0124] Figure 3B According to some embodiments, the atomic layer etch Figure 3A Schematic diagram of a cross-sectional view of a HAR structure on a substrate shown in FIG, wherein the silicon nitride layer 320 is selectively etched to form a groove without attacking the adjacent silicon oxide or silicon substrate. Figure 3A The depth of the groove measured from the surface of the unetched silicon nitride layer in the embodiment of the present invention can be about 1 nm to about 20 nm. The process of etching the silicon nitride layer 320 can be performed at Figure 44. The process flow shown in FIG. 4 is described. A semiconductor substrate including one or more HAR structures including one or more silicon nitride layers is supplied into a reaction chamber (operation 402). The reaction chamber temperature may be about 20° C. and the chamber pressure may be about 10 Torr. In operation 404, water vapor is supplied to the interior of the chamber so that one or more monolayers of water molecules are adsorbed on the surface of the HAR structure 300 including the silicon nitride layer 320. In operation 406, gaseous phosphine is supplied to the adsorbed water layer to form phosphoric acid on the surface of the structure. In operation 408, an oxidant such as oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2) and / or a mixture thereof is then supplied to the surface of the HAR structure 300 to oxidize unreacted phosphine to P2O5, which may react with the water provided in operation 404 or water in the reaction chamber to generate phosphoric acid in situ. In some embodiments, the amount of silicon nitride removed by the phosphoric acid may depend on the chamber temperature (or substrate temperature) and may not be important during operations 406 - 408. Note that operations 406 and 408 may be configured to occur simultaneously or substantially simultaneously.

[0125] Subsequently, water vapor is provided to the surface of structure 300 (operation 410), and the substrate temperature may be adjusted to above 100°C, or to between about 100°C and about 180°C, or to between about 120°C and about 180°C (operation 412). Providing additional water at an elevated temperature increases the amount of phosphoric acid produced and also increases the reaction of the phosphoric acid with the silicon nitride layer. Operation 412 involves extensive etching of silicon nitride layer 320. Phosphoric acid selectively etches adjacent silicon oxide 310, but not silicon nitride layer 320 and / or silicon substrate 330. Silicon nitride layer 320 is etched from the surface, thereby forming a silicon nitride layer such as Figure 3BThe groove shown. The etching of the silicon nitride layer can be performed substantially in a horizontal direction. The degree of etching in the silicon nitride layer can be determined by, for example, the amount of water vapor, the substrate temperature and / or the etching time. Removing silicon nitride by phosphoric acid can produce one or more etching byproducts. The etching byproducts may include silicon, such as orthosilicic acid (Si(OH)4), or phosphorus, such as phosphorus oxide (P2O5). The etching byproducts may remain on the surface of the silicon nitride layer in the HAR structure. In operation 414, the etching byproducts can be removed from the surface of the silicon nitride layer by heating the substrate to above about 100°C, above about 120°C, or between about 100°C and about 120°C, or above about 130°C, or above about 140°C, while reacting the etching byproducts with a suitable etching compound (e.g., hydrogen fluoride) that can decompose the etching byproducts into volatile byproducts. Alternatively, the etching products (e.g., P2O5) can be removed by thermal sublimation above about 360°C, above about 375°C, or above about 400°C. P2O5 can be removed by reacting with hydrogen fluoride to generate PF5. Depending on the desired recess depth in the silicon nitride layer, operations 404-414 (or operations 406-414) can be optionally repeated until the desired portion of the silicon nitride layer is etched.

[0126] According to some embodiments, the atomic layer etching process does not include supplying reactants in liquid form. Instead, only gaseous reactants are supplied to the chamber to generate gaseous etching chemicals in situ, thereby allowing a uniform etching reaction to be performed over the entire position on the surface of the silicon nitride layer. For high-density storage devices with more cells and smaller cell sizes, the capillary force of the liquid etching chemicals from the wet etching may affect the stability of the features or stacks. According to some embodiments, the nitride etching process may not be affected by capillary forces because of the properties of the gaseous reactants involved. The etching process also allows the etching to be controlled to the angstrom level by controlling parameters including the flow rate and duration of water vapor, substrate temperature or duration.

[0127] Although the above embodiments have been described in detail to a certain extent for the purpose of clear understanding, it is apparent that certain variations and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternatives to the processes, systems, and equipment of the embodiments of the present invention. Therefore, the embodiments of the present invention should be considered illustrative rather than restrictive, and these embodiments are not limited to the details given herein.

Claims

1. A method for treating a silicon nitride layer, the method comprising: (a) generating phosphoric acid on the surface of the silicon nitride layer; as well as (b) treating the surface of the silicon nitride layer using the phosphoric acid. 2 . The method of claim 1 , further comprising: (c) providing water vapor to form one or more monolayers of water molecules on the surface of the silicon nitride layer before (a).

3. The method of claim 1 or claim 2, wherein the temperature of the surface of the silicon nitride layer ranges between about 0°C and about 100°C, and the pressure of the surface of the silicon nitride layer ranges between about 1 Torr and about 100 Torr.

4. The method according to any one of claims 1 to 3, wherein generating the phosphoric acid comprises: providing a first reactant; providing a second reactant; as well as reacting the first reactant and the second reactant to form the phosphoric acid, Wherein the first reactant comprises phosphorus.

5. The method of claim 4, wherein the first reactant is selected from the group consisting of phosphine, phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halides, trimethylphosphine, triethylphosphine, tripropylphosphine and / or mixtures thereof.

6. The method of claim 4, wherein the second reactant is selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (N2O), nitrogen dioxide (NO2) and / or mixtures thereof.

7. An apparatus for processing a substrate, the apparatus comprising: a processing chamber for processing the substrate; a susceptor comprising one or more heating elements for heating the substrate; a gas distribution unit for delivering one or more gaseous reactants to the substrate; A controller configured to: controlling the gas distribution unit to control the flow rate and duration of the one or more gaseous reactants and / or vapors, and Operation of the heating element is controlled to control the temperature of the substrate.

8. The apparatus of claim 7, wherein the one or more heating elements are located on the back side of the substrate.

9. The device of claim 7, wherein the one or more heating elements comprise one or more light emitting diode (LED) units.

10. The apparatus of claim 7, wherein the one or more gaseous reactants include: water vapor; A first reactant selected from the group consisting of phosphine, phosphorus trioxide (P2O3), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halides, trimethylphosphine, triethylphosphine, tripropylphosphine and / or mixtures thereof; a second reactant selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2) and / or mixtures thereof; or hydrogen fluoride.

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