Semiconductor device

Abstract

The technical problem is to provide a semiconductor device capable of improving yield. As a solution, a semiconductor device according to one embodiment includes: a first insulating plate; the first metal plate is arranged on the first surface of the first insulating plate; a second metal plate provided on a second surface of the first insulating plate facing the first surface; the semiconductor chip is arranged on the second metal plate; and a resin member that seals the semiconductor chip. In the semiconductor device, only one semiconductor chip is arranged on the second metal plate.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] In high-voltage power modules used in electric vehicles, semiconductor chips such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) are mounted on insulating boards. In such power modules, many semiconductor chips are usually used, so improvement in yield is required.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 4972503 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] Embodiments of the present invention provide a semiconductor device capable of improving yield.

[0008] Means for solving technical problems

[0009] A semiconductor device according to one embodiment includes: a first insulating plate; a first metal plate provided on a first surface of the first insulating plate; a second metal plate provided on a second surface of the first insulating plate opposite to the first surface; a semiconductor chip provided on the second metal plate; and a resin member for sealing the semiconductor chip. In the semiconductor device, the number of semiconductor chips provided on the second metal plate is only one. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a cross-sectional view schematically showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 2 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a second embodiment.

[0012] Figure 3 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the second embodiment.

[0013] Figure 4 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a third embodiment.

[0014] Figure 5 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a fourth embodiment.

[0015] Figure 6 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a fifth embodiment.

[0016] Figure 7 It is a cross-sectional view showing an exploded structure of the semiconductor device according to the sixth embodiment.

[0017] Figure 8 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention.

[0019] (First Embodiment)

[0020] Figure 1 It is a cross-sectional view schematically showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device 1 shown includes a first metal plate 11 , a first insulating plate 12 , a second metal plate 13 , a first bonding material 14 , a semiconductor chip 15 , bonding wires 16 , and a resin member 17 .

[0021] The first metal plate 11 is bonded to the back surface (first surface) of the first insulating plate 12. The first metal plate 11 functions as a heat sink for dissipating heat generated by the operation of the semiconductor chip 15. The first metal plate 11 can be formed by processing copper (Cu) into a plate shape, for example.

[0022] The first insulating plate 12 includes an insulating material such as silicon nitride (SiN), aluminum nitride (AlN), or aluminum oxide (Al2O3). The first insulating plate 12 can be formed by processing one of these insulating materials into a plate shape.

[0023] The second metal plate 13 is bonded to the front surface (second surface) of the first insulating plate 12. The second metal plate 13 is used to connect the semiconductor chip 15 to the terminal (on the Figure 1 The second metal plate 13 can be formed by processing copper into a plate shape, for example. A circuit pattern for connecting various electrodes provided on the semiconductor chip 15 to the terminals is formed on the second metal plate 13.

[0024] The first bonding material 14 is provided between the second metal plate 13 and the semiconductor chip 15. For example, a solder material or a sintered material can be used as the first bonding material 14. The sintered material includes, for example, silver or copper. If the first bonding material 14 is a sintered material, thermal resistance can be reduced.

[0025] The semiconductor chip 15 is bonded to the second metal plate 13 via the first bonding material 14. The semiconductor chip 15 has a semiconductor element including a compound semiconductor such as SiC (silicon carbide). The semiconductor element using SiC includes, for example, MOSFET or IGBT.

[0026] When the semiconductor element is a MOSFET, a drain electrode is formed on the back side of the semiconductor chip 15. On the other hand, a source electrode and a gate electrode are formed on the front side of the semiconductor chip 15. When the semiconductor element is an IGBT, a collector electrode is formed on the back side of the semiconductor chip 15. On the other hand, an emitter electrode and a gate electrode are formed on the front side of the semiconductor chip 15.

[0027] One end of the bonding wire 16 is bonded to the source electrode (emitter electrode when the semiconductor chip 15 is an IGBT) or gate electrode of the semiconductor chip 15. The other end of the bonding wire 16 is bonded to the second metal plate 13. The bonding wire 16 is formed of, for example, aluminum and is bonded to the semiconductor chip 15 and the second metal plate 13 by ultrasonic bonding.

[0028] In addition, Figure 1 In the figure, only one bonding wire 16 is shown, but there is no particular limitation on the number of bonding wires 16. In addition, instead of the bonding wire 16, the semiconductor chip 15 and the second metal plate 13 may be electrically connected by ribbon bonding.

[0029] The resin member 17 seals the semiconductor chip 15 and the bonding wires 16. The resin member 17 is a mold resin.

[0030] In the semiconductor device 1 configured as described above, assuming that a plurality of semiconductor chips 15 are mounted on one first insulating plate 12, if one defect occurs in the electrical testing process for inspecting the electrical characteristics of the semiconductor chip 15, the qualified semiconductor chip 15 is also regarded as a defective product, which results in a reduction in the yield.

[0031] On the other hand, in the semiconductor device 1 of the present embodiment, the number of semiconductor chips 15 mounted on one first insulating plate 12 is only one. Therefore, it is possible to avoid treating a good semiconductor chip 15 as a defective product. This can improve the yield.

[0032] (Second Embodiment)

[0033] Figure 2 2 is a cross-sectional view showing a schematic structure of a semiconductor device according to the second embodiment. The same components as those of the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0034] exist Figure 2 In the semiconductor device 2a shown, the third metal plate 18 is bonded to the front surface of the semiconductor chip 15 via the second bonding material 19. The third metal plate 18 is made of a copper plate like the first metal plate 11 and the second metal plate 13 described in the first embodiment. In addition, the second bonding material 19 is made of a solder material or a sintered material like the first bonding material 14.

[0035] The third metal plate 18 has a first portion 181 and a second portion 182. The first portion 181 is electrically connected to the gate electrode of the semiconductor chip 15. On the other hand, the second portion 182 is electrically connected to the emitter electrode or the source electrode of the semiconductor chip 15.

[0036] Figure 3 FIG. 2 is a cross-sectional view showing a schematic structure of a semiconductor device according to a modified example of the second embodiment. Figure 3 In the semiconductor device 2b shown in FIG. 1 , a semiconductor chip 151 is provided instead of the semiconductor chip 15. The semiconductor chip 151 is a flip chip. Figure 2 The semiconductor chip 15 shown is reversed 180 degrees relative to the first insulating plate 12. Therefore, the source electrode (the emitter electrode when the semiconductor chip 151 is an IGBT) and the gate electrode are arranged on the back side of the semiconductor chip 151, and the drain electrode (the collector electrode when the semiconductor chip 151 is an IGBT) is arranged on the front side of the semiconductor chip 151.

[0037] In addition, in the semiconductor device 2b of this modification, the first portion 181 of the third metal plate 18 is bonded to the first portion 131 of the second metal plate 13 via the third bonding material 20. In addition, the second portion 182 of the third metal plate 18 is bonded to the second portion 132 of the second metal plate 13 via the third bonding material 20. The third bonding material 20 is made of a solder material or a sintered material, similarly to the first bonding material 14 and the second bonding material 19.

[0038] In this modification, in order to make the thickness of the third metal plate 18 function as a stress relief layer, it is preferably within the range of 50 μm to 200 μm. In addition, the thickness of the third bonding material 20 is thinner than the thickness of the third metal plate 18. However, if the thickness of the third bonding material 20 is too thin, the bonding between the third metal plate 18 and the second metal plate 13 may become insufficient. Therefore, the thickness of the third bonding material 20 is preferably within the range of 20 μm to 40 μm, for example.

[0039] Furthermore, in the semiconductor device 2b of this modification, the fourth metal plate 21 is bonded to the front surface of the semiconductor chip 151 through the first bonding material 14. The fourth metal plate 21 is a copper plate like the other metal plates. The fourth metal plate 21 is electrically connected to the drain electrode of the semiconductor chip 15 (the collector electrode when the semiconductor chip 15 is an IGBT).

[0040] In the semiconductor device 2a of the present embodiment described above, the number of semiconductor chips 15 mounted on the first insulating plate 12 is only one. In addition, in the semiconductor device 2b of this modified example, the number of semiconductor chips 151 mounted on the first insulating plate 12 is only one. Therefore, in this embodiment, it is also possible to avoid that a qualified semiconductor chip is treated as a defective product. Therefore, the yield rate can be improved.

[0041] (Third Embodiment)

[0042] Figure 4 2 is a cross-sectional view schematically showing the structure of a semiconductor device according to the third embodiment. The same components as those of the first and second embodiments are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0043] exist Figure 4 In the semiconductor device 3 shown, a first recess 133 is provided on the upper portion of the second metal plate 13. A semiconductor chip 15 is arranged in the first recess 133. In the semiconductor device 3 of the present embodiment, a plating layer 22 is formed on the surface of each of the first metal plate 11, the second metal plate 13, and the third metal plate 18.

[0044] The plating layer 22 can be formed, for example, by chemical plating. In the present embodiment, the plating layer 22 is flattened after the chemical plating. In the flattening, the plating layer 22 is ground so that the height h1 from the bottom of the first recess 133 to the plating layer 22 formed at the upper end of the first recess 133 and the height h2 from the bottom of the first recess 133 to the plating layer 22 formed on the upper surface of the third metal plate 18 are equal to each other. Through the flattening, three wirings connected to the gate electrode, the drain electrode (collector electrode when the semiconductor chip 15 is an IGBT) and the emitter electrode (source power) can be formed in the same wiring layer.

[0045] In the present embodiment described above, the number of semiconductor chips 15 mounted on the first insulating plate 12 is only one. Therefore, as in the first and second embodiments described above, it is possible to avoid treating a qualified semiconductor chip 15 as a defective product. Therefore, the yield rate can be improved.

[0046] (Fourth Embodiment)

[0047] Figure 5 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a fourth embodiment. Figure 5 The semiconductor device 4 shown is a case-type power module in which the plurality of semiconductor devices 1 described in the first embodiment are accommodated in a case 43 .

[0048] In this embodiment, each semiconductor device 1 is bonded to a substrate 42 by a fourth bonding material 41. That is, the semiconductor device 4 is provided with the same number of substrates 42 as the semiconductor devices 1. The fourth bonding material 41 is, for example, a solder material. In addition, the substrate 42 functions as a heat sink for dissipating heat generated by the semiconductor chip 15 of the semiconductor device 1. The substrate 42 includes, for example, copper or aluminum.

[0049] In the semiconductor device 4 of the present embodiment, each semiconductor device 1 is mounted on a substrate 42. That is, the substrate 42 is provided for each semiconductor device 1. The back surface of the substrate 42 is exposed from the housing 43. The housing 43 is formed of, for example, resin.

[0050] The housing 43 is fixed to the heat sink 40 using screws 47 and washers 48. A grease material 49 is applied between the housing 43 and the heat sink 40. The grease material 49 fills the gap formed between the housing 43 and the heat sink 40, thereby enabling the heat generated by the semiconductor chip 15 to be efficiently transferred to the heat sink 40.

[0051] The housing 43 is filled with a sealing material 44. For example, a transparent gel is used as the sealing material 44. The upper opening of the housing 43 is sealed by a lid 45. Thus, each semiconductor device 1 is sealed in the housing 43.

[0052] Furthermore, the housing 43 is provided with a terminal 46 . One end of the terminal 46 is joined to the second metal plate 13 of each semiconductor device 1 . The other end of the terminal 46 is exposed to the outside of the housing 43 .

[0053] When semiconductor device 4 is mounted in a power converter such as an inverter, the power converted from DC to AC by the switching operation of each semiconductor chip 15 is supplied to a load such as a motor connected to the other end of terminal 46. Thus, terminal 46 can function as a power terminal.

[0054] In addition, one end of the terminal 46 is sometimes connected to the gate electrode of the semiconductor chip 15. In this case, the other end of the terminal 46 is connected to a gate drive circuit (not shown). The gate drive circuit generates a control signal that turns on and off the semiconductor chip 15. The control signal controls the switching action of the semiconductor chip 15. In this way, the terminal 46 can also function as a signal terminal.

[0055] In the present embodiment described above, one power module is formed by assembling a plurality of semiconductor devices 1. In the assembled semiconductor device 1, the number of semiconductor chips 15 mounted on one first insulating plate 12 is only one. Therefore, it is possible to avoid treating the semiconductor chips 15 that are qualified products before being assembled in the power module as defective products. Therefore, in the present embodiment, the yield rate can also be improved.

[0056] (Fifth Embodiment)

[0057] Figure 6 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a fifth embodiment. Figure 6 The semiconductor device 5 shown is a double-sided heat dissipation type power module that dissipates heat from both sides of the semiconductor chip 15 and the semiconductor chip 151 described in the second embodiment.

[0058] In this embodiment, the semiconductor device 2a and the semiconductor device 2b are sealed by a resin member 50. The resin member 50 is, for example, a molded resin. In the resin member 50, the third metal plate 18 of the semiconductor device 2a is bonded to the seventh metal plate 52 via a fifth bonding material 51. The fifth bonding material 51 is, for example, a solder material. The seventh metal plate 52 is, for example, a copper plate.

[0059] The seventh metal plate 52 is bonded to the back surface of the third insulating plate 53. The third insulating plate 53 includes an insulating material such as silicon nitride (SiN), aluminum nitride (AlN), or aluminum oxide (Al2O3) similarly to the first insulating plate 12. An eighth metal plate 54 is bonded to the surface of the third insulating plate 53. The upper surface of the eighth metal plate 54 is exposed from the resin member 50. The eighth metal plate 54 is, for example, a copper plate.

[0060] In the semiconductor device 2 a of the present embodiment, heat generated on the front surface side of the semiconductor chip 15 is transferred to the seventh metal plate 52 and the third insulating plate 53 , and is finally dissipated from the eighth metal plate 54 .

[0061] Furthermore, in the resin member 50, the fourth metal plate 21 of the semiconductor device 2b is bonded to the fifth metal plate 57 via the sixth bonding material 56. The sixth bonding material 56 is, for example, a solder material. The fifth metal plate 57 is, for example, a copper plate.

[0062] The fifth metal plate 57 is bonded to the back surface of the second insulating plate 58. The second insulating plate 58 includes an insulating material such as silicon nitride (SiN), aluminum nitride (AlN), or aluminum oxide (Al2O3) similarly to the first insulating plate 12. A sixth metal plate 59 is bonded to the front surface of the second insulating plate 58. The upper surface of the sixth metal plate 59 is exposed from the resin member 50. The sixth metal plate 59 is, for example, a copper plate.

[0063] In the semiconductor device 2 b of the present embodiment, the heat generated on the front surface side of the semiconductor chip 151 is transferred to the fifth metal plate 57 and the second insulating plate 58 , and is finally dissipated from the sixth metal plate 59 .

[0064] In addition, in the semiconductor device 5 of the present embodiment, a terminal 55a is joined to the second metal plate 13 of the semiconductor device 2a. The terminal 55a can function as a power terminal electrically connected to the drain electrode (collector electrode when the semiconductor chip 15 is an IGBT) of the semiconductor chip 15. In addition, a terminal 55b is joined to the first portion 131 of the second metal plate 13 of the semiconductor device 2b. The terminal 55b can function as a signal terminal electrically connected to the gate electrode of the semiconductor chip 151.

[0065] In the present embodiment described above, a power module is formed by assembling the semiconductor device 2a and the semiconductor device 2b. In the assembled semiconductor device 2a and the semiconductor device 2b, the number of semiconductor chips 15 or semiconductor chips 151 mounted on one first insulating plate 12 is only one, respectively. Therefore, it is possible to avoid treating the semiconductor chips 15 and the semiconductor chips 151 that are qualified products before being assembled in the power module as defective products. Therefore, in this embodiment, the yield rate can also be improved.

[0066] (Sixth Embodiment)

[0067] Figure 7 It is a cross-sectional view showing an exploded structure of the semiconductor device according to the sixth embodiment. Figure 8 It is a cross-sectional view schematically showing the structure of a semiconductor device according to a sixth embodiment. Figure 7 as well as Figure 8 The semiconductor device 6 shown is a power module having a component built-in structure in which the semiconductor device 3 described in the third embodiment is embedded in a printed circuit board 60. Figure 7 as well as Figure 8 In the embodiment, only one semiconductor device 3 is embedded in the printed circuit board 60 , but the number of semiconductor devices 3 may be at least one.

[0068] In the semiconductor device 6 of this embodiment, the printed circuit board 60 is formed using epoxy resin. Figure 7 As shown in FIG. 1 , a second recess 601 is provided on the lower side of the printed circuit board 60. The semiconductor device 3 is embedded in the second recess 601. Figure 8As shown, a portion of the semiconductor device 3 is buried in the second recess 601. For example, in order to ensure the sealing property of the semiconductor chip 15 while avoiding the deterioration of the heat dissipation property, the semiconductor chip 15, the second metal plate 13 and the third metal plate 18 are arranged in the second recess 601, and the first metal plate 11 and the first insulating plate 12 are exposed from the second recess 601.

[0069] In addition, a plurality of wirings 61 are provided in the printed circuit board 60. Each wiring 61 is formed of, for example, a plated metal wire. The plurality of wirings 61 are connected to the gate electrode, the drain electrode (collector electrode when the semiconductor chip 15 is an IGBT), and the source electrode (emitter electrode when the semiconductor chip 15 is an IGBT) of the semiconductor chip 15, respectively.

[0070] In the semiconductor device 3, as described in the third embodiment, the height h1 from the bottom of the first recess 133 to the plating layer 22 formed at the upper end of the first recess 133 and the height h2 from the bottom of the first recess 133 to the plating layer 22 formed on the upper surface of the third metal plate 18 are equal to each other. Therefore, the wiring 61 connected to each electrode of the semiconductor chip 15 can be formed in the same wiring layer. As a result, the electrical loss and heat loss generated by the wiring 61 can be reduced. In addition, Figure 8 In the embodiment, the plating layer 22 is not connected to the wiring 61, but they are connected via, for example, a contact plug (not shown).

[0071] In addition, in the semiconductor device 6 of the present embodiment, the pad 62 is formed at the joint portion of the printed circuit board 60. An electronic component 63 is mounted on the pad 62. The pad 62 is made of, for example, copper foil. The electronic component 63 includes passive components such as capacitors and coils, or active components such as LSI (Large Scale Integration). Passive components are used, for example, for circuit elements such as DC-DC converters. In addition, active components are used, for example, for the gate drive circuit of the semiconductor chip 15.

[0072] In the present embodiment described above, one power module is formed by embedding at least one semiconductor device 3 in the printed circuit board 60. In the embedded semiconductor device 3, the number of semiconductor chips 15 mounted on one first insulating plate 12 is only one. Therefore, it is possible to avoid treating the semiconductor chip 15 that is a qualified product before embedding in the printed circuit board 60 as a defective product. Therefore, in the present embodiment, the yield rate can also be improved.

[0073] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0074] Description of Reference Numerals

[0075] 1-6: Semiconductor devices

[0076] 11: First metal plate

[0077] 12: First insulation board

[0078] 13: Second metal plate

[0079] 15, 151: Semiconductor chips

[0080] 16: Bonding line

[0081] 17: Resin parts

[0082] 18: The third metal plate

[0083] 20: Third bonding material

[0084] 21: Fourth metal plate

[0085] 22: Plating

[0086] 42: Base material

[0087] 43: Shell

[0088] 50: Resin parts

[0089] 57: Fifth metal plate

[0090] 59: Sixth Metal Plate

[0091] 60: Printed substrate

[0092] 63: Electronic components

[0093] 133: First recess

[0094] 601: Second recess

Claims

1. A semiconductor device comprising: a first insulating plate; A first metal plate, disposed on a first surface of the first insulating plate; a second metal plate, disposed on a second surface of the first insulating plate opposite to the first surface; A semiconductor chip is disposed on the second metal plate; as well as A resin component seals the semiconductor chip. The number of the semiconductor chip disposed on the second metal plate is only one.

2. The semiconductor device according to claim 1, wherein A bonding wire is further provided, one end of the bonding wire being bonded to the semiconductor chip and the other end of the bonding wire being bonded to the second metal plate. The bonding wires are sealed together with the semiconductor chip by the resin member.

3. The semiconductor device according to claim 1, wherein further comprising a third metal plate disposed on the semiconductor chip, The third metal plate is sealed together with the semiconductor chip by the resin member.

4. The semiconductor device according to claim 1, wherein The semiconductor chip is a flip chip, The semiconductor device further comprises: A third metal plate is disposed between the flip chip and the second metal plate; and The bonding material is disposed between the second metal plate and the third metal plate.

5. The semiconductor device according to claim 4, wherein: The thickness of the third metal plate is in the range of 50 μm to 200 μm. The thickness of the bonding material is in the range of 20 μm to 40 μm.

6. The semiconductor device according to claim 1, wherein A first recess for arranging the semiconductor chip is provided on the upper portion of the second metal plate. The semiconductor device further comprises: A third metal plate is disposed on the semiconductor chip; and The plating layer is respectively arranged on the upper end of the first recess and the upper surface of the third metal plate.

7. The semiconductor device according to claim 6, wherein: A height from the bottom of the recessed portion to the plating layer provided on the upper end portion of the recessed portion is equal to a height from the bottom to the plating layer provided on the upper surface of the third metal plate.

8. The semiconductor device according to claim 2, wherein: Also available: a housing for accommodating the plurality of semiconductor devices; and A plurality of substrates are provided for each of the semiconductor devices.

9. The semiconductor device according to claim 4, wherein: Also available: a fourth metal plate, disposed on the flip chip; a fifth metal plate joined to the fourth metal plate; A second insulating plate, disposed on the fifth metal plate; as well as The sixth metal plate is arranged on the second insulating plate.

10. The semiconductor device according to claim 6, wherein The resin component is a printed circuit board, and a second recessed portion for arranging the semiconductor chip, the second metal plate, and the third metal plate is provided at the bottom of the printed circuit board. The semiconductor device further includes an electronic component provided on an upper portion of the printed circuit board.

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