Determining lock state of clock tracking circuit

Abstract

An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A state signal of the phase detector is based at least in part on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator can sample the state signal of the phase detector. The logic circuit may determine a locked state of the clock tracking circuit based at least in part on a sample of the state signal of the phase detector.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 375,351, filed on September 12, 2022, entitled "DUAL EDGE PFD WITH DYNAMIC DOUBLING AND EDGELOCKING CLARITY," under 35 U.S.C. §119(e), and claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 375,348, filed on September 12, 2022, entitled "PLL PHASE ERROR BASED DIGITAL LOCK DETECTION," under 35 U.S.C. §119(e), the contents and disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more examples generally relate to error detection, including phase error detection and frequency error detection. One or more examples generally relate to determining a lock state of a clock tracking circuit. Background Art

[0004] Clock tracking circuits, such as phase-locked loops and delay-locked loops, are circuits used to generate signals that have a predetermined relationship to a clock or other oscillating signal. The output signal of the clock tracking circuit is locked to the phase and frequency of the reference signal. Clock tracking circuits are used in a variety of operating contexts, including situations where two signals with a known relationship are used to transmit information. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram of an apparatus for determining a lock state of a clock tracking circuit according to one or more examples.

[0007] Figure 2 is a block diagram depicting an apparatus for phase threshold detection according to one or more examples.

[0008] Figure 3 is a block diagram of an apparatus for determining and indicating a lock status of a clock tracking circuit according to one or more examples.

[0009] Figure 4 is a block diagram of an apparatus for determining and indicating a lock status of a clock tracking circuit according to one or more examples.

[0010] Figure 5 is a block diagram depicting an apparatus for setting a sampling rate according to one or more examples.

[0011] Figure 6 is a block diagram depicting an apparatus for sampling a state signal of a phase detector at a set sampling rate according to one or more examples.

[0012] Figure 7 is a block diagram depicting an apparatus for generating a sampling clock for sampling a state signal of a phase detector according to one or more examples.

[0013] Figure 8 is a flow chart depicting a process for determining a lock state of a clock tracking circuit according to one or more examples.

[0014] Fig. 9 is a flow chart depicting a process for setting a state signal of a phase detector according to one or more examples.

[0015] Fig.10 is a flow chart depicting a process for setting a state signal of a phase detector according to one or more examples.

[0016] Fig.11 is a flow chart depicting a process for setting a state signal to indicate a state of a phase difference between a reference clock and a feedback clock according to one or more examples.

[0017] Fig.12 is a flow chart depicting a process for determining a lock state of a clock tracking circuit based at least in part on a state signal of a phase detector according to one or more examples.

[0018] Fig.13 is a block diagram depicting a clock tracking circuit that provides lock state determination according to one or more examples.

[0019] Fig.14 is a timing diagram depicting a non-limiting example of a conventional double-edge based lock detection experiencing a NULL condition at 180 degrees.

[0020] Fig.15 is a timing diagram depicting a non-limiting example of a conventional double-edge based lock detection experiencing a NULL condition at 180 degrees due to a missed detected edge caused by RESET.

[0021] Fig.16 is a block diagram depicting an apparatus providing single-edge and double-edge phase error detection according to one or more examples.

[0022] Fig.17is a block diagram depicting an apparatus providing single-edge and double-edge phase error detection according to one or more examples.

[0023] Fig.18 is a flow chart depicting a process for improved double-edge phase error detection according to one or more examples.

[0024] Fig.19 is a flow chart depicting a process for setting a state signal to indicate a state of a phase difference between a reference clock and a feedback clock according to one or more examples.

[0025] Fig. 20 is a flow chart depicting a process for setting a state signal to indicate a state of a phase difference between a reference clock and a feedback clock according to one or more examples.

[0026] Fig.21 is a flow chart depicting a process for determining a state of a phase difference between a reference clock and a feedback clock according to one or more examples.

[0027] Fig. 22 is a flow chart depicting a process for determining phase error according to one or more examples.

[0028] Fig.23 is a flow chart depicting a process for setting a phase error signal to indicate the magnitude and direction of a phase difference between a reference clock and a feedback clock according to one or more examples.

[0029] Fig.24 An example 2400 is illustrated for setting a state signal to indicate a state of a phase relationship between a reference clock and a feedback clock based on a false NULL condition threshold according to one or more examples.

[0030] Fig.25 is to describe such as Fig.17 A timing diagram depicting example operation of a double-edge PFD device.

[0031] Fig.26 is a graph showing a simulated plot of a single edge mode phase-frequency detector transfer function that exhibits a NULL condition only at 0° and therefore always aligns rising edges with rising edges.

[0032] Fig. 27 is a graph showing a simulated plot of a nominal dual edge mode PFD transfer function exhibiting a false NULL condition at 180° and a desired NULL condition at 0°.

[0033] Fig.28is a graph showing a simulated plot of a curve representing a dynamic double edge triggered transfer function.

[0034] Fig.29 are block diagrams of circuits that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0035] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0036] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0037] The following description may include examples to help enable one of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary," "such as," and "for example" means that the related description is illustrative, and while the scope of the present disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0038] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0039] In addition, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0040] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0041] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general purpose computer including a processor executes computing instructions (e.g., software code) associated with the examples disclosed herein, the general purpose computer is considered a special purpose computer.

[0042] Examples may be described in terms of processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operable actions as continuous processes, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, a function may be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that facilitates transferring a computer program from one location to another.

[0043] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0044] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, by at least 95%, or even by at least 99%.

[0045] As used herein, any relative terms (such as "above", "below", "on", "below", "upper", "lower", but not limited to) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0046] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless otherwise expressly indicated or the context would otherwise indicate to one of ordinary skill in the art.

[0047] As used herein, the term "assert" when used with "signal" means to set a signal to an active state. As used herein, the term "disable" when used with "signal" means to set a signal to an inactive or default state. For example, a signal may be active high and inactive low, or active low and inactive high.

[0048] A "clock signal," or simply "clock," is a signal that oscillates between two discrete states, a low state and a high state, in a reliable and predictable manner. A change from a low state to a high state, or from a high state to a low state, is called an "edge." The type or direction of the change (from a low state to a high state, or from a high state to a low state) is called the "polarity" of the edge. A change from a low state to a high state is called a "positive polarity" or a "rising edge." A change from a high state to a low state is called a "negative polarity" or a "falling edge." As a non-limiting example, one or more circuits may coordinate actions in response to a rising edge or a falling edge of a clock.

[0049] A clock tracking circuit (such as a phase-locked loop (PLL), but not limited thereto) generates an output signal that exhibits a phase, frequency, or both that has a predetermined relationship to the phase or frequency of a reference signal. Causing and maintaining such a predetermined relationship between the phase or frequency of the output signal and the reference signal is referred to herein as "tracking". The predetermined relationship may be that the output signal and the reference signal are in phase or within a predetermined phase difference. The predetermined relationship may be that the frequency of the output signal is the same as the frequency of the reference signal or is a multiple thereof. As a non-limiting example, the frequency of the output signal may be an integer or fractional multiple of the frequency of the reference signal, such as 1 / 200, 1 / 10, 10, or 200 times the frequency of the reference signal.

[0050] A typical clock tracking circuit includes an electronic oscillator that is controlled by the clock tracking circuit to generate an output signal that tracks a reference signal. The electronic oscillator may include one or more control element groups (e.g., capacitors, inductors, delay circuits, but not limited thereto) that are voltage controlled, current controlled, digitally controlled, or a combination or sub-combination thereof. Depending on the circumstances, enabling and disabling the corresponding control element changes the capacitance, inductance, or delay of the electronic oscillator in a predictable manner, which changes the output phase and frequency of the electronic oscillator in a predictable manner.

[0051] The electronic oscillator may include multiple inputs for controlling (enabling / disabling) various control element groups and thus governing the phase and frequency of the output signal. Non-limiting examples of electronic oscillators include: a voltage controlled oscillator (VCO) that generates an output signal exhibiting a phase or frequency governed by the voltage of the control signal; a current controlled oscillator (CCO) that generates an output signal exhibiting a phase or frequency governed by the current of the control signal; a digitally controlled oscillator (DCO) that generates an output signal exhibiting a phase or frequency governed at least in part by the value of a control code; and combinations / sub-combinations thereof.

[0052] When the clock tracking circuit reliably tracks the output signal to the reference signal, it is said to be "locked" or in a "locked state." Being in a locked state is also referred to as a "NULL condition" because the phase error is zero or suitably small or "NULL." When locked, if the phase or frequency of the reference signal changes, the clock tracking circuit correspondingly adjusts the phase or frequency of the output signal to maintain a predetermined relationship. Similarly, when locked, if the phase or frequency of the output signal changes, the clock tracking circuit correspondingly adjusts the phase or frequency of the output signal to maintain a predetermined relationship. An internal signal is generated at the clock tracking circuit to indicate the locked state. As a non-limiting example, such a locked state signal can be used to enable the output driver and initiate other clock tracking calibration functions.

[0053] As a non-limiting example, the threshold used to determine the locked state (i.e., the threshold used to determine that the output signal is operating within a stable, defined range, but not limited thereto) depends on the specific operating conditions. For example, some applications may tolerate less accuracy (i.e., a larger difference) between the target frequency and the output frequency, while other applications will not tolerate this less accuracy.

[0054] Sometimes, an analog control signal to an electronic oscillator (e.g., but not limited to, an analog proportional input to the electronic oscillator) is used to determine the lock state. Whether the output signal operates within a stable, defined range can be inferred based on the control signal. The inventors of the present disclosure recognized that this approach requires an analog reference and comparator that targets a specific operating point of the clock tracking circuit that defines its stable, defined range, and that analog components require a large amount of space compared to digital components. In addition, while analog control signals can be generated based on phase error, they do not directly include phase error information. Inferring the lock state, which may be imprecise or completely inaccurate, or using a control signal to determine the lock state, which is an imperfect representation of the phase error, in either case, the lock state determination is affected by the error.

[0055] One or more examples relate to a lock state detector for a clock tracking circuit. In some examples, the lock state detector determines the lock state based at least in part on a reference clock and a feedback clock, an UP signal and a DOWN signal generated by a binary error detector (e.g., by a phase-frequency detector, but not limited thereto), or both.

[0056] In one or more examples, the lock state detector includes a phase detector having a phase threshold and a state signal. The phase threshold is settable. The phase detector compares the phase difference between two input signals (e.g., a reference clock and a feedback clock, but not limited thereto) with the phase threshold. If the phase difference between the two input signals is greater than or equal to the phase threshold, the phase detector sets its output to a first value. If the phase difference between the two input signals is less than the phase threshold, the phase detector sets its state signal to a second value, which is different from the first value. The value of the state signal of the phase detector indicates the relationship between the phase difference and the phase threshold. The first value indicates that the phase difference between the two input signals is greater than or equal to the phase threshold, and one of the input signals (e.g., the feedback clock, but not limited thereto) operates outside the set dead zone of the phase detector. The second value indicates that the phase difference between the two input signals is less than the phase threshold, and one of the input signals (e.g., the feedback clock, but not limited thereto) operates within the set dead zone of the phase detector.

[0057] The term "dead band" generally refers to a region of operation where a phase detector (or phase detector output - error signal) exhibits zero gain or near zero gain (e.g., here, gain refers to the magnitude of the error signal) because the phase difference between the two input signals is zero or near zero. In one or more examples, the phase detector has a "set dead band". The set dead band is set via a phase threshold. In one or more examples, the phase error region associated with the set dead band can be the same or different than the phase error region associated with the actual dead band of the phase error detector.

[0058] The state signal may change from indicating being outside the dead band to indicating being within the dead band in response to a changing phase difference between the input signals. The state signal may change from indicating being within a set dead band to indicating being outside the set dead band in response to a changing phase difference between the input signals. In the context of lock state detection, the set dead band corresponds to a predetermined range of phase error that is pre-associated with a lock state.

[0059] The phase threshold of the phase detector can be settable (e.g., programmable, configurable, or otherwise settable, but not limited thereto), and thus the phase detector is adaptive or adaptable to operating conditions based at least in part on the phase threshold, as appropriate. In one or more examples, the phase threshold can be pre-set or set in real time.

[0060] In one or more examples, a state signal of a phase detector is sampled and the state signal samples are decoded to determine a locked state. In one or more examples, a digital discriminator distinguishes steady-state phase error information from transient phase error information in the state signal. A steady-state phase error is a phase error that exists when a clock tracking circuit is locked. A transient phase error is a phase error that is temporary in nature and may or may not exist at any given time. In general, information about a steady-state phase error should be used to determine a locked state, while information about a transient phase error should be reduced or eliminated in such a determination.

[0061] In one or more examples, the digital discriminator is a digital filter that retains or passes a digital signal indicating a steady-state phase error (e.g., in a state signal, but not limited thereto) and blocks or removes a digital signal indicating a transient phase error (e.g., in a state signal, but not limited thereto). In one or more examples, the digital discriminator is a state machine that implements a pattern matcher that performs a bit-by-bit comparison of the digital signal and a predetermined pattern indicating a locked state of the phase detector. In one or more examples, the digital discriminator is an accumulator and a comparator, wherein the accumulator accumulates the state of the state signal, and the comparator detects when the accumulated state is above a predetermined threshold indicating a steady-state phase error. The output of the comparator is used as a locked state signal.

[0062] The state signal samples are the values ​​of the state signal at specific intervals, i.e., discrete time, discrete valued signals. It is noteworthy that the state signal of the phase detector may be a digital signal, which is a discrete time, discrete valued signal. Thus, as a non-limiting example, the state signal may be a series of samples received in a shift register. In one or more examples, a sampling rate may be set to ensure that a set of samples obtained represents the state of the phase detector. Generally speaking, the higher the sampling rate, the greater the number of state signal samples and the more representative the state of the phase detector.

[0063] Figure 1 is a block diagram of an apparatus 100 for determining a lock state of a clock tracking circuit according to one or more examples. The apparatus 100 may also be referred to as a "lock state detector 100".

[0064] The apparatus 100 includes a phase detector 102 , a digital discriminator 106 , and a logic circuit 112 .

[0065] The device 100 receives a reference clock 118, a feedback clock 120, a phase threshold 116, and generates a lock status signal 110 at least in part in response thereto. The feedback clock 120 is generated by a clock tracking circuit to track the reference clock 118. The reference clock 118 represents a target frequency and phase tracked by the clock tracking circuit. In one or more examples, the feedback clock 120 may be derived from an output clock that is generated by the clock tracking circuit to track the reference clock 118 and is optionally fed back through a frequency divider for comparison with the reference clock 118. The feedback clock 120 may be the same as the output clock generated by the clock tracking circuit (e.g., the output clock is directly fed to the input of the phase detector 102, but is not limited thereto), or may indicate one or more of the phase, frequency, or pulse width of the output clock. In the example of FIG. 1 , the feedback clock 120 may be generated by the clock tracking circuit to track the reference clock 118, and ... Figure 1 In the particular non-limiting example depicted, the reference clock 118 and the feedback clock 120 are fed directly to the inputs of the phase detector 102. In one or more examples, one or more signals indicative of the phase relationship between the reference clock 118 and the feedback clock 120 may be fed to one or more inputs of the phase detector 102, such as, but not limited to, the output of a binary phase detector (such as, but not limited to, a bang-bang phase detector), the output of a digital or analog sub-sampling phase detector, the output of a digital or analog sampling phase detector.

[0066] Phase threshold 116 is a predetermined value or range of values ​​representing a threshold value of a set deadband at phase threshold 116 and, in the context of lock state detection, also represents an amount of phase error pre-associated with a lock state.

[0067] The phase detector 102 uses the phase threshold 116 to determine the state of the phase error between the reference clock 118 and the feedback clock 120. If the phase error is greater than or equal to the phase threshold 116, it indicates that the phase error is outside the range associated with the locked state, and if the phase error is less than the phase threshold 116, it indicates that the phase error is within the range associated with the locked state. As a non-limiting example, if the phase threshold 116 is set to ±5 degrees (e.g., by a logic circuit or a user, but not limited thereto), the device 100 considers that the phase error is within the range associated with the locked state as long as the phase difference between the feedback clock 120 and the reference clock 118 is within +5 to -5 degrees.

[0068] The lock state signal 110 indicates the lock state of the clock tracking circuit, that is, whether the clock tracking circuit is in a lock state. In one or more examples, a first value of the lock state signal 110 indicates that the clock tracking circuit is not in a lock state, and a second value of the lock state signal 110 indicates that the clock tracking circuit is in a lock state. The first value and the second value of the lock state signal 110 are different.

[0069] Phase detector 102 receives reference clock 118, feedback clock 120, and phase threshold 116 and, at least in part in response thereto, generates status signal 104. Status signal 104 indicates whether feedback clock 120 operates within a set deadband of phase detector 102, as described below.

[0070] The phase detector 102 determines the phase difference between the reference clock 118 and the feedback clock 120 and whether it is less than the phase threshold 116. If the phase detector 102 determines that the phase difference is less than the phase threshold 116, it is determined that the feedback clock 120 operates within the set dead band, and the phase detector 102 sets the state signal 104 to a value indicating that the feedback clock 120 operates within the set dead band of the phase detector 102. If the phase detector 102 determines that the phase difference is greater than or equal to the phase threshold 116, it is determined that the feedback clock 120 operates outside the set dead band, and the phase detector 102 sets the state signal 104 to a value indicating that the feedback clock 120 operates outside the set dead band of the phase detector 102. Since the feedback clock 120 is based on the output clock of the clock tracking circuit, determining whether the feedback clock 120 operates within the set dead band is also determining whether the output signal operates within the set dead band.

[0071] The phase detector 102 may change the value of the state signal 104 from a value indicating being outside the set dead band to a value indicating being within the set dead band in response to the changing phase difference between the reference clock 118 and the feedback clock 120. The phase detector 102 may change the value of the state signal 104 from a value indicating being within the set dead band to a value indicating being outside the set dead band in response to the changing phase difference between the reference clock 118 and the feedback clock 120. Thus, the state of the state signal 104 may change over time at least in part in response to a change in the phase difference between the reference clock 118 and the feedback clock 120.

[0072] The value of the phase threshold 116 may be predetermined based at least in part on an acceptable amount of phase difference for determining a locked state. The value of the state signal 104 is based at least in part on whether the phase difference between the reference clock 118 and the feedback clock 120 is less than the phase threshold 116, so that the state signal 104 indicates the locked state of the clock tracking circuit. In other words, information about the phase difference between the feedback clock 120 and the reference clock 118 and the locked state of the clock tracking circuit is included in the state signal 104. The state signal 104 includes information about the steady-state phase error between the feedback clock 120 and the reference clock 118, and the locked state of the clock tracking circuit can be determined based on the steady-state phase error information. Therefore, in one or more examples, the state of the state signal 104 can be decoded to determine the locked state of the clock tracking circuit, as described below.

[0073] Digital discriminator 106 receives state signal 104 and processes state signal 104 to produce samples 108 of state signal 104. Digital discriminator 106 distinguishes between steady-state phase error information and transient phase error information in state signal 104. Digital discriminator 106 stores samples 108 of state signal 104 including steady-state phase information.

[0074] Logic circuit 112 processes samples 108 to determine a pattern indicating a lock state in the state information about phase detector 102 included in the set of samples 108. Logic circuit 112 determines a lock state of the clock tracking circuits of reference clock 118 and feedback clock 120. If logic circuit 112 determines that the lock state is a lock state, it sets lock state signal 110 to a value indicating a lock state. If logic circuit 112 determines that the lock state is an unlock state, it sets lock state signal 110 to a value indicating a not in lock state.

[0075] The state signal 104 and the state signal samples 108 include steady-state phase error information that is used by the logic circuit 112 to determine (e.g., infer, but not limited to) the lock state of the clock tracking circuit. The phase detector 102 changes the state of the state signal 104 in a predictable manner so that the state information can be used to determine the lock state.

[0076] Figure 2 2 is a block diagram depicting an apparatus 200 as an example of a phase detector according to one or more examples. The apparatus 200 may also be referred to herein as a “phase detector 200”. The apparatus 200 is Figure 1 Non-limiting example of a phase detector 102 .

[0077] Generally speaking, if the two input signals exhibit a transition from a low state to a high state (rising edge) within a predetermined range, the device 100 asserts the threshold detection signal 212, and if the two input signals do not exhibit a rising edge within the predetermined range, the device 100 deasserts the threshold detection signal 212. The device 200 performs a binary check, either the phase relationship is within the predetermined range, or it is not within the predetermined range.

[0078] In one or more examples, the threshold detection signal 212 can be used as the state signal 104. When the rising edge of the two signals arrives, the phase detector is restarted for the next comparison. In other words, the device 200 sets the threshold detection signal 212 to an active (high) state in response to determining that the time difference between the occurrence of the rising edge of the first signal 214 and the occurrence of the rising edge of the second signal 216 is less than the phase threshold 116, and sets the threshold detection signal 212 to an inactive (low inactive) state in response to determining that the time difference between the occurrence of the rising edge of the first signal 214 and the occurrence of the rising edge of the second signal 216 is greater than the phase threshold 116.

[0079] The apparatus 200 includes a first flip-flop 202 , a second flip-flop 204 , a third flip-flop 220 , a fourth flip-flop 218 , a first delay circuit 208 , a second delay circuit 222 , a NAND gate 206 , and a NOR gate 210 .

[0080] The first flip-flop 202, the second flip-flop 204, the third flip-flop 220, and the fourth flip-flop 218 are edge-triggered flip-flops, which are types of flip-flops that respond to changes (or "edges") of their clock inputs rather than the level of the clock inputs. Each flip-flop 202, 204, 220, and 224 has a data (D) input, a clock (CLK) input, and an output (Q). In response to the state at the clock (CLK) input undergoing a specified edge transition (rising or falling, but in this example, a rising edge), the state at the data (D) input is captured and transmitted to the output (Q). When the clock (CLK) input undergoes an edge transition other than a specified edge transition, the state at the data (D) input is not captured or transmitted, and the state at the output (Q) is the state at the data (D) input when the specified edge transition occurred at the clock (CLK) input for the last time.

[0081] In one or more examples, a flip-flop may have a single output Q capable of exhibiting at least two states, or alternatively, two separate outputs Q and Q' that each represent one of the two states.

[0082] NAND gate 206 is an electronic logic gate that produces a false output only when all of its inputs are true. In other words, if any of its inputs are in a low state, the output will be in a high state. NOR gate 210 is an electronic logic gate that produces a true output only when all of its inputs are false. In other words, if any of its inputs are true, the output will be false.

[0083] The first delay circuit 208 and the second delay circuit 222 are delay circuits that introduce respective predetermined amounts of time delay to the propagation of a signal from its input to its output. In one or more examples, the respective predetermined amounts of time delay introduced are equal to or based at least in part on the phase threshold 116. In one or more examples, the first delay circuit 208 and the second delay circuit are programmable, wherein the amount of delay varies based in part on the phase threshold 116.

[0084] The respective data (D) inputs of the first flip-flop 202 and the second flip-flop 204 are coupled to the power supply voltage to set the data (D) input to a high state. The clock (CLK) input of the first flip-flop 202 is coupled to receive the first signal 214, and the clock (CLK) input of the second flip-flop 204 is coupled to receive the second signal 216. In one or more examples, one of the first signal 214 or the second signal 216 is set as the reference clock 118, and the other of the first signal 214 or the second signal 216 is set as the feedback clock 120.

[0085] In one or more examples, the first signal 214 and the second signal 216 can be set by a signal indicating a phase relationship between the reference clock 118 and the feedback clock 120, such as UP and DOWN signals generated by a phase / frequency detector (such as, but not limited to, a bang-bang phase-frequency detector). As long as the timing of the rising edges of the first signal 214 and the second signal 216 includes phase information about the signals of interest (e.g., the reference clock 118 and the feedback clock 120, but not limited thereto), the device 200 can use them to determine whether the phase difference is within the phase error threshold.

[0086] The output (Q) of the first flip-flop 202 is coupled to the data (D) input of the third flip-flop 220, the input of the first delay circuit 208, and the input of the NAND gate 206. The output (Q) of the second flip-flop 204 is coupled to the data (D) input of the fourth flip-flop 218, the input of the second delay circuit 222, and the other input of the NAND gate 206. The output of the NAND gate 206 is coupled to the respective reset (R) inputs of the first flip-flop 202 and the second flip-flop 204. The output of the first delay circuit 208 is coupled to the clock (CLK) input of the third flip-flop 220, and the output of the second delay circuit 222 is coupled to the clock (CLK) input of the fourth flip-flop 218. The Q output of the third flip-flop 220 is coupled to the first input of the NOR gate 210, and the Q output of the fourth flip-flop 218 is coupled to the second output of the NOR gate 210. The output of the NOR gate 210 represents the threshold detection signal 212.

[0087] The outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are received at the NAND gate 206. If the outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are both in a high state, the output of the NAND gate 206 is set to a low state, and this low state at the output of the NAND gate 206 resets the first flip-flop 202 and the second flip-flop 204 because their respective reset (R) inputs are active low. When the first flip-flop 202 and the second flip-flop 204 are reset, their outputs (Q) are forced to a low state (i.e., the low state at the reset (R) input overrides the data (D) input and the clock (CLK) input and forces the output (Q) to a low state).

[0088] When one or both of the outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are in a low state, the output of the NAND gate 206 is set to a high state. The reset (R) inputs of the first flip-flop 202 and the second flip-flop 204 are active low, so when a high state is received at the corresponding reset (R) inputs, the first flip-flop 202 and the second flip-flop 204 operate normally and are not reset, and only respond to the data (D) input and the clock (clk) input.

[0089] Therefore, if both outputs (Q) of the first flip-flop 202 and the second flip-flop 204 are in a high state, the NAND gate 206 resets the two flip-flops, making the corresponding outputs (Q) of the first flip-flop 202 and the second flip-flop 204 in a low state.

[0090] For the purpose of example, assume that all of the first flip-flop 202 , the second flip-flop 204 , the third flip-flop 220 , and the fourth flip-flop 218 are initialized to output a low state.

[0091] If the output (Q) of the first flip-flop 202 changes to a high state in response to the rising edge of the first signal 214, and the output (Q) of the second flip-flop 204 is in a low state, since the rising edge of the second signal 216 has not yet occurred, a high state is received at the data (D) input of the third flip-flop 220 and at the input of the first delay circuit 208, and the received high state is propagated through the first delay circuit 208. The low state at the output terminal (Q) of the second flip-flop 204 is received at the data (D) input of the fourth flip-flop 218 and at the input of the second delay circuit 222, and the received low state is propagated through the second delay circuit 222.

[0092] After the predetermined delay time of the first delay circuit 208 and the second delay circuit 222 (i.e., the delay set by the phase threshold 116), the delayed high state (i.e., the output (Q) of the first flip-flop 202 delayed by the first delay circuit 208) is received at the clock (CLK) input of the third flip-flop 220, so the clock (CLK) input of the third flip-flop 220 undergoes a change from a low state to a high state (rising edge) and triggers, thereby transferring the high state received at the data (D) input of the third flip-flop 220 to the Q output of the third flip-flop 220. Also after the predetermined delay time, the delayed low state (i.e., the delayed output (Q) of the second flip-flop 204) is received at the clock (CLK) input of the fourth flip-flop 218, and the fourth flip-flop 218 does not undergo a change from a low state to a high state and does not trigger. The output of the third flip-flop 220 is a high state, and the output of the fourth flip-flop 218 is the last value at the data (D) input when it was triggered, which is a low state in this example. Since the Q output of the third flip-flop 220 is high, the output of the NOR gate 210 (i.e., the threshold detection signal 212) is low. As described above, the threshold detection signal 212 in the low state indicates that the time difference between the occurrence of the rising edge of the first signal 214 and the occurrence of the rising edge of the second signal 216 is greater than the phase threshold 116.

[0093] If the second signal 216 exhibits a rising edge before the predetermined time delay, the second flip-flop 204 is triggered, and the Q output of the second flip-flop 204 is set to a high state. Since the Q outputs of the first flip-flop 202 and the second flip-flop 204 are in a high state, the NAND gate 206 resets the first flip-flop 202 and the second flip-flop 204, so that the Q outputs of the first flip-flop 202 and the second flip-flop 204 fall to a low state. After the predetermined delay time of the first delay circuit 208, the delayed high state (i.e., the output (Q) of the first flip-flop 202 delayed by the first delay circuit 208) is received at the clock (CLK) input of the third flip-flop 220, so the clock (CLK) input of the third flip-flop 220 undergoes a change from a low state to a high state (rising edge) and is triggered, thereby transmitting the low state received at the data (D) input of the third flip-flop 220 to the Q output of the third flip-flop 220. Similarly, after the predetermined delay time of the second delay circuit 222, the delayed high state (i.e., the output (Q) of the second flip-flop 204 delayed by the second delay circuit 222) is received at the clock (CLK) input of the fourth flip-flop 218, and thus the clock (CLK) input of the fourth flip-flop 218 undergoes a change from a low state to a high state (rising edge) and triggers, thereby transmitting the low state received at the data (D) input of the fourth flip-flop 218 to the Q output of the fourth flip-flop 218. Since the Q outputs of the third flip-flop 220 and the fourth flip-flop 218 are both low, the output of the NOR gate 210 (i.e., the threshold detection signal 212) is therefore high.

[0094] Although described above in an example where the rising edge of the first signal 214 precedes the rising edge of the second signal 216 , those skilled in the art will recognize that the same result occurs when the rising edge of the second signal 216 precedes the rising edge of the first signal 214 .

[0095] If both the first signal 214 and the second signal 216 exhibit rising edges within the phase threshold 116 (i.e., when the time between the first signal 214 exhibiting a rising edge and the second signal 216 exhibiting a rising edge is less than the phase threshold 116), the device 200 sets the threshold detection signal 212 to a low state, and if neither the first signal 214 nor the second signal 216 exhibits a falling edge within the phase threshold 116 (i.e., when the time between the first signal 214 exhibiting a rising edge and the second signal 216 exhibiting a rising edge is greater than the phase threshold 116), the device 200 sets the threshold detection signal 212 to a high state. Figure 2In the particular non-limiting example depicted, asserting the threshold detection signal 212 is setting it to a low state, and deasserting the threshold detection signal 212 is setting it to a high state, but use of other states is within the scope of this disclosure.

[0096] Figure 3 is a block diagram of an apparatus 300 for distinguishing between steady-state and transient phase errors in a state signal of a phase detector and optionally determining a lock state based thereon, according to one or more examples. The apparatus 300 is Figure 1 1 and 12. Non-limiting examples of digital identifiers 106 and logic circuits 112.

[0097] The apparatus 300 includes the phase detector 102, the digital discriminator 106, and the logic circuit 112. The digital discriminator 106 includes a digital filter 302 and a register 304.

[0098] The digital filter 302 filters the state signal 104 of the phase detector 102 to block the state signal indicating the transient phase error and pass the state signal indicating the steady-state phase error. As a non-limiting example, the digital filter 302 may be a digital low-pass filter that allows the steady-state phase error signal to pass while attenuating high-frequency transient phase error signals. Non-limiting examples of digital low-pass filters include moving average filters, finite impulse response (FIR) filters, digital loop filters, and adaptive filters.

[0099] Register 304 receives and stores the status signal samples provided by digital filter 302. The status signal samples include steady-state phase error information that can be used to determine the lock status of the clock tracking circuit.

[0100] Logic circuit 112 monitors the status signal samples stored at register 304, determines lock status information from the status signal samples, determines a lock status of the clock tracking circuit based at least in part on the status information, and sets lock status signal 110 to indicate the determined lock status.

[0101] Figure 4 4 is a block diagram of an apparatus 400 for distinguishing between steady-state and transient phase errors in a state signal of a phase detector and optionally determining a lock state based thereon, according to one or more examples. The apparatus 400 is Figure 1 1 and 12. Non-limiting examples of digital identifiers 106 and logic circuits 112.

[0102] The device 400 includes the digital discriminator 106 and the logic circuit 112. The digital discriminator 106 includes an accumulation register 402 and a comparator 404.

[0103] Accumulator register 402 accumulates the state of state signal 104. Accumulator value 408 ("acc value 408") stored at accumulator register 402 is provided to comparator 404, the accumulator value representing the integral of the state of state signal 104. The integral of the state of state signal 104 is steady-state phase error information.

[0104] Comparator 404 is a digital comparator that determines a relationship between acc value 408 and a threshold value and sets a corresponding output of comparator 404 to indicate the determined relationship. In one or more examples, the relationship may be whether the accumulated value is less than or greater than a predetermined threshold value. If the accumulated value is greater than a predetermined threshold value indicating a locked state of the clock tracking circuit, it is a locked state, and if the accumulated value is less than a predetermined threshold value indicating a locked state of the clock tracking circuit, it is an unlocked state. Logic circuit 112 may set lock state signal 110 to indicate the locked state indicated by comparator 404. Alternatively, in one or more examples, the output of comparator 404 may be provided as lock state signal 110.

[0105] In one or more examples, the number of samples generated is based at least in part on a sampling rate. In one or more examples, the sampling rate at the apparatus 400 can be set to enable the digital discriminator 106 to process the state signal 104 and maintain a suitable resolution of the steady-state phase error information. The suitable resolution is a resolution that ensures that a set of state signal samples represents the phase error information. In general, the higher the sampling rate, the greater the number of state signal samples and the higher the resolution.

[0106] In some cases, a processing rate may be set at phase detector 102 as described below to increase the resolution of state signal 104. State signal 104 may be a digital signal that is a discrete-time, discrete-valued signal. Increasing Processing Rate Phase detector 102 increases the frequency with which it updates state signal 104. One way to increase the processing rate is to increase the clock rates of feedback clock 120 and reference clock 118.

[0107] Figure 5 is a block diagram illustrating an apparatus 500 for setting a sampling rate according to one or more examples. The apparatus 500 includes a phase detector 102 and a sampling clock divider 502 .

[0108] The sampling clock divider 502 receives the feedback clock 120, the reference clock 118, and the sampling rate 504, divides the feedback clock 120 and the reference clock 118 by an amount corresponding to the sampling rate 504, and generates a divided reference clock 506 and a divided feedback clock 508. For example, based on the sampling rate 504, the clock rates of the divided reference clock 506 and the divided feedback clock 508 may be greater than or less than the clock rates of the reference clock 118 and the feedback clock 120.

[0109] As non-limiting examples, sampling rate 504 may be a value representing the number of clock cycles per sampling interval, the number of samples per unit interval, or a frequency division factor. Sampling rate 504 may be preset by a user or logic circuit.

[0110] The apparatus 600 includes a sampling logic circuit 602 , an interpolator 604 , a decimator 606 , a multiplexer 612 , and an optional digital discriminator 106 .

[0111] The sampling logic circuit 602 receives the sampling rate 608, determines whether to perform upsampling (i.e., increasing the number of samples based on interpolation) or downsampling (reducing the number of samples based on decimation) based on the sampling rate 608, generates a decimation rate 614 for the decimator 606 or an interpolation rate 616 for the interpolator 604 based at least in part on the determination, and generates a selection signal 610 to select the output of the decimator 606 or the interpolator 604 as the state signal sample provided to the digital discriminator 106 via the multiplexer 612. If the sampling logic circuit 602 determines based on the sampling rate 608 to perform upsampling, the sampling logic circuit 602 determines a value for a target interpolation rate based on the sampling rate 608, and sets the interpolation rate 616 based on the determined value. In one or more examples, when upsampling, the sampling logic circuit 602 may set the decimation rate 614 to a value indicating no decimation. If sampling logic circuit 602 determines to perform downsampling based on sampling rate 608, sampling logic circuit 602 determines a value for a target decimation rate based on sampling rate 608 and sets decimation rate 614 based on the determined value. In one or more examples, when downsampling, sampling logic circuit 602 can set interpolation rate 616 to a value indicating no interpolation.

[0112] The decimator 606 receives the state signal 104 and the decimation rate 614, selects every Nth value of the state signal 104 (where the Nth value is based at least in part on the decimation rate 614), and provides the selected value as a state signal sample. As a non-limiting example, the decimator 606 may include a shift register for holding and moving bits of the state signal 104 and logic circuitry for selecting which values ​​of the state signal 104 to retain (and conversely, which values ​​to remove). The decimator 606 retains the values ​​of the state signal 104 that the logic circuitry selects to retain, and removes the remaining values.

[0113] Interpolator 604 receives state signal 104 and interpolation rate 616, upsamples the value of state signal 104 based at least in part on interpolation rate 616, and provides the upsampled value as a state signal sample. As a non-limiting example, interpolator 604 may include a shift register that holds and shifts bits of the original value of state signal 104 and thereby inserts gaps (e.g., the corresponding gaps may include one or more zeros, but is not limited thereto) between bits of the original value of state signal 104, and logic circuitry for interpolating values ​​between the original values ​​of state signal 104 and replacing zeros (filling the gaps) with interpolated values.

[0114] Sometimes it may be advantageous to base the sampling clock or signal that sets the sampling rate of state signal 104 at least in part on reference clock 118, feedback clock 120, or a phase difference therebetween to increase the amount of steady-state phase information in state signal 104 or its samples.

[0115] Sometimes it may be advantageous to base the sampling clock or signal that sets the sampling rate of state signal 104 at least in part on reference clock 118, feedback clock 120, or a phase difference therebetween to increase the amount of steady-state phase information in state signal 104 or its samples.

[0116] Figure 7 is a block diagram depicting an apparatus 700 for generating a sampling clock for sampling a state signal of a phase detector according to one or more examples. Apparatus 300 is a non-limiting example of a clock source for optional sampling clock 306 or optional sampling clock 410.

[0117] The apparatus 700 includes a sampling clock divider 704 and a NAND gate 708. The sampling clock divider 704 receives a generated clk 710 and a sampling rate 706, divides the generated clk 710 based at least in part on the sampling rate 706, and generates the sampling clock 702. The NAND gate 708 generates the generated clk 710 based at least in part on the reference clock 118 and the feedback clock 120.

[0118] Figure 8 is a flow chart depicting a process 800 for determining a lock state of a clock tracking circuit according to one or more examples.

[0119] Although the example process 800 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 800. In other examples, different components of the example device or system implementing the process 800 may perform functions substantially simultaneously or in a particular order.

[0120] According to one or more examples, process 800 includes setting a state signal of a phase detector, wherein the state signal of the phase detector is set based at least in part on an amount of a phase difference between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock at operation 802. In one or more examples, the state signal can be set directly based on the feedback clock and the reference clock, or directly based on one or more signals indicating a phase difference between the reference clock and the feedback clock, such as an UP signal and a DOWN signal generated by a phase-frequency detector.

[0121] According to one or more examples, process 800 includes generating a signal indicating a lock status of a clock tracking circuit based at least in part on a status signal of a phase detector at operation 804 .

[0122] Fig. 9 is a flow chart depicting a process 900 for setting a state signal of a phase detector according to one or more examples. As non-limiting examples, some or all of the operations of process 900 may be performed by device 100, phase detector 102, or device 200.

[0123] Although the example process 900 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 900. In other examples, different components of the example device or system implementing the process 900 may perform functions substantially simultaneously or in a particular order.

[0124] According to one or more examples, process 900 includes determining whether a phase relationship between a reference clock and a feedback clock falls within a predetermined range at operation 902. In one or more examples, the phase relationship is a phase difference between the reference clock and the feedback clock. In one or more examples, a phase threshold represents a boundary condition of the predetermined range. At operation 902, process 900 uses a phase threshold to check whether the phase relationship between the reference clock and the feedback clock falls within a predetermined range, and does not require measuring an exact phase difference.

[0125] According to one or more examples, process 900 includes setting a state signal of a phase detector based at least in part on the determination at operation 904. In one or more examples, operation 902 is a binary check, the phase relationship is either within a phase threshold or not within a phase threshold. Setting the state signal can include setting it to a value indicating a result of the binary check of operation 902.

[0126] Fig.10 is a flow chart depicting a process 1000 for setting a state signal of a phase detector according to one or more examples.

[0127] Although the example process 1000 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1000. In other examples, different components of an example device or system implementing the process 1000 may perform functions substantially simultaneously or in a particular order.

[0128] According to one or more examples, process 1000 includes, at operation 1002 , setting a state signal of a phase detector to a first value in response at least in part to determining that the determined difference is greater than a phase threshold.

[0129] According to one or more examples, process 1000 includes setting a state signal of a phase detector to a second value in response at least in part to determining that the determined difference is equal to or less than a phase threshold, wherein at operation 1004 the second value is different from the first value.

[0130] Fig.11 1600 or the phase error detector 1604.

[0131] Although the example process 1100 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1100. In other examples, different components of an example device or system implementing the process 1100 may perform functions substantially simultaneously or in a particular order.

[0132] According to one or more examples, process 1100 includes detecting occurrences of similar corresponding edges of a reference clock and a feedback clock at operation 1102 .

[0133] According to one or more examples, process 1100 includes setting a status signal at operation 1104 to indicate whether the detected occurrence of similar corresponding edges is within a predetermined range.

[0134] According to one or more examples, process 1100 includes, at operation 1106 , optionally setting the status signal to a first value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being less than a phase threshold.

[0135] According to one or more examples, process 1100 includes, at operation 1108 , optionally setting the status signal to a second value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being greater than or equal to a phase threshold.

[0136] Fig.12 is a flow chart depicting a process 1200 for determining a lock state of a clock tracking circuit based at least in part on a state signal of a phase detector according to one or more examples.

[0137] Although the example routines depict a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without substantially affecting the functionality of the routines. In other examples, different components of the example devices or systems implementing the routines may perform functions substantially simultaneously or in a particular order.

[0138] According to one or more examples, process 1200 includes obtaining samples of a state signal of a phase detector, and setting a state of the phase detector based at least in part on whether a phase relationship between a reference clock and a feedback clock falls within a predetermined range at operation 1202. In one or more examples, process 1200 can obtain the samples by processing (e.g., via digital discriminator 106, but not limited thereto) the state signal in a manner that passes or retains steady-state phase error information and removes or blocks transient phase error information.

[0139] According to one or more examples, process 1200 includes optionally obtaining a sample including extracting a status signal at operation 1204 .

[0140] According to one or more examples, process 1200 includes optionally obtaining samples including interpolating values ​​based on the state signal at operation 1206 .

[0141] As non-limiting examples, apparatus 600 may perform some or all of optional operation 1206 and optional operation 1208, operations for decimation, interpolation, or both. In one or more examples, the decimation rate or interpolation rate may be set in response to or based on the sampling rate.

[0142] According to one or more examples, process 1200 includes decoding state information from samples of a state signal of a phase detector at operation 1208 .

[0143] According to one or more examples, process 1200 includes determining a lock state of a clock tracking circuit based at least in part on the decoded state information at operation 1210 .

[0144] According to one or more examples, process 1200 includes, at operation 1212 , optionally setting a signal indicative of a lock state of the clock tracking circuit to the determined lock state.

[0145] Fig.13 1 is a block diagram depicting an apparatus 1300 for tracking a clock that provides a lock state determination (and may also be referred to herein as a "clock tracking circuit 1300") according to one or more examples. In one or more examples, the clock tracking circuit 1300 may be a hybrid PLL or a digital PLL.

[0146] In general, the clock tracking circuit 1300 operates to generate an output clock signal 1308 that is phase-locked and frequency-locked with a reference clock 1314. The clock tracking circuit 1300 includes an error detector 1302, a controller 1304, a controlled oscillator 1306, and a lock state detector 1318.

[0147] The lock state detector 1318 determines a lock state of the clock tracking circuit 1300 and generates a lock state signal 1322 to indicate the determined lock state. In one or more examples, the lock state detector 1318 may be or include the device 100 or the device 300.

[0148] In one or more examples, the lock state detector 1318 can determine the lock state of the clock tracking circuit 1300 based on the reference clock 1314 and the feedback clock signal 1316 , or alternatively, the error signal generated by the error detector 1302 . Fig.13 A specific non-limiting example is depicted in which the error detector 1302 generates two error signals that include magnitude and direction information about the phase difference between the sample set reference clock 1314 and the feedback clock signal 1316, and indirectly about the magnitude and direction information about the frequency difference between the reference clock 1314 and the feedback clock signal 1316. The present disclosure is not limited to determining the lock state based on the error signal in the case where the error signal is an UP and DOWN signal. Any error signal in which the timing of the falling edge includes phase information about the signal of interest (e.g., the reference clock 118 and the feedback clock 120, but not limited thereto) may be utilized. As a non-limiting example, in the case where the error signal generated by the error detector 1302 is not suitable for determining the lock state of the clock tracking circuit 1300, or in the case where operating conditions may otherwise indicate, the reference clock 1314 and the feedback clock signal 1316 may be utilized in the determined lock state of the clock tracking circuit 1300.

[0149] The error detector 1302 receives the reference clock 1314 and the feedback clock signal 1316, and generates an error signal including UP 1312 and DOWN 1320 in response thereto, at least in part. More specifically, the error detector 1302 generates an error signal that is proportional to the phase difference between the two input signals of the error detector 1302. More specifically, the magnitude and direction of the error signal are proportional to the phase difference between the input signals. If the phase and frequency of the two input signals are substantially the same, the magnitude and direction information in UP 1312 and DOWN 1320 will be zero, indicating that the phase and frequency of the two signals are the same. If there is a phase or frequency difference between the two input signals, the magnitude and direction information in UP 1312 or DOWN 1320 will be non-zero and proportional to the difference between the phase (and indirectly, frequency) of the two input signals.

[0150] In one or more examples, the error detector 1302 can be a binary phase detector that generates the error detector 1302 as a binary signal having two separate and distinct component signals, an UP signal and a DOWN signal. The error detector 1302 generates the UP signal and the DOWN signal as a series of pulses, wherein the pulses on the respective ones of the UP signal and the DOWN signal indicate the magnitude and direction of the error. The one of the UP signal and the DOWN signal that first presents the pulse indicates which of the two input selection signals leads the other; and conversely, which of the two input selection signals lags the other. The magnitude of the error signal is represented by the pulse width of the pulse generated in the UP signal or the DOWN signal. A larger pulse width indicates a larger phase difference between the two input signals, and a smaller pulse width indicates a smaller phase difference. One of the inputs of the error detector 1302 is preset as a reference input that leads, lags, or locks, and the other of the inputs of the error detector 1302 is preset as a feedback (or "controlled") input that leads, lags, or locks. As a non-limiting example, in a clock tracking circuit, a reference signal is provided to a reference input, and an output signal (or a derivative thereof) is provided to a feedback input.

[0151] The reference clock 1314 may be generated by any suitable clock source for a given operating context. The feedback clock signal 1316 may be the same as the output clock signal 1308 generated by the clock tracking circuit 1300 (e.g., the output clock signal 1308 is directly provided to the input of the error detector 1302, but is not limited thereto), or may be a clock signal that indicates the phase and frequency of the output clock signal 1308. For example, the phase and frequency of the feedback clock signal 1316 may be the same as or different from the output clock signal 1308, but in either case, can be related to the phase and frequency of the output clock signal 1308. In one or more examples, the feedback clock signal 1316 may be a divided version of the output clock signal 1308 (e.g., via a divider or buffer, but is not limited thereto). In one or more, the error detector 1302 may be any suitable error detector for generating a digital signal representing the phase error between the reference clock 1314 and the feedback clock signal 1316, and may be a switch-mode phase detector as a non-limiting example, but is not limited thereto.

[0152] The digitally controlled oscillator 1306 is an electronic oscillator for generating an output clock signal 1308 in response, at least in part, to a control signal 1310 , which is a digital control signal or a digital control code. The control signal 1310 is fed to an input of the digitally controlled oscillator 1306 .

[0153] Controller 1304 provides control signal 1310 to digitally controlled oscillator 1306 to adjust output clock signal 1308. In one or more examples, controller 1304 can include circuitry (analog, digital, or both) to provide a proportional control path and an integral control path for controlling digitally controlled oscillator 1306.

[0154] A typical phase frequency detector (PFD) is either rising edge triggered or falling edge triggered, but not both. In order to utilize both the rising and falling edges of the input clock signal, two PFDs are sometimes utilized: one PFD is triggered by the rising edge and the other PFD is triggered by the falling edge.

[0155] Ideally, the two PFDs are perfectly matched with respect to at least the following aspects: rise time and fall time, input-to-output delay (also called "response time"), layout, output load and non-ideal factors (e.g., non-ideal factors caused by the manufacturing process, but not limited to such). A rising edge triggered PFD and a falling edge triggered PFD may exhibit non-negligible behavioral differences because they are not perfectly matched. Therefore, sometimes two PFDs are utilized that are triggered by similar edges (i.e., both PFDs are rising edge triggered or both PFDs are falling edge triggered), and one of the PFDs receives a non-inverted version of the input clock signal and the other of the PFDs receives an inverted version of the input clock signal.

[0156] Edge lock ambiguity may occur when edges having a first polarity are converted to edges having a second, different polarity (e.g., a rising edge is converted to a falling edge or vice versa, but not limited to this) for dual edge detection respectively. Due to the PFD transfer curve NULL condition at approximately 180 degrees, a clock tracking circuit using dual edge detection may falsely lock a rising edge to a falling edge, or vice versa. The NULL condition at 180 degrees (i.e., where the two signals are 180 degrees out of phase) is a false alarm and may cause the clock tracking circuit to be in an opposite phase lock. If the clock tracking circuit is locked in an opposite phase (e.g., a rising edge and a falling edge), intervention may be required to unlock.

[0157] Additionally, due to differences between rising and falling edge detection circuit paths, reference spurs may occur when the clock tracking circuit locks to the opposite edge. Reference spurs degrade noise performance. "Reference spurs" are undesired phase or frequency components in the output signal due to residuals between the output signal and a reference signal, which remain uncorrected due to non-idealities and imperfections in an error detector or loop filter, as non-limiting examples.

[0158] Fig.14 is a timing diagram 1400 depicting a non-limiting example of a conventional double-edge based lock detection that experiences a false NULL condition at 180 degrees, as known to the inventors of the present disclosure.

[0159] Timing diagram 1400 includes waveforms with DOWN signals: reference clock, feedback clock, UP signal, DOWN signal, and RESET signal. The waveforms depict an example with a 180 degree phase difference (Δφ) between the feedback clock and the reference clock.

[0160] At time T0, the UP signal is asserted (rising edge) in response to the rising edge of the reference clock (REFCLK), and the DOWN signal is asserted (rising edge) in response to the falling edge of the feedback clock (FBCLK). A short period of time after time T0, the RESET signal is asserted (rising edge) in response to both the reference clock and the feedback clock being in a high state. Both the UP signal and the DOWN signal are deasserted (falling edge) in response to the asserted RESET signal.

[0161] At time T1, the UP signal is asserted (rising edge) in response to the falling edge of the reference clock (REFCLK), and the DOWN signal is asserted (rising edge) in response to the rising edge of the feedback clock (FBCLK). A short period of time after time T1, the RESET signal is asserted (rising edge) in response to both the reference clock and the feedback clock being in a high state. Both the UP signal and the DOWN signal are deasserted (falling edge) in response to the asserted RESET signal.

[0162] If a phase comparison is performed based on the UP and DOWN signals, the phase difference will appear to be zero or negligible, and a conventional double-edge based lock detector may determine that the clock tracking circuit is in lock based on these UP and DOWN signals.

[0163] Sometimes, an edge occurs during the PFD reset interval and is missed. A missed edge can cause a false NULL condition when the input signals are 180 degrees out of phase.

[0164] Fig.15 is a timing diagram 1500 depicting a non-limiting example of a false NULL condition of a 180 degree phase difference due to a missed detected edge as known by the inventors of the present disclosure.

[0165] At time T0, the DOWN signal is asserted in response to the rising edge of the feedback clock (rising edge). The UP signal is already in a high state that was asserted earlier in response to the rising edge of the reference clock. It is worth noting that the phase difference between the reference clock and the feedback clock is close to 180 degrees.

[0166] At time T1 , the RESET signal is asserted (rising edge) in response to the rising edges of both the UP signal and the DOWN signal being in a high state.

[0167] At time T2, when the RESET signal is asserted, the reference clock exhibits a falling edge, and the falling edge of the reference clock is missed. The next edge detected is the falling edge of the feedback clock at time T3, and the DOWN signal is asserted (rising edge) in response to the falling edge of the feedback clock.

[0168] At time T4, the UP signal is asserted in response to the rising edge of the reference clock (rising edge).

[0169] At time T5, the RESET signal is asserted (rising edge) in response to both the UP signal and the DOWN signal being in a high state. Also at time T5, both the UP signal and the DOWN signal are deasserted (falling edge) in response to the RESET signal being asserted.

[0170] exist Fig.15 In the case shown, the phase information in the first set of UP and DOWN signals is accurate, but the phase information in the second set of UP and DOWN signals is inaccurate because the falling edge of the reference clock is missed.

[0171] One or more examples involve single edge and double edge triggered phase error detection. Double edge phase error detection is not performed until the phase error is less than a false NULL condition threshold. The false NULL condition threshold is a threshold, 180 degrees or less, which ensures that a false NULL condition does not occur, depending on specific operating conditions.

[0172] Fig.16 is a block diagram illustrating an apparatus 1600 for providing single-edge and double-edge triggered phase error detection according to one or more examples.

[0173] The apparatus 1600 includes a phase detector 1602 and a phase error detector 1604. The phase error detector 1604 may alternatively be single edge triggered 1606 or double edge triggered 1608.

[0174] Phase detector 1602 generates state signal 1616 at least partially in response to two input signals, here reference clock 1610 and feedback clock 1612. Phase detector 1602 determines a phase difference between reference clock 1610 and feedback clock 1612 and a state of the determined phase difference. State signal 1616 indicates a state of phase difference 1618 between reference clock 1610 and feedback clock 1612.

[0175] The state of the phase difference 1618 is a value representing an instantaneous state of the phase difference between the reference clock 1610 and the feedback clock 1612 , or a set of sequential values ​​representing continuous states of the phase difference between the reference clock 1610 and the feedback clock 1612 .

[0176] In one or more examples, the state of the phase difference 1618 detected by the phase detector 1602 is whether the phase relationship between the reference clock 1610 and the feedback clock 1612 is less than a false NULL condition threshold (e.g., 180 degrees), optionally less than the false NULL condition threshold by a certain threshold amount to avoid a false NULL condition. If the phase detector 1602 determines that the phase relationship between the reference clock 1610 and the feedback clock 1612 is less than the false NULL condition threshold, the phase detector 1602 sets the state signal 1616 to a first value. If the phase detector 1602 determines that the phase relationship between the reference clock 1610 and the feedback clock 1612 is greater than the false NULL condition threshold, the phase detector 1602 sets the state signal 1616 to a second value different from the first value.

[0177] Phase detector 1602 can change the value of state signal 1616 from a value indicating that the phase relationship is less than 180 degrees to a value indicating that the phase relationship is not less than 180 degrees in response to a changing (i.e., increasing) phase difference between reference clock 1610 and feedback clock 1612. Thus, in one or more examples, the state of phase difference 1618 and the state of state signal 1616 can change over time at least in part in response to a change in the phase difference between reference clock 1610 and feedback clock 1612.

[0178] Phase error detector 1604 receives reference clock 1610 , feedback clock 1612 , and phase threshold state signal 1616 , and generates error signal 1614 at least partially in response thereto.

[0179] In one or more examples, the phase error detector 1604 generates an error signal that is proportional to the phase difference between the two input selection signals (again, the reference clock 1610 and the feedback clock 1612). More specifically, the magnitude and direction of the phase error indicated in the error signal is proportional to the phase difference between the input selection signals. If the phase and frequency of the two input selection signals are substantially the same, the magnitude and direction information in the error signal will be zero, indicating that the phase and frequency of the two signals are the same. If there is a phase or frequency difference between the two input signals, the magnitude and direction information in the error signal will be non-zero and proportional to the difference between the phase (and indirectly, frequency) of the two input signals.

[0180] In one or more examples, the phase error detector 1604 can be a binary phase detector that generates the error signal 1614 as a binary signal having two separate and distinct component signals, an UP signal and a DOWN signal. The phase error detector 1604 generates the UP signal and the DOWN signal as a series of pulses, wherein the pulses on the corresponding ones of the UP signal and the DOWN signal indicate the magnitude and direction of the error. The one of the UP signal and the DOWN signal that first presents the pulse indicates which of the two input selection signals leads the other; and conversely, which of the two input selection signals lags the other. The magnitude of the error signal 1614 is represented by the pulse width of the pulse generated in the UP signal or the DOWN signal. A larger pulse width indicates a larger phase difference between the two input signals, and a smaller pulse width indicates a smaller phase difference. One of the inputs of the phase error detector 1604 is preset as a reference input that leads, lags, or locks, and the other of the inputs of the phase error detector 1604 is preset as a feedback (or "controlled") input that leads, lags, or locks. As a non-limiting example, in a clock tracking circuit, a reference signal is provided to a reference input, and an output signal (or a derivative thereof) is provided to a feedback input.

[0181] The phase error detector 1604 operates according to one of single edge triggering 1606 or double edge triggering 1608 .

[0182] When single edge triggering 1606 is used, the phase error detector 1604 triggers only on edges of the reference clock 1610 and the feedback clock 1612 having a first polarity (i.e., generates an error signal 1614 in response thereto), and does not trigger on edges having a second, different polarity. The edge having the first polarity may be one of a rising edge or a falling edge, and the edge having the second polarity may be the other of a rising edge or a falling edge. Single edge triggering may also be referred to as "single polarity edge triggering." When single edge triggering 1606 is used, phase information about the reference clock 1610 and the feedback clock 1612 in the error signal 1614 is based only on edges of the reference clock 1610 and the feedback clock 1612 having the first polarity.

[0183] When double edge triggered 1608, the phase error detector 1604 triggers (i.e., generates an error signal 1614 in response thereto) edges of the reference clock 1610 and the feedback clock 1612 having a first polarity and edges of the reference clock 1610 and the feedback clock 1612 having a second, different polarity. The edge having the first polarity may be one of a rising edge or a falling edge, and the edge having the second polarity may be the other of a rising edge or a falling edge. Double edge triggering may also be referred to as "bipolar edge triggering," where "bipolar" refers to a first polarity and a second, different polarity. When double edge triggered 1608, phase information about the reference clock 1610 and the feedback clock 1612 in the error signal 1614 is based on edges of the reference clock 1610 and the feedback clock 1612 having the first polarity and edges of the reference clock 1610 and the feedback clock 1612 having the second polarity.

[0184] The phase error detector 1604 is set to single edge triggering 1606 or double edge triggering 1608 at least in part in response to the value of the state signal 1616. The first value of the state signal 1616 indicates that the phase difference between the reference clock 1610 and the feedback clock 1612 is less than the false NULL condition threshold. The second value of the state signal 1616 indicates that the phase difference between the reference clock 1610 and the feedback clock 1612 is greater than or equal to the false NULL condition threshold. In this way, the phase error detector 1604 can operate under single edge triggering 1606 when the phase difference between the reference clock 1610 and the feedback clock 1612 is greater than or equal to the false NULL condition threshold, and operate under double edge triggering 1608 when the phase difference between the reference clock 1610 and the feedback clock 1612 is less than the false NULL condition threshold.

[0185] When double edge triggered, the edges fed to the phase error detector 1604 are converted to the same polarity unless they are already that polarity. If the edges of the feedback clock 1612 or the reference clock 1610 have different polarities, they are converted to the same polarity. If the phase error is greater than or equal to 180 degrees, the phase error detector 1604 can lock the edges of the feedback clock 1612 and the reference clock 1610 with different polarities. Limiting the phase error detection based on the edge with the first polarity until the phase error is less than 180 degrees and then detecting the phase error based on both the edge with the first polarity and the edge with the second polarity ensures that a false NULL condition does not occur.

[0186] One or more examples generally involve phase error detection that operates under single edge triggering until the phase error between two input signals is less than 180 degrees, and then operates under double edge triggering. During the single edge mode, the phase error detection is based at least in part on an unconverted version of the input signal. During the double edge mode, the phase error detection is based at least in part on a converted version of the input signal.

[0187] Examples reduce or eliminate false NULL conditions that would otherwise occur in a dual edge mode PFD transfer function and that might prevent a clock tracking circuit from being locked at a suitably small phase error.

[0188] Fig.17 is a block diagram illustrating an apparatus 1700 that provides single-edge and double-edge triggered phase error detection according to one or more examples. The apparatus 1700 may also be referred to herein as a "phase error detector 1700."

[0189] The device 1700 dynamically changes from single edge lock detection to dual edge lock detection. The device 1700 changes from single edge lock detection in response to determining that the phase error between the two input signals is less than a false NULL condition threshold (here 180 degrees).

[0190] Device 1700 includes a phase detector 1702, an inverter 1704, an inverter 1706, an AND gate 1708, an AND gate 1710, a first flip-flop 1712, a second flip-flop 1714, a third flip-flop 1716, a fourth flip-flop 1718, an OR gate 1722, an OR gate 1724, a delay 1726, and a NAND gate 1728.

[0191] Phase detector 1702 is Fig.16 Non-limiting example of a phase detector 1602 (only the state of the phase difference 1618 is omitted to avoid unnecessary confusion Fig.17 ). Fig.17 The remaining sequential logic circuits in Fig.16 1604 , and UP signal 1738 and DOWN signal 1740 are examples of component error signals of error signal 1614 .

[0192] Phase detector 1702 generates state signal 1732 at least in part in response to two input signals, here reference clock 1734 and feedback clock 1736. As a non-limiting example, phase detector 1702 may be Figure 2The phase detector 200 of FIG. 1702 is a phase detector 200, wherein the false NULL condition threshold is set to 180 degrees. The state signal 104 indicates the phase relationship between the reference clock 1734 and the feedback clock 1736, that is, whether it is less than the false NULL condition threshold to ensure that the above-mentioned NULL condition does not occur. The phase detector 1702 determines whether the phase relationship between the reference clock 1734 and the feedback clock 1736 is less than 180 degrees, and sets the state signal 1732 to a value based on the determination. Fig.17 In the particular non-limiting example depicted, the set value of the state signal 1732 is maintained unless / until the phase difference increases above the 180 degree threshold. In other examples, it is specifically contemplated that the value of the state signal 1732, once set to indicate that the phase difference is less than 180 degrees, does not change unless / until the phase relationship increases above the 180 degree threshold.

[0193] If phase detector 1702 determines that the phase difference is not less than 180 degrees, then phase detector 1702 sets state signal 1732 to indicate the same value. Fig.17 In the particular non-limiting example depicted, phase detector 1702 utilizes a high state or "1" to indicate that the phase difference is less than 180 degrees, and utilizes a low state or "0" to indicate that the phase difference is not less than 180 degrees. Other conventions may be utilized with minor circuit modifications to device 1700, as will be apparent to one of ordinary skill in the art, and thus use of other conventions does not exceed the scope of the present disclosure.

[0194] The first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, and the fourth flip-flop 1718 are edge-triggered flip-flops. Each flip-flop 202, 204, 220, and 224 has a data (D) input, a clock (CLK) input, and an output (Q).

[0195] When the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, or the fourth flip-flop 1718 is reset, its corresponding output (Q) is forced to a low state (i.e., the low state at the reset (R) input overrides the data (D) input and the clock (CLK) input and forces the output (Q) to a low state). The corresponding reset (R) inputs of the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, and the fourth flip-flop 1718 are active low.

[0196] Delay 1726 is a delay circuit that introduces a predetermined amount of time delay into the propagation of a signal from its input to its output. In one or more examples, the predetermined amount of time delay introduced is equal to or based at least in part on a suitable time to allow components in the clock tracking circuit to have a minimum ON time so that they can stabilize before the state of the output of phase error detector 1700 changes.

[0197] The corresponding data (D) inputs of the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, and the fourth flip-flop 1718 are coupled to the power supply voltage to set the data (D) input to a high state. The clock (CLK) input of the first flip-flop 1712 receives the reference clock 1734, and the clock (CLK) input of the third flip-flop 1716 receives the feedback clock 1736. One of the inputs of the OR gate 1722 receives the output (Q) of the first flip-flop 1712, and one of the inputs of the OR gate 1722 receives the output of the second flip-flop 1714. The output of the OR gate 1722 is provided as an UP signal 1738. One of the inputs of the OR gate 1724 receives the output (Q) of the third flip-flop 1716, and one of the inputs of the OR gate 1724 receives the output of the fourth flip-flop OR gate 1724. The output of the OR gate 1724 is provided as a DOWN signal 1740.

[0198] The input of the delay 1726 receives the output of the NAND gate 1728. The respective reset (R) inputs of the first flip-flop 1712 and the third flip-flop 1716 receive the output of the delay 1726, which is the delayed output of the NAND gate 1728. The output of the delay 1726 (i.e., the delayed output of the NAND gate 1728) may also be referred to herein as a reset signal 1742. As long as at least one input of the NAND gate 1728 is set to a low state, its output is set to a high state, which does not reset the first flip-flop 1712 or the third flip-flop 1716.

[0199] When the phase difference between the reference clock 1734 and the feedback clock 1736 is greater than or equal to 180 degrees, the phase detector 1702 maintains the clock (CLK) input of the second flip-flop 1714 and the fourth flip-flop 1718 to a low state via the inverter 1704, the AND gate 1708, the inverter 1706, and the AND gate 1710. When the clock (CLK) input is maintained in a low state, the corresponding outputs (Q) of the second flip-flop 1714 and the fourth flip-flop 1718 do not change from the reset state and are therefore in a low state. This condition corresponds to setting the device 1700 to operate as a single edge trigger. When the phase difference between the reference clock 1734 and the feedback clock 1736 is less than 180 degrees, the phase detector 1702 sets the device 1700 to operate under double edge triggering, as described below.

[0200] In single edge mode, the device 1700 is rising edge triggered. When one of the reference clock 1734 or the feedback clock 1736 changes from a low state to a high state (i.e., presents a rising edge), the corresponding one of the UP signal 1738 or the DOWN signal 1740 changes from a low state to a high state. When the other of the reference clock 1734 or the feedback clock 1736 changes from a low state to a high state, the other corresponding one of the UP signal 1738 or the DOWN signal 1740 changes from a low state to a high state. The first flip-flop 1712 and the third flip-flop 1716 are reset after a predetermined delay time provided by the delay 1726 in response to both the UP signal 1738 and the DOWN signal 1740 having changed from a low state to a high state through the action of the NAND gate 1728. The respective outputs (Q) of the first flip-flop 1712 and the third flip-flop 1716 are set to a low state (forced to a low state) in response to the reset. The UP signal 1738 and the DOWN signal 1740 change from a high state to a low state in response to the outputs (Q) of the first flip-flop 1712 and the third flip-flop 1716 changing from a high state to a low state. When the corresponding outputs (Q) of the flip-flops are forced to a low state, the reset signal 1742 changes from a high state to a low state due to the action of the NAND gate 1728.

[0201] When the phase difference between the reference clock 1734 and the feedback clock 1736 is less than 180 degrees, the phase detector 1702 enables the double edge mode at the device 1700. Specifically, the phase detector 1702 sets the state signal 1732 to a high state and maintains the high state. One of the inputs of the AND gate 1708 and the AND gate 1710 is set to a high state in response to the state signal 1732 being set to a high state. The other inputs of the AND gate 1708 and the AND gate 1710 receive the inverted reference clock 1734 via the inverter 1704 and the inverted feedback clock 1736 via the inverter 1706, respectively. Maintaining one of the inputs of AND gate 1708 and AND gate 1710 in a high state effectively sets the respective outputs of AND gate 1708 and AND gate 1710 to be responsive to reference clock 1734 and feedback clock 1736, respectively, and thus sets the respective clock (CLK) inputs of second flip-flop 1714 and fourth flip-flop 1718 to be responsive to inverted reference clock 1734 and inverted feedback clock 1736, respectively. Setting the respective clock (CLK) inputs of second flip-flop 1714 and fourth flip-flop 1718 to be responsive to inverted reference clock 1734 and feedback clock 1736 effectively sets the respective clock (CLK) inputs of second flip-flop 1714 and fourth flip-flop 1718 to be responsive to falling edges of reference clock 1734 and feedback clock 1736. Therefore, when one of the reference clock 1734 or the feedback clock 1736 changes from a high state to a low state (i.e., exhibits a falling edge), the corresponding one of the second flip-flop 1714 or the fourth flip-flop 1718 is triggered and its output (Q) changes from a low state to a high state.

[0202] In the dual edge mode, the rising edge trigger is performed the same as in the single edge mode, as described above. For the falling edge trigger, when one of the reference clock 1734 or the feedback clock 1736 changes from a high state to a low state (i.e., exhibits a falling edge), then the corresponding one of the UP signal 1738 or the DOWN signal 1740 changes from a low state to a high state through the OR gate 1722 and the OR gate 1724. When the other of the reference clock 1734 or the feedback clock 1736 changes from a high state to a logic low, then the other corresponding one of the UP signal 1738 or the DOWN signal 1740 changes from a low state to a high state. The first flip-flop 1712 and the third flip-flop 1716 are reset in response to both the UP signal 1738 and the DOWN signal 1740 having changed from a low state to a high state due to the action of the NAND gate 1728 after a predetermined delay time provided by the delay 1726. The respective outputs (Q) of the second flip-flop 1714 and the fourth flip-flop 1718 are set to a low state (forced to a low state) in response to the reset. The UP signal 1738 and the DOWN signal 1740 change from a high state to a low state in response to the outputs (Q) of the first flip-flop 1712 and the third flip-flop 1716 changing from a high state to a low state.

[0203] Fig.18 18 is a flow chart depicting a process 1800 for improved double edge detection according to one or more examples. As non-limiting examples, some or all of the operations of the process 1800 may be performed by the apparatus 1600 or the phase error detector 1604, the phase error detector 1700.

[0204] Although the example process 1800 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1800. In other examples, different components of an example device or system implementing the process 1800 may perform functions substantially simultaneously or in a particular order.

[0205] According to one or more examples, the method includes, at operation 1802 , generating, via a phase error detector, an error signal proportional to a phase difference between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock.

[0206] According to one or more examples, the method includes, at operation 1804 , in response to a state signal indicating a state of a phase difference between a reference clock and a feedback clock, setting a phase error detector to respond to any of the following.

[0207] Edges of the reference clock and the feedback clock having a first polarity; or edges of the reference clock and the feedback clock having a first polarity and edges of the reference clock and the feedback clock having a second polarity, wherein the second polarity is different from the first polarity.

[0208] Fig.19 1600 is a flow chart depicting a process 1900 for setting a state signal to indicate a state of a phase difference between a reference clock and a feedback clock according to one or more examples. As non-limiting examples, some or all of the operations of process 1900 may be performed by apparatus 1600 or phase detector 1602.

[0209] Although the example process 1900 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1900. In other examples, different components of an example device or system implementing the process 1900 may perform functions substantially simultaneously or in a particular order.

[0210] According to one or more examples, the method includes, at operation 1902 , determining a corresponding state of a phase difference between a reference clock and a feedback clock.

[0211] According to one or more examples, the method includes, at operation 1904 , setting a status signal to indicate a corresponding status of the determined phase difference.

[0212] Fig. 20 1600 is a flow chart depicting a process 2000 for setting a state signal to indicate a state of a phase difference between a reference clock and a feedback clock according to one or more examples. As non-limiting examples, some or all of the operations of process 2000 may be performed by apparatus 1600 or phase detector 1602.

[0213] Although the example process 2000 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 2000. In other examples, different components of an example device or system implementing the process 2000 may perform functions substantially simultaneously or in a particular order.

[0214] According to one or more examples, the method includes, at operation 2002 , setting a status signal to a first value to indicate that a phase difference between a reference clock and a feedback clock is less than a false NULL condition threshold.

[0215] According to one or more examples, the method includes, at operation 2004 , setting the status signal to a second value to indicate that a phase difference between the reference clock and the feedback clock is greater than or equal to a false NULL condition threshold, wherein the second value is different from the first value.

[0216] Fig.21 21 is a flow chart depicting a process 2100 for determining a state of a phase difference between a reference clock and a feedback clock according to one or more examples. As non-limiting examples, some or all of the operations of process 2100 may be performed by apparatus 1600 or phase detector 1602.

[0217] Although the example process 2100 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 2100. In other examples, different components of an example device or system implementing the process 2100 may perform functions substantially simultaneously or in a particular order.

[0218] According to one or more examples, the method includes determining a first state of a phase relationship in response to determining that the phase relationship is less than a false NULL condition threshold at operation 2102 .

[0219] According to one or more examples, the method includes determining a second state of the phase relationship in response to determining that the phase relationship is greater than or equal to a false NULL condition threshold at operation 2104 .

[0220] Fig. 22 22 is a flow diagram depicting a process 2200 for determining a phase error according to one or more examples. As non-limiting examples, some or all of the operations of the process 2200 may be performed by the apparatus 1600 or the phase error detector 1604.

[0221] Although the example process 2200 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 2200. In other examples, different components of an example device or system implementing the process 2200 may perform functions substantially simultaneously or in a particular order.

[0222] According to one or more examples, the method includes, at operation 2202, when the phase error detector is set to respond to edges of a reference clock and a feedback clock having a first polarity, determining, by the phase error detector, a phase error based at least in part on edges of the first polarity.

[0223] According to one or more examples, the method includes, at operation 2204, when the phase error detector is set to respond to edges of a reference clock and a feedback clock having a first polarity and edges of a reference clock and a feedback clock having a second polarity, determining, by the phase error detector, a phase error based at least in part on edges of the reference clock and the feedback clock having the first polarity and edges of the reference clock and the feedback clock having the second polarity.

[0224] Fig.23 2300 for setting a phase error signal to indicate the magnitude and direction of a phase difference between a reference clock and a feedback clock according to one or more examples. As non-limiting examples, some or all of the operations of process 2200 may be performed by apparatus 1600 or phase error detector 1604.

[0225] Although the example process 2300 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 2300. In other examples, different components of an example device or system implementing the process 2300 may perform functions substantially simultaneously or in a particular order.

[0226] According to one or more examples, the method includes, at operation 2302, when the phase error detector is set to respond to edges of a reference clock and a feedback clock having a first polarity, setting an error signal (e.g., Fig.16 The error signal 1614, or Fig.17 The UP signal 1738 and the DOWN signal 1740 of FIG. 17 are provided to indicate the magnitude and direction of the phase error between the edges of the reference clock and the feedback clock having the first polarity, but are not limited thereto.

[0227] According to one or more examples, the method includes, at operation 2304, when the phase error detector is set to respond to edges of the reference clock and the feedback clock having a first polarity and edges of the reference clock and the feedback clock having a second polarity, setting an error signal (e.g., Fig.16 The error signal 1614, or Fig.17 UP signal 1738 and DOWN signal 1740 (but not limited to this) to indicate the magnitude and direction of the phase difference between the edges of the reference clock and feedback clock having the first polarity and the edges of the reference clock and feedback clock having the second polarity.

[0228] Fig.24 An example 2400 is illustrated for setting a state signal to indicate a state of a phase relationship between a reference clock and a feedback clock based on a false NULL condition threshold according to one or more examples.

[0229] Although example 2400 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order, which would not substantially affect the functionality of 2400. In other examples, different components of the example device or system implementing 2400 may perform functions substantially simultaneously or in a particular order.

[0230] According to some examples, the method includes, at operation 2402 , detecting occurrences of similar corresponding edges of a reference clock and a feedback clock.

[0231] According to some examples, the method includes, at block 2404 , setting the status signal to a first value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being less than a false NULL condition threshold.

[0232] According to some examples, the method includes, at block 2406 , setting the status signal to a second value in response to a time difference between the detected occurrences of similar corresponding edges of the reference clock and the feedback clock being greater than or equal to a false NULL condition threshold.

[0233] Fig.25 is a timing diagram 2500 depicting example operation of a double-edge PFD such as, but not limited to, device 1700 .

[0234] Timing diagram 2500 includes waveforms of signals reference clock 1734, feedback clock 1736, UP signal 1738, DOWN signal 1740, and reset signal 1742. The waveforms depict an example with a small phase difference (Δφ).

[0235] At time T0 , UP signal 1738 is asserted (causing a rising edge) in response to a rising edge of reference clock 1734 .

[0236] At time T1 , the DOWN signal 1740 is asserted (causing a rising edge) in response to the rising edge of the feedback clock 1736 .

[0237] At time T1 (plus the delay 1726 but not Fig.18 ), in response to the rising edge UP signal 1738 and the DOWN signal 1740 and both being in a high state, the reset signal 1742 is asserted (causing a rising edge), maintained in a high state for a predetermined period of time, and then asserted (causing a falling edge). It is worth noting that in Fig.17 In the example device 1700 of , the reset signal 1742 is active low (as described above with respect to Fig.17The reset (R) input of the corresponding flip-flop of the device 1700 is discussed), however, for ease of description, Fig.25 Pulses are depicted (low state to high state, and then high state to low state). Any convention may be used without exceeding the scope (eg, active low or active high).

[0238] At time T1+predetermined time period (during which time period UP signal 1738 and DOWN signal 1740 are maintained at high level states), both UP signal 1738 and DOWN signal 1740 are deasserted (causing corresponding falling edges) in response to assertion of reset signal 1742.

[0239] From time T o At time T1, the phase frequency detector PFD performs a phase comparison between the reference clock 1734 and the feedback clock 1736 using the timing of their respective rising edges, and the phase detector PFD determines that the phase difference (Δφ) is less than 180 degrees and asserts the state signal 1732 ( Fig.25 1732) is asserted. Asserting the status signal 1732 enables double edge detection, and more specifically, triggering on both the rising and falling edges of the reference clock 1734 and the feedback clock 1736.

[0240] At time T2 , UP signal 1738 is asserted (causing a rising edge) in response to the falling edge of reference clock 1734 .

[0241] At time T3 , the DOWN signal 1740 is asserted (causing a rising edge) in response to the falling edge of the feedback clock 1736 .

[0242] At time T3 + a predetermined time period, in response to the falling edges of the UP signal 1738 and the DOWN signal 1740 and both being in a low level state, the reset signal 1742 is asserted (causing a rising edge), maintained in a high level state for a predetermined time period, and then asserted (causing a falling edge).

[0243] At time T3 + a predetermined time period (during which the UP signal 1738 and the DOWN signal 1740 are maintained at a high state), both the UP signal 1738 and the DOWN signal 1740 are deasserted (causing corresponding falling edges) in response to the assertion of the reset signal 1742.

[0244] Fig.26is a graph 2600 showing a simulated plot of a curve representing a single edge mode PFD transfer function of a phase error detector according to one or more examples. The PFD exhibits a NULL condition only at 0 degrees, not 180 degrees, and therefore always aligns rising edges with rising edges.

[0245] Fig. 27 is a graph 2700 showing a simulated plot of a curve representing a nominal dual edge mode PFD transfer function with an undesired NULL at 180 degrees and a desired NULL at 0 degrees. The false NULL condition at 180 degrees allows the clock tracking circuit to phase lock to the opposite edge and increase mismatch and reference spurs.

[0246] Fig.28 28 is a graph 2800 showing a simulated plot of a curve representing a dynamic dual edge mode transfer function. There is no longer a NULL condition at 180 degrees. Therefore, the PFD will push the PLL to lock the rising edge to the rising edge, as in the single edge mode case. When the phase error is small, the dual edge mode is enabled, resulting in a transfer curve gain of exactly 2X (triggering on both the rising and falling edges, rather than just on one of the rising or falling edges) and a doubled PFD rate. The portion of the curve that exhibits a 2X slope corresponds to the circuit operating in dual edge mode with a 2X gain (for this phase error range). A negative phase error refers to a situation where the feedback clock is ahead of the reference clock. A positive phase error refers to a situation where the feedback clock lags behind the reference clock.

[0247] Those of ordinary skill in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.29 Non-limiting examples illustrating specific implementations of the functional elements disclosed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware capable of executing the functional elements.

[0248] Fig.292900 is a block diagram of a circuit system 2900 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. The circuit system 2900 includes one or more processor processors 2902 (sometimes referred to herein as "processors 2902") operably coupled to one or more data storage devices storage devices 2906 (sometimes referred to herein as "storage devices 2906"). The storage devices 2906 include machine executable code 2908 stored thereon, and the processor processor 2902 includes logic circuits 2904. The machine executable code 2908 information describes functional elements that can be implemented by the logic circuit 2904 (e.g., executed by the logic circuit). The logic circuit 2904 is adapted to implement (e.g., execute) the functional elements described by the machine executable code 2908. When the functional elements described by the machine executable code 2908 are executed, the circuit system 2900 should be regarded as dedicated hardware for performing the functional elements disclosed herein. In some examples, processor 2902 may execute the functional elements described by machine executable code logic 2904 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process streams.

[0249] When implemented by the logic circuit machine executable code 2908 of the processor processor 2902, the machine executable code 2908 adapts the processor processor 2902 to perform the operations of the examples disclosed herein, including for determining the lock state of the clock tracking circuit. As a non-limiting example, the machine executable code 2908 may adapt the processor 2902 to perform some or all of the operations of one or more of the following: process 800, process 900, process 1000, process 1100, or process 1200.

[0250] Likewise, by way of non-limiting example, the machine executable code 2908 may adapt the processor 2902 to perform some or all of the features, functions, or operations disclosed herein of one or more of the following: device 100, device 200, device 300, device 400, device 500, device 600, device 700. More specifically, one or more of the features, functions, or operations disclosed herein: Figure 1 The phase detector 102, the digital discriminator 106 and the logic circuit 112; the device 200 includes a first trigger 202, a second trigger 204, a third trigger 220, and a fourth trigger 218; Figure 2The first delay circuit 208, the second delay circuit 222, the NAND gate 206 and the NOR gate 210; and the digital filter 302 and the register 304; the accumulator register 402, the comparator 404, the sampling clock divider 502, the sampling logic circuit 602, the interpolator 604, the extractor 606, the multiplexer 612, the clock tracking circuit 1300, the error detector 1302, the controller 1304, the controlled oscillator 1306 or the lock state detector 1318.

[0251] When implemented by the logic circuit machine executable code 2908 of the processor processor 2902, the machine executable code 2908 adapts the processor processor 2902 to perform the operations of the examples disclosed herein, including for double edge triggered phase error detection. As a non-limiting example, the machine executable code 2908 may adapt the processor 2902 to perform some or all of the operations of one or more of the following: process 1800, process 1900, process 2000, process 2100, process 2200, process 2300, 2400, timing diagram 2500, graph 2600, graph 2700, or graph 2800.

[0252] Likewise, by way of non-limiting example, the machine executable code 2908 may adapt the processor 2902 to perform some or all of the features, functions, or operations disclosed herein of one or more of the following: the device 1600 and the device 1700. More specifically, the features, functions, or operations disclosed herein of one or more of the following: the phase detector 1602, the phase error detector 1604, the single edge trigger 1606, the double edge trigger 1608; the phase detector 1702, the inverter 1704, the inverter 1706, the AND gate 1708, the AND gate 1710, the first flip-flop 1712, the second flip-flop 1714, the third flip-flop 1716, the fourth flip-flop 1718, the OR gate 1722, the OR gate 1724, the delay 1726, the NAND gate 1728.

[0253] Processor Processor 2902 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer executes functional elements corresponding to the machine executable code 2908 (e.g., software code, firmware code, hardware description) associated with the examples of the present disclosure. It should be noted that a general-purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor 502 may include any conventional processor, controller, microcontroller, or state machine. Processor 2902 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0254] In some examples, storage device 2906 includes volatile data storage device (e.g., random access memory (RAM)), non-volatile data storage device (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 2902 and storage device 2906 may be implemented in a single device (e.g., semiconductor device product, system on chip (SOC), but not limited thereto). In some examples, processor 2902 and storage device 2906 may be implemented in separate devices.

[0255] In some examples, machine executable code 2908 may include computer readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer readable instructions may be stored by storage device 2906, directly accessed by processor 2902, and executed by processor 2902 using at least logic circuit 2904. Also by way of non-limiting example, the computer readable instructions may be stored on storage device 2906, transferred to a memory device (not shown) for execution, and executed by processor 502 using at least logic circuit 2904. Thus, in some examples, logic circuit 508 includes electrically configurable logic circuit 2904.

[0256] In some examples, machine executable code 2908 may describe hardware (e.g., circuits) to be implemented in logic circuit 2904 to perform functional elements. The hardware may be described at any of a variety of abstraction levels from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). By way of non-limiting example, Verilog TM 、SystemVerilog TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0257] The HDL description may be converted into a description at any of a variety of other abstraction levels as needed. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 2904 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic piece, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 2908 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0258] In examples where the machine executable code 2908 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 2906) implements the hardware description described by the machine executable code 2908. By way of non-limiting example, the processor 2902 may include a programmable logic device (e.g., an FPGA or PLC), and the logic circuit 2904 may be electrically controlled to implement circuitry corresponding to the hardware description into the logic circuit 2904. Likewise, by way of non-limiting example, the logic circuit 2904 may include hard-wired logic manufactured by a manufacturing system (not shown, but including storage 2906) according to the hardware description of the machine executable code 2908.

[0259] Regardless of whether the machine executable code 2908 includes computer readable instructions or a hardware description, the logic circuit 2904 is adapted to perform the functional elements described by the machine executable code 2908 when implementing the functional elements of the machine executable code 2908. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0260] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that performs the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., computer-readable media, processing devices, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0261] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or any of various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0262] The terms used in this disclosure and in particular in the appended claims (e.g., the subject matter of the appended claims, but not limited thereto) are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," but not limited thereto). As used herein, the term "each" means "some or all." As used herein, the terms "each and every" mean "all."

[0263] Additionally, if a specific number of introduced claim expressions is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim expressions. However, the use of such phrases should not be construed to imply that a claim expression introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim expression to examples containing only one such expression, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "a kind" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more", but not limited to such); the same is true when a claim expression is introduced using a definite article.

[0264] Furthermore, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted as intending at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers intends at least two recitations, or two or more recitations, but not limited thereto). Furthermore, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited thereto.

[0265] In addition, any discrete word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0266] Additional non-limiting examples include:

[0267] Embodiment 1: A device comprising: a phase detector, wherein a state signal of the phase detector is based at least in part on a phase relationship between a reference clock and a feedback clock, the feedback clock being generated by a clock tracking circuit to track the reference clock; a digital discriminator for sampling the state signal of the phase detector; and a logic circuit for determining a locking state of the clock tracking circuit based at least in part on a sample of the state signal of the phase detector.

[0268] Embodiment 2: The apparatus according to embodiment 1, wherein the phase detector is used to set the state signal based at least in part on a phase threshold and the phase relationship between the reference clock and the feedback clock.

[0269] Embodiment 3: The device according to any one of embodiments 1 and 2, wherein the value of the phase threshold is settable.

[0270] Embodiment 4: The apparatus of any one of embodiments 1 to 3, wherein the phase detector is configured to set the state signal to a first value at least in part in response to determining that the determined difference is greater than a phase threshold.

[0271] Embodiment 5: An apparatus according to any one of embodiments 1 to 4, wherein the phase detector is used to: set the state signal of the phase detector to a second value, at least in part in response to determining that the determined difference is equal to or less than a phase threshold, wherein the second value is different from the first value.

[0272] Embodiment 6: An apparatus according to any one of embodiments 1 to 5, wherein, in order to determine the locking state of the clock tracking circuit, the logic circuit is used to: decode locking state information from samples of the state signal of the phase detector; and determine the locking state of the clock tracking circuit at least partially based on the decoded locking state information.

[0273] Embodiment 7: The device according to any one of embodiments 1 to 6, wherein the logic circuit is used to set the lock state signal to a first value to indicate a lock state and set the lock state signal to a second value to indicate an unlock state.

[0274] Embodiment 8: An apparatus according to any one of embodiments 1 to 7, wherein the phase detector is used to: detect the occurrence of similar corresponding edges of the reference clock and the feedback clock; and set the status signal to indicate whether the occurrence of the detected similar corresponding edges is within a predetermined range.

[0275] Embodiment 9: An apparatus according to any one of embodiments 1 to 8, wherein the phase detector is used to set the state signal to a first value in response to the time difference between the occurrence of similar corresponding edges detected by the reference clock and the feedback clock being less than a phase threshold.

[0276] Embodiment 10: An apparatus according to any one of embodiments 1 to 9, wherein the phase detector is used to set the state signal to a second value in response to the time difference between the occurrence of similar corresponding edges detected by the reference clock and the feedback clock being greater than or equal to a phase threshold.

[0277] Embodiment 11: The device according to any one of embodiments 1 to 10, wherein the digital discriminator includes an extractor for extracting the value of the state signal.

[0278] Embodiment 12: The apparatus of any one of embodiments 1 to 11, wherein the digital discriminator comprises an interpolator for interpolating values ​​based on the status signal.

[0279] Embodiment 13: The apparatus according to any one of embodiments 1 to 12, wherein the digital discriminator comprises a digital filter for blocking a state signal indicating a transient phase error and passing a state signal indicating a steady-state phase error.

[0280] Embodiment 14: A method, comprising: setting a state signal of a phase detector, wherein the state signal of the phase detector is set at least in part based on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock; and generating a signal indicating a locking state of the clock tracking circuit based at least in part on the state signal of the phase detector.

[0281] Embodiment 15: According to the method described in Embodiment 14, the method includes: determining whether the phase relationship between the reference clock and the feedback clock falls within a predetermined range; and setting the status signal of the phase detector based at least in part on the determination.

[0282] Embodiment 16: The method of any one of Embodiments 14 and 15, comprising: setting the state signal of the phase detector to a first value at least in part in response to determining that the determined difference is greater than a phase threshold.

[0283] Embodiment 17: According to the method described in any one of embodiments 14 to 16, the method includes: at least partially in response to determining that the determined difference is equal to or less than a phase threshold, setting the state signal of the phase detector to a second value, wherein the second value is different from the first value.

[0284] Embodiment 18: According to the method described in any one of Embodiments 14 to 17, the occurrence of similar corresponding edges of the reference clock and the feedback clock is detected; and the status signal is set to indicate whether the occurrence of the detected similar corresponding edges is within a predetermined range.

[0285] Embodiment 19: A method according to any one of Embodiments 14 to 18, wherein setting the status signal to indicate whether the occurrence of the detected similar corresponding edges is within the predetermined range includes: setting the status signal to a first value in response to the time difference between the occurrence of the detected similar corresponding edges of the reference clock and the feedback clock being less than a phase threshold.

[0286] Embodiment 20: A method according to any one of Embodiments 14 to 19, wherein setting the status signal to indicate whether the occurrence of the detected similar corresponding edges is within the predetermined range includes: setting the status signal to a second value in response to the time difference between the occurrence of the detected similar corresponding edges of the reference clock and the feedback clock being greater than or equal to a phase threshold.

[0287] Embodiment 21: According to the method described in any one of Embodiments 14 to 120, a sample of the status signal of the phase detector is obtained; locking status information is decoded from the sample of the status signal of the phase detector; and the locking status of the clock tracking circuit is determined at least in part based on the decoded locking status information.

[0288] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: a phase detector, wherein a state signal of the phase detector is based at least in part on a phase relationship between a reference clock and a feedback clock, the feedback clock being generated by a clock tracking circuit to track the reference clock; a digital discriminator, the digital discriminator being used to sample the state signal of the phase detector; and Logic circuitry is provided for determining a lock state of the clock tracking circuit based at least in part on samples of the state signal of the phase detector.

2. The apparatus of claim 1, wherein the phase detector is to set the state signal based at least in part on a phase threshold and the phase relationship between the reference clock and the feedback clock. The apparatus according to claim 2 , wherein the value of the phase threshold is configurable.

4. The apparatus of claim 1 , wherein the phase detector is configured to: The status signal is set to a first value in response at least in part to determining that the determined difference is greater than a phase threshold.

5. The apparatus of claim 1 , wherein the phase detector is configured to: The state signal of the phase detector is set to a second value in response at least in part to determining that the determined difference is equal to or less than a phase threshold, wherein the second value is different from the first value.

6. The apparatus of claim 1 , wherein to determine the lock state of the clock tracking circuit, the logic circuit is configured to: decoding lock status information from samples of the status signal of a phase detector; and determining the lock status of the clock tracking circuit based at least in part on the decoded lock status information.

7. The apparatus of claim 1, wherein the logic circuit is to set a lock status signal to a first value to indicate a locked state and to set the lock status signal to a second value to indicate an unlocked state.

8. The apparatus of claim 1, wherein the phase detector is configured to: detecting occurrences of similar corresponding edges of the reference clock and the feedback clock; and setting the status signal to indicate whether the detected occurrences of similar corresponding edges are within a predetermined range.

9. The apparatus of claim 8, wherein the phase detector is configured to: The status signal is set to a first value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being less than a phase threshold.

10. The apparatus of claim 8, wherein the phase detector is configured to: The status signal is set to a second value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being greater than or equal to a phase threshold.

11. The apparatus of claim 1, wherein the digital discriminator comprises a decimator for extracting a value of the state signal.

12. The apparatus of claim 1, wherein the digital discriminator comprises an interpolator for interpolating a value based on the status signal.

13. The apparatus of claim 1, wherein the digital discriminator comprises a digital filter for blocking a state signal indicative of a transient phase error and passing a state signal indicative of a steady-state phase error.

14. A method comprising: setting a state signal of a phase detector, wherein the state signal of the phase detector is set based at least in part on a phase relationship between a reference clock and a feedback clock generated by a clock tracking circuit to track the reference clock; as well as A signal indicative of a lock status of the clock tracking circuit is generated based at least in part on the status signal of the phase detector.

15. The method according to claim 14, comprising: determining whether the phase relationship between the reference clock and the feedback clock falls within a predetermined range; as well as The state signal of the phase detector is set based at least in part on the determination.

16. The method according to claim 14, comprising: The state signal of the phase detector is set to a first value in response at least in part to determining that the determined difference is greater than a phase threshold.

17. The method according to claim 14, comprising: The state signal of the phase detector is set to a second value in response at least in part to determining that the determined difference is equal to or less than a phase threshold, wherein the second value is different from the first value.

18. The method according to claim 14, detecting occurrences of similar corresponding edges of the reference clock and the feedback clock; and setting the status signal to indicate whether the detected occurrences of similar corresponding edges are within a predetermined range.

19. The method of claim 18, wherein setting the status signal to indicate whether the detected occurrence of similar corresponding edges is within the predetermined range comprises: The status signal is set to a first value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being less than a phase threshold.

20. The method of claim 18, wherein setting the status signal to indicate whether the detected occurrence of similar corresponding edges is within the predetermined range comprises: The status signal is set to a second value in response to a time difference between detected occurrences of similar corresponding edges of the reference clock and the feedback clock being greater than or equal to a phase threshold.

21. The method according to claim 14, obtaining a sample of the state signal of the phase detector; decoding lock status information from samples of the status signal of the phase detector; as well as The lock status of the clock tracking circuit is determined based at least in part on the decoded lock status information.

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