Semiconductor device

Abstract

The invention provides a semiconductor device capable of reducing the risk of thermal damage. According to one embodiment, a semiconductor device includes: a first electrode; a second electrode facing the first electrode in the first direction; a semiconductor layer of a first conductivity type provided between the first electrode and the second electrode; a plurality of first semiconductor regions of a second conductivity type provided on the first electrode side in the semiconductor layer and extending in a second direction orthogonal to the first direction; a plurality of second semiconductor regions provided on the front surface side of the plurality of first semiconductor regions, the second semiconductor regions having a second conductivity type impurity concentration higher than that of the first semiconductor regions; and a plurality of PIN diode regions provided on the first electrode side in the semiconductor layer, extending in a third direction orthogonal to the first direction and the second direction, and electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device. Background Art

[0002] In a JBS (Junction Barrier Schottky Diode), which is one of the Schottky barrier diodes (SBD), multiple p-type semiconductor regions are formed in a stripe shape. In addition, in a JBS, a PIN diode region is dispersedly arranged in an n-type semiconductor region. In the PIN diode region, a metal silicide layer is formed between the anode electrode and the p-type semiconductor region to reduce the contact resistance. The PIN diode region can make a large forward surge current flow in the n-type semiconductor region by using conductivity modulation.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 6995725 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] In the n-type semiconductor region, holes existing at a position far from the PIN diode region have a long distance to the electrode, so the resistance becomes large. As a result, the element may be destroyed by the heat generated in the process of the holes reaching the electrode.

[0008] An object of the present invention is to provide a semiconductor device capable of reducing the risk of thermal destruction.

[0009] Technical solutions for solving technical problems

[0010] A semiconductor device in one embodiment comprises: a first electrode; a second electrode, opposite to the first electrode in a first direction; a semiconductor layer of a first conductivity type, arranged between the first electrode and the second electrode; a plurality of first semiconductor regions of a second conductivity type, arranged on the first electrode side of the semiconductor layer and extending in a second direction orthogonal to the first direction; a plurality of second semiconductor regions, arranged on the surface side of the plurality of first semiconductor regions, the impurity concentration of the second conductivity type being higher than that of the first semiconductor regions; and a plurality of PIN diode regions, arranged on the first electrode side of the semiconductor layer, extending in a third direction orthogonal to the first direction and the second direction, and electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1It is a top view of the semiconductor device according to the first embodiment.

[0012] Figure 2 It is along Figure 1 A cross-sectional view along the cutting line AA is shown.

[0013] Figure 3 It is a cross-sectional view for explaining the step of forming a p-type semiconductor region.

[0014] Figure 4 It is used to illustrate p + A cross-sectional view of the step of forming a type semiconductor region.

[0015] Figure 5 It is a cross-sectional view for explaining the step of forming a metal silicide layer.

[0016] Figure 6 is a top view of a semiconductor device according to a comparative example.

[0017] Figure 7 It is along Figure 6 A cross-sectional view along the cutting line BB is shown.

[0018] Figure 8 It is a top view of the semiconductor device according to the second embodiment.

[0019] Fig. 9 It is along Figure 8 A cross-sectional view along the cutting line CC is shown.

[0020] Fig.10 It is a top view of the semiconductor device according to the third embodiment.

[0021] Fig.11 It is along Fig.10 A cross-sectional view along the cutting line DD is shown.

[0022] Fig.12 It is a top view of a semiconductor device according to a fourth embodiment.

[0023] Fig.13 It is along Fig.12 A cross-sectional view along the cutting line EE is shown. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention.

[0025] (First Embodiment)

[0026] Figure 1 It is a top view of the semiconductor device according to the first embodiment. Figure 2 It is along Figure 1The semiconductor device 1 of the present embodiment is a SBD, more specifically a JBS. The semiconductor device 1 includes an n-type semiconductor layer 10, an anode electrode 20, and a cathode electrode 30. The n-type semiconductor layer 10, the anode electrode 20, and the cathode electrode 30 correspond to a first conductive type semiconductor layer, a first electrode, and a second electrode, respectively.

[0027] In the following description, the X-axis, Y-axis, and Z-axis shown in each figure are sometimes used to illustrate the configuration and structure of each part of the semiconductor device. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction (third direction), the Y direction (second direction), and the Z direction (first direction), respectively. In addition, the Z direction is sometimes described as the top and the opposite direction is described as the bottom. In this embodiment, the X direction and the Y direction represent the in-plane directions parallel to the semiconductor device 1, and the Z direction represents the out-of-plane direction orthogonal to the semiconductor device 1. In addition, p, p + The expression means that the p-type impurity concentration becomes higher in this order.

[0028] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). In addition, the relative level of the impurity concentration can also be determined, for example, based on the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). In addition, the depth and distance of the semiconductor region can be obtained, for example, by SIMS.

[0029] The n-type semiconductor layer 10 is provided between the anode electrode 20 and the cathode electrode 30. The n-type semiconductor layer 10 is composed of, for example, epitaxially grown SiC (silicon carbide). Figure 2 As shown, a plurality of p-type semiconductor regions 40 and a plurality of PIN diode regions 50 are provided on the surface side of the n-type semiconductor layer 10 in contact with the anode electrode 20 .

[0030] Each p-type semiconductor region 40 corresponds to a first semiconductor region. + Type semiconductor region 41. p + The p-type semiconductor region 41 corresponds to a second semiconductor region having a higher p-type impurity concentration than that of the p-type semiconductor region 40 .

[0031] like Figure 1 As shown, the p-type semiconductor region 40 and the p + The type semiconductor region 41 is formed in a stripe shape extending in the Y direction.

[0032] like Figure 1As shown in FIG. 1 , each PIN diode region 50 extends along the X direction on the surface side of the n-type semiconductor layer 10. The planar shape of each PIN diode region 50 is a rectangle whose length in the X direction is longer than its length in the Y direction. In addition, each PIN diode region 50 is connected to at least one of the plurality of p-type semiconductor regions 40 and the plurality of p-type semiconductor regions 40. + At least one of the semiconductor regions 41 is electrically connected.

[0033] In addition, if Figure 1 As shown, the plurality of PIN diode regions 50 are evenly arranged so that the center distances d are equal to each other. For example, two PIN diode regions 50 arranged apart from each other in the X direction and one PIN diode region 50 arranged offset from the two PIN diode regions 50 in the Y direction are arranged in an equilateral triangle shape.

[0034] Each PIN diode region 50 includes a p-type semiconductor region 51, a p + The p-type semiconductor region 52 and the metal silicide layer 53. The p-type semiconductor region 51 corresponds to a third semiconductor region having the same p-type impurity concentration as the p-type semiconductor region 40. + The p-type semiconductor region 52 corresponds to a region with a higher p-type impurity concentration than the p-type semiconductor region 51 and + A fourth semiconductor region having the same type as the semiconductor region 41.

[0035] Each p-type semiconductor region 51 has the same thickness as that of the p-type semiconductor region 40 . In addition, each p-type semiconductor region 51 is in contact with at least one of the plurality of p-type semiconductor regions 40 in the PIN diode region 50 .

[0036] Each p + The p-type semiconductor region 52 is provided on the surface side of the p-type semiconductor region 51. + The semiconductor region 52 has a p + The same thickness as the type semiconductor region 41. + The PIN diode region 50 is connected to a plurality of p + type semiconductor regions 41 are in contact with at least one of the semiconductor regions 41.

[0037] Each metal silicide layer 53 is disposed on p + The metal silicide layer 53 is formed between the semiconductor region 52 and the anode electrode 20. + The contact between the semiconductor region 52 and the anode electrode 20 becomes an ohmic contact.

[0038] like Figure 2 As shown, the anode electrode 20 is connected to the n-type semiconductor layer 10, the p-type semiconductor region 40, and the p +The anode electrode 20 is formed of a metal layer. The structure of the metal layer can be a single layer structure or a stacked structure of, for example, titanium and aluminum. The anode electrode 20 is opposite to the cathode electrode 30 in the Z direction via the n-type semiconductor layer 10.

[0039] The cathode electrode 30 is in contact with the back side (bottom side) of the n-type semiconductor layer 10. The cathode electrode 30 is composed of a metal layer. The structure of the metal layer may be a single layer composed of nickel silicide, titanium, nickel, silver, gold, etc., or a stacked structure in which a plurality of materials arbitrarily selected from these metal groups are stacked.

[0040] Next, refer to Figure 2 to Figure 5 , an example of a method for manufacturing the semiconductor device 1 configured as described above will be described.

[0041] First, if Figure 3 As shown, a p-type semiconductor region 40 and a p-type semiconductor region 51 are simultaneously formed on the surface side of the n-type semiconductor layer 10. The p-type semiconductor region 40 and the p-type semiconductor region 51 can be formed, for example, by ion implanting a p-type impurity into the surface of the n-type semiconductor layer 10 using a mask having an opening at a location where each p-type semiconductor region is formed. In this case, the p-type impurity is, for example, aluminum. In this case, the p-type impurity concentration is 1×10 16 cm -3 In addition, the material of the mask is, for example, an oxide film or a resist.

[0042] Then, if Figure 4 As shown, a p-type semiconductor region 40 is formed on the surface of the p-type semiconductor region 40. + At the same time as the p-type semiconductor region 41, a p-type semiconductor region 51 is formed on the surface of the p-type semiconductor region 51. + Type semiconductor region 52. Similar to p-type semiconductor regions 40 and 51, p + The semiconductor regions 41 and 52 can also be formed by using the + The p-type semiconductor region 52 is formed by ion implanting p-type impurities into the surface of each p-type semiconductor region. However, the concentration of the aluminum implanted at this time is higher than that when the p-type semiconductor regions 40 and 51 are formed, and is, for example, about 1×10 20 cm -3 .

[0043] Then, if Figure 5 As shown in p + The metal silicide layer 53 is formed on the surface of the p-type semiconductor region 52. Thus, the PIN diode region 50 is completed. When the metal silicide layer 53 is formed, first, +A silicon film is formed on the surface of the semiconductor region 52. Next, a metal film made of nickel (Ni) or titanium (Ti) is formed by sputtering, for example. Then, the metal silicide layer 53 is formed by reacting the silicon with the metal by annealing or the like.

[0044] Finally, return Figure 2 The anode electrode 20 and the cathode electrode 30 are formed on both surfaces of the n-type semiconductor layer 10, thereby completing the semiconductor device 1 of this embodiment. The above-mentioned manufacturing process is an example of the manufacturing method of the semiconductor device 1 of the first embodiment, and does not limit the manufacturing method.

[0045] Here, refer to Figure 6 and Figure 7 , a comparative example to be compared with the present embodiment will be described.

[0046] Figure 6 is a top view of a semiconductor device according to a comparative example. Figure 7 It is along Figure 6 The sectional view is shown along the cutting line BB. Figure 6 as well as Figure 7 In the present invention, the same components as those of the semiconductor device 1 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0047] In the semiconductor device 100 of this comparative example, Figure 6 As shown, the plurality of PIN diode regions 50 are not arranged evenly. For example, three PIN diode regions 50 are arranged so that their respective centers become vertices of an isosceles triangle. In this case, the center distance d1 of two PIN diode regions 50 separated in the X direction, i.e., the length of the base of the isosceles triangle, is different from the center distance d2 of the PIN diode regions 50 corresponding to the length of the hypotenuse of the isosceles triangle.

[0048] In the semiconductor device 100 configured as described above, when a voltage is applied to set the anode electrode 20 to a low potential and the cathode electrode 30 to a high potential, the electrons e in the n-type semiconductor layer 10 move toward the cathode electrode 30 .

[0049] On the other hand, the holes h in the n-type semiconductor layer 10 move toward the PIN diode region 50. At this time, the PIN diode regions 50 are not evenly arranged in the semiconductor device 100. Therefore, the distance to the PIN diode region 50 becomes longer for some holes h. As a result, there is a concern that the semiconductor device 100 may be thermally destroyed by the heat generated by the movement of the holes h.

[0050] On the other hand, in the semiconductor device 1 of the present embodiment, Figure 2 As shown, p +The p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. In addition, the PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h leaving the PIN diode region 50 are as follows: Figure 2 As shown in FIG. 1 , the holes h move toward the p-type semiconductor region 40. As a result, the moving distance of the holes h is shortened compared to the comparative example, so that heat is less likely to be generated.

[0051] Therefore, according to this embodiment, the risk of thermal destruction can be reduced.

[0052] (Second Embodiment)

[0053] Figure 8 It is a top view of the semiconductor device according to the second embodiment. Fig. 9 It is along Figure 8 The cross-sectional view is shown along the cutting line CC. Figure 8 as well as Fig. 9 In the present invention, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0054] In the semiconductor device 2 of this embodiment, as Figure 8 As shown in FIG. 1 , the PIN diode regions 50 are evenly arranged similarly to the first embodiment. That is, the three PIN diode regions 50 are arranged in an equilateral triangle shape.

[0055] On the other hand, in this embodiment, the shape of the PIN diode region 50 is different from that in the first embodiment. Specifically, the p-type semiconductor region 51 has a first region 51a and a second region 51b. The first region 51a is a region opposite to the metal silicide layer 53 in the Z direction. In addition, the second region 51b is a cross-linked region extending from the outer periphery of the first region 51a in the X direction. The length (vertical width) of the second region 51b in the Y direction is shorter than the length (vertical width) of the first region 51a in the Y direction.

[0056] In addition, in this embodiment, p + The semiconductor region 52 has a first region 52a and a second region 52b. The first region 52a is a region provided between the first region 51a and the metal silicide layer 53. In addition, the second region 52b is a cross-linked region extending from the outer periphery of the first region 52a in the X direction on the second region 51b. The length (vertical width) of the second region 52b in the Y direction is shorter than the length (vertical width) of the first region 52a in the Y direction.

[0057] Furthermore, in this embodiment, the length (lateral width) of the metal silicide layer 53 in the X direction is shorter than that in the first embodiment. Figure 1As shown, the length (width) of the metal silicide layer 53 in the X direction is longer than the length (width) in the Y direction, so that all p + The semiconductor region 41 is connected to the p + The type semiconductor region 52 is electrically connected to at least one metal silicide layer 53 .

[0058] On the other hand, in this embodiment, if Figure 8 As shown, multiple p + A portion of the p-type semiconductor region 41 + The type semiconductor region 41 is electrically connected to at least one metal silicide layer 53 via the first region 52a, and the remaining p + The type semiconductor region 41 is electrically connected to at least one metal silicide layer 53 via the second region 52b and the first region 52a. Therefore, the lateral width of the metal silicide layer 53 is shortened.

[0059] The semiconductor device 2 of this embodiment can be manufactured by the same process as the semiconductor device 1 of the first embodiment. However, when forming the p-type semiconductor region 51, a mask along the shape of the first region 51a and the second region 51b is used to ion-implant the p-type impurity (for example, aluminum). + When forming the p-type semiconductor region 52, a p-type impurity (eg, aluminum) is ion-implanted using a mask along the shapes of the first region 52a and the second region 52b.

[0060] According to this embodiment, similarly to the first embodiment, p + The p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. In addition, the PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h leaving the PIN diode region 50 are as follows: Fig. 9 As shown in FIG. 1 , the holes h move toward the p-type semiconductor region 40. As a result, the moving distance of the holes h is shortened, and thus it is difficult to generate heat. Therefore, the risk of thermal destruction can be reduced.

[0061] In this embodiment, the lateral width of the metal silicide layer 53 is shorter than that of the first embodiment. Therefore, the area of ​​the metal silicide layer 53 is smaller than that of the first embodiment, so the effective area that functions as an SBD increases. This can improve the forward voltage characteristics.

[0062] (Third Embodiment)

[0063] Fig.10 It is a top view of the semiconductor device according to the third embodiment. Fig.11 It is along Fig.10 The sectional view is shown along the cutting line DD. Fig.10 as well as Fig.11In the present invention, the same components as those of the first embodiment and the second embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0064] In the semiconductor device 3 of this embodiment, as Fig.10 As shown in FIG. 1 , the PIN diode regions 50 are evenly arranged similarly to the second embodiment. That is, the three PIN diode regions 50 are arranged in an equilateral triangle shape.

[0065] In the semiconductor device 3 of the present embodiment, the p + The p-type semiconductor region 52 includes a first region 52 a and a second region 52 b similarly to the second embodiment. The first region 52 a is a region provided between the p-type semiconductor region 51 and the metal silicide layer 53 .

[0066] Furthermore, in the semiconductor device 3 of the present embodiment, similarly to the second embodiment, the length (lateral width) of the metal silicide layer 53 in the X direction is shortened.

[0067] On the other hand, in the semiconductor device 3 of the present embodiment, as Fig.11 As shown, the second region 52b is disposed inside the n-type semiconductor layer 10. Therefore, through the second region 52b, the first region 52a and the n-type semiconductor layer 10 are + The n-type semiconductor regions 41 are electrically connected at the lower portions of the respective side surfaces. In addition, since the second region 52 b is provided inside the n-type semiconductor layer 10 , the n-type semiconductor layer 10 exists between the second region 52 b and the anode electrode 20 .

[0068] The semiconductor device 3 of this embodiment can be manufactured by the same process as the semiconductor device 1 of the first embodiment. + When forming the n-type semiconductor region 52, p-type impurities (e.g., aluminum) are ion-implanted at different timings using a mask different from that of the first region 52a and the second region 52b. When forming the first region 52a, p-type impurities are ion-implanted into the surface of the n-type semiconductor layer 10 (p-type semiconductor region 51). On the other hand, when forming the second region 52b, p-type impurities are ion-implanted into the interior of the n-type semiconductor layer 10.

[0069] According to this embodiment, similarly to the second embodiment, p + The p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. In addition, the PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h leaving the PIN diode region 50 are as follows: Fig.11As shown in FIG. 1 , the holes h move toward the p-type semiconductor region 40. As a result, the moving distance of the holes h is shortened, and thus it is difficult to generate heat. Therefore, the risk of thermal destruction can be reduced.

[0070] In addition, in this embodiment, p + The second region 52b of the n-type semiconductor region 52 is provided inside the n-type semiconductor layer 10, so the n-type semiconductor layer 10 exists between the second region 52b and the anode electrode 20. Therefore, the area of ​​the n-type semiconductor layer 10 is smaller than that of the second embodiment, so the effective area that functions as an SBD is further increased. Thus, the forward voltage characteristics can be further improved.

[0071] (Fourth Embodiment)

[0072] Fig.12 It is a top view of a semiconductor device according to a fourth embodiment. Fig.13 It is along Fig.12 The sectional view is shown along the cutting line EE. Fig.12 as well as Fig.13 In the present invention, the same components as those of the first embodiment and the second embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0073] In the semiconductor device 4 of this embodiment, as Fig.12 As shown in FIG. 1 , the PIN diode regions 50 are evenly arranged similarly to the second embodiment. That is, the three PIN diode regions 50 are arranged in an equilateral triangle shape.

[0074] In addition, in the semiconductor device 4 of the present embodiment, similarly to the second embodiment, p + The type semiconductor region 52 includes a first region 52a and a second region 52b. In addition, the length (lateral width) of the metal silicide layer 53 in the X direction is shortened.

[0075] On the other hand, in the semiconductor device 4 of the present embodiment, the p-type semiconductor region 51 has a third region 51c in addition to the first region 51a and the second region 51b. The third region 51c is a region protruding from the bottom surface of the first region 51a toward the cathode electrode 30 directly below the metal silicide layer 53 .

[0076] The semiconductor device 4 of this embodiment can be manufactured by the same process as the semiconductor device 1 of the first embodiment. However, when forming the p-type semiconductor region 51, in order to form the third region 51c, the p-type impurity is ion-implanted to a position deeper than the first region 51a from the surface of the n-type semiconductor layer 10.

[0077] According to this embodiment, similarly to the second embodiment, p +The p-type semiconductor region 41 is provided on the surface of the p-type semiconductor region 40. In addition, the PIN diode regions 50 are evenly arranged. Therefore, when a voltage is applied between the anode electrode 20 and the cathode electrode 30, the holes h leaving the PIN diode region 50 are as follows: Fig.13 As shown in FIG. 1 , the holes h move toward the p-type semiconductor region 40. As a result, the moving distance of the holes h is shortened, and thus it is difficult to generate heat. Therefore, the risk of thermal destruction can be reduced.

[0078] In addition, in the present embodiment, the third region 51c is provided at a deep position directly below the metal silicide layer 53 in the PIN diode region 50. Therefore, the electric field is concentrated in the third region 51c, so that the voltage can be locally broken down directly below the metal silicide layer 53. As a result, the holes h can be efficiently discharged from the n-type semiconductor layer 10.

[0079] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0080] Description of Reference Numerals

[0081] 1, 2, 3, 4: Semiconductor devices

[0082] 10: n-type semiconductor layer

[0083] 20: Anode electrode (first electrode)

[0084] 30: cathode electrode (second electrode)

[0085] 40: p-type semiconductor region (first semiconductor region)

[0086] 41: p + Type semiconductor region (second semiconductor region)

[0087] 50: PIN diode area

[0088] 51: p-type semiconductor region (third semiconductor region)

[0089] 52: p + Type semiconductor region (fourth semiconductor region)

[0090] 52a: First Area

[0091] 52b: Second area

[0092] 53: Metal silicide layer

Claims

1. A semiconductor device, characterized in that: have: a first electrode; a second electrode, opposite to the first electrode in a first direction; A semiconductor layer of a first conductivity type is disposed between the first electrode and the second electrode; A plurality of first semiconductor regions of a second conductivity type, arranged on the first electrode side of the semiconductor layer, and extending in a second direction orthogonal to the first direction; A plurality of second semiconductor regions, which are arranged on the surface side of the plurality of first semiconductor regions and have a second conductivity type impurity concentration higher than that of the first semiconductor regions; as well as A plurality of PIN diode regions are arranged on the first electrode side in the semiconductor layer, extend in a third direction orthogonal to the first direction and the second direction, and are electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions.

2. The semiconductor device according to claim 1, wherein: The plurality of PIN diode regions respectively have: A third semiconductor region of the second conductivity type is in contact with at least one of the plurality of first semiconductor regions; a fourth semiconductor region disposed on the surface side of the third semiconductor region, wherein the second conductivity type impurity concentration is higher than that of the third semiconductor region; as well as A metal silicide layer is disposed between the fourth semiconductor region and the first electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that: The plurality of PIN diode regions are evenly arranged so that center distances are equal to each other.

4. The semiconductor device according to claim 3, wherein: Three of the plurality of PIN diode regions are arranged in a regular triangle shape.

5. The semiconductor device according to claim 1 or 2, characterized in that: The planar shape of the plurality of PIN diode regions is a rectangle whose length in the third direction is longer than that in the second direction.

6. The semiconductor device according to claim 2, wherein: The fourth semiconductor region includes a first region provided between the metal silicide layer and the third semiconductor region, and a second region extending from an outer periphery of the first region in the third direction.

7. The semiconductor device according to claim 6, wherein: A portion of the plurality of second semiconductor regions is electrically connected to the metal silicide layer via the first region, The remaining regions of the plurality of second semiconductor regions except for the partial region are electrically connected to the metal silicide layer via the second region and the first region.

8. The semiconductor device according to claim 6, wherein: The second region is disposed inside the semiconductor layer.

9. The semiconductor device according to claim 2, wherein: The third semiconductor region has a region protruding toward the second electrode just below the metal silicide layer.

10. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device is a Schottky barrier diode.

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