Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes: a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface; a plurality of protrusions having a top surface, which is a part of the first surface, and having side surfaces connected to the top surface; a first electrode forming a Schottky junction with the plurality of protrusions; the second electrode is arranged on the second surface; a first semiconductor region of a first conductivity type provided in the SiC layer; a second semiconductor region of a second conductivity type, which is provided in the SiC layer between the plurality of protrusions, and which is located between the first semiconductor region and the first electrode; and a third semiconductor region of the first conductivity type, which is provided on the side surface of the protrusion portion, is located between the first electrode and the first semiconductor region in the protrusion portion, and has a higher impurity concentration of the first conductivity type than the first semiconductor region.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] As one of the semiconductor devices, a Schottky barrier diode (SBD) is known, which is a junction between metal and semiconductor. The SBD has a forward voltage (V F ) is small and has the advantages of short reverse recovery time. SBD also has a leakage current (I R ) has a large disadvantage, but in order to suppress leakage current, a JBS (Junction Barrier Schottky Diode) structure is used in which a p-type region is buried on the surface of an n-type semiconductor layer. Furthermore, in order to simultaneously reduce forward voltage and leakage current, it is known to set the metal interface side of the n-type semiconductor layer as a trench structure.

[0003] In order to achieve a high withstand voltage, silicon carbide (SiC) is used as a semiconductor material. However, in a trench structure SBD using SiC, the Schottky junction characteristics are different on the surface and side of the trench, so there is a rise voltage (V th ), technical problems with forward voltage deviation.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-55009

[0007] Patent Document 2: Japanese Patent No. 7067698

[0008] Patent Document 3: Japanese Patent No. 5557581

[0009] Patent Document 4: Japanese Patent Application Publication No. 2023-046669 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] The technical problem to be solved by the present invention is to provide a semiconductor device capable of suppressing the variation in the rise voltage and the forward voltage.

[0012] Means for solving technical problems

[0013] A semiconductor device of an embodiment comprises: a SiC layer having a first surface composed of a silicon surface and a second surface composed of a carbon surface on the opposite side of the first surface; a plurality of protrusions arranged in the SiC layer, with a part of the first surface as a top surface, and having a side surface connected to the top surface; a first electrode forming a Schottky junction with the plurality of protrusions; a second electrode arranged on the second surface; a first semiconductor region of a first conductivity type arranged in the SiC layer; a second semiconductor region of a second conductivity type arranged in the SiC layer between the plurality of protrusions and located between the first semiconductor region and the first electrode; and a third semiconductor region of the first conductivity type arranged on the side surface of the protrusion, located between the first electrode and the first semiconductor region in the protrusion, and having a higher impurity concentration of the first conductivity type than the first semiconductor region. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional view of the semiconductor device according to the first embodiment.

[0015] Figure 2 Yes Figure 1 A magnified view of area A.

[0016] Figure 3 is the I of the Schottky barrier diode when the Schottky characteristic adjustment unit is not provided. F -V F Characteristics graph.

[0017] Figure 4 1 is a graph showing the I of the Schottky barrier diode of the semiconductor device according to the first embodiment. F -V F Characteristics graph.

[0018] Figure 5 It is a partial cross-sectional view of a semiconductor device according to a second embodiment.

[0019] Figure 6 1 is a graph showing the I of the Schottky barrier diode of the semiconductor device according to the second embodiment. F -V F Characteristics graph.

[0020] Figure 7 It is a partial cross-sectional view of a semiconductor device according to a third embodiment.

[0021] Figure 8 It is a diagram showing a partial cross section of another semiconductor device to which the Schottky characteristic adjustment portion of the first to third embodiments can be applied.

[0022] Fig. 9 yes Figure 8A partial top view of a semiconductor device is shown.

[0023] Fig.10 It is a partial top view of a semiconductor device including a high-concentration anode region having an octagonal planar shape. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual, and the ratios of the various parts may not be the same as in reality. In the specification and the accompanying drawings, the same reference numerals are given to the same elements as those previously described with respect to the accompanying drawings that have already appeared, and detailed descriptions are appropriately omitted.

[0025] In the following description, n is sometimes used to indicate the relative high and low impurity concentrations in a semiconductor region. + 、n、n - 、p + ,p,p - The statement of + Indicates that the concentration of n-type impurities is relatively higher than n, n - Indicates that the n-type impurity concentration is relatively lower than n. + Indicates that the p-type impurity concentration is relatively higher than p, p - Indicates that the p-type impurity concentration is relatively lower than p. n-type, n + Type and n - The p-type is an example of the first conductivity type in the claims. + Type and p - The first conductivity type is an example of the second conductivity type in the claims. In addition, in the following description, the n-type and the p-type may be reversed. That is, the first conductivity type may be the p-type and the second conductivity type may be the n-type.

[0026] The impurity concentration can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined based on the level of the carrier concentration obtained by, for example, SCM (Scanning Capacitance Microscopy).

[0027] (First Embodiment)

[0028] Reference Figure 1 and Figure 2 , a semiconductor device according to a first embodiment is described. Figure 1 It is a cross-sectional view of the semiconductor device 1 according to the present embodiment. Figure 2 Yes Figure 1 A magnified view of area A. In addition, Figure 1This is a common drawing for the second and third embodiments described later.

[0029] like Figure 1 As shown, the semiconductor device 1 includes a SiC layer 10, a silicide layer 16, an anode electrode 20, a cathode electrode 30, and a field oxide film 40. The semiconductor device 1 is a trench SBD in which the metal interface side of the n-type semiconductor layer is provided with a trench structure, and more specifically, a trench JBS in which a p-type semiconductor region is provided at the bottom of the trench.

[0030] The SiC layer 10 is a single crystal SiC (silicon carbide), for example, composed of 4H-SiC. In addition, the SiC layer 10 may be an epitaxial layer, or a semiconductor substrate, or may be composed of a semiconductor substrate and an epitaxial layer disposed thereon. In addition, the SiC layer 10 may be other crystal types such as 3C-SiC and 6H-SiC.

[0031] like Figure 1 As shown, the SiC layer 10 has an upper surface 10a and a lower surface 10b, which is a main surface opposite to the upper surface 10a. The upper surface 10a is a (0001) plane, and the lower surface 10b is a (000-1) plane. The (0001) plane is sometimes called a silicon plane, and the (000-1) plane is sometimes called a carbon plane.

[0032] In addition, the upper surface 10a and the lower surface 10b of the SiC layer 10 may not strictly coincide with the (0001) plane and the (000-1) plane, respectively. For example, the upper surface 10a is a plane inclined at 0 degrees or more and 8 degrees or less relative to the (0001) plane, and the lower surface 10b is a plane inclined at 0 degrees or more and 8 degrees or less relative to the (000-1) plane.

[0033] In the present application, when a surface is described as "composed of a silicon surface", the above range is included. That is, when the upper surface 10a is referred to as being composed of a silicon surface, the upper surface 10a is a surface that is inclined at 0 degrees or more and 8 degrees or less relative to the (0001) surface. Similarly, when the lower surface 10b is referred to as being composed of a carbon surface, the lower surface 10b is a surface that is inclined at 0 degrees or more and 8 degrees or less relative to the (000-1) surface.

[0034] A plurality of protrusions 10p are provided in the SiC layer 10. These protrusions 10p are formed by forming a plurality of grooves on the upper surface 10a of the SiC layer 10. Each protrusion 10p has a top surface 10pt and a side surface 10ps connected to the top surface 10pt. The top surface 10pt is a part of the upper surface 10a of the SiC layer 10 and is a surface composed of a silicon surface. A silicide layer 16 is provided on the surface connecting adjacent protrusions 10p (i.e., the bottom surface of the groove).

[0035] A plurality of semiconductor regions are provided in the SiC layer 10, namely, a drift region 11 of a first conductivity type, an anode region 12 of a second conductivity type, a Schottky characteristic adjustment portion 13 of a first conductivity type, a cathode region 14 of a first conductivity type, high-concentration anode regions 15 and 15e of a second conductivity type, and a reduced surface electric field (resurf) region 19 of a second conductivity type.

[0036] The first conductivity type semiconductor region contains, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) as an n-type impurity, and the second conductivity type semiconductor region contains, for example, aluminum (Al) or boron (B) as a p-type impurity.

[0037] like Figure 1 and Figure 2 As shown, the anode electrode 20 is provided so as to bury the plurality of protrusions 10p on the upper surface 10a side of the SiC layer 10. Schottky junctions are formed between the anode electrode 20 and the plurality of protrusions 10p.

[0038] The anode electrode 20 includes titanium (Ti), molybdenum (Mo), vanadium (V), nickel (Ni), or a stacked film of titanium and aluminum (Ti / Al). In addition, the anode electrode 20 may also have a conductive layer (not shown) composed of a material different from the above materials (copper, aluminum, etc.) on the conductive layer composed of the above materials.

[0039] The cathode electrode 30 is provided on the lower surface 10b of the SiC layer 10. An ohmic junction is formed between the cathode electrode 30 and the SiC layer 10 (cathode region 14 in this embodiment). The anode electrode 20 is, for example, a stacked film of titanium and aluminum (Ti / Al).

[0040] The field oxide film 40 is provided on the upper surface 10a of the SiC layer 10 so as to cover the RESURF region 19. The field oxide film 40 is made of, for example, a silicon oxide film.

[0041] Next, each semiconductor region provided in the SiC layer 10 will be described.

[0042] The drift region 11 is provided in the SiC layer 10. - The impurity concentration of the n-type impurity in the drift region 11 is, for example, 1×10 15 cm -3 Above and 2×10 16 cm -3 Hereinafter, the drift region 11 is an example of a first semiconductor region in the claims.

[0043] The anode region 12 is a p-type semiconductor region provided in the SiC layer 10 between the plurality of protrusions 10p. The anode region 12 is located between the drift region 11 and the anode electrode 20. By providing the anode region 12, the depletion layer expands when a reverse bias is applied, and leakage current can be suppressed. The anode region 12 is an example of a second semiconductor region in the claims.

[0044] The impurity concentration of the p-type impurity in the anode region 12 is, for example, 5×10 16 cm -3 Above and 5×10 18 cm -3 The anode region 12 is formed, for example, by forming a trench on the upper surface 10 a of the SiC layer 10 and then ion-implanting a p-type impurity into the bottom surface of the trench.

[0045] The Schottky characteristic adjustment portion 13 is an n-type or n-type Schottky characteristic adjustment portion 13 provided on the side surface 10ps of the protrusion 10p. + The n + The n-type semiconductor region is located between the anode electrode 20 and the drift region 11 in the protrusion 10p. The impurity concentration of the n-type impurity in the Schottky characteristic adjustment portion 13 is higher than that of the drift region 11, for example, 1×10 16 cm -3 Above and 1×10 20 cm -3 The Schottky characteristic adjustment portion 13 is an example of a third semiconductor region in the claims.

[0046] The Schottky characteristic adjustment portion 13 is configured to increase the Schottky barrier height (φ) on the side surface 10ps of the protrusion 10p. B ) is lowered and is set close to the Schottky barrier height in the top surface 10pt. For more details, refer to Figure 3 and Figure 4 Describe in more detail.

[0047] The Schottky characteristic adjustment portion 13 is formed by implanting n-type impurity ions into the side 10ps (side of the groove) of the protrusion 10p by an inclined ion implantation method, etc. Alternatively, a mask having an opening at the end of the protrusion 10p may be formed on the upper surface 10a of the SiC layer 10, and n-type impurities may be implanted into the opening to form the Schottky characteristic adjustment portion 13.

[0048] The cathode region 14 is provided in the SiC layer 10 and is located between the drift region 11 and the cathode electrode 30. + The impurity concentration of the n-type impurity in the cathode region 14 is, for example, 1×10 18 cm -3 Above and 1×10 21cm -3 the following.

[0049] The high-concentration anode regions 15 and 15e are arranged in the anode region 12. + The impurity concentration of the p-type impurities in the high-concentration anode regions 15 and 15e is higher than that of the anode region 12, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 The high-concentration anode regions 15 and 15e are formed, for example, by implanting p-type impurity ions into the bottom surface of the trench using a mask with a portion of the bottom surface of the trench opened after forming the anode region 12. The high-concentration anode region 15 is, for example, arranged in a rectangular shape when viewed from above. The high-concentration anode region 15e is arranged at the outer peripheral portion of the anode region 12 so as to surround the element region including the high-concentration anode region 15 (see Fig. 9 ).

[0050] The RESURF region 19 is provided in the SiC layer 10 to improve the withstand voltage of the semiconductor device 1. - The impurity concentration of the p-type impurity in the RESURF region 19 is lower than the impurity concentration of the p-type impurity in the anode region 12, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 Next, the RESURF region 19 is electrically connected to the anode electrode 20 .

[0051] The silicide layer 16 is provided between the high-concentration anode regions 15 and 15e and the anode electrode 20. The silicide layer 16 is made of, for example, nickel silicide. The silicide layer 16 is provided to reduce the resistance between the anode region 12 and the anode electrode 20. The silicide layer 16 is formed by a sputtering method or the like after the anode region 12 and the high-concentration anode regions 15 and 15e are formed.

[0052] Furthermore, an n-type buffer layer (not shown) having an n-type impurity concentration between the impurity concentration of the drift region 11 and the impurity concentration of the cathode region 14 may be provided between the drift region 11 and the cathode region 14. In addition, the high-concentration anode regions 15, 15e and / or the silicide layer 16 may be omitted.

[0053] Next, refer to Figure 3 and Figure 4 , the effect brought about by the Schottky characteristic adjustment portion 13 is described. Figure 3 I represents the Schottky barrier diode (SBD) when the Schottky characteristic adjustment unit 13 is not provided. F -VF Features. Figure 3 In the figure, characteristic C1 represents the I of the Schottky junction at the top surface 10 pt of the protrusion 10 p. F -V F Characteristics, characteristic C2 represents the I of the Schottky junction at the side 10ps of the protrusion 10p. F -V F characteristic. Figure 4 I represents the SBD of the semiconductor device of this embodiment. F -V F characteristic.

[0054] In the SiC layer 10, the Schottky barrier height of the Schottky junction on the side 10ps is higher than the Schottky barrier height of the top surface 10pt of the silicon surface. For example, when the SiC layer 10 is composed of 4H-SiC and the anode electrode 20 is composed of titanium, the Schottky barrier height in the carbon surface is 1.30eV, and the Schottky barrier height in the silicon surface is 1.17eV. The Schottky barrier height in the side 10ps is a value between 1.17eV and 1.30eV. Since the Schottky barrier height of the side 10ps is higher than the Schottky barrier height of the top surface 10pt, in a structure where the Schottky characteristic adjustment portion 13 is not provided, as Figure 3 As shown, the rising voltage V of the SBD in 10ps is th2 Greater than the rise voltage V of the SBD within 10pt of the top surface th1 In addition, regarding the forward voltage, the side surface 10ps is also larger than the top surface 10pt.

[0055] On the other hand, in the semiconductor device 1 of the present embodiment, a layer composed of n + The Schottky characteristic adjustment section 13 is composed of a semiconductor region of the type. Therefore, the Schottky barrier height in the side 10ps is reduced. As a result, Figure 4 As shown, the rising voltage V of the SBD in 10ps is th2 With the rising voltage V th1 Roughly equal.

[0056] Therefore, according to the present embodiment, the variation in the rise voltage and the forward voltage between the top surface 10 pt and the side surface 10 ps can be reduced, and a Schottky barrier diode having excellent characteristics of uniformity of the rise voltage and the forward voltage can be provided.

[0057] (Second Embodiment)

[0058] Next, refer to Figure 5 The semiconductor device of the second embodiment is described below. In this embodiment, the Schottky barrier height on the side surface 10ps is not reduced, but the Schottky barrier height on the top surface 10pt is increased.

[0059] The overall schematic structure of the semiconductor device of the second embodiment is similar to that of the semiconductor device of the first embodiment. Figure 1 same. Figure 5 This is a characteristic portion of the semiconductor device of this embodiment (with Figure 2 corresponding area).

[0060] like Figure 5 As shown, in the second embodiment, a Schottky characteristic adjustment portion 17 is provided on the top surface 10pt of the protrusion 10p instead of the Schottky characteristic adjustment portion 13 described in the first embodiment. The Schottky characteristic adjustment portion 17 is a p-type or p + The type semiconductor region is located between the anode electrode 20 and the drift region 11 in the protrusion 10p.

[0061] The impurity concentration of the p-type impurity in the Schottky characteristic adjustment portion 17 is, for example, 1×10 16 cm -3 Above and 1×10 20 cm -3 The Schottky characteristic adjustment portion 17 is an example of a fourth semiconductor region in the claims. The Schottky characteristic adjustment portion 17 is formed by, for example, ion implanting a p-type impurity into the top surface 10 pt of the protrusion 10 p .

[0062] Figure 6 FIG. 1 shows an SBD of the semiconductor device according to the second embodiment. F -V F Characteristics. Figure 6 As shown, by providing the Schottky characteristic adjustment portion 17, the Schottky barrier height is increased in the top surface 10 pt, thereby increasing the rise voltage V of the SBD in the top surface 10 pt. th1 The rising voltage V of the SBD with 10ps on the side th2 Therefore, according to the present embodiment, it is possible to provide a Schottky barrier diode capable of suppressing variations in the rise voltage and the forward voltage.

[0063] (Third Embodiment)

[0064] Next, refer to Figure 7 A semiconductor device according to a third embodiment will be described. In this embodiment, instead of providing a semiconductor region in the protrusions 10p, a conductive portion is provided between the protrusions 10p (inside the trench).

[0065] The overall schematic structure of the semiconductor device of the third embodiment is similar to that of the semiconductor device of the first embodiment. Figure 1 same. Figure 7 This is a characteristic portion of the semiconductor device of this embodiment (with Figure 2 corresponding area).

[0066] like Figure 7 As shown, in the third embodiment, instead of the Schottky characteristic adjustment portion 13 described in the first embodiment, a Schottky characteristic adjustment portion 18 is provided so as to cover the side surface 10ps of the protrusion 10p. The Schottky characteristic adjustment portion 18 is located between the anode electrode 20 and the drift region 11 in the protrusion 10p.

[0067] The Schottky characteristic adjustment portion 18 is a conductive portion made of a conductive material with a smaller work function than the anode electrode 20. The conductive portion is made of, for example, vanadium or titanium silicide. Figure 7 As shown, the Schottky characteristic adjustment portion 18 is provided so as to cover the space between the protrusions 10 p (ie, the interior of the trench).

[0068] The Schottky characteristic adjustment portion 18 of the present embodiment is formed by, for example, forming the anode region 12, the high-concentration anode region 15, and the silicide layer 16, covering the upper surface 10a of the SiC layer 10 with a mask material having openings between the protrusions 10p, and depositing a conductive material by sputtering or chemical vapor deposition (CVD). Figure 7 As shown, in addition to the side surfaces 10ps of the protrusion 10p, a conductive portion is formed to cover the anode region 12 and the silicide layer 16. The Schottky characteristic adjustment portion 18 does not need to cover the anode region 12, but only needs to cover at least the side surfaces 10ps of the protrusion 10p.

[0069] By providing the Schottky characteristic adjustment portion 18, the Schottky barrier height at the side surface 10ps of the protrusion 10p is reduced. Therefore, similarly to the first embodiment, the rise voltage V of the SBD at the side surface 10ps is th2 Lower, with the top surface 10pt SBD rising voltage V th1 Therefore, according to the present embodiment, it is possible to provide a Schottky barrier diode capable of suppressing variations in the rise voltage and the forward voltage.

[0070] As described above, in the first to third embodiments, the Schottky characteristic adjustment portions 13, 17, and 18 are provided between the anode electrode 20 and the drift region 11 in the protrusion 10p to make the characteristics of the Schottky junction in the side surface 10ps of the protrusion 10p consistent with the characteristics of the Schottky junction in the top surface 10pt. Thus, the deviation of the rise voltage and the forward voltage between the top surface 10pt and the side surface 10ps can be reduced, and a Schottky barrier diode having excellent characteristics of the uniformity of the rise voltage and the forward voltage can be provided.

[0071] In addition, the Schottky characteristic adjustment portions 13, 17, and 18 of the first to third embodiments may be arbitrarily combined. For example, both the Schottky characteristic adjustment portion 13 and the Schottky characteristic adjustment portion 17 may be provided. Alternatively, at least one of the Schottky characteristic adjustment portion 13 and the Schottky characteristic adjustment portion 17 may be provided, and further the Schottky characteristic adjustment portion 18 may be provided. When the Schottky characteristic adjustment portion 13 is provided in this manner, the Schottky characteristic adjustment portion 13 is provided so as to be located between the Schottky characteristic adjustment portion 18 and the drift region 11 in the protrusion 10p.

[0072] In addition, the semiconductor device to which the Schottky characteristic adjustment unit is applied is not limited to Figure 1 The structure shown. Figure 8 A partial cross section of another applicable semiconductor device is shown. Fig. 9 yes Figure 8 A top view of a semiconductor device is shown. Figure 8 It is along Fig. 9 In such a semiconductor device, the Schottky characteristic adjustment portion 13 or the Schottky characteristic adjustment portion 18 may be provided on the side surface of the protrusion 10p, and the Schottky characteristic adjustment portion 17 may be provided on the top surface of the protrusion 10p.

[0073] like Fig. 9 As shown in FIG. 1 , the high-concentration anode region 15 is arranged in a rectangular shape when viewed from above. The planar shape of the high-concentration anode region 15 is not limited thereto. For example, it may also be arranged in a rectangular shape. Fig.10 The shape shown is a regular octagon.

[0074] According to the semiconductor device of at least one embodiment described above, it is possible to provide a semiconductor device that has a high withstand voltage and can suppress variations in rise voltage and forward voltage.

[0075] The embodiments of the present invention have been described, but the embodiments and examples are presented as examples and are not intended to limit the scope of the invention. The embodiments and examples can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and their variations are included in the scope or main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: The SiC layer has a first surface consisting of a silicon surface and a second surface consisting of a carbon surface on the opposite side of the first surface; a plurality of protrusions disposed in the SiC layer, with a portion of the first surface as a top surface and having side surfaces connected to the top surface; A first electrode, forming a Schottky junction with the plurality of protrusions; A second electrode, disposed on the second surface; A first semiconductor region of a first conductivity type is disposed in the SiC layer; A second semiconductor region of a second conductivity type is disposed in the SiC layer between the plurality of protrusions and is located between the first semiconductor region and the first electrode; as well as The third semiconductor region of the first conductivity type is provided on the side surface of the protrusion and is located between the first electrode and the first semiconductor region in the protrusion. The third semiconductor region has a higher first conductivity type impurity concentration than the first semiconductor region.

2. The semiconductor device according to claim 1, wherein The first electrode includes titanium, molybdenum, vanadium, nickel, or a stacked film of titanium and aluminum.

3. The semiconductor device according to claim 1, wherein The semiconductor device further includes a seventh semiconductor region of the second conductivity type, which is provided in the second semiconductor region and has a higher second conductivity type impurity concentration than the second semiconductor region.

4. The semiconductor device according to claim 3, wherein: A silicide layer is further provided, and the silicide layer is provided between the seventh semiconductor region and the first electrode.

5. A semiconductor device comprising: The SiC layer has a first surface consisting of a silicon surface and a second surface consisting of a carbon surface on the opposite side of the first surface; a plurality of protrusions disposed in the SiC layer, with a portion of the first surface as a top surface and having side surfaces connected to the top surface; A first electrode, forming a Schottky junction with the plurality of protrusions; A second electrode, disposed on the second surface; A first semiconductor region of a first conductivity type is disposed in the SiC layer; A second semiconductor region of a second conductivity type is disposed in the SiC layer between the plurality of protrusions and is located between the first semiconductor region and the first electrode; as well as A fourth semiconductor region of the second conductivity type is disposed on the top surface of the protrusion and is located between the first electrode and the first semiconductor region in the protrusion.

6. The semiconductor device according to claim 5, wherein: The first electrode includes titanium, molybdenum, vanadium, nickel, or a stacked film of titanium and aluminum.

7. The semiconductor device according to claim 5, wherein: The semiconductor device further includes a seventh semiconductor region of the second conductivity type, which is provided in the second semiconductor region and has a higher second conductivity type impurity concentration than the second semiconductor region.

8. The semiconductor device according to claim 7, wherein: A silicide layer is further provided, and the silicide layer is provided between the seventh semiconductor region and the first electrode.

9. A semiconductor device comprising: The SiC layer has a first surface consisting of a silicon surface and a second surface consisting of a carbon surface on the opposite side of the first surface; a plurality of protrusions disposed in the SiC layer, with a portion of the first surface as a top surface and having side surfaces connected to the top surface; A first electrode, forming a Schottky junction with the plurality of protrusions; A second electrode, disposed on the second surface; A first semiconductor region of a first conductivity type is disposed in the SiC layer; A second semiconductor region of a second conductivity type is disposed in the SiC layer between the plurality of protrusions and is located between the first semiconductor region and the first electrode; as well as The conductive portion is provided so as to cover at least the side surface of the protrusion and has a smaller work function than the first electrode.

10. The semiconductor device according to claim 9, wherein The conductive portion includes vanadium or titanium silicide.

11. The semiconductor device according to claim 9, wherein A fifth semiconductor region of the first conductivity type is further provided, the fifth semiconductor region of the first conductivity type is provided on the side surface of the protrusion, is located between the conductive portion and the first semiconductor region in the protrusion, and has a higher first conductivity type impurity concentration than the first semiconductor region.

12. The semiconductor device according to claim 9, wherein: A sixth semiconductor region of the second conductivity type is further provided, and the sixth semiconductor region of the second conductivity type is provided on the top surface of the protrusion and is located between the first electrode and the first semiconductor region in the protrusion.

13. The semiconductor device according to claim 9, wherein: The first electrode includes titanium, molybdenum, vanadium, nickel, or a stacked film of titanium and aluminum.

14. The semiconductor device according to claim 9, wherein The semiconductor device further includes a seventh semiconductor region of the second conductivity type, which is provided in the second semiconductor region and has a higher second conductivity type impurity concentration than the second semiconductor region.

15. The semiconductor device according to claim 14, wherein: The invention further includes a silicide layer provided between the seventh semiconductor region and the first electrode.

16. A semiconductor device comprising: The SiC layer has a first surface consisting of a silicon surface and a second surface consisting of a carbon surface on the opposite side of the first surface; a plurality of protrusions disposed in the SiC layer, with a portion of the first surface as a top surface and having side surfaces connected to the top surface; a first electrode, forming a Schottky junction with the plurality of protrusions; A second electrode, disposed on the second surface; A first semiconductor region of a first conductivity type is disposed in the SiC layer; A second semiconductor region of a second conductivity type is disposed in the SiC layer between the plurality of protrusions and is located between the first semiconductor region and the first electrode; as well as The Schottky characteristic adjustment portion is provided between the first electrode and the first semiconductor region in the protrusion, and makes the characteristics of the Schottky junction on the side surface of the protrusion consistent with the characteristics of the Schottky junction on the top surface of the protrusion.

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