Semiconductor device
By designing a divided first semiconductor region and a multi-part second semiconductor region in the semiconductor device and forming Schottky contact with the conductive components, the problem of difficulty in optimizing leakage current and forward voltage in the prior art is solved, and better characteristics and surge resistance are achieved.
Patent Information
- Application Number
- CN202480003838.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-13
- Filing Date
- 2024-02-15
- Publication Date
- 2025-04-11
AI Technical Summary
There are shortcomings in the improvement of characteristics of existing semiconductor devices, especially in terms of leakage current and forward voltage, which are difficult to optimize simultaneously.
A semiconductor device is designed, which includes a first electrode, a first conductive member, a first semiconductor region of the first conductive type, and a second semiconductor region of the second conductive type. The first semiconductor region is divided by a first partial region, a second partial region and a third partial region, and forms Schottky contact with the first conductive member. The second semiconductor region then forms a depletion layer through a plurality of portions extending in different directions to suppress leakage current.
Through this design, leakage current can be effectively suppressed and a large Schottky contact area can be maintained, thereby obtaining a lower forward voltage and an improved surge resistance, which significantly improves the characteristics of the semiconductor device.
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Figure CN119817186A_ABST
Abstract
Description
Technical Field
[0001] An embodiment of the present invention relates to a semiconductor device. Background Art
[0002] For example, in semiconductor devices such as junction barrier Schottky diodes (JBS: Junction Barrier Schottky Diode), improvement in characteristics is desired.
[0003] Prior art literature:
[0004] Patent Literature:
[0005] Patent Document 1: Japanese Patent No. 7098906 Summary of the invention
[0006] Problems to be solved by the invention:
[0007] Embodiments provide a semiconductor device capable of improving characteristics.
[0008] Means used to solve the problem:
[0009] According to an embodiment, a semiconductor device includes a first electrode, a first conductive component, a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The first semiconductor region is provided between the first electrode and the first conductive component. The first semiconductor region includes a first partial region, a second partial region, and a third partial region. The first semiconductor region and the first conductive component are in Schottky contact. The second semiconductor region includes a plurality of first portions extending along a first direction, a plurality of second portions extending along a second direction, and a third portion. The first direction intersects with a third direction from the first electrode to the first conductive component. The second direction intersects with a first plane including the first direction and the third direction. The third portion is provided around the plurality of second portions in a second plane including the first direction and the second direction. The third portion is continuous with the plurality of second portions. The first partial region is provided between the first electrode and the plurality of first portions and between the first electrode and the second partial region in the third direction. The second partial region is provided between one of the plurality of first portions and another of the plurality of first portions in the second direction. The third partial region is provided between the plurality of first portions and the first conductive component and between the second partial region and the first conductive component in the third direction. The third partial region is disposed between one of the plurality of second portions and another one of the plurality of second portions in the first direction. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 (a)~ Figure 1 (c) is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
[0011] Figure 2 (a)~ Figure 2 (c) is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
[0012] Figure 3 (a) and Figure 3 (b) is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
[0013] Figure 4 (a)~ Figure 4 (c) is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
[0014] Figure 5 (a)~ Figure 5 (c) is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. DETAILED DESCRIPTION
[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the sizes and ratios may be shown differently depending on the drawings.
[0017] In the present specification and each drawing, regarding the drawings that have already appeared, the same reference numerals are given to the same elements as those described above, and detailed description thereof will be appropriately omitted.
[0018] (First Embodiment)
[0019] Figure 1 (a)~ Figure 1 (c) Figure 2 (a)~ Figure 2 (c) Figure 3 (a) and Figure 3 (b) is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
[0020] Figure 1 (a)~ Figure 1 (c) is Figure 3 (a) and Figure 3 (b) is a cross-sectional view along the A1-A2 line, the A3-A4 line and the A5-A6 line. Figure 2 (a)~ Figure 2(c) is Figure 3 (a) and Figure 3 (b) is a cross-sectional view along the lines B1-B2, B3-B4 and B5-B6.
[0021] like Figure 1 (a)~ Figure 1 (c) and Figure 2 (a)~ Figure 2 As shown in FIG. 5( c ), the semiconductor device 110 according to the embodiment includes a first electrode 51 , a first conductive member 61 , a first semiconductor region 10 , and a second semiconductor region 20 .
[0022] The first semiconductor region 10 is disposed between the first electrode 51 and the first conductive component 61. The first semiconductor region 10 is of the first conductivity type. The first semiconductor region 10 includes a first partial region 11, a second partial region 12, and a third partial region 13. The first semiconductor region 10 and the first conductive component 61 are in Schottky contact.
[0023] The second semiconductor region 20 is of the second conductivity type. The first conductivity type is one of the n-type and the p-type. The second conductivity type is the other of the n-type and the p-type. Hereinafter, the first conductivity type is the n-type and the second conductivity type is the p-type.
[0024] like Figure 3 As shown in (a), the second semiconductor region 20 includes a plurality of first portions 21, a plurality of second portions 22, and a third portion 23. The plurality of first portions 21 extend along a first direction D1. The plurality of second portions 22 extend along a second direction D2. The first direction D1 intersects with a third direction D3 from the first electrode 51 to the first conductive component 61. The second direction D2 intersects with a first plane including the first direction D1 and the third direction D3.
[0025] The first direction D1 is, for example, the X-axis direction. A direction perpendicular to the X-axis direction is set as the Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is set as the Z-axis direction. The third direction D3 is, for example, the Z-axis direction. In one example, the second direction D2 may also be the Y-axis direction. The second direction D2 may also be inclined relative to the first direction D1. The first plane corresponds to, for example, the XZ plane.
[0026] For example, the plurality of first portions 21 are arranged along the second direction D2. The plurality of second portions 22 are arranged along the first direction D1. For example, the plurality of second portions 22 are in contact with the plurality of first portions 21. The boundaries between the plurality of second portions 22 and the plurality of first portions 21 may be clear or unclear.
[0027] Figure 3 (a) is a cross-sectional view of the XY plane including a plurality of second portions 22. Figure 3As shown in (a), the third portion 23 is arranged around the plurality of second portions 22 in the second plane including the first direction D1 and the second direction D2. The second plane corresponds to the XY plane, for example. The third portion 23 is continuous with the plurality of second portions 22. For example, the third portion 23 surrounds the plurality of second portions 22 in the second plane (XY plane). The third portion 23 is, for example, a peripheral annular pin structure.
[0028] The inner side of the region surrounded by the third portion 23 is, for example, a cell region, and the outer side of the third portion 23 is, for example, a peripheral region.
[0029] The third portion 23 may also be disposed around the plurality of first portions 21 in the second plane. The third portion 23 may also be continuous with the plurality of first portions 21.
[0030] like Figure 1 (a) and Figure 1 As shown in (b), the first partial region 11 is provided between the first electrode 51 and the plurality of first portions 21 and between the first electrode 51 and the second partial region 12 in the third direction D3. The first partial region 11 is provided between the first electrode 51 and the second partial region 12 in the third direction D3.
[0031] like Figure 2 (a) and Figure 2 As shown in (b), the second partial region 12 is disposed between one of the plurality of first portions 21 and another of the plurality of first portions 21 in the second direction D2. The third partial region 13 is disposed between the plurality of first portions 21 and the first conductive component 61 and between the second partial region 12 and the first conductive component 61 in the third direction D3.
[0032] like Figure 1 (a) and Figure 1 As shown in (b), the third partial region 13 is provided between one of the plurality of second portions 22 and another of the plurality of second portions 22 in the first direction D1.
[0033] like Figure 1 (c) and Figure 2 As shown in (c), the semiconductor device 110 may further include a second electrode 52. The second electrode 52 is electrically connected to the first conductive member 61. In this example, the first conductive member 61 is provided between at least a portion of the second semiconductor region 20 and at least a portion of the second electrode 52.
[0034] In the semiconductor device 110, the characteristics of the current flowing between the first electrode 51 and the second electrode 52 change according to the polarity of the relative potentials in the first electrode 51 and the second electrode 52. The semiconductor device 110 is, for example, a diode. A state in which the potential of the second electrode 52 is higher than the potential of the first electrode 51 is a forward state. A state in which the potential of the second electrode 52 is lower than the potential of the first electrode 51 is a reverse bias state.
[0035] In the semiconductor device 110, the first semiconductor region 10 and the first conductive member 61 are in Schottky contact. Furthermore, the semiconductor device 110 includes a second semiconductor region 20 of the second conductivity type. The semiconductor device 110 is, for example, a JBS. The first partial region 11 corresponds to, for example, an n-type drift layer.
[0036] In the JBS, there is a first reference example in which a plurality of p-type regions extending in one direction are provided. In the first reference example, when a reverse bias voltage is applied, a depletion layer is formed in a region including a p-type region and an n-type drift layer. By covering the Schottky contact with the depletion layer, for example, leakage current can be reduced. In the first reference example, if the area or density of the p-region is increased in order to suppress leakage current, the area of the Schottky contact is reduced. As a result, the forward voltage increases, and the superiority as a Schottky barrier diode is impaired.
[0037] In the semiconductor device 110, a plurality of first portions 21 extending along the first direction D1 and a plurality of second portions 22 extending along the second direction D2 are provided. The plurality of first portions 21 are provided at positions away from the first conductive component 61. A third partial region 13 of the first conductive type (n-type) exists between the plurality of first portions 21 and the first conductive component 61. In the semiconductor device 110, for example, a depletion layer is effectively formed over a large area when a reverse bias voltage is applied by the plurality of first portions 21 and the plurality of second portions 22. Thus, leakage current is suppressed. In the semiconductor device 110, the third partial region 13 forms a Schottky contact with the first conductive component 61. Thus, the area of the Schottky contact is maintained large. Thus, a sufficiently low forward voltage can be obtained.
[0038] In the embodiment, the third portion 23 is provided around the plurality of second portions 22 in the second plane (XY plane). The third portion 23 is continuous with the plurality of second portions 22. By providing such a third portion 23, it is easy to improve surge tolerance. According to the embodiment, in addition to a smaller leakage current and a lower forward current, a large surge tolerance can be obtained. According to the embodiment, a semiconductor device capable of improving characteristics can be provided.
[0039] For example, consider the second reference example in which the third portion 23 (peripheral annular pin structure) is not provided. In the embodiment, the outer peripheral annular pin structure can improve the surge tolerance compared to the second reference example.
[0040] like Figure 1 (c) and Figure 2 As shown in (c), the semiconductor device 110 may further include a third semiconductor region 30. The third semiconductor region 30 is of the second conductivity type. The second conductivity type impurity concentration in the third semiconductor region 30 is higher than the second conductivity type impurity concentration in the second semiconductor region 20. The third semiconductor region 30 is, for example, a p+ region. The second semiconductor region 20 is, for example, a p region.
[0041] The third semiconductor region 30 includes a peripheral region 30p. The peripheral region 30p is disposed between the third portion 23 and the first conductive component 61 in the third direction D3. In this example, the semiconductor device 110 further includes a compound component 65. The compound component 65 includes a peripheral component 65p. The peripheral component 65p is disposed between the peripheral region 30p and the first conductive component 61 in the third direction D3. The first conductive component 61 includes a first metal element. The compound component 65 includes a first metal element and silicon. The first metal element is, for example, Ni. In this case, the compound component 65 includes Ni silicide.
[0042] Good ohmic contact can be obtained by such a peripheral region 30p and a peripheral component 65p. Thus, for example, when a reverse bias is applied to the diode, holes in the second semiconductor region 20 can be efficiently discharged to the first conductive component 61 (Schottky electrode). For example, a depletion layer is generated at a high speed around the second semiconductor region 20. As a result, the recovery characteristics can be improved. For example, the reverse recovery time can be shortened. For example, the reverse recovery current can be reduced.
[0043] like Figure 1 (c) and Figure 1 As shown in (c), the second semiconductor region 20 may also include a fourth portion 24. At least a portion of the fourth portion is disposed between one of the plurality of second portions 22 and another of the plurality of second portions 22 in the first direction D1. The third semiconductor region 30 further includes an inner region 30i. The inner region 30i is disposed between the fourth portion 24 and the first conductive component 61 in the third direction D3. The compound component 65 further includes an inner component 65i. The inner component 65i is disposed between the inner region 30i and the first conductive component 61 in the third direction D3.
[0044] The first semiconductor region 10, the second semiconductor region 20 and the third semiconductor region 30 can improve the withstand voltage of the chip. For example, in the pin structure (point portion and outermost peripheral portion), the breakdown voltage is lower than the breakdown voltage of the Schottky interface (the interface between the first conductive component and the third partial region). For example, when a reverse bias surge is applied, the pin structure breaks down first, and the current flows through the pin structure first. Thus, it is possible to suppress the situation where damage is caused by applying a high electric field to the Schottky interface.
[0045] Figure 3 (b) illustrates a cross section in the XY plane including the third semiconductor region 30. On the other hand, as already described, Figure 3 (a) illustrates a cross section in the XY plane including a plurality of second portions 22. Figure 3 As shown in (a), for example, the third portion 23 may also include a first extension portion 23a, a second extension portion 23b, a third extension portion 23c, and a fourth extension portion 23d. The first extension portion 23a extends along the second direction D2. The second extension portion 23b extends along the second direction D2. The third extension portion 23c extends along the first direction D1. The fourth extension portion 23d extends along the first direction D1. The direction from the second extension portion 23b to the first extension portion 23a is along the first direction D1. The direction from the third extension portion 23c to the fourth extension portion 23d is along the second direction D2. These multiple extension portions may also be continuous with each other.
[0046] like Figure 1 As shown in (a), the thickness of one of the first portions 21 in the third direction D3 is set to be the first thickness t21. Figure 1 As shown in (b), the thickness of one of the plurality of second portions 22 in the third direction D3 is set to a second thickness t22. In one example, the first thickness t21 may be greater than 0.5 μm and less than 1.5 μm. The second thickness t22 may also be greater than 0.5 μm and less than 1.5 μm, for example.
[0047] In the embodiment, for example, the first semiconductor region 10 and the second semiconductor region 20 include SiC. The first semiconductor region 10 and the second semiconductor region 20 may include at least one selected from the group consisting of 4H-SiC, 6H-SiC, and 3C-SiC. These semiconductor regions include crystals.
[0048] For example, the first semiconductor region 10 contains at least one element selected from the group consisting of N, P, and As (a first element as an impurity of the first conductivity type). For example, the second semiconductor region 20 contains at least one element selected from the group consisting of B, Al, and Ga (a second element as an impurity of the second conductivity type).
[0049] like Figure 1 (a)~ Figure 1 (c) and Figure 2 (a)~ Figure 2 As shown in (c), the semiconductor device 110 may also include a fourth semiconductor region 40. The fourth semiconductor region 40 is of the first conductivity type. The fourth semiconductor region 40 is provided between the first electrode 51 and the first semiconductor region 10. The first conductivity type impurity concentration in the fourth semiconductor region 40 is higher than the first conductivity type impurity concentration in the first semiconductor region 10. A lower resistance is obtained between the first electrode 51 and the first semiconductor region 10.
[0050] In one example, the concentration of the first element (n-type) in the first semiconductor region 10 is, for example, 1.0×10 15 cm -3 Above and 1.0×10 17 cm -3 In one example, the concentration of the second element (p-type) in the second semiconductor region 20 is, for example, 1.0×10 12 cm -3 Above and 1.0×10 14 cm -3 In one example, the concentration of the second element (p-type) in the third semiconductor region 30 is, for example, 1.0×10 12 cm -3 Above and 1.0×10 14 cm -3 In one example, the concentration of the first element (n-type) in the fourth semiconductor region 40 is, for example, 0.5×10 18 cm -3 Above and 0.5×10 19 cm -3 the following.
[0051] The first conductive member 61 includes at least one (for example, a first metal element) selected from the group consisting of Pt, V, and Ti, so that a Schottky contact can be stably obtained.
[0052] The first electrode 51 includes, for example, at least one selected from the group consisting of Ti, Ni, and Au. The second electrode 52 includes, for example, Al or the like.
[0053] In the above-described semiconductor device 110 , the third portion 23 overlaps with the plurality of first portions 21 in the XY plane. The plurality of first portions 21 and the third portion 23 are continuous.
[0054] (Second Embodiment)
[0055] Figure 4 (a)~ Figure 4 (c) and Figure 5 (a)~ Figure 5 (c) is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment.
[0056] Figure 4 (a)~ Figure 4 (c) is related to Figure 3 (a) and Figure 3 (b) is a cross-sectional view corresponding to the A1-A2 line, the A3-A4 line and the A5-A6 line. Figure 5 (a)~ Figure 5 (c) is related to Figure 3 (a) and Figure 3 (b) is a cross-sectional view corresponding to the line B1-B2, line B3-B4 and line B5-B6.
[0057] As in the semiconductor device 111, at least a portion of the third portion 23 may not overlap with the plurality of first portions 21 in the XY plane. In such a semiconductor device 111, a small leakage current and a low forward voltage can also be obtained. According to the embodiment, a semiconductor device with improved characteristics can be provided.
[0058] In the embodiment, information on the length and thickness is obtained by electron microscope observation, etc. Information on the composition of the material is obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy dispersive X-ray spectroscopy), etc.
[0059] The implementation method may also include the following technical solutions.
[0060] (Technical Solution 1)
[0061] A semiconductor device comprising:
[0062] a first electrode;
[0063] a first conductive member;
[0064] A first semiconductor region of a first conductivity type is disposed between the first electrode and the first conductive component, the first semiconductor region includes a first partial region, a second partial region, and a third partial region, and the first semiconductor region and the first conductive component form a Schottky contact; and
[0065] A second semiconductor region of a second conductivity type, the second semiconductor region includes a plurality of first portions extending along a first direction, a plurality of second portions extending along a second direction, and a third portion, the first direction intersects with a third direction from the first electrode to the first conductive component, the second direction intersects with a first plane including the first direction and the third direction, the third portion is arranged around the plurality of second portions in a second plane including the first direction and the second direction, the third portion is continuous with the plurality of second portions, the first partial region is arranged between the first electrode and the plurality of first portions and between the first electrode and the second partial region in the third direction, the second partial region is arranged between one of the plurality of first portions and another of the plurality of first portions in the second direction, the third partial region is arranged between the plurality of first portions and the first conductive component and between the second partial region and the first conductive component in the third direction, and the third partial region is arranged between one of the plurality of second portions and another of the plurality of second portions in the first direction.
[0066] (Technical Solution 2)
[0067] The semiconductor device according to claim 1, wherein the third portion is continuous with the plurality of first portions.
[0068] (Technical Solution 3)
[0069] The semiconductor device according to Technical Solution 1 or 2, wherein the third portion surrounds the plurality of second portions in the second plane.
[0070] (Technical Solution 4)
[0071] The semiconductor device according to any one of technical solutions 1 to 3, wherein the third part comprises:
[0072] a first extending portion extending along the second direction,
[0073] a second extending portion extending along the second direction,
[0074] a third extending portion extending along the first direction, and
[0075] a fourth extending portion extending along the first direction,
[0076] A direction from the second extension portion to the first extension portion is along the first direction,
[0077] A direction from the third extending portion to the fourth extending portion is along the second direction.
[0078] (Technical Solution 5)
[0079] A semiconductor device according to any one of technical solutions 1 to 4, wherein:
[0080] further comprising a third semiconductor region of the second conductivity type,
[0081] The third semiconductor region includes a peripheral region,
[0082] The peripheral region is disposed between the third portion and the first conductive component in the third direction,
[0083] The concentration of the second conductivity type impurities in the third semiconductor region is higher than the concentration of the second conductivity type impurities in the second semiconductor region.
[0084] (Technical Solution 6)
[0085] The semiconductor device according to technical solution 5, wherein:
[0086] Also has compound parts,
[0087] The compound component includes a peripheral component,
[0088] The peripheral component is disposed between the peripheral region and the first conductive component in the third direction,
[0089] The first conductive component comprises a first metal element,
[0090] The compound component includes the first metal element and silicon.
[0091] (Technical Solution 7)
[0092] The semiconductor device according to claim 6, wherein:
[0093] The second semiconductor region further comprises a fourth portion,
[0094] At least a portion of the fourth portion is disposed between the one of the plurality of second portions and the other of the plurality of second portions in the first direction,
[0095] The third semiconductor region further includes an inner region,
[0096] The inner region is disposed between the fourth portion and the first conductive component in the third direction,
[0097] The compound part further comprises an inner part,
[0098] The inner member is disposed between the inner region and the first conductive member in the third direction.
[0099] (Technical Solution 8)
[0100] The semiconductor device according to any one of claims 1 to 7, wherein the first conductive member includes at least one selected from the group consisting of Pt, V, and Ti.
[0101] (Technical Solution 9)
[0102] The semiconductor device according to any one of technical solutions 1 to 8, wherein the plurality of second portions are in contact with the plurality of first portions.
[0103] (Technical Solution 10)
[0104] The semiconductor device according to any one of claims 1 to 9, wherein a first thickness of the one of the plurality of first portions in the third direction is not less than 0.5 μm and not more than 1.5 μm.
[0105] (Technical Solution 11)
[0106] The semiconductor device according to claim 10, wherein a second thickness of the one of the plurality of second portions in the third direction is greater than or equal to 0.5 μm and less than or equal to 1.5 μm.
[0107] (Technical Solution 12)
[0108] The semiconductor device according to any one of claims 1 to 11, wherein the first semiconductor region and the second semiconductor region include SiC.
[0109] (Technical Solution 13)
[0110] The semiconductor device according to any one of claims 1 to 11, wherein the first semiconductor region and the second semiconductor region include at least one selected from the group consisting of 4H-SiC, 6H-SiC, and 3C-SiC.
[0111] (Technical Solution 14)
[0112] The semiconductor device according to any one of technical solutions 1 to 13, wherein the first semiconductor region includes at least one selected from the group consisting of N, P, and As,
[0113] The second semiconductor region includes at least one selected from the group consisting of B, Al, and Ga.
[0114] (Technical Solution 15)
[0115] The semiconductor device according to any one of technical solutions 1 to 14, wherein the first partial region is provided between the first electrode and the second partial region in the third direction.
[0116] (Technical Solution 16)
[0117] A semiconductor device according to any one of technical solutions 1 to 15, wherein:
[0118] The plurality of first portions are arranged along the second direction,
[0119] The plurality of second portions are arranged along the first direction.
[0120] (Technical Solution 17)
[0121] The semiconductor device according to any one of claims 1 to 16, further comprising a second electrode electrically connected to the first conductive member.
[0122] (Technical Solution 18)
[0123] A semiconductor device according to Technical Solution 17, wherein the second electrode contains Al.
[0124] (Technical Solution 19)
[0125] A semiconductor device according to Technical Solution 17 or 18, wherein the first conductive component is arranged between at least a portion of the second semiconductor region and at least a portion of the second electrode.
[0126] (Technical Solution 20)
[0127] A semiconductor device according to any one of technical solutions 1 to 19, wherein:
[0128] further comprising a fourth semiconductor region of the first conductivity type,
[0129] The fourth semiconductor region is disposed between the first electrode and the first semiconductor region,
[0130] A concentration of impurities of the first conductivity type in the fourth semiconductor region is higher than a concentration of impurities of the first conductivity type in the first semiconductor region.
[0131] According to the embodiment, a semiconductor device having improved characteristics can be provided.
[0132] The embodiments of the present invention are described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, as long as a person skilled in the art can implement the present invention in the same manner and obtain the same effect by appropriately selecting from the known range, the specific structure of each element such as a semiconductor region, a conductive component, and an electrode included in a semiconductor device is included in the scope of the present invention.
[0133] Furthermore, embodiments in which two or more elements of the specific examples are combined within a technically possible range are also included in the scope of the present invention as long as they include the gist of the present invention.
[0134] Furthermore, as embodiments of the present invention, all semiconductor devices that can be appropriately designed and modified by a person skilled in the art based on the above-described semiconductor device also belong to the scope of the present invention as long as they include the gist of the present invention.
[0135] Furthermore, within the scope of the concept of the present invention, a person skilled in the art can conceive of various changes and modifications, and these changes and modifications also belong to the scope of the present invention.
[0136] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments or their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and their equivalents.
[0137] Description of reference numerals:
[0138] 10: first semiconductor region; 11-13: first to third partial regions; 20: second semiconductor region; 21-24: first to fourth parts; 23a-23d: first to fourth extension parts; 30: third semiconductor region; 30i: inner region; 30p: peripheral region; 40: fourth semiconductor region; 51, 52: first and second electrodes; 61: first conductive component; 65: compound component; 65i: inner component; 65p: peripheral component; 110, 111: semiconductor device; D1-D3: first to third directions; t21, t22: first and twenty-second thicknesses.
Claims
1. A semiconductor device, wherein: have: a first electrode; a first conductive member; A first semiconductor region of a first conductivity type, disposed between the first electrode and the first conductive component, the first semiconductor region comprising a first partial region, a second partial region and a third partial region, the first semiconductor region and the first conductive component being in Schottky contact; as well as A second semiconductor region of a second conductivity type, the second semiconductor region includes a plurality of first portions extending along a first direction, a plurality of second portions extending along a second direction, and a third portion, the first direction intersects with a third direction from the first electrode to the first conductive component, the second direction intersects with a first plane including the first direction and the third direction, the third portion is arranged around the plurality of second portions in a second plane including the first direction and the second direction, the third portion is continuous with the plurality of second portions, the first partial region is arranged between the first electrode and the plurality of first portions and between the first electrode and the second partial region in the third direction, the second partial region is arranged between one of the plurality of first portions and another of the plurality of first portions in the second direction, the third partial region is arranged between the plurality of first portions and the first conductive component and between the second partial region and the first conductive component in the third direction, and the third partial region is arranged between one of the plurality of second portions and another of the plurality of second portions in the first direction.
2. The semiconductor device according to claim 1, wherein The third portion is continuous with the plurality of first portions.
3. The semiconductor device according to claim 1 or 2, wherein: further comprising a third semiconductor region of the second conductivity type, The third semiconductor region includes a peripheral region, The peripheral area is arranged between the third portion and the first conductive component in the third direction, The concentration of the second conductivity type impurities in the third semiconductor region is higher than the concentration of the second conductivity type impurities in the second semiconductor region.
4. The semiconductor device according to claim 3, wherein: Also has compound parts, The compound component includes a peripheral component, The peripheral component is disposed between the peripheral region and the first conductive component in the third direction, The first conductive component comprises a first metal element, The compound component includes the first metal element and silicon.
5. The semiconductor device according to claim 4, wherein: The second semiconductor region further comprises a fourth portion, At least a portion of the fourth portion is disposed between the one of the plurality of second portions and the other of the plurality of second portions in the first direction, The third semiconductor region further includes an inner region, The inner region is disposed between the fourth portion and the first conductive component in the third direction, The compound part further comprises an inner part, The inner member is disposed between the inner region and the first conductive member in the third direction.