Ferroelectric random access memory cell

Abstract

A ferroelectric random access memory (FeRAM) cell (10) is provided. The FeRAM cell (10) includes a vertical channel (310) between a bottom source / drain region and a top source / drain region (630); gate oxidation (320) around the vertical channel (310); and a ferroelectric layer (400) surrounding the gate oxide (320), wherein the ferroelectric layer (400) has two or more sections of different horizontal thicknesses between the bottom source / drain region and the top source / drain region (630). A method of manufacturing a FeRAM cell (10) is also provided.

Description

Background Art

[0001] The present invention relates to the manufacture of semiconductor integrated circuits, and more particularly to ferroelectric random access memory cells and methods for manufacturing the same.

[0002] Using emerging memories for analog computing has been seen as a viable option for artificial intelligence (AI) applications. For example, some recently commercialized ferroelectric random access memory (FeRAM) cells have been used for memory applications, where each FeRAM cell stores one of two logic states (logic "1" or logic "0") depending on the polarization state of the ferroelectric layer in the FeRAM cell.

[0003] For analog computing applications, it is desirable to have a single FeRAM cell capable of holding multiple logic states, which can be achieved by gradually changing the polarization of the FeRAM cell to form a continuous value or multiple discrete values ​​(rather than just two values, "1" or "0"), depending on the programming voltage. However, it has been recognized that having a FeRAM cell with its polarization gradually changing is extremely challenging, if not impossible. Summary of the invention

[0004] Embodiments of the present invention provide a ferroelectric random access memory (FeRAM) cell based on, for example, a ferroelectric vertical transfer field effect transistor (Fe-VTFET). The FeRAM cell includes a vertical channel between a bottom source / drain region and a top source / drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, wherein the ferroelectric layer has two or more sections of different horizontal thicknesses between the bottom source / drain region and the top source / drain region. Two or more sections of these ferroelectric layers can be programmed to have different polarization combinations, thereby providing multiple logic states.

[0005] In one embodiment, the FeRAM cell further includes a gate metal surrounding the ferroelectric layer, the gate metal having two or more horizontal thicknesses that complement the different horizontal thicknesses of the two or more sections of the ferroelectric layer such that the horizontal thickness measured from the vertical channel is uniform.

[0006] In another embodiment, the ferroelectric layer includes a bottom segment, a middle segment, and a top segment of three different levels of thickness, and the three different levels of thickness are arranged in a stair shape.

[0007] In one embodiment, the top segment of the ferroelectric layer is adapted to be programmed to have a polarization state different from that of the middle and bottom segments. In another embodiment, the top and middle segments of the ferroelectric layer are adapted to be programmed to have a polarization state different from that of the bottom segment.

[0008] In one embodiment, the ferroelectric layer of the FeRAM comprises doped hafnium oxide. In another embodiment, the horizontal thickness difference between two of the two or more segments of the ferroelectric layer is at least 0.5 nm, which enables controllability of programming different segments of the ferroelectric layer with different and / or desired polarizations.

[0009] An embodiment of the present invention also provides a method for forming a FeRAM cell. The method includes: forming a vertical channel on top of a bottom epitaxial layer; forming a gate oxide at a side surface of the vertical channel; forming a first layer of ferroelectric material around a first segment of the vertical channel; forming a second layer of ferroelectric material around a second segment of the vertical channel and the first layer of ferroelectric material; forming a third layer of ferroelectric material around a third segment of the vertical channel and the second layer of ferroelectric material; forming a gate metal around the third layer of ferroelectric material; and forming a top epitaxial layer at the top of the vertical channel.

[0010] In one embodiment, forming a first layer of ferroelectric material includes forming a first conformal layer of ferroelectric material surrounding a vertical channel; covering a first portion of the first conformal layer of ferroelectric material with a first sacrificial material having a vertical height corresponding to a first segment of the vertical channel; and removing exposed portions of the first conformal layer of ferroelectric material not covered by the first sacrificial material.

[0011] In another embodiment, forming a second layer of ferroelectric material includes: forming a second conformal layer of ferroelectric material surrounding the first layer of ferroelectric material and the portion of the vertical channel not covered by the first layer of ferroelectric material; covering a second portion of the second conformal layer of ferroelectric material with a second sacrificial material, the second portion having a vertical height corresponding to the sum of the heights of the first segment and the second segment of the vertical channel; and removing the exposed portion of the second conformal layer of ferroelectric material not covered by the second sacrificial material.

[0012] In another embodiment, forming a third layer of ferroelectric material includes: forming a third conformal layer of ferroelectric material surrounding the second layer of ferroelectric material and the portion of the vertical channel not covered by the second layer of ferroelectric material; covering a third portion of the third conformal layer of ferroelectric material with a third sacrificial material, the third portion having a vertical height corresponding to the sum of the heights of the first segment, the second segment, and the third segment of the vertical channel; and removing the exposed portion of the third conformal layer of ferroelectric material not covered by the third sacrificial material.

[0013] Embodiments of the present invention also include: after removing the exposed portion of the third conformal layer ferroelectric material, forming a top spacer around the remaining portion of the vertical channel to expose the remaining portion of the vertical channel therebelow; and also include: before forming gate oxidation, forming a bottom spacer on the top of the bottom epitaxial layer to surround the vertical channel.

[0014] In one embodiment, forming the gate oxide includes exposing the vertical channel to an oxygen-containing environment to oxidize side surfaces of the vertical channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention will be more fully understood and appreciated according to the following specific implementation of the embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

[0016] Figures 1 to 24 is an illustrative diagram of a cross-sectional view of a ferroelectric random access memory (FeRAM) cell during the process of manufacturing the same according to an embodiment of the present invention; and

[0017] Fig.25 is an illustrative illustration of a flow chart of a method of fabricating a FeRAM cell according to an embodiment of the present invention.

[0018] It will be understood that for the sake of similarity and clarity, the elements shown in the drawings are not necessarily drawn to scale. In addition, if applicable, in various functional block diagrams, two connected devices and / or elements may not necessarily be shown as connected. In some other cases, the grouping of certain elements in the functional block diagrams may be for descriptive purposes only and does not necessarily mean that they are in a single physical entity, or that they are embodied in a single physical entity. DETAILED DESCRIPTION

[0019] In the following detailed description and the accompanying drawings, it will be understood that the various layers, structures and regions shown in the accompanying drawings are illustrative and schematic illustrations, which are not drawn to scale. In addition, for ease of explanation, one or more types of layers, structures and regions that are commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or figure. This does not mean that any layer, structure and region that is not explicitly shown is omitted in the actual semiconductor structure. In addition, it will be understood that the embodiments discussed herein are not limited to the specific materials, features and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it will be emphasized that the description provided herein is not intended to cover all processing steps in the processing steps that may be required to form a functional semiconductor integrated circuit device. On the contrary, in order to save the description space, some processing steps that are commonly used to form semiconductor devices are not purposefully described in this article, such as wet cleaning and annealing steps.

[0020] It will be understood that the terms "approximately" or "substantially" as used herein with respect to thickness, width, percentage, range, etc., are intended to mean close to or approximately close to, rather than completely equal. For example, the terms "approximately" or "substantially" as used herein mean that there may be a smaller margin of error, such as, by way of example only, 1% or less of the amount. Similarly, the terms "on...", "above...", or "on top of..." used herein to describe the positional relationship between two layers or structures are intended to be interpreted broadly and should not be understood to exclude the presence of one or more intermediate layers or intermediate structures.

[0021] In order to provide spatial context to the different structural orientations of the semiconductor structures shown in the drawings, XYZ Cartesian coordinates may be provided in some of the drawings. The terms "vertical" or "vertical direction" or "vertical height" as used herein refer to the Z direction of the Cartesian coordinate system shown in the drawings, and the terms "horizontal" or "horizontal direction" or "lateral" as used herein refer to the X direction and / or Y direction of the Cartesian coordinate system shown in the drawings.

[0022] In addition, although different reference numerals may be used across different drawings, the same or similar reference numerals are used in all drawings to represent the same or similar features, elements or structures, and therefore, in order to save description space, detailed descriptions of the same or similar features, elements or structures may not be repeated in every drawing in the drawings. In order not to make the drawings appear too crowded, the labels for the same or similar elements in some drawings may also be omitted.

[0023] Figure 1 is an illustrative illustration of a cross-sectional view of a FeRAM cell 10 at a step of manufacturing the same according to an embodiment of the present invention. More specifically, an embodiment of the present invention provides a support structure that receives a semiconductor substrate 101, and forms an epitaxial layer on top of the semiconductor substrate 101. The semiconductor substrate 101 may be a bulk substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate, or may be a silicon-on-insulator (SOI) substrate or a silicon-germanium-on-insulator (SiGeOI) substrate. Other types of substrates may also be used as a support structure. The epitaxial layer may be an epitaxially grown silicon layer, an epitaxially grown germanium layer, or an epitaxially grown silicon germanium layer. Figure 1 As shown in FIG. 1 , the epitaxial layer may be formed as a bottom epitaxial layer 210 to serve as a bottom source / drain region of a vertical transistor serving as part of the FeRAM cell 10. Hereinafter, the bottom epitaxial layer 210 may also sometimes be referred to as a bottom source / drain region.

[0024] Embodiments of the present invention also provide for forming a vertical channel 310 on top of the bottom epitaxial layer 210. The vertical channel 310 may be made of silicon material and may be formed by, for example, photolithographic patterning and etching of a crystalline silicon layer on top of the bottom epitaxial layer 210 using a hard mask 301. In one embodiment, the vertical channel 310 may have a vertical height between about 15 nm and about 50 nm. The hard mask 301 may be silicon nitride (SiN) or other suitable hard mask materials.

[0025] Figure 2 According to one embodiment of the present invention, Figure 1 1 is an illustrative illustration of a cross-sectional view of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, embodiments of the present invention provide for forming a bottom spacer 220 on top of the bottom epitaxial layer 210. The bottom spacer 220 surrounds the vertical channel 310 at its bottom portion and can be a dielectric material layer such as silicon nitride (SiN), silicon oxide (SiO), or other low dielectric constant materials (e.g., SiOC, SiON, SiOCN, SiBCN). Other suitable insulating materials may also be used when forming the bottom spacer 220. The bottom spacer 220 may have a vertical thickness of approximately 5 nanometers to 15 nanometers.

[0026] Figure 3 According to one embodiment of the present invention, Figure 2 3 is an illustrative illustration of a cross-sectional view of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, an embodiment of the present invention provides for forming a gate oxide 320 at the side surface of the vertical channel 310. For example, an embodiment of the present invention may include exposing the vertical channel 310 to an oxygen environment to oxidize the side surface of the straight channel 310, thereby turning the side surface of the vertical channel 310 into a thin oxide layer to become the gate oxide 320. The oxidation process can be performed after forming the bottom spacer 220, so that only the portion of the side surface of the vertical channel 310 between the hard mask 301 and the bottom spacer 220 can be oxidized to the gate oxide 320.

[0027] Figure 4 According to one embodiment of the present invention, Figure 3illustrative illustration of a cross-sectional view of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, embodiments of the present invention provide a ferroelectric material forming a first conformal layer 410 surrounding the vertical channel 310. For example, in one embodiment, the ferroelectric material of the first conformal layer 410 can be formed on the top of the bottom spacer 220 and the hard mask 301, the sidewalls of the hard mask 301, and the gate oxide 320 surrounding the vertical channel 310 by, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) GV, an atomic layer deposition (ALD) process, or other existing or future developed methods. The first conformal layer 410 can have a thickness from about 1 nm to about 5 nm.

[0028] Figure 5 According to one embodiment of the present invention, Figure 4 301. An illustrative illustration of a cross-section of the FeRAM cell 10 at a step in its fabrication, after the step shown in . More specifically, embodiments of the present invention provide for performing an anisotropic etching process, such as a reactive ion etching (RIE) process, to remove horizontal portions of the first conformal layer 410 ferroelectric material. For example, the anisotropic etching process can remove portions of the first conformal layer 410 on top of the bottom spacer 220 and on top of the hard mask 301, leaving only a vertical portion of the first conformal layer 410 relative to the gate oxide 320.

[0029] Figure 6 According to one embodiment of the present invention, Figure 5 1 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, embodiments of the present invention provide for forming a sacrificial material layer, such as a first organic planarization layer (OPL) 510, on top of the FeRAM cell 10 in manufacturing. For example, the first OPL 510 may cover the bottom spacer 220, the vertical portion 411 of the first conformal layer 410, and the top surface of the hard mask 301, having a height higher than the top surface of the hard mask 301.

[0030] Figure 7 According to one embodiment of the present invention, Figure 6 1 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, embodiments of the present invention include chamfering the first OPL 510 to expose a portion of the vertical portion 411 of the first conformal layer 410. For example, chamfering the first OPL 510 includes creating a first sacrificial material layer, e.g., a modified first OPL 511, having a vertical height V1 that covers a lower portion of the vertical portion 411 of the first conformal layer 410. Chamfering the first OPL 510 may include etching the OPL material through a RIE process.

[0031] Figure 8 According to one embodiment of the present invention, Figure 7 5. More specifically, embodiments of the present invention provide for removing the exposed portion of the vertical portion 411 of the first conformal layer 410 ferroelectric material that is not covered by the modified first OPL 511, thereby forming a first layer of ferroelectric material 412 having a vertical height V1 that surrounds the first segment of the vertical channel 310. Figure 8 As shown in FIG. 3 , the first section of the vertical channel 310 has a corresponding vertical height V1 .

[0032] Fig. 9 According to one embodiment of the present invention, Figure 8 1 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, embodiments of the present invention provide for removing the first sacrificial material layer of the modified first OPL 511 to expose the first layer of ferroelectric material 412. The first layer of ferroelectric material 412 may have a horizontal thickness that is the same as the thickness of the first conformal layer 410, ranging from about 1 nm to about 5 nm.

[0033] Fig.10 According to one embodiment of the present invention, Fig. 9 3. An illustrative illustration of a cross-section of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, embodiments of the present invention provide a method of forming a second conformal layer 420 of ferroelectric material surrounding the exposed portion of the vertical channel 310 and the first layer of ferroelectric material 412. For example, the second conformal layer 420 of ferroelectric material can be formed on the top of the bottom spacer 220, the top and sidewalls of the hard mask 301, the gate oxide 320 surrounding the exposed portion of the vertical channel 310, and the first layer of ferroelectric material 412 by, for example, a CVD process, PVG, an ALD process, or any other suitable method. The second conformal layer 420 can have a thickness from about 1 nm to about 5 nm.

[0034] Fig.11 According to one embodiment of the present invention, Fig.10 1 is an illustrative illustration of a cross section of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, embodiments of the present invention provide for performing an anisotropic etching process such as an RIE process) to remove a horizontal portion of the second conformal layer 420 ferroelectric material, which step is similar to Figure 5For example, the anisotropic etching process can remove the horizontal portion of the second conformal layer 420 on top of the bottom spacer 220 and the hard mask 301, thereby leaving only the vertical portion 421 of the second conformal layer 420 relative to the gate oxide 320 and the first layer of ferroelectric material 412.

[0035] Fig.12 According to one embodiment of the present invention, Fig.11 1 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, embodiments of the present invention provide for forming a sacrificial material layer, such as the second OPL 520, on the FeRAM cell 10 in manufacturing. For example, the second OPL 520 may cover the bottom spacer 220, the vertical portion 421 of the second conformal layer 420, and the top surface of the hard mask 301 to have a height higher than the top surface of the hard mask 301.

[0036] Fig.13 According to one embodiment of the present invention, Fig.12 3. An illustrative illustration of a cross-section of the FeRAM cell 10 at a step in its fabrication, after the steps shown in . More specifically, embodiments of the present invention provide for chamfering the second OPL 520 to expose a portion of the vertical portion 421 of the second conformal layer 420 that is directly opposite to the gate oxide 320 and directly above the first layer of ferroelectric material 412. For example, chamfering the second OPL 520 includes creating a second sacrificial material layer, e.g., a modified second OPL 521, having a vertical height V2 that covers a lower portion of the vertical segment 421 of the second conformal layer 420. The lower portion of the vertical segment 421 of the second conformal layer 420 covers the first layer of ferroelectric material 412 and a second segment of the vertical channel 310 that is directly above the first segment of the vertical channel 310. Chamfering the second OPL 520 may include etching the OPL material by a RIE process.

[0037] Fig.14 According to one embodiment of the present invention, Fig.13 5. More specifically, embodiments of the present invention provide for removing the exposed portion of the second conformal layer 420 ferroelectric material vertical portion 421 that is not covered by the modified second OPL 521, thereby forming a second layer of ferroelectric material 422 surrounding the second segment of the vertical channel 310 and the first layer of ferroelectric material 412, which has a vertical height V2. Fig.14 As shown in FIG. 4 , the sum of the height of the second section of the vertical channel 310 and the height of the first layer of ferroelectric material 412 corresponds to the vertical height V2 of the second layer of ferroelectric material 422 .

[0038] Fig.15 According to one embodiment of the present invention, Fig.14 1 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, embodiments of the present invention provide for removing the second sacrificial material layer of the modified second OPL 521 to expose the second ferroelectric material layer 422. The second layer of ferroelectric material 422 may have the same horizontal thickness as the thickness of the second conformal layer 420, ranging from about 1 nm to about 5 nm.

[0039] Fig.16 According to one embodiment of the present invention, Fig.15 3 is an illustrative illustration of a cross-section of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, embodiments of the present invention provide for forming a third conformal layer 430 ferroelectric material layer around the exposed portion of the vertical channel 310 and the second layer of ferroelectric material 422. For example, the third conformal layer 430 ferroelectric material can be formed on the top of the bottom spacer 220, the top and sidewalls of the hard mask 301, the gate oxide 320 around the exposed portion of the vertical channel 310, and the second layer of ferroelectric material 422 by, for example, a CVD process, a PVD process, an ALD process, or any other suitable method. The third conformal layer 430 ferroelectric material can have a thickness from about 1 nm to about 5 nm.

[0040] Fig.17 According to one embodiment of the present invention, Fig.16 More specifically, embodiments of the present invention provide for performing an anisotropic etching process, such as an RIE process, to remove horizontal portions of the third conformal layer 430 ferroelectric material, similar to the steps shown in FIG. Figure 5 as well as Fig.11 For example, the anisotropic etching process can remove the horizontal portion of the third conformal layer 430 ferroelectric material on top of the bottom spacer 220 and on top of the hard mask 301, thereby leaving only the vertical portion 431 of the third conformal layer 430 ferroelectric material adjacent to the gate oxide 320 and the second layer of ferroelectric material 422.

[0041] Fig.18 According to one embodiment of the present invention, Fig.171 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, embodiments of the present invention provide a sacrificial material layer, such as the third OPL 530, formed on top of the FeRAM cell 10 in manufacturing. For example, the third OPL 530 may cover the bottom spacer 220, the vertical portion 431 of the third conformal layer 430, and the top side of the hard mask 301 to have a height higher than the top side of the hard mask 301.

[0042] Fig.19 According to one embodiment of the present invention, Fig.18 3. An illustrative illustration of a cross-section of the FeRAM cell 10 in steps of manufacturing the same, after the steps shown in . More specifically, embodiments of the present invention provide for chamfering the third OPL 530 to expose a portion of the vertical portion 431 of the third conformal layer 430 that is directly opposite to the gate oxide 320 and directly above the second layer of ferroelectric material 422. For example, chamfering the third OPL 530 includes creating a third sacrificial material layer, e.g., a modified third OPL 531, having a vertical height V3 that covers a lower portion of the vertical portion 431 of the third conformal layer 430. The lower portion of the vertical portion 431 of the third conformal layer 430 covers the second layer of ferroelectric material 422 and a third segment of the vertical channel 310, which is located directly above the second segment of the vertical channel 310. Chamfering the third OPL 530 may include etching the OPL material by a RIE process.

[0043] Fig. 20 According to one embodiment of the present invention, Fig.19 5. More specifically, embodiments of the present invention provide for removing the exposed portion of the vertical portion 431 of the ferroelectric material of the third conformal layer 430 that is not covered by the modified third OPL 531, thereby forming a third layer of ferroelectric material 432 having a vertical height V3 surrounding the third segment of the vertical channel 310 and the second layer of ferroelectric material 422. Fig. 20 As shown in FIG. 4 , the sum of the height of the third section of the vertical channel 310 and the height of the second layer of ferroelectric material 422 corresponds to the vertical height V3 of the third layer of ferroelectric material 432 .

[0044] Fig.21 According to one embodiment of the present invention, Fig. 201 is an illustrative illustration of a cross-section of the FeRAM cell 10 in a step of manufacturing the same after the step shown in . More specifically, an embodiment of the present invention provides for removing the third sacrificial material layer of the modified third OPL 531 to expose the third layer of ferroelectric material 432. The third layer of ferroelectric material 432 has the same horizontal thickness as the thickness of the third conformal layer 430, ranging from about 1 nm to about 5 nm.

[0045] According to one embodiment, Fig.21 As illustratively shown in FIG. 1 , the first layer of ferroelectric material 412, the second layer of ferroelectric material 422, and the third layer of ferroelectric material 432 may together form a ferroelectric layer 400 surrounding the vertical channel 310 of the FeRAM cell 10. In other words, the ferroelectric layer 400 may have two or more sections of different horizontal thicknesses between the bottom epitaxial layer 210 as the bottom source / drain region and the top source / drain region 630 (see FIG. 1 ). Fig.24 ). Two or more sections of these ferroelectric layers 400 can be programmed to have different polarization combinations, thereby providing multiple logic states.

[0046] For example, the ferroelectric layer 400 may have a bottom segment having a first vertical height 413 and a first horizontal thickness 414, a middle segment having a second vertical height 423 and a second horizontal thickness 424, and a top segment having a third vertical height 433 and a third horizontal thickness 434. Here, the bottom segment, the middle segment, and the top segment of the ferroelectric layer 400 are different from the first layer 412, the second layer 422, and the third layer 432 of ferroelectric material. In addition, the bottom segment, the middle segment, and the top segment of the ferroelectric layer 400 do not correspond to the first segment, the second segment, and the third segment of the vertical channel 310, which are related to the process of forming the first layer 412, the second layer 422, and the third layer 432 of ferroelectric material.

[0047] According to another embodiment, the bottom section, the middle section and the top section of the ferroelectric layer 400 have three different horizontal thicknesses, and the three different horizontal thicknesses can be arranged in a stepped shape. For example, the bottom section 413, the middle section 423 and the top section 433 of the ferroelectric layer 400 respectively have a first horizontal thickness 414, a second horizontal thickness 424 and a third horizontal thickness 434, and the second horizontal thickness 424 can be greater than the third horizontal thickness 434, but less than the first horizontal thickness 414.

[0048] In one embodiment, the difference between the first horizontal thickness 414 and the second horizontal thickness 424 (between the first segment 413 and the second segment 423) of the ferroelectric layer 400 or the difference between the second horizontal thickness 424 and the third horizontal thickness 434 (between the second segment 423 and the third segment 433) of the ferroelectric layer 400 can be at least 0.5nm, can be greater than 1nm, and in some embodiments can be as large as 5nm. In other words, the horizontal thickness difference between any two segments of the first segment, the second segment, and the third segment is at least 0.5nm. This difference of at least 0.5nm enables the control ability to program different segments of the ferroelectric layer to have different and / or desired polarizations. In another embodiment, the ferroelectric layer 400 can be made of or include hafnium zirconium oxide (HZO) or a suitable perovskite oxide having the general chemical formula ABO3 or a suitable perovskite oxide having the general chemical formula ABO3.

[0049] According to another embodiment, the first vertical height 413 of the bottom segment, the second vertical height 423 of the middle segment, and the third vertical height 433 of the top segment may be the same. In another embodiment, in order to balance and / or adjust the difference in operating currents in different states, as described in more detail below, the first vertical height, the second vertical height, and the third vertical height of the bottom segment 413, the middle segment 423, and the top segment 433 may be different. More specifically, considering that the volumes of the ferroelectric materials in the bottom segment, the middle segment, and the top segment are brought closer to each other, the second vertical height 423 of the middle segment may be greater than the first vertical height 413 of the bottom segment, but less than the third vertical height 433 of the top segment of the ferroelectric layer 400.

[0050] Fig. 22 According to one embodiment of the present invention, Fig.21 1 is an illustrative illustration of a cross section of the FeRAM cell 10 at a step in its fabrication after the steps shown in . More specifically, embodiments of the present invention provide for forming a gate metal 540 surrounding the third layer of ferroelectric material 432 and on top of the bottom spacer 220. Fig. 22As illustratively shown in , in one embodiment, the sum of the horizontal thicknesses of the gate metal 540 and the ferroelectric layer 400 remains substantially constant at different sections of the ferroelectric layer 400. In other words, the gate metal 540 can have multiple horizontal thicknesses that are complementary to the horizontal thickness of the ferroelectric layer 400. For example, the bottom section of the ferroelectric layer 400 can have the largest horizontal thickness, while the gate metal 540 surrounding the bottom section of the ferroelectric layer 400 can have the smallest horizontal thickness. On the other hand, the top section of the ferroelectric layer 400 can have the smallest horizontal thickness, while the gate metal 540 surrounding the top section of the ferroelectric layer 400 can have the largest horizontal thickness. Therefore, a uniform horizontal thickness measured from the outer sidewall of the vertical channel 310 to the gate metal 540 can be achieved.

[0051] In one embodiment, the gate metal 540 may include, for example, tungsten (W), copper (Cu), ruthenium (Ru), and other suitable materials, and may be formed by, for example, a CVD process, a PVD process, or an ALD process, and then chamfered to have a height corresponding to the vertical height V3 of the third layer of ferroelectric material 432.

[0052] Fig.23 According to one embodiment of the present invention, Fig. 22 3 is an illustrative illustration of a cross-section of the FeRAM cell 10 at a step in its fabrication, after the step shown in . More specifically, embodiments of the present invention provide for forming a top spacer 610 on top of the gate metal 540. The top spacer 610 may be deposited over the top of the gate metal 540 to surround the remaining exposed portion of the vertical channel 310, and may include a dielectric material such as SiN, SiO, SiOC, SiON, SiOCN, SiBCN, and / or other suitable insulating materials.

[0053] Fig.24 According to one embodiment of the present invention, Fig.23 6 is an illustrative illustration of a cross section of the FeRAM cell 10 in the steps of manufacturing it after the steps shown in . More specifically, an embodiment of the present invention provides a dielectric layer (ILD) 620 deposited above the top of the top spacer 610. The ILD layer 620 can be deposited to a level higher than the hard mask 301. A CMP process can then be applied to flatten the top surface of the ILD layer 620 to expose the hard mask 301. After the CMP process, the hard mask 301 can be selectively removed to expose the end surface of the vertical channel 310 below. The top epitaxial source / drain region 630 can then be formed by an epitaxial growth process. For example, the top source / drain region can be an epitaxial silicon germanium (SiGe) region.

[0054] According to one embodiment, during operation, the FeRAM cell 10 can be programmed to have multiple logic states. For example, in one embodiment, the top segment of the ferroelectric layer 400 can be programmed to have a polarization state different from the polarization state of the middle segment and the bottom segment. In another embodiment, the top segment and the middle segment of the ferroelectric layer 400 can be programmed to have a polarization state different from the polarization state of the bottom segment.

[0055] The polarization states of the bottom, middle, and top segments of the ferroelectric layer 400 may be controlled by a programming voltage applied to the gate metal 540. For example, in a first case, when a high voltage is applied to the gate metal 540, the bottom, middle, and top segments of the ferroelectric layer 400 may be programmed to have the same polarization state, thereby causing the FeRAM to generate a maximum sensing current. In a second case, when a medium voltage is applied to the gate metal 540, only the middle and top segments of the ferroelectric layer 400 may be programmed to have the same polarization state, and the medium voltage may not be sufficient to program the bottom segment, resulting in the bottom segment having a different polarization state from the middle and top segments, and thus generating a sensing current smaller than the sensing current in the first case. In the third case, when a low voltage is applied to the gate metal 540, only the top segment of the ferroelectric layer 400 can be programmed to have the same polarization state, and the low voltage may not be sufficient to program the middle segment and the bottom segment, resulting in the middle segment and the bottom segment having a different polarization state from the top segment, and thus generating a sensing current that is smaller than the sensing current in the first and second cases. In the fourth case, when no voltage is applied to the gate metal 540, the polarization states of the bottom segment, the middle segment, and the top segment are still different from the first case, and the FeRAM does not generate a sensing current. It can be clearly seen from the above that embodiments of the present invention provide FeRAMs that can have multiple (e.g., 4) logical states. However, embodiments of the present invention are not limited in this respect, for example, more or fewer different segments of the ferroelectric layer can be used to create a ferroelectric random access memory with more or fewer different logical states.

[0056] Fig.251 is a flowchart example of a method for manufacturing a ferroelectric random access memory (FeRAM) cell according to an embodiment of the present invention. The method includes: (901) forming a vertical channel on top of a bottom epitaxial layer, the bottom epitaxial layer forming a bottom source / drain region; (902) forming a bottom dielectric material spacer on top of the bottom source / drain region, the bottom spacer surrounding a bottom portion of the vertical channel; (903) forming a gate oxidation at a side surface of the vertical channel, wherein the gate oxidation can be formed, for example, by an oxidation process of the side surface of the vertical channel; (904) forming a first layer of ferroelectric material surrounding a first segment of the vertical channel; (905) forming a second layer of ferroelectric material surrounding a second segment of the vertical channel and the first layer of ferroelectric material; (906) forming a third layer of ferroelectric material surrounding a third segment of the vertical channel and the second layer of ferroelectric material; (907) forming a gate metal surrounding the third layer of ferroelectric material; and (908) forming a top dielectric material spacer and a top epitaxial source / drain region.

[0057] It will be understood that the exemplary methods discussed herein can be easily combined with other semiconductor processing flows, semiconductor devices, and integrated circuits having various analog and digital circuit devices or mixed signal circuit devices. In particular, integrated circuit chips having various devices such as field effect transistors, bipolar transistors, metal oxide semiconductor transistors, diodes, capacitors, inductors, etc. can be manufactured. Integrated circuits according to the present invention can be used for applications, hardware and / or electronic systems. Hardware and systems suitable for implementing the present invention include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones), solid-state media storage devices, functional circuit devices, etc. Systems and hardware containing such integrated circuits are considered to be part of the embodiments described herein. In view of the description provided herein, those skilled in the art can envision other implementations and applications of the technology of the present invention.

[0058] Therefore, at least part of the semiconductor structures in one or more of the semiconductor structures described herein can be implemented in an integrated circuit. The resulting integrated circuit chip can be distributed by the manufacturer in a bare wafer form (i.e., as a single wafer with multiple unpackaged chips), a bare die form, or a packaged form. In the latter case, the chip can be mounted in a single chip package (e.g., a plastic carrier having pins fixed to a motherboard or other advanced carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip can then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product (e.g., a motherboard) or a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and a central processing unit.

[0059] The description of various embodiments of the present invention exists only for illustrative purposes, and it is not intended to be exhaustive, and the present invention is not limited to the disclosed embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or improvements to existing technologies in the market, and to enable those of ordinary skill in the art to understand the embodiments disclosed herein. Those of ordinary skill in the art will now think of many modifications, substitutions, changes, and equivalents. These modifications, changes, and / or alternative embodiments can be carried out without departing from the scope of the present invention, and are therefore all considered within the scope of the present invention. Therefore, it will be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the present invention.

Claims

1. A ferroelectric random access memory (FeRAM) cell comprising: a vertical channel between a bottom source / drain region and a top source / drain region; a gate oxide surrounding the vertical channel; as well as A ferroelectric layer surrounding the gate oxide, The ferroelectric layer has two or more sections with different horizontal thicknesses between the bottom source / drain region and the top source / drain region.

2. The FeRAM cell according to claim 1 , further comprising: A gate metal surrounds the ferroelectric layer, the gate metal having two or more horizontal thicknesses that are complementary to the different horizontal thicknesses of the two or more sections of the ferroelectric layer.

3. The FeRAM cell of claim 1 , wherein the ferroelectric layer comprises: A bottom section, a middle section, and a top section of three different levels of thickness, the three different levels of thickness being arranged in a step shape. 4 . The FeRAM cell of claim 3 , wherein the top section of the ferroelectric layer is adapted to be programmed to have a polarization state different from polarization states of the middle section and the bottom section.

5. The FeRAM cell of claim 3, wherein the top and middle sections of the ferroelectric layer are adapted to be programmed to have a polarization state different from a polarization state of the bottom section.

6. The FeRAM cell of claim 1, wherein the ferroelectric layer comprises doped hafnium oxide.

7. The FeRAM cell of claim 1, wherein a horizontal thickness difference between two of the two or more sections of the ferroelectric layer is at least 0.5 nm.

8. A ferroelectric random access memory (FeRAM) cell comprising: a vertical channel between a bottom source / drain region and a top source / drain region; a gate oxide surrounding the vertical channel; a ferroelectric layer surrounding the gate oxide; as well as The gate metal surrounding the ferroelectric layer, The ferroelectric layer has a bottom section, a middle section and a top section arranged in a stair shape.

9. The FeRAM cell of claim 8, wherein the bottom segment, the middle segment, and the top segment of the ferroelectric layer have a first horizontal thickness, a second horizontal thickness, and a third horizontal thickness, respectively, wherein the second horizontal thickness is greater than the third horizontal thickness but less than the first horizontal thickness.

10. The FeRAM cell of claim 8, wherein the bottom segment, the middle segment, and the top segment of the ferroelectric layer have a first vertical height, a second vertical height, and a third vertical height, respectively, wherein the second vertical height is less than the third vertical height but greater than the first vertical height.

11. The FeRAM cell of claim 8, wherein the top segment of the ferroelectric layer is adapted to be programmed to have a first polarization state, and the middle segment and the bottom segment of the ferroelectric layer are adapted to be programmed to have a second polarization state, wherein the second polarization state is different from the first polarization state.

12. The FeRAM cell of claim 8, wherein the top segment and the middle segment of the ferroelectric layer are adapted to be programmed to have a first polarization state, and the bottom segment of the ferroelectric layer is adapted to be programmed to have a second polarization state, wherein the second polarization state is different from the first polarization state.

13. The FeRAM cell of claim 8, wherein the top segment, the middle segment, and the bottom segment of the ferroelectric layer have a horizontal thickness difference of at least 0.5 nm.

14. A method of forming a ferroelectric random access memory (FeRAM) cell, the method comprising: forming a vertical channel on top of the bottom epitaxial layer; forming gate oxidation at the side surfaces of the vertical channel; forming a first layer of ferroelectric material surrounding a first segment of the vertical channel; forming a second layer of ferroelectric material surrounding a second segment of the vertical channel and the first layer of ferroelectric material; forming a third layer of ferroelectric material surrounding a third segment of the vertical channel and the second layer of ferroelectric material; forming a gate metal surrounding the third layer of ferroelectric material; as well as A top epitaxial layer at the top of the vertical channel is formed.

15. The method of claim 14, wherein forming the first layer of ferroelectric material comprises: forming a first conformal layer of ferroelectric material surrounding the vertical channel; covering a first section of the first conformal layer ferroelectric material with a first layer of sacrificial material, the first section having a vertical height corresponding to the first section of the vertical channel; as well as Exposed sections of the first conformal layer ferroelectric material not covered by the first sacrificial material layer are removed.

16. The method of claim 15, wherein forming the second layer of ferroelectric material comprises: forming a second conformal layer of ferroelectric material surrounding the first layer of ferroelectric material and a section of the vertical channel not covered by the first layer of ferroelectric material; covering a second section of the second conformal layer ferroelectric material by a second layer of sacrificial material, the second section having a vertical height corresponding to the sum of the first section and the second section of the vertical channel; as well as Exposed sections of the second conformal layer ferroelectric material not covered by the second sacrificial material layer are removed.

17. The method of claim 16, wherein forming the third layer of ferroelectric material comprises: forming a third conformal layer of ferroelectric material surrounding the second layer of ferroelectric material and a section of the vertical channel not covered by the second layer of ferroelectric material; covering a third section of the third conformal layer ferroelectric material by a third layer of sacrificial material, the third section having a vertical height corresponding to a sum of the first section, the second section, and the third section of the vertical channel; and Exposed sections of the third conformal layer ferroelectric material not covered by the third sacrificial material layer are removed.

18. The method according to claim 17, further comprising: After removing the exposed segments of the third conformal layer ferroelectric material, a top spacer is formed around the remaining segments of the vertical channel to expose the remaining segments of the vertical channel therebelow.

19. The method of claim 14, wherein forming the gate oxide comprises exposing the vertical channel to an oxygen-containing environment to oxidize the side surfaces of the vertical channel.

20. The method of claim 14, further comprising: Prior to forming the gate oxide, a bottom spacer is formed on top of the bottom epitaxial layer to surround the vertical channel.

21. A computer program comprising program code adapted to perform the method steps of any one of claims 14 to 20 when said program is run on a computer.

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