Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device provided with a MOS gate structure, the semiconductor device being provided with: an underlayer provided on the front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the base layer; a contact hole provided in the interlayer insulating film and reaching the base layer from the upper surface of the interlayer insulating film; the first alloy layer is arranged at the bottom of the contact hole; and the second alloy layer is arranged on the side wall of the contact hole. Further, a method of manufacturing a semiconductor device is provided, including: a step of forming an initial polycrystalline film and a first initial metal film on an inner wall of the contact hole; and a step of forming a first alloy layer at the bottom of the contact hole and forming a second alloy layer on the side wall of the contact hole by heating the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Patent Document 1 describes a semiconductor device in which a “silicide layer” is provided in a “contact hole”.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2003-318396 Summary of the invention

[0006] Technical issues

[0007] It is desirable to improve reliability on the front side of a semiconductor device.

[0008] Technical Solution

[0009] In a first embodiment of the present invention, a semiconductor device is provided, which has a MOS gate structure, and the semiconductor device has: a base layer, which is arranged on the front side of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film, which is arranged above the base layer; a first contact hole, which is arranged in the interlayer insulating film and reaches the base layer from the upper surface of the interlayer insulating film; a first alloy layer, which is arranged at the bottom of the contact hole; and a second alloy layer, which is arranged on the side wall of the contact hole.

[0010] The first alloy layer may include an alloy layer formed by reacting polycrystal deposited inside the first contact hole.

[0011] The second alloy layer may be an alloy layer formed by reacting polycrystal deposited inside the first contact hole.

[0012] The second alloy layer may have a thickness of 0.01 μm or more and 0.2 μm or less.

[0013] The semiconductor device may include a first barrier metal layer provided inside the first alloy layer and the second alloy layer in the contact hole.

[0014] The first barrier metal layer may have a layer.

[0015] The semiconductor device may include a tungsten plug layer provided in the first contact hole in contact with the first barrier metal layer.

[0016] The semiconductor substrate may have a transistor portion and a diode portion.

[0017] The interlayer insulating film may further include a second contact hole extending from an upper surface of the interlayer insulating film to the base layer, and the second contact hole may not include the second alloy layer on a side wall.

[0018] The semiconductor device may include an impurity-introduced polycrystalline layer provided in contact with the first alloy layer.

[0019] The semiconductor device may include an impurity-introduced polycrystalline layer provided at least between the lower surface of the first alloy layer and the base layer, and the conductivity type of the base layer may be consistent with the conductivity type of the impurity-introduced polycrystalline layer.

[0020] A second barrier metal layer may be provided on a side wall of the second contact hole in contact with the interlayer insulating film.

[0021] The semiconductor substrate may have a recessed portion provided in the base layer below the first contact hole, and the first alloy layer may be provided in the recessed portion.

[0022] The semiconductor substrate may include a lifetime control region including a lifetime inhibitor on at least a portion of the front surface side of the semiconductor substrate.

[0023] The semiconductor substrate may include a transistor portion and a diode portion, the transistor portion may include a main region separated from the diode portion and a boundary region between the main region and the diode portion, and the lifetime control region may be provided in the diode portion and the boundary region.

[0024] In a second embodiment of the present invention, a method for manufacturing a semiconductor device is provided, which includes: a step of forming a MOS gate structure on the front side of a semiconductor substrate; a step of forming an interlayer insulating film above a base layer arranged on the front side of the semiconductor substrate or above the semiconductor substrate; a step of forming a first contact hole in the interlayer insulating film above the base layer, starting from the upper surface of the interlayer insulating film and reaching the base layer; a step of forming an initial polycrystalline film and a first initial metal film on the inner wall of the contact hole; and a step of forming a first alloy layer at the bottom of the first contact hole by heating the semiconductor substrate, and forming a second alloy layer on the side wall of the first contact hole.

[0025] The initial polycrystalline film may be formed before the first initial metal film is formed.

[0026] The initial polycrystalline film may be formed after the first initial metal film is formed.

[0027] The method for manufacturing a semiconductor device may include forming a first barrier metal layer on the first alloy layer and the second alloy layer.

[0028] The method for manufacturing a semiconductor device may include forming a second initial metal film before heating the semiconductor substrate.

[0029] In a third embodiment of the present invention, a semiconductor device is provided, which has a MOS gate structure, and the semiconductor device has: a base layer, which is arranged on the front side of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film, which is arranged above the base layer; a second contact hole, which is arranged in the interlayer insulating film and reaches the base layer from the upper surface of the interlayer insulating film; a third alloy layer, which is arranged at the bottom of the second contact hole; and a second alloy layer, which is arranged on the upper surface of the interlayer insulating film.

[0030] The third alloy layer may include an alloy layer formed by reacting the base layer.

[0031] A second barrier metal layer may be provided on a side wall of the second contact hole in contact with the interlayer insulating film.

[0032] The second barrier metal layer may include: a Ti layer in contact with the interlayer insulating film at a side wall of the second contact hole; and a TiN layer stacked on the Ti layer.

[0033] The semiconductor device may include a first barrier metal layer provided on an upper surface of the third alloy layer.

[0034] The first barrier metal layer may have a TiN layer disposed on the third alloy layer.

[0035] The semiconductor device may include a first barrier metal layer provided on an upper surface of the second alloy layer.

[0036] The first barrier metal layer may have a TiN layer disposed on the second alloy layer.

[0037] In a fourth embodiment of the present invention, a method for manufacturing a semiconductor device is provided, which includes: a step of forming a MOS gate structure on the front side of a semiconductor substrate; a step of forming an interlayer insulating film above a base layer arranged on the front side of the semiconductor substrate or above the semiconductor substrate; a step of forming an initial polycrystalline film on the upper surface of the interlayer insulating layer; a step of forming a second contact hole in the interlayer insulating film from the upper surface of the interlayer insulating film to the base layer; a step of forming a first metal film on the inner wall of the second contact hole and on the upper surface of the initial polycrystalline film; and a step of forming a third alloy layer at the bottom of the second contact hole and a second alloy layer on the upper surface of the interlayer insulating film by heating the semiconductor substrate.

[0038] The method for manufacturing a semiconductor device may include the step of forming a second preliminary metal film on the first preliminary metal film.

[0039] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A An example of a top view of the semiconductor device 100 is shown.

[0041] Figure 1B Show Figure 1A An example of the a-a' section in FIG.

[0042] Figure 2A A plan view showing a modified example of the semiconductor device 100 .

[0043] Figure 2B A plan view showing a modified example of the semiconductor device 100 .

[0044] Figure 2C A cross section taken along the line bb′ of a modification of the semiconductor device 100 is shown.

[0045] Figure 3A It is an enlarged view of a cross section of the semiconductor device 100 .

[0046] Figure 3B It is an enlarged view of a cross section of the semiconductor device 100 .

[0047] Figure 3C It is an enlarged view of a cross section of the semiconductor device 100 .

[0048] Figure 3D It is an enlarged view of a cross section of the semiconductor device 100 .

[0049] Figure 4A It is an enlarged view of a cross section of the semiconductor device 100 .

[0050] Figure 4B It is an enlarged view of a cross section of the semiconductor device 100 .

[0051] Figure 4C It is an enlarged view of a cross section of the semiconductor device 100 .

[0052] Figure 5A It is an enlarged view of a cross section of the semiconductor device 100 .

[0053] Figure 5B It is an enlarged view of a cross section of the semiconductor device 100 .

[0054] Figure 6 It is an enlarged view of a cross section of the semiconductor device 100 .

[0055] Figure 7 Show Figure 2B An example of the b-b' section in FIG.

[0056] Figure 8 Show Figure 2B Another example of the b-b' section in FIG.

[0057] Fig. 9 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 100 .

[0058] Fig. 10A It is a diagram showing an example of a manufacturing process of the semiconductor device 100 .

[0059] Fig. 10B It is a diagram showing an example of a manufacturing process of the semiconductor device 100 .

[0060] Fig. 10C It is a diagram showing an example of a manufacturing process of the semiconductor device 100 .

[0061] Fig.11A It is an enlarged view of a cross section of a modification of the semiconductor device 100 .

[0062] Fig. 11B It is an enlarged view of a cross section of a modification of the semiconductor device 100 .

[0063] Fig. 11C It is an enlarged view of a cross section of a modification of the semiconductor device 100 .

[0064] Fig.11D It is an enlarged view of a cross section of a modification of the semiconductor device 100 .

[0065] Fig.12 It is an enlarged view of a cross section of a modification of the semiconductor device 100 .

[0066] Fig.13A It is an enlarged view of a cross section of the semiconductor device 200 .

[0067] Fig. 13B It is an enlarged view of a cross section of the semiconductor device 200 .

[0068] Fig.14 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 200 .

[0069] Fig.15A It is a diagram showing an example of a manufacturing process of the semiconductor device 200 .

[0070] Fig. 15B It is a diagram showing an example of a manufacturing process of the semiconductor device 200 .

[0071] Fig. 15CIt is a diagram showing an example of a manufacturing process of the semiconductor device 200 .

[0072] Fig.16A It is an enlarged view of a cross section of a modification of the semiconductor device 200 .

[0073] Fig. 16B It is an enlarged view of a cross section of a modification of the semiconductor device 200 .

[0074] Fig. 16C It is an enlarged view of a cross section of a modification of the semiconductor device 200 .

[0075] Explanation of symbols

[0076] 10…semiconductor substrate, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 17…well region, 18…drift region, 19…plug region, 20…buffer region, 21…front surface, 22…collector region, 23…back surface, 24…collector electrode, 25…connection portion, 27…recess, 30…dummy trench portion, 31…extension portion, 32…dummy insulating film, 33…connection portion, 34…dummy conductive portion, 38…interlayer insulating film, 40…gate trench portion, 41…extension portion, 42…gate insulating film, 43…connection portion, 44…gate conductive portion, 50…gate metal layer, 52…emitter electrode, 54…contact hole, 55…contact hole, 56…contact hole, 60…first barrier metal layer, 61…initial polycrystalline film, 62…first alloy layer, 63 …second alloy layer, 64…plug layer, 65…trench contact portion, 66…impurity-introduced polycrystalline layer, 67…first initial metal film, 68…third alloy layer, 69…second initial metal film, 70…transistor portion, 71…table portion, 74…second barrier metal layer, 80…diode portion, 81…table portion, 82…cathode region, 85…extension region, 90…boundary region, 91…table portion, 100…semiconductor device, 102…end side, 112…gate pad, 120…active portion, 130…peripheral gate wiring, 131…gate wiring between active portions, 140…edge terminal structure portion, 151…back side lifetime control region, 152…front side lifetime control region, 212…source region, 214…base region, 219…plug region, 240…gate electrode, 252…source electrode. DETAILED DESCRIPTION

[0077] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0078] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is actually installed.

[0079] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is recorded without recording the positive and negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0080] In this specification, the orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction including the X-axis and the Y-axis and parallel to the upper surface and the lower surface of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0081] In this specification, when described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0082] Figure 1A FIG. 1 shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor portion 70. The semiconductor device 100 is not limited to a transistor as long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10.

[0083] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. It should be noted that the transistor section 70 may also be other transistors such as a MOSFET.

[0084] In this figure, the area around the active part of the semiconductor device 100 is shown, and other areas are omitted. For example, an edge terminal structure portion can be provided in the area on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge terminal structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion has, for example, a guard ring, a field plate, a surface electric field reduction portion, and a structure formed by combining them. It should be noted that in this example, for convenience, the edge on the negative side of the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0085] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. The semiconductor substrate 10 may be a III-V compound such as GaN, Ga 2 O 3 or C, etc. The semiconductor substrate 10 in this example is a silicon substrate. It should be noted that the situation referred to as a top view in this specification refers to the situation viewed from the upper surface side of the semiconductor substrate 10. As described later, the semiconductor substrate 10 has a front surface 21 and a back surface 23.

[0086] The semiconductor device 100 of this example includes a gate groove portion 40, a dummy groove portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are examples of a front-side metal layer. The gate groove portion 40 is an example of a MOS gate structure provided in the semiconductor device 100. It should be noted that the semiconductor device 100 of this example is a transistor having a MOS gate structure, but may also be a diode having a MOS gate structure.

[0087] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. In addition, the gate metal layer 50 is disposed above the connection portion 25 and the well region 17.

[0088] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), copper (Cu), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), copper (Cu), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0089] The emitter electrode 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10 via the interlayer insulating film 38. Figure 1A The interlayer insulating film 38 is omitted in FIG. The interlayer insulating film 38 is provided with a contact hole 54 , a contact hole 55 , and a contact hole 56 penetrating therethrough.

[0090] The contact hole 55 electrically connects the gate metal layer 50 to the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer made of tungsten, copper or the like may be provided inside the contact hole 55. The plug layer will be described later.

[0091] The contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30. A plug layer made of tungsten, copper or the like may be provided inside the contact hole 56.

[0092] The connection portion 25 is connected to the front side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is arranged between the gate metal layer 50 and the gate conductive portion. The connection portion 25 of this example can be extended along the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 can also be arranged between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not arranged between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 of this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is arranged above the front side 21 of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0093] The gate groove portion 40 is an example of a plurality of groove portions extending along a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate groove portion 40 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The gate groove portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0094] The connection portion 43 is preferably at least partially formed into a curved shape. By connecting the ends of the two extension portions 41 of the gate groove portion 40, the electric field concentration at the ends of the extension portion 41 can be alleviated. In the connection portion 43 of the gate groove portion 40, the gate metal layer 50 can be electrically connected to the gate conductive portion via the connection portion 25. In other examples, the connection portion 25 may not be provided, and a contact hole 55 may be provided directly above the extension portion 41 or the connection portion 43 to connect the gate metal layer 50 to the gate conductive portion. Alternatively, Figure 1A The gate metal layer 50 is not provided within the range of Figure 1AThe gate metal layer 50 or a gate pad described later is connected to the connection portion 25 through the contact hole 55 outside the range.

[0095] The dummy groove portion 30 is an example of a plurality of groove portions extending along a predetermined extension direction on the front side 21 of the semiconductor substrate 10. The dummy groove portion 30 is a groove portion electrically connected to the emitter electrode 52. Similar to the gate groove portion 40, the dummy groove portion 30 is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy groove portion 30 of this example has an I-shape on the front side 21 of the semiconductor substrate 10, but may also have a U-shape on the front side 21 of the semiconductor substrate 10 similarly to the gate groove portion 40. That is, the dummy groove portion 30 may have two extension portions extending along the extension direction, and a connection portion connecting the two extension portions.

[0096] The transistor portion 70 of this example has a structure in which two gate trench portions 40 and two dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 of this example has the gate trench portion 40 and the dummy trench portion 30 at a ratio of 1:1. For example, the transistor portion 70 has one dummy trench portion 30 between two extension portions 41.

[0097] However, the ratio of the gate groove portion 40 to the dummy groove portion 30 is not limited to this example. The ratio of the gate groove portion 40 may be greater than the ratio of the dummy groove portion 30, and the ratio of the dummy groove portion 30 may be greater than the ratio of the gate groove portion 40. The ratio of the gate groove portion 40 to the dummy groove portion 30 may be 2:3 or 2:4. In addition, the transistor portion 70 may not have a dummy groove portion 30 and all the groove portions may be set as gate groove portions 40. In another example, the groove portions may also be discretely arranged. In another example, the groove portion may also have an intersection portion in the active portion 120. The discrete groove portion may be a state in which a circular groove portion that does not have an extension portion when viewed from above is discretely arranged. In this case, the shape of the groove portion when viewed from above may be a quadrilateral, a hexagon, etc., or may be other shapes. Alternatively, it may be a state in which a groove portion formed by connecting an extension portion for a circle is discretely arranged. In addition, the arrangement of the groove portions in a plan view may be quadrilateral, hexagonal, etc. The groove portions may have intersections in the active portion 120 so that the conductors inside the grooves are electrically connected.

[0098] The well region 17 is a region of the second conductivity type disposed on the front surface 21 side of the semiconductor substrate 10 more closely than the drift region 18 described later. The well region 17 is an example of a well region disposed on the peripheral side of the active portion 120. The active portion 120 will be described later. As an example, the well region 17 is of P+ type. The well region 17 is disposed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is disposed. The diffusion depth of the well region 17 may be deeper than the depth of the gate groove portion 40 and the dummy groove portion 30. A portion of the gate groove portion 40 and the dummy groove portion 30 on the side close to the gate metal layer 50 is disposed in the well region 17. The bottom of the end portions of the gate groove portion 40 and the dummy groove portion 30 in the extension direction may be covered by the well region 17.

[0099] The contact hole 54 is provided above each region of the emitter region 12 and the contact region 15 in the transistor portion 70. The contact hole 54 is not provided above the well region 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are provided in the interlayer insulating film. One or more contact holes 54 may be provided in a manner extending along the extension direction.

[0100] The mesa portion 71 is a mesa portion provided adjacent to the groove portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion refers to a portion of the semiconductor substrate 10 sandwiched between two adjacent groove portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each groove portion. The extension portion of each groove portion may be set as one groove portion. That is, the region sandwiched between two extension portions may be set as the mesa portion.

[0101] The mesa portion 71 is disposed adjacent to at least one of the dummy groove portion 30 and the gate groove portion 40 in the transistor portion 70. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, in the mesa portion 71, the emitter region 12 and the contact region 15 are alternately disposed in the extension direction. In another example, in the mesa portion 71, the emitter region 12 may be disposed in contact with the groove portion, and the contact region 15 may be disposed in contact with the emitter region 12 and separated from the groove portion.

[0102] The base region 14 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. As an example, the base region 14 is of P-type. The base region 14 can be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Figure 1A Only one end portion of the base region 14 in the Y-axis direction is shown.

[0103] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. As an example, the emitter region 12 of this example is of N+ type. An example of a dopant of the emitter region 12 is arsenic (As). The emitter region 12 is disposed in contact with the gate groove portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 can extend from one of the two groove portions clamping the mesa portion 71 along the X-axis direction to the other groove portion. The emitter region 12 is also disposed below the contact hole 54.

[0104] In addition, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0105] The contact region 15 is a region of the second conductivity type disposed above the base region 14 and having a higher doping concentration than the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is disposed on the front surface 21 of the mesa portion 71. The contact region 15 may be disposed along the X-axis direction from one of the two groove portions clamping the mesa portion 71 to the other groove portion. The contact region 15 may or may not be in contact with the gate groove portion 40 or the dummy groove portion 30. The contact region 15 of this example is in contact with the dummy groove portion 30 and the gate groove portion 40. The contact region 15 is also disposed below the contact hole 54.

[0106] Figure 1B Show Figure 1A 1 is an example of the a-a' cross section in FIG. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor portion 70. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross section. The collector electrode 24 is an example of a back side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0107] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is of N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0108] The buffer region 20 is a region of the first conductivity type disposed on the back surface 23 side of the semiconductor substrate 10 closer to the drift region 18. As an example, the buffer region 20 of this example is of N type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. It should be noted that the buffer region 20 can be omitted.

[0109] The collector region 22 is provided below the buffer region 20 in the transistor portion 70. The collector region 22 has the second conductivity type. As an example, the collector region 22 in this example is of the P+ type.

[0110] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10 . The collector electrode 24 is formed of a conductive material such as metal. The material of the collector electrode 24 may be the same as that of the emitter electrode 52 or may be different from that of the emitter electrode 52 .

[0111] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0112] The emitter region 12 is disposed above the base region 14. The emitter region 12 is disposed between the base region 14 and the front surface 21. The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0113] The accumulation region 16 is a region of the first conductivity type provided on the front surface 21 side of the semiconductor substrate 10 relative to the drift region 18. As an example, the accumulation region 16 of this example is of N+ type. However, the accumulation region 16 may not be provided.

[0114] The accumulation region 16 is disposed in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The ion implantation dose of the accumulation region 16 may be 1.0E+12 cm -2 Above and 1.0E+13cm -2 In addition, the ion implantation dose of the accumulation region 16 may also be 3.0E+12cm -2 Above and 6.0E+12cm -2 By providing the accumulation region 16 , the carrier injection enhancement effect (IE effect) can be enhanced, thereby reducing the on-voltage of the transistor portion 70 .

[0115] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the front side 21. Each groove portion is provided from the front side 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each groove portion also penetrates these regions to reach the drift region 18. The method of manufacturing the groove portion penetrating the doped region is not limited to the method of forming the groove portion after forming the doped region. The method of forming the doped region between the groove portions after forming the groove portion is also included in the method of the groove portion penetrating the doped region.

[0116] The gate groove portion 40 has a gate groove formed on the front side 21, a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is provided in a manner covering the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate groove. The gate conductive portion 44 is provided inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 on the front side 21. The upper end of the gate conductive portion 44 can be at the same height as the front side 21, can be located at a position lower than the front side 21, or can be located at a position higher than the front side 21.

[0117] The gate conductive portion 44 includes a region facing the base region 14 adjacent to the mesa portion 71 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is in contact with the gate trench.

[0118] The dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy groove portion 30 may be covered by an interlayer insulating film 38 on the front side 21. The upper end of the dummy conductive portion 34 may be at the same height as the front side 21, may be located at a position further below than the front side 21, or may be located at a position further above than the front side 21.

[0119] The interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 of this example is provided in contact with the front surface 21 of the semiconductor substrate 10. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10 are provided in the interlayer insulating film 38. The contact holes 55 and the contact holes 56 can also be provided in a similar manner to penetrate the interlayer insulating film 38. The film thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto.

[0120] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a BPSG (Boro-phosphoSilicate Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. The interlayer insulating film 38 may also include a high temperature silicon oxide (HTO: High Temperature Oxide) film.

[0121] The back side lifetime control region 151 can be provided in the transistor portion 70. However, the back side lifetime control region 151 can also be omitted. The back side lifetime control region 151 is a region where a lifetime inhibitor is intentionally formed by injecting impurities or the like into the interior of the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 can also be formed by injecting protons. By providing the back side lifetime control region 151, the turn-off time can be reduced, the tail current can be suppressed, and the loss during switching can be reduced.

[0122] The lifetime inhibitor is a recombination center of carriers. The lifetime inhibitor may be a lattice defect. For example, the lifetime inhibitor may be a vacancy, multiple vacancies, a composite defect of these and an element constituting the semiconductor substrate 10, or a dislocation. In addition, the lifetime inhibitor may also be a rare gas element such as helium or neon, or a metal element such as platinum. The lattice defect may be formed using an electron beam or a proton.

[0123] The lifetime inhibitor concentration refers to the recombination center concentration of carriers. The lifetime inhibitor concentration may be the concentration of lattice defects. For example, the lifetime inhibitor concentration may be a hole concentration such as a hole or a plurality of holes, or a composite defect concentration of these holes and elements constituting the semiconductor substrate 10, or a dislocation concentration. In addition, the lifetime inhibitor concentration may be a chemical concentration of a rare gas element such as helium or neon, or a chemical concentration of a metal element such as platinum.

[0124] The back side lifetime control zone 151 is arranged at a position closer to the back side 23 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The back side lifetime control zone 151 of this example is arranged in the buffer zone 20. The back side lifetime control zone 151 of this example is arranged on the entire surface of the semiconductor substrate 10 in the XY plane and can be formed without using a mask. The back side lifetime control zone 151 can be arranged on a part of the semiconductor substrate 10 in the XY plane. The dose of impurities used to form the back side lifetime control zone 151 can be 0.5E+10cm -2 Above and 1.0E+14cm -2 Below, can also be 5.0E+10cm -2 Above and 1.0E+13cm -2 the following.

[0125] The back-side lifetime control region 151 can be formed by implanting from the back side 23 of the semiconductor substrate 10. Thus, it is easy to avoid the influence on the front side 21 of the semiconductor substrate 10. For example, the back-side lifetime control region 151 is formed by irradiating helium or protons from the back side 23 of the semiconductor substrate 10. Here, the state of the front side 21 can be obtained by the SR method or the measurement of the leakage current, thereby judging whether the back-side lifetime control region 151 is formed by implanting from the front side 21 of the semiconductor substrate 10 or by implanting from the back side 23 of the semiconductor substrate 10.

[0126] Figure 2A A plan view of a modified example of the semiconductor device 100 is shown. In this example, only a part of the components of the semiconductor device 100 is shown, and a part of the components is omitted.

[0127] The semiconductor substrate 10 has an edge 102 in a plan view. The semiconductor substrate 10 of this example has two sets of edge 102 that face each other in a plan view. In this example, the X axis and the Y axis are parallel to one of the edge 102.

[0128] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode 52 is provided above the active portion 120, but is omitted in this figure.

[0129] The active portion 120 is provided with at least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Figure 2AIn the example, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) in the front surface 21 of the semiconductor substrate 10. In another example, only one of the transistor portion 70 and the diode portion 80 may be provided in the active portion 120.

[0130] In this example, the region where the transistor portion 70 is disposed is marked with a symbol "I", and the region where the diode portion 80 is disposed is marked with a symbol "F". The transistor portion 70 and the diode portion 80 may each have a length in the extension direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor portion 70 and the diode portion 80 may be the same as the length direction of each groove portion described later.

[0131] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back side 23 of the semiconductor substrate 10 onto the front side 21 of the semiconductor substrate 10. The cathode region 82 will be described later. On the back side 23 of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region other than the cathode region 82. In this specification, an extension region 85 in which the diode portion 80 is extended along the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region 22 may be provided on the back side 23 of the extension region 85.

[0132] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. Each pad is arranged near the end 102. The vicinity of the end 102 refers to the area between the end 102 and the emitter electrode 52 when viewed from above. When the semiconductor device 100 is actually installed, each pad can be connected to an external circuit via wiring such as a wire.

[0133] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion 40. Figure 2A In FIG. 1 , the gate wiring is marked with oblique hatching.

[0134] The gate wiring of this example has a peripheral gate wiring 130 and an inter-active portion gate wiring 131. The gate wiring can be formed by appropriately combining any one of the gate metal layer 50 and the connecting portion 25 or both. The peripheral gate wiring 130 and the inter-active portion gate wiring 131 can be of the same structure or different structures. The peripheral gate wiring 130 is arranged between the active portion 120 and the end 102 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 120 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above can also be set as the active portion 120. In addition, the peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 can be composed of the gate metal layer 50 and the connecting portion 25.

[0135] The inter-active portion gate wiring 131 is provided between the plurality of active portions 120. Figure 2A In the embodiment, two active portions 120 are arranged side by side in the Y-axis direction. By providing the inter-active portion gate wiring 131 between the plurality of active portions 120 inside the semiconductor substrate 10, the variation of the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0136] The inter-active portion gate wiring 131 is connected to the gate trench portion of the active portion 120. The inter-active portion gate wiring 131 is disposed above the semiconductor substrate 10. The inter-active portion gate wiring 131 of this example is composed of a gate metal layer 50 and a connection portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0137] The inter-active portion gate wiring 131 may be connected to the peripheral gate wiring 130. The inter-active portion gate wiring 131 of this example is provided so as to extend from the peripheral gate wiring 130 on one side to the peripheral gate wiring 130 on the other side in the X-axis direction in a manner that crosses the active portion 120 at approximately the center in the Y-axis direction. When the active portion 120 is divided by the inter-active portion gate wiring 131, the transistor portion 70 and the diode portion 80 may be alternately arranged in each divided region in the X-axis direction.

[0138] The edge termination structure portion 140 is provided on the front surface 21 of the semiconductor substrate 10. The edge termination structure portion 140 is provided between the active portion 120 and the edge 102 in a plan view. The edge termination structure portion 140 of this example is arranged between the peripheral gate wiring 130 and the edge 102. The edge termination structure portion 140 alleviates the electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure portion 140 may include at least one of a guard ring provided in an annular shape surrounding the active portion 120, a field plate, and a surface electric field reduction portion.

[0139] Figure 2BFIG. 1 is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor portion 70 and a diode portion 80. Figure 2A An enlarged view of the upper surface of area A in FIG.

[0140] The semiconductor device 100 of this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 provided inside the front surface 21 side of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are each an example of a trench portion.

[0141] The dummy trench 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10 similarly to the gate trench 40. That is, the dummy trench 30 may have two extending portions 31 extending in the extending direction and a connecting portion 33 connecting the two extending portions 31.

[0142] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor portion 70 of this example includes a boundary region 90 located at the boundary between the transistor portion 70 and the diode portion 80. The region of the transistor portion 70 other than the boundary region 90, that is, the region of the transistor portion 70 separated from the diode portion 80 may also be referred to as a main region.

[0143] The boundary region 90 is a region provided between the main region of the transistor portion 70 and the diode portion 80 and adjacent to the diode portion 80. The boundary region 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In one example, the groove portion of the boundary region 90 includes a gate groove portion 40 and a dummy groove portion 30. The boundary region 90 of this example is configured in such a manner that both ends in the X-axis direction become the dummy groove portions 30, but in other examples, it may also be configured in such a manner that one end in the X-axis direction becomes the dummy groove portion 30 and the other end becomes the gate groove portion 40.

[0144] The contact hole 54 is provided above the base region 14 in the diode portion 80. The contact hole 54 is provided above the contact region 15 in the boundary region 90. None of the contact holes 54 is provided above the well regions 17 provided at both ends in the Y-axis direction.

[0145] The mesa portion 91 is provided in the boundary region 90. The mesa portion 91 has an emitter region 12 and a contact region 15 on the front surface 21 of the semiconductor substrate 10, similarly to the main region of the transistor portion 70. In order to take into account the structures of the transistor portion 70 and the diode portion 80, the boundary region 90 may have a buffer structure different from that of the main region. As an example of a buffer structure, the mesa portion 91 closest to the diode portion 80 may not have an emitter region 12. In addition, the base region 14 may be exposed on the front surface 21 of the semiconductor substrate 10 in a manner that extends over a plurality of mesa portions 91. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0146] The mesa portion 81 is provided in a region sandwiched between adjacent dummy trench portions 30 in the diode portion 80. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0147] The emitter region 12 is provided in the mesa portion 71 , but may not be provided in the mesa portion 81 and the mesa portion 91 closest to the diode portion 80 . The contact region 15 is provided in the mesa portion 71 and the mesa portion 91 , but may not be provided in the mesa portion 81 .

[0148] Figure 2C The bb' cross section of the modified example of the semiconductor device 100 is shown. Figure 2B The semiconductor device 100 of this example includes a back-side lifetime control region 151 and a front-side lifetime control region 152. However, the semiconductor device 100 may not include one of the back-side lifetime control region 151 and the front-side lifetime control region 152. The semiconductor device 100 of this example includes a collector region 22 and a cathode region 82 on the lower surface side of the buffer zone 20, that is, on the back side 23 side of the semiconductor substrate 10.

[0149] The emitter region 12 is provided above the base region 14 in the mesa portion 71. The emitter region 12 is provided in contact with the gate trench portion 40 in the mesa portion 71. In other cross sections, the emitter region 12 may be provided on the front surface 21 of the mesa portion 71.

[0150] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0151] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 may not be provided in the diode section 80.

[0152] The cathode region 82 is provided below the buffer region 20 in the diode portion 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. That is, the collector region 22 is provided below the boundary region 90 in this example.

[0153] The back side lifetime control region 151 is provided in both the transistor portion 70 and the diode portion 80. Thus, the semiconductor device 100 of this example can accelerate the recovery in the diode portion 80, thereby further improving the switching loss. The back side lifetime control region 151 can be formed by the same method as the back side lifetime control region 151 of other embodiments.

[0154] The front-side lifetime control region 152 is provided at a position closer to the front side 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The front-side lifetime control region 152 of this example is provided in the drift region 18. The front-side lifetime control region 152 is provided in both the transistor portion 70 and the diode portion 80. The front-side lifetime control region 152 may be provided in the diode portion 80 and the boundary region 90, and may not be provided in a part of the transistor portion 70. In other examples, the front-side lifetime control region 152 may be provided on the entire surface of the transistor portion 70, may not be provided on the entire surface of the transistor portion 70, and may not be provided on a part or the entire surface of the diode portion 80. The front-side lifetime control region 152 can suppress hole injection from the base region 14 of the diode portion 80 and the contact region 15 of the transistor portion 70, thereby reducing reverse recovery loss.

[0155] The front-side lifetime control region 152 can be formed by any method of the method for forming the back-side lifetime control region 151. The elements and doses used to form the back-side lifetime control region 151 and the front-side lifetime control region 152 can be the same or different. In the case of adjusting the lifetime of the entire region in the Z-axis direction of the semiconductor substrate 10 by electron beam irradiation, this can also be regarded as an example of forming the front-side lifetime control region 152.

[0156] The front-side lifetime control region 152 of this example is set to extend from the diode portion 80 to the boundary region 90. The front-side lifetime control region 152 can be formed by irradiation from the front side 21 of the semiconductor substrate 10. The front-side lifetime control region 152 can also be formed by irradiation from the back side 23 of the semiconductor substrate 10. The front-side lifetime control region 152 of this example is set below the gate groove portion 40. Since the particle beam or the like used to form the front-side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects are sometimes generated at the interface between the gate oxide film and the semiconductor substrate.

[0157] The semiconductor device 100 may be a power semiconductor device for controlling electric power, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure including a back surface metal layer on the back surface 23 of the semiconductor substrate 10 .

[0158] It should be noted that in this example, a trench gate structure RC-IGBT is used as an example for the semiconductor device 100. However, the semiconductor device 100 may also be a planar gate structure semiconductor device, or may be another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0159] Figure 3A 1 is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near the contact hole 54A is shown. The contact hole 54A is an example of the contact hole 54. The cross section of this example is an XZ cross section through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The contact hole 54A (contact hole 54) has a bottom 54b and a sidewall 54w. The first barrier metal layer 60, the first alloy layer 62, the second alloy layer 63 and the plug layer 64 are provided in the contact hole 54A. The contact hole 54A is an example of the first contact hole.

[0160] It should be noted that, in this specification, for convenience, the portion of the inner wall of the contact hole 54 above the front surface 21 of the semiconductor substrate 10 is set as the side wall 54w, and the portion of the inner wall of the contact hole 54 below the front surface 21 of the semiconductor substrate 10 is set as the bottom 54b. In addition, in this specification, the contact hole 54 is sometimes used to describe the structure near the contact hole, but the same structure can also be applied to other contact holes such as the contact hole 55 and the contact hole 56. That is, the first barrier metal layer 60, the first alloy layer 62, the second alloy layer 63, and the plug layer 64 can also be provided in other contact holes such as the contact hole 55 and the contact hole 56.

[0161] The first alloy layer 62 is provided in a manner covering the bottom 54b of the contact hole 54A. The first alloy layer 62 of this example is an alloy layer obtained by reacting polycrystalline. By providing the first alloy layer 62, a good contact can be obtained. For example, the first alloy layer 62 is formed by annealing the polycrystalline silicon formed at the bottom 54b of the contact hole 54A, i.e., the initial polycrystalline film, and the titanium (Ti) first initial metal film. 2 .

[0162] The second alloy layer 63 is provided so as to cover the side wall 54w of the contact hole 54A. The second alloy layer 63 of this example is an alloy layer obtained by polycrystalline reaction, similarly to the first alloy layer 62. For example, the second alloy layer 63 is formed by annealing the polycrystalline silicon formed on the side wall 54w of the contact hole 54A, i.e., the initial polycrystalline film, and the titanium (Ti) first initial metal film. 2 The first alloy layer 62 and the second alloy layer 63 can be formed by the same film forming and annealing process.

[0163] The second alloy layer 63 may be continuous with the first alloy layer 62 at the lower end. That is, the inner wall of the contact hole 54A may be covered by the first alloy layer 62 and the second alloy layer 63. It should be noted that in the drawings, the first alloy layer 62 and the second alloy layer 63 are clearly distinguished, but this is only for convenience. The portion on the bottom 54b of the contact hole 54 in the alloy layer formed integrally in the same process may be referred to as the first alloy layer 62, and the portion on the side wall 54w may be referred to as the second alloy layer 63.

[0164] The thickness T of the second alloy layer 63 in this example is not less than 0.01 μm and not more than 0.2 μm. Here, the thickness T of the second alloy layer 63 is a distance in a direction perpendicular to the side wall 54 w of the contact hole 54A, and may be the film thickness at the thickest position.

[0165] The first barrier metal layer 60 is provided inside the first alloy layer 62 and the second alloy layer 63 in the contact hole 54A. The first barrier metal layer 60 includes at least one of titanium (Ti), cobalt (Co), magnesium (Mg), vanadium (V), lanthanum (La), palladium (Pd), tantalum (Ta) and zirconium (Zr). The first barrier metal layer 60 of this example is formed by treating TiN formed as the second initial metal film by sputtering and TiN formed by sputtering through an annealing process. The first barrier metal layer 60 can be formed by the same annealing process as the first alloy layer 62 and the second alloy layer 63. In addition, the first barrier metal layer 60 may also include a layer obtained by directly remaining the Ti film formed as the first initial metal film, and a layer obtained by nitriding through an annealing process.

[0166] The plug layer 64 is provided in contact with the first barrier metal layer 60 in the contact hole 54A. For example, the material of the plug layer 64 is tungsten. By using tungsten with good embedding properties, the front element structure can be miniaturized. In addition, by providing the first barrier metal layer 60, it is possible to avoid the situation where the gas during the formation of the plug layer 64 corrodes the interlayer insulating film 38, the first alloy layer 62, and the second alloy layer 63.

[0167] The bottom 54b of the contact hole 54A can be set at a position lower than the front side 21 of the semiconductor substrate 10. That is, the semiconductor substrate 10 has a recess 27 provided in the emitter region 12 below the contact hole 54A, and the first alloy layer 62 can be provided to be accommodated in the recess 27. The emitter region 12 is an example of a base layer provided on the front side 21 of the semiconductor substrate 10 or above the semiconductor substrate 10. In this example, the upper surface of the base layer is located at the same height as the front side 21. The upper surface of the base layer can be located at the same height as the front side 21, can be located lower than the front side 21, or can be located higher than the front side 21. As an example in which the upper surface of the base layer is located lower than the front side 21, as described later, there can be a plug region 19 of the trench contact portion 65 of the mesa portion, a gate conductive portion 44, a dummy conductive portion 34, and the like. As an example of the upper surface of the base layer being located above the front surface 21, there may be a connection portion 25, etc., as described later, and there may also be a temperature sensing diode, a field plate of the edge termination structure portion 140, etc. The upper surface of the first alloy layer 62 may protrude from the recess 27, that is, may be located above the front surface 21 of the semiconductor substrate 10.

[0168] The interlayer insulating film 38 has a contact hole 54A and is provided above the semiconductor substrate 10. The interlayer insulating film 38 has a single insulating film provided above the front surface 21, but may have a plurality of stacked insulating films. The interlayer insulating film 38 may be a silicon oxide film such as BPSG.

[0169] Here, if an electron beam or particle beam used to form a lifetime control region passes through a MOS gate structure, defects may sometimes be generated near the interface between the oxide film of the MOS gate structure and the semiconductor layer. Furthermore, if a metal such as Ti having a hydrogen storage effect exists near the MOS gate structure, hydrogen diffused toward the gate portion may be occluded, thereby hindering the hydrogen termination of dangling bonds of the MOS gate structure and causing the threshold voltage to fluctuate. In the past, since the silicide layer provided at the bottom of the contact hole is formed by combining a first initial metal film such as Ti with silicon of a semiconductor substrate, an unreacted first initial metal film having a hydrogen storage effect may sometimes remain on the upper and lower surface sides of the silicide layer. In addition, since there are no elements of the semiconductor substrate that react with the first initial metal film on the side of the contact hole, an unreacted first initial metal film may sometimes remain.

[0170] The semiconductor device 100 of this example combines the initial polycrystalline film formed to form the first alloy layer 62 and the second alloy layer 63 with the first initial metal film, thereby preventing the first initial metal film having the hydrogen storage effect from remaining or reducing the amount of the remaining film. Thus, the influence of the hydrogen storage effect can be suppressed, and the hydrogen termination of the dangling bonds of the MOS gate structure can be promoted. Thus, the fluctuation of the threshold voltage can be suppressed.

[0171] It should be noted that the electron beam and particle beam used to form the lifetime control region have a greater impact on the MOS gate structure when irradiated from the front side 21 of the semiconductor substrate 10, but may also have an impact on the MOS gate structure when irradiated from the back side 23 of the semiconductor substrate 10. Therefore, the semiconductor device 100 can also recover the damage of the MOS gate structure when irradiated from the back side 23, thereby suppressing the fluctuation of the threshold voltage. It should be noted that when a particle beam or the like is irradiated from the back side 23 of the semiconductor substrate 10, the acceleration voltage becomes larger and the device becomes larger, but in the semiconductor device 100 of this example, the impact of the particle beam or the like irradiated from the front side 21 can be suppressed, so the lifetime control region can be formed with a smaller device.

[0172] It should be noted that the first initial metal film may not react completely with the initial polycrystalline film but may remain on the upper surface or lower surface of the second alloy layer 63 directly or in the form of a product obtained by reacting with the atmosphere during annealing, and may also constitute a part of the first barrier metal layer 60. In the case where the first initial metal film is formed on the initial polycrystalline film, the first initial metal film may remain on the upper surface of the second alloy layer 63. In the case where the initial polycrystalline film is formed on the first initial metal film, the first initial metal film may remain on the lower surface of the second alloy layer 63. The same is true for the bottom 54b of the contact hole 54A. In this way, even in the case where the first initial metal film remains, the combination of the initial polycrystalline film and the first initial metal film can reduce the first initial metal film having a hydrogen storage effect, and can suppress the fluctuation of the threshold voltage.

[0173] In the case where the first initial metal film remains on the upper surface of the second alloy layer 63, or in the case where the first initial metal film remains on the upper surface of the first alloy layer 62, an enlarged view of the cross section of the semiconductor device 100 passing through the emitter region 12 may be as shown. Figure 3A As shown, a layer derived from the first initial metal film may be stacked with a layer derived from the second initial metal film to form a portion of the first barrier metal layer 60 .

[0174] On the other hand, in the case where the first initial metal film remains on the lower surface of the second alloy layer 63, an enlarged view of the cross section of the semiconductor device 100 passing through the emitter region 12 is as shown in FIG. Figure 3BAs shown. On the sidewall 54w of the contact hole, a first barrier metal layer 60 originating from the second initial metal film, a second alloy layer 63 formed by the reaction of the initial polycrystalline film and the first initial metal film, and a first barrier metal layer 60 originating from the first initial metal film are formed from the upper surface side. Similarly, on the bottom 54b of the contact hole, a first barrier metal layer 60 originating from the second initial metal film, a first alloy layer 62 formed by the reaction of the initial polycrystalline film and the first initial metal film, a first barrier metal layer 60 originating from the first initial metal film, and a first alloy layer 62 formed by the reaction of silicon in the mesa portion 71 and the first initial metal film can be formed from the upper surface side. A stacked structure can be formed on one or both of the sidewall 54w and the bottom 54b of the contact hole.

[0175] exist Figure 3B In the first barrier metal layer 60 in the example shown below, it is also possible to Figure 3B Similarly, a layer derived from the first initial metal film is sometimes formed on the sidewall 54w of the contact hole or on the upper surface of the interlayer insulating film 38 as described later, on the lower surface of the second alloy layer 63. In addition, at the bottom 54b of the contact hole, the first barrier metal layer 60 may sometimes form a layer with the first alloy layer 62 or the third alloy layer 68 described later.

[0176] In addition, if Figure 3C As shown, the second alloy layer 63 may also be formed on the upper surface outside the contact hole 54A of the interlayer insulating film 38. The second alloy layer 63 on the upper surface of the interlayer insulating film 38 may be formed integrally with the second alloy layer 63 formed on the sidewall 54w of the contact hole 54A. The first barrier metal layer 60 may not be formed on the upper surface of the second alloy layer 63 on the upper surface outside the contact hole 54A of the interlayer insulating film 38. After the first barrier metal layer 60 is formed integrally with the upper surface of the second alloy layer 63 formed on the sidewall 54w of the contact hole 54A, only the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38 is etched back, thereby manufacturing the contact hole 54A shown in this example. Figure 3C In the examples shown below, although the second alloy layer 63 is not formed on the upper surface outside the contact hole of the interlayer insulating film 38, the second alloy layer 63 may be formed on the upper surface of the interlayer insulating film 38 as in this example.

[0177] Figure 3D is an enlarged view of a cross section of the semiconductor device 100. Figure 3A The cross section of FIG. 1 is different in that the front side 21 of the semiconductor substrate 10 passes through the contact area 15. In this example, Figure 3A The differences are specially explained.

[0178] A P+ type plug region 19 having a higher doping concentration than the contact region 15 may be provided below the contact hole 54A. The plug region 19 is an example of a base layer provided on the front surface 21 of the semiconductor substrate 10 or above the semiconductor substrate 10. The plug region 19 may be provided below the contact hole 54A and above the contact region 15. The lower end of the plug region 19 may be provided shallower than the lower end of the contact region 15. Holes are extracted from the contact region 15 and the plug region 19 through the contact hole 54A. The plug region 19 improves the contact resistance between the first barrier metal layer 60 of the contact hole 54A and the contact region 15, thereby improving the latch-up tolerance.

[0179] The plug region 19 may be provided below the contact hole 54A and above the base region 14. The plug region 19 may be provided in the mesa portion 71 and the mesa portion 91. The plug region 19 may not be provided below the contact hole 54A and not be provided above the emitter region 12. In this case, the plug region 19 may be discretely provided along the contact hole 54A in the mesa portion 71 and the mesa portion 91 corresponding to the repeated structure of the emitter region 12 and the contact region 15.

[0180] When the contact hole 54A is provided in the mesa portion 81, the plug region 19 is provided below the contact hole 54A. Thus, the contact resistance between the base region 14 and the first alloy layer 62 is improved. It should be noted that the plug region 19 may be provided locally and discretely instead of being provided in the entire region of the contact region 15 or the base region 14. In the portion where the plug region 19 is not formed, the contact region 15 or the base region 14 may be an example of a base layer provided on the front surface 21 of the semiconductor substrate 10 or above the semiconductor substrate 10. Thus, in the region where the plug region 19 is not formed, when the diode portion 80 is turned on, the injection of holes into the semiconductor substrate 10 is suppressed. When the contact hole 54A is provided in the mesa portion 81, by providing the second alloy layer 63 on the side wall 54w of the contact hole, providing the first alloy layer 62 on the bottom 54b, and removing or reducing the Ti layer included in the first barrier metal layer 60, the fluctuation of the threshold value of the mesa portion 71 and the mesa portion 91 can be suppressed.

[0181] Figure 4A is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near the contact hole 54A is shown. The cross section of this example is an XZ cross section through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. Figure 3A The embodiment of the present invention is different in that, in the contact hole 54A, an impurity-introducing polycrystalline layer 66 is provided on the lower surface of the second alloy layer 63 .

[0182] The impurity-introduced polycrystalline layer 66 of this example is provided between the bottom 54b, which is the lower surface of the first alloy layer 62, and the first alloy layer 62. The impurity-introduced polycrystalline layer 66 is also provided between the lower surface of the second alloy layer 63, that is, the sidewall 54w, and the second alloy layer 63. In the case where the second alloy layer 63 is also formed on the upper surface of the interlayer insulating film 38, the impurity-introduced polycrystalline layer 66 may be provided on the lower surface of the second alloy layer 63 as well as on the upper surface of the interlayer insulating film 38.

[0183] The impurity-introduced polycrystalline layer 66 may be disposed on the lower surface of the first alloy layer 62 but not on the lower surface of the second alloy layer 63. The impurity-introduced polycrystalline layer 66 may also be disposed on the lower surface of the second alloy layer 63 instead of on the lower surface of the first alloy layer 62. The impurity-introduced polycrystalline layer 66 may also be partially disposed on the lower surfaces of the first alloy layer 62 and the second alloy layer 63.

[0184] In the case where the initial polycrystalline film formed to form the first alloy layer 62 and the second alloy layer 63 does not combine with the first initial metal film and remains, an impurity-introduced polycrystalline layer 66 is formed by introducing impurities into the remaining initial polycrystalline film. Impurities can be doped during film formation or introduced by ion implantation after film formation. The impurity-introduced polycrystalline layer 66N is an example of the impurity-introduced polycrystalline layer 66. The impurity-introduced polycrystalline layer 66N disposed above the emitter region 12 is of N type.

[0185] Figure 4B is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near the contact hole 54A is shown. The cross section of this example is an XZ cross section through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. Figure 4A The embodiment of FIG. 5 is different in that, in the contact hole 54A, an impurity-introduced polycrystalline layer 66N is provided on the upper surface of the second alloy layer 63 .

[0186] The impurity-introduced polycrystalline layer 66N of this example is disposed on the upper surface of the first alloy layer 62, that is, between the first barrier metal layer 60 and the first alloy layer 62. The impurity-introduced polycrystalline layer 66N is also disposed on the upper surface of the second alloy layer 63, that is, between the first barrier metal layer 60 and the second alloy layer 63.

[0187] The impurity-introduced polycrystalline layer 66N is disposed on the upper surface of the first alloy layer 62 and the second alloy layer 63. The impurity-introduced polycrystalline layer 66N may be disposed on the upper surface of the first alloy layer 62 but not on the upper surface of the second alloy layer 63. The impurity-introduced polycrystalline layer 66N may also be disposed on the upper surface of the second alloy layer 63 instead of on the upper surface of the first alloy layer 62. The impurity-introduced polycrystalline layer 66N may also be partially disposed on the upper surfaces of the first alloy layer 62 and the second alloy layer 63.

[0188] Figure 4C is an enlarged view of a cross section of the semiconductor device 100. Figure 4A The cross section of the embodiment of FIG. 1 is different in that the front surface 21 passes through the contact region 15. The impurity-introduced polycrystalline layer 66P is an example of the impurity-introduced polycrystalline layer 66. The impurity-introduced polycrystalline layer 66P provided above the contact region 15 is of P type.

[0189] In this way, by providing the impurity-introduced polycrystalline layer 66 on the lower surface of the first alloy layer 62 , it is possible to suppress an increase in resistance caused by the remaining initial polycrystalline film and suppress interference with the movement of charges. Figure 4A , 4B In 4C, the impurity-introduced polycrystalline layer 66 is disposed on the entire lower surface or upper surface side of both the first alloy layer 62 and the second alloy layer 63, but it may be disposed on the lower surface or upper surface of either one, or may be disposed in a local manner. The polarity of the impurity-introduced polycrystalline layer 66 on the lower surface of the first alloy layer 62 only needs to be consistent with the polarity of the emitter region 12, the contact region 15, or the plug region 19 at least partially in the portion in contact with them, and may not be consistent with the polarity of the impurity-introduced polycrystalline layer 66 on the lower surface of the second alloy layer 63. In addition, when the initial polycrystalline film remains on the lower surface of the second alloy layer 63, impurities may not be introduced.

[0190] Figure 5A 1 is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near the contact hole 54B is shown. The cross section of this example is an XZ cross section through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The contact hole 54B is an example of the contact hole 54. In this example, Figure 3A to Figure 4C The difference between the contact hole 54A and the contact hole 54A will be described.

[0191] The contact hole 54B has a third alloy layer 68 disposed at the bottom 54b, a second barrier metal layer 74 disposed on the side wall 54w, and a first barrier metal layer 60 disposed on the third alloy layer 68. The third alloy layer 68 is not disposed on the side wall 54w of the contact hole 54B. That is, in the contact hole 54B, the third alloy layer 68 is disposed instead of the first alloy layer 62 of the contact hole 54A, and the second alloy layer 63 is not disposed. The contact hole 54B is an example of a second contact hole.

[0192] The third alloy layer 68 is formed by annealing the first initial metal film such as Ti. In this example, the emitter region 15 as an example of the base layer reacts with the first initial metal film to form the third alloy layer 68. The third alloy layer 68 in this example is TiSi formed by combining Ti formed as the first initial metal film on the bottom 54b of the contact hole 54B with silicon of the semiconductor substrate 10. 2 .

[0193] The second barrier metal layer 74 of this example may be a stacked structure formed by sputtering a TiN film as a second initial metal film on a Ti film of a first initial metal film formed on a side wall 54w of the contact hole 54B as a first initial metal film. In addition, it may also include a TiN film formed by annealing the Ti of the first initial metal film in a nitrogen atmosphere. In the contact hole 54B, especially on the side wall 54w, the proportion of the unreacted first initial metal film with a hydrogen storage effect is sometimes high. Therefore, the contact hole 54B can be set in an area, range, and degree where the remaining unreacted first initial metal film does not affect the threshold voltage.

[0194] Figure 5B FIG. 1 is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near the contact hole 54B is shown. Figure 5A The cross section of FIG. 1 is different in that the front side 21 of the semiconductor substrate 10 passes through the contact area 15. In this example, Figure 5A The differences are specially explained.

[0195] and Figure 3D and Figure 4C Similarly, a P+ type plug region 19 having a doping concentration higher than that of the contact region 15 may be provided below the contact hole 54B. In this example, the plug region 19 as an example of a base layer reacts with the first initial metal film to form a third alloy layer 68.

[0196] In the diode portion 80, a contact hole 54B may be provided in the mesa portion 81 where the plug region 19 is formed. As described above, the third alloy layer 68 is provided in the contact hole 54B instead of the first alloy layer 62 and the second alloy layer 63. Since the initial polycrystalline film is not formed in the contact hole 54B, titanium reacts only with silicon in the mesa portion 81 to form the third alloy layer 68. Therefore, compared with the case where titanium reacts with the initial polycrystalline film to form the first alloy layer 62, the plug region 19 of the P+ type with a high doping concentration is reduced. Therefore, by providing the contact hole 54B in the mesa portion 81 where the plug region 19 is formed, hole injection from the plug region 19 can be suppressed. It should be noted that in the portion where the plug region 19 is not provided, the contact region 15 and the base region 14, which are an example of the base layer, react with the first initial metal film to form the third alloy layer 68.

[0197] Figure 6 1 is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near the contact hole 54A is shown. The cross section of this example is an XZ cross section through the contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the Figure 3A to Figure 4C The difference between the contact hole 54A and the contact hole 54A will be described.

[0198] The contact hole 54A of this example has a trench contact portion 65 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction. That is, the contact hole 54A has a region extending from the upper surface of the interlayer insulating film 38 to the front surface 21 of the semiconductor substrate 10, and a region (the trench contact portion 65) extending from the front surface 21 of the semiconductor substrate 10 in the depth direction. The bottom 54b of the contact hole 54A is the lower end of the trench contact portion 65, and the side wall 54w of the contact hole 54A is a region of the inner wall of the contact hole 54A from the upper surface of the interlayer insulating film 38 to the front surface 21 of the semiconductor substrate 10, and the bottom 54b is the inner wall of the trench contact portion 65.

[0199] The lower end of the trench contact portion 65 of this example is shallower than the lower end of the contact region 15. The lower end of the trench contact portion 65 may also be deeper than the lower end of the contact region 15. The lower end of the trench contact portion 65 of this example is shallower than the upper end of the gate conductive portion 44. The lower end of the trench contact portion 65 may also be deeper than the upper end of the gate conductive portion 44.

[0200] In this way, the semiconductor device 100 of this example can increase the contact area with the semiconductor substrate 10 and reduce the contact resistance by providing the contact hole 54A having the trench contact portion 65, and can achieve low resistance with respect to hole current by shortening the distance from the base region 14 to the plug layer 64. By providing the contact hole 54A in the transistor portion 70, holes can be easily extracted and latch-up can be suppressed.

[0201] It should be noted that the cross section of the contact hole 54A passing through the emitter region 12 is the same as that of the embodiment of the present invention except that the trench contact portion 65 is provided. Figure 3A The lower end of the trench contact portion 65 of the present example is shallower than the lower end of the emitter region 12. The lower end of the trench contact portion 65 may also be deeper than the lower end of the emitter region 12. The lower end of the trench contact portion 65 of the present example is shallower than the upper end of the gate conductive portion 44. The lower end of the trench contact portion 65 may also be deeper than the upper end of the gate conductive portion 44. At the lower end of the trench contact portion 65, a plug region 19 shared with the contact region 15 may be provided. In addition, the structure having the trench contact portion 65 may also be applied to the contact hole 54B.

[0202] Figure 7 Show Figure 2B The semiconductor device 100 of this example includes a transistor portion 70 and a diode portion 80. The semiconductor device 100 of this example includes a back-side lifetime control region 151 and a front-side lifetime control region 152.

[0203] In the semiconductor device 100 of this example, the contact hole 54 provided in the main region of the transistor portion 70 is Figure 5A and Figure 5BThe contact hole 54B shown in the figure is provided in the diode portion 80 and the boundary region 90. Figure 3A and Figure 3D The contact hole 54A shown in FIG. 5A may also be Figure 4A to Figure 4C The contact hole shown in FIG. 1 (with impurities introduced into the polycrystalline layer 66). Figure 6 As shown, the contact hole 54A and the contact hole 54B may also be provided with a trench contact 65 .

[0204] That is, in the semiconductor device 100 of this example, the contact hole 54A is provided only in the diode portion 80 and the boundary region 90 where the front-side lifetime control region 152 is provided. Thus, in the region through which the electron beam and the particle beam for forming the front-side lifetime control region 152 pass, the unreacted first initial metal film having the hydrogen storage effect is replaced by the first alloy layer and the second alloy layer, and the fluctuation of the threshold voltage caused by the influence of the hydrogen storage effect can be suppressed. In addition, since the P+ type plug region 19 with a high doping concentration remains in the boundary region 90, it is easy to extract holes even if the current is concentrated at the time of shutdown, and it is possible to make it without problems even if the threshold reduction is not completely suppressed.

[0205] Figure 8 Show Figure 2B Another example of the b-b' section in FIG. In this example, in particular, Figure 7 The differences are explained.

[0206] In the semiconductor device 100 of this example, the contact hole 54 provided in the main region of the transistor portion 70 is Figure 3A and Figure 3D The contact hole 54A shown in the figure is provided in the diode portion 80 and the boundary region 90. Figure 5A and Figure 5B Contact hole 54B is shown.

[0207] That is, in the semiconductor device 100 of this example, the contact hole 54A is provided only in the main region of the transistor portion 70 where the front-side lifetime control region 152 is not provided. In the case where the area of ​​the main region of the transistor portion 70 where the front-side lifetime control region 152 is not provided is larger than the areas of the diode portion 80 and the boundary region 90 where the front-side lifetime control region 152 is provided, by replacing the unreacted first initial metal film having the hydrogen storage effect with the first alloy layer and the second alloy layer in the main region of the transistor portion 70 having a high area ratio, it is possible to suppress fluctuations in the threshold voltage caused by the influence of the hydrogen storage effect.

[0208] In addition, in the main region of the transistor portion 70, an initial polycrystalline film is formed at the bottom 54b of the contact hole 54A, so titanium is not combined with silicon of the mesa portion 71, and a P+ type plug region 19 with a high doping concentration remains. Therefore, although holes are easily accumulated due to the lack of the front-side lifetime control region 152, holes are easily extracted at the time of shutdown, and latch-up is suppressed. On the other hand, in the boundary region 90, titanium is combined with silicon of the mesa portion 91, and the P+ type plug region 19 with a high doping concentration is reduced. Therefore, when the diode is operating, hole injection from the plug region 19 of the mesa portion 91 and the contact region 15 can be suppressed.

[0209] It should be noted that Figure 7 , 8 In the figure, corresponding to the boundary of the front-side lifetime control region 152, the boundary region 90 and the diode portion 80 have the same contact hole 54B, and the main region of the transistor portion 70 has a different contact hole 54A, but the present invention is not limited thereto. It is also possible to appropriately select which of the contact holes 54A and 54B to set in each region, so as to achieve a balance between suppressing the reduction of the threshold voltage and the concentration of holes in the mesa portion by reducing the amount of the unreacted first initial metal film having the hydrogen storage effect. The boundary of the front-side lifetime control region 152 and the switching of the contact hole 54A and the contact hole 54B may also be inconsistent. In the case where the front-side lifetime control region 152 is set on the entire surface of the semiconductor device, is not set on the entire surface of the semiconductor device, or is divided into a plurality of regions, the contact hole 54A and the contact hole 54B may be appropriately set in the transistor portion 70 and the diode portion 80.

[0210] Fig. 9 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 100 . Figures 10A to 10C FIG. 1 is a diagram showing an example of a manufacturing process of the semiconductor device 100. Figure 10A to Figure 10C An example of a manufacturing process of the semiconductor device 100 is described with reference to the drawings of each process shown in FIG.

[0211] In step S100, the element structure on the front side 21 of the semiconductor substrate 10 is formed. In step S100, a process of forming a dummy trench portion 30 and a gate trench portion 40 as the element structure on the front side 21 may be included. Step S100 may also include a process of forming a base region 14, an emitter region 12, and a contact region 15 as the element structure on the front side 21 by ion implantation into the semiconductor substrate 10.

[0212] In step S102, an interlayer insulating film 38 is formed on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a silicon oxide film such as BPSG. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films.

[0213] In step S104, the contact hole is formed by etching the interlayer insulating film 38. Here, the recess 27 is formed by over-etching on the front surface 21 of the semiconductor substrate 10. In other words, after reaching the front surface 21 of the semiconductor substrate 10, etching is performed until the recess 27 is formed, thereby forming a contact hole 54 of a sufficient size. In addition, a trench contact portion 65 may also be formed. In addition, the plug region 19 may also be formed between step S104 and step S106.

[0214] In step S104, contact holes such as contact hole 54, contact hole 55, and contact hole 56 may be formed in the interlayer insulating film 38. Figure 3A and Figure 3D The contact hole 54A shown is used as an example for explanation.

[0215] In step S106, the initial polycrystalline film 61 is formed to cover the bottom 54b and the sidewall 54w of the contact hole 54A. The initial polycrystalline film 61 may also be formed on the upper surface of the interlayer insulating film 38. At the bottom 54b of the contact hole 54A, the initial polycrystalline film 61 may be formed in the recess 27, that is, the upper surface of the initial polycrystalline film 61 formed at the bottom 54b of the contact hole 54A may be located below the front surface 21 of the semiconductor substrate 10. The initial polycrystalline film 61 is preferably formed to have a film thickness such that the first initial metal film 67 does not remain on the sidewall 54w of the contact hole 54A after step S110 described later.

[0216] In step S108, a first initial metal film 67 is formed on the initial polycrystalline film 61 in the contact hole 54A. The first initial metal film 67 may also be formed on the interlayer insulating film 38. For example, the first initial metal film 67 is a Ti film formed by sputtering. It should be noted that the order of step S106 and step S108 may be reversed to form the initial polycrystalline film 61 on the first initial metal film 67.

[0217] In step S110, a second initial metal film 69 is formed on the first initial metal film 67. The second initial metal film 69 may be formed on the upper surface of the interlayer insulating film 38. For example, the second initial metal film 69 is a TiN film formed by sputtering. The second initial metal film 69 may be formed continuously by the same apparatus as the first initial metal film 67 in step S108.

[0218] In step S112, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. As a result, the initial polycrystalline film 61 reacts with the first initial metal film 67 to form a first alloy layer 62 at the bottom 54b of the contact hole 54A, and a first barrier metal layer 60 is formed in contact with the upper surface of the first alloy layer 62. A second alloy layer 63 is formed on the sidewall 54w of the contact hole 54A and the upper surface of the interlayer insulating film 38, and a first barrier metal layer 60 is formed in contact with the upper surface of the second alloy layer 63. The first alloy layer 62 and the second alloy layer 63 in this example are TiSi formed by the reaction of the first initial metal film 67 of Ti with the initial polycrystalline film 61 of polycrystalline silicon to form silicide. 2 .

[0219] Ti of the first initial metal film 67 is combined with the initial polycrystalline film 61 and replaced with the first alloy layer 62 and the second alloy layer 63. The thickness T of the second alloy layer 63 is greater than or equal to 0.01 μm and less than or equal to 0.2 μm. It should be noted that a portion of the first initial metal film 67 may also be combined with the semiconductor substrate 10 to form the first alloy layer 62.

[0220] It should be noted that after step S112, unreacted polycrystalline film may remain, especially on the sidewall 54w of the contact hole 54A. Therefore, after step S106, impurities may be injected into the initial polycrystalline film 61, or / and in step S106, impurities may be introduced into the initial polycrystalline film 61 while deposition is performed, so as to form a first alloy layer 62 and the bottom 54b and a second alloy layer 63 and the sidewall 54w. Figure 4A to Figure 4C The impurities shown are introduced into the polycrystalline layer 66 .

[0221] The first barrier metal layer 60 may be the second initial metal film 69. In addition, through the annealing of step S112, the first initial metal film 67 that is not bonded to the initial polycrystalline film 61 may be nitrided to form a TiN film at the bottom 54b of the contact hole 54A, the sidewall 54w, and the upper surface of the interlayer insulating film 38, and may constitute a portion of the first barrier metal layer 60. In addition, a portion of the first initial metal film 67 formed at the bottom 54b of the contact hole 54A, the sidewall 54w, and the upper surface of the interlayer insulating film 38 may remain without being bonded to the initial polycrystalline film 61, nitrogen, etc., and may constitute a portion of the first barrier metal layer 60.

[0222] It should be noted that step S110 may be omitted, and the first barrier metal layer 60 may be formed only from a TiN film formed by nitriding the first initial metal film 67. Since the TiN film formed by annealing has a denser structure than the TiN film formed by sputtering, the interlayer insulating film 38 and the first alloy layer 62 can be more reliably protected from the influence of the gas during the formation of the plug layer 64 described later.

[0223] The annealing of the semiconductor substrate 10 in the nitrogen atmosphere can be divided into the annealing process after step S110 and step S112. The former is an annealing process for forming the first alloy layer 62 and the second alloy layer 63 and for nitriding the remaining first initial metal film 67, and the latter is an annealing process for improving the adhesion of the second initial metal film 69. The conditions of each annealing can be the same or different. In addition, in other examples, only the annealing process before the former step S110 can be performed, and the annealing process after the latter step S110 can be omitted. The annealing process can be performed before forming the plug layer 64.

[0224] In step S114, the plug layer 64 is formed. In this example, the plug layer 64 of tungsten is formed by CVD (Chemical Vapor Deposition) to fill the inside of the contact hole 54 and to be stacked on the interlayer insulating film 38.

[0225] In step S116, the plug layer 64 is etched back. In this way, it is possible to remove unnecessary tungsten film outside the contact hole 54. The etch back can be performed by dry etching or CMP (Chemical Mechanical Polishing).

[0226] After the plug layer 64 is etched back, the second alloy layer 63 and the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38 may be removed by etching back. The initial polycrystalline film 61, the first initial metal film 67, the second initial metal film 69, the second alloy layer 63 and the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38 may also be removed after steps S108, S110 and S112.

[0227] It should be noted that step S116 may be omitted and the plug layer 64 may remain outside the contact hole 54. Alternatively, steps S114 and S116 may be omitted and the plug layer 64 may not be formed.

[0228] After step S116, the emitter electrode 52 may be formed on the semiconductor substrate 10. In addition, after step S116, components on the back surface 23 side such as the collector electrode 24 may be formed. After step S116, the back surface lifetime control region 151 and the front surface lifetime control region 152 may be formed.

[0229] Fig.11A , Fig. 11B as well as Fig. 11C FIG. 1 is an enlarged view of a cross section of a modified example of the semiconductor device 100. Fig.11A , Fig. 11B as well as Fig. 11C In the example of FIG. 1 , the structures of the first barrier metal layer 60 and the second alloy layer 63 are similar to Figure 3A to Figure 4C different. Fig.11A , Fig. 11B as well as Fig. 11C An enlarged view of a cross section near the contact hole 54A is shown. Fig.11A , Fig. 11B as well as Fig. 11C The cross section is an XZ cross section through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. It should be noted that since the XZ cross section through the contact region 15 on the front surface 21 of the semiconductor substrate 10 is provided with the contact region 15 instead of Fig.11A , Fig. 11B as well as Fig. 11C The emission area 12 outside this area, with Fig.11A , Fig. 11B as well as Fig. 11C The XZ cross sections are the same and therefore are omitted from the illustration.

[0230] exist Fig.11A In the example, Figure 3A to Figure 4C The difference is that the first barrier metal layer 60 and the second alloy layer 63 are arranged above the interlayer insulating film 38 outside the contact hole 54A. The second alloy layer 63 can be arranged outside the contact hole 54A in contact with the upper surface of the interlayer insulating film 38. The second alloy layer 63 may not be Fig. 10C The etched-back is removed in step S116 and remains on the upper surface of the interlayer insulating film 38.

[0231] The first barrier metal layer 60 may be disposed outside the contact hole 54A in contact with the upper surface of the second alloy layer 63. Fig. 10C In step S116, the first barrier metal layer 60 may not be removed by etching back, but may remain on the interlayer insulating film 38. Since the first barrier metal layer 60 is also formed on the interlayer insulating film 38, the reliability of mounting such as wire bonding and resin packaging can be improved.

[0232] exist Fig. 11B In the example, Fig.11A The difference is that the plug layer 64 is provided outside the contact hole 54A and above the interlayer insulating film 38. The plug layer 64 can be provided outside the contact hole 54A and above the interlayer insulating film 38 in contact with the first barrier metal layer 60. Since the plug layer 64 is also provided above the interlayer insulating film, the reliability during mounting such as wire bonding and resin packaging can be further improved.

[0233] exist Fig. 11C In the example, Fig.11AThe difference is that the plug layer 64 is not provided in the contact hole 54A, but an emitter electrode 52 is provided instead. The emitter electrode 52 is connected to the front surface 21 of the semiconductor substrate 10 via the contact hole 54A. In the case where the width of the terrace is wide and the width of the contact hole is set wide, the emitter electrode can be directly filled without providing a plug layer. In this case, since the first barrier metal layer 60 is also formed on the interlayer insulating film 38, the reliability during mounting such as wire bonding and resin sealing can also be improved.

[0234] exist Fig.11D In the example, Fig.11A The difference is that the first barrier metal layer 60 and the second alloy layer 63 are not provided on the upper surface of the interlayer insulating film 38, but a second barrier metal layer 74 is provided instead. Fig. 9 , 10A After step S106 of the manufacturing process shown in FIG. 10C, the initial polycrystalline film 61 on the upper surface of the interlayer insulating film 38 around the contact hole 54A is removed, thereby forming a second barrier metal layer 74 on the upper surface of the interlayer insulating film 38. By providing the second barrier metal layer 74 on the upper surface of the interlayer insulating film 38, the residual amount of the first initial metal film 67 is larger than the residual amount of the first barrier metal layer 60, thereby Fig.11A Compared with the example shown in FIG. 1 , the ion resistance can be improved. Fig. 11B In the case where the plug layer 64 is left above the interlayer insulating film 38, the second barrier metal layer 74 may be provided therebetween in such a manner that Fig. 11C When the emitter electrode is buried in the contact hole 54A without forming a plug layer, the second barrier metal layer 74 may be provided therebetween in this manner.

[0235] Fig.12 1 is an enlarged view of a cross section of a modified example of the semiconductor device 100. The semiconductor device 100 of this example has a gate electrode 240 of a planar structure instead of the gate trench portion 40. The cross section of this example is an XZ cross section passing through the source electrode 252, the interlayer insulating film 38, the first conductivity type source region 212, the second conductivity type base region 214, the second conductivity type contact region 215, the second conductivity type plug region 219, and the gate electrode 240 on the front surface 21 of the semiconductor substrate 10. The first barrier metal layer 60, the first alloy layer 62, and the second alloy layer 63 are provided in the contact hole 54A.

[0236] The semiconductor device 100 of this example may not include the plug layer 64. Compared with the trench structure, the planar structure can be provided with a wider pitch, so the contact hole 54A can be filled with the source electrode 252.

[0237] In this case, with Fig. 11CSimilarly, the first barrier metal layer 60 and the second alloy layer 63 may be provided outside the contact hole 54A and above the interlayer insulating film 38. It should be noted that in other examples, the second alloy layer 63, the first barrier metal layer 60, and the plug layer 64 above or on the sidewall of the interlayer insulating film 38 may also be provided as shown in FIG. FIG. 3A to FIG. 11B The gate trench portion 40 may be provided as described above with reference to the contact hole 54A shown in the figure, instead of providing the gate electrode 240 of the planar structure.

[0238] Fig.13A It is an enlarged view of the cross section of the semiconductor device 200. The semiconductor device 200 has the same structure as the semiconductor device 100 except for the structure near the contact hole 54, so the same elements are denoted by the same reference numerals, and the description will focus on the differences.

[0239] The cross section of this example is an XZ cross section passing through the emitter region 12 at the front surface 21 of the semiconductor substrate 10. The third alloy layer 68, the first barrier metal layer 60, the second barrier metal layer 74, and the plug layer 64 are provided in the contact hole 54B. In addition, the second alloy layer 63 and the first barrier metal layer 60 are provided above the interlayer insulating film 38.

[0240] First, the structure in the contact hole 54B is described. The third alloy layer 68 is provided in a manner covering the bottom 54b of the contact hole 54B. The third alloy layer 68 of this example is formed by combining Ti formed as the first initial metal film 67 on the bottom 54b of the contact hole 54B with silicon of the semiconductor substrate 10. By providing the third alloy layer 68, a good contact can be obtained. For example, the third alloy layer 68 is TiSi 2 .

[0241] On the side wall 54w of the contact hole 54B, the second barrier metal layer 74 is provided in contact with the interlayer insulating film 38. The second barrier metal layer 74 may be a stacked structure consisting of a first initial metal film 67 for forming the third alloy layer 68 formed on the side wall 54w of the contact hole 54B and remaining without being combined with nitrogen or the like, and a TiN film formed by sputtering as the second initial metal film 69. In addition, the TiN film may be formed by annealing Ti formed as the first initial metal film 67 on the side wall 54w of the contact hole 54B in a nitrogen atmosphere.

[0242] At the bottom 54b of the contact hole 54B, the first barrier metal layer 60 and the third alloy layer 68 are stacked. The first barrier metal layer 60 may be a TiN film formed by sputtering as the second initial metal film 69. In addition, the first initial metal film 67 for forming the third alloy layer 68 is formed at the bottom 54b of the contact hole 54B and remains without being combined with the semiconductor substrate 10, nitrogen, etc., and a TiN film formed by annealing Ti formed at the bottom 54b of the contact hole 54B as the first initial metal film 67 in a nitrogen atmosphere.

[0243] The plug layer 64 is provided in contact with the first barrier metal layer 60 and the second barrier metal layer 74 in the contact hole 54B. For example, the material of the plug layer 64 is tungsten. By using tungsten with good embedding properties, the front element structure can be miniaturized. The plug layer 64 can also be provided above the interlayer insulating film 38.

[0244] By providing the first barrier metal layer 60 and the second barrier metal layer 74 in the contact hole 54B, the adhesion of the plug layer 64 can be improved. In addition, by providing the first barrier metal layer 60 and the second barrier metal layer 74, it is possible to avoid the interlayer insulating film 38 and the third alloy layer 68 being corroded by the gas during the formation of the plug layer 64.

[0245] Next, the structure of the upper surface of the interlayer insulating film 38 near the contact hole 54B is described. The second alloy layer 63 is provided on the upper surface of the interlayer insulating film 38. The second alloy layer 63 of this example is an alloy layer formed by a polycrystalline reaction. For example, the second alloy layer 63 is formed by annealing the polycrystalline silicon (initial polycrystalline film 61) and the Ti (first initial metal film 67) formed on the upper surface of the interlayer insulating film 38. 2 The third alloy layer 68 and the second alloy layer 63 may be formed through the same annealing process.

[0246] The first barrier metal layer 60 is stacked with the second alloy layer 63. The first barrier metal layer 60 may be a TiN film formed by sputtering as the second initial metal film 69. In addition, the first initial metal film 67 for forming the second alloy layer 63 may be formed on the upper surface of the interlayer insulating film 38 and may be a layer that remains without being combined with the initial polycrystalline film 61, nitrogen, etc., or a TiN film formed by annealing Ti formed on the upper surface of the interlayer insulating film 38 as the first initial metal film 67 in a nitrogen atmosphere. By providing the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38, the ion permeation resistance can be improved.

[0247] In the semiconductor device 200 of this example, the initial polycrystalline film 61 formed to form the second alloy layer 63 is combined with the first initial metal film 67 above the interlayer insulating film 38, thereby preventing the first initial metal film 67 having a hydrogen storage effect from remaining and reducing the amount of the remaining film. As a result, the influence of the hydrogen storage effect can be suppressed, and the hydrogen termination of the dangling bonds of the MOS gate structure can be promoted. As a result, the fluctuation of the threshold voltage can be suppressed.

[0248] Fig. 13B is an enlarged view of a cross section of the semiconductor device 200. Fig.13A The difference between the cross section of the embodiment is that the cross section of the embodiment passes through the contact area 15 at the front side 21 of the semiconductor substrate 10. In the embodiment, in particular Fig.13A The differences are explained.

[0249] A P+ type plug region 19 having a higher doping concentration than the contact region 15 may be provided below the contact hole 54B. The plug region 19 may be provided below the contact hole 54B and above the contact region 15. The lower end of the plug region 19 may be provided shallower than the lower end of the contact region 15. Holes are extracted from the contact region 15 and the plug region 19 through the contact hole 54. Since the plug region 19 improves the contact resistance between the third alloy layer 68 of the contact hole 54B and the contact region 15, the latch-up tolerance is improved.

[0250] The plug region 19 may be provided below the contact hole 54B and above the base region 14. The plug region 19 may be provided in the mesa portion 71 and the mesa portion 91. The plug region 19 may not be provided below the contact hole 54 and above the emitter region 12. In this case, the plug region 19 may be discretely provided along the contact hole 54B in the mesa portion 71 and the mesa portion 91 corresponding to the repeated structure of the emitter region 12 and the contact region 15.

[0251] When the contact hole 54B is provided in the mesa portion 81, the plug region 19 is provided below the contact hole 54B. Thus, the contact resistance between the base region 14 and the first alloy layer 62 is improved. It should be noted that the plug region 19 may be provided locally and discretely instead of being provided in the entire region of the contact region 15 and the base region 14. Thus, in the region where the plug region 19 is not formed, when the diode portion 80 is turned on, the injection of holes into the semiconductor substrate 10 is suppressed.

[0252] Fig.14 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 200 . Figures 15A to 15C FIG. 2 is a diagram showing an example of a manufacturing process of the semiconductor device 200. Figures 15A to 15C An example of a manufacturing process of the semiconductor device 200 is described with reference to the drawings of each process shown in FIG.

[0253] In step S200, the element structure on the front side 21 of the semiconductor substrate 10 is formed. In step S200, a process of forming a dummy trench portion 30 and a gate trench portion 40 as the element structure on the front side 21 may be included. Step S200 may also include a process of forming a base region 14, an emitter region 12, and a contact region 15 as the element structure on the front side 21 by ion implantation into the semiconductor substrate 10.

[0254] In step S202, an interlayer insulating film 38 is formed on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a silicon oxide film such as BPSG. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films.

[0255] In step S204, an initial polycrystalline film 61 is formed on the upper surface of the interlayer insulating film 38. The initial polycrystalline film 61 is preferably formed to such a thickness that the first initial metal film 67 does not remain on the upper surface of the interlayer insulating film 38 after step S212 described below.

[0256] In step S206, the contact hole is formed by etching the interlayer insulating film 38. Here, the recess 27 is formed by over-etching on the front surface 21 of the semiconductor substrate 10. In other words, after reaching the front surface 21 of the semiconductor substrate 10, etching is performed until the recess 27 is formed, thereby forming a contact hole 54B of a sufficient size. In addition, a trench contact portion 65 can also be formed. In addition, the plug region 19 can also be formed between step S206 and step S208.

[0257] After step S204, step S206 is performed. That is, when step S206 is completed, the silicon of the semiconductor substrate 10 and the interlayer insulating film 38 are exposed at the bottom 54b and the sidewall 54w of the contact hole 54B, respectively, and the initial polycrystalline film 61 remains only on the upper surface of the interlayer insulating film 38 surrounding the contact hole 54B. In addition, in step S206, contact holes such as the contact hole 54B, the contact hole 55, and the contact hole 56 can be formed in the interlayer insulating film 38.

[0258] In step S208, a first initial metal film 67 is formed on the inner wall of the contact hole 54B and on the upper side of the interlayer insulating film 38. For example, the first initial metal film 67 is a Ti film formed by sputtering. The first initial metal film 67 is formed in such a manner that the bottom 54b and the side wall 54w of the contact hole 54B are in contact with the silicon of the semiconductor substrate 10 and the interlayer insulating film 38, respectively. The first initial metal film 67 is formed in contact with the upper surface of the initial polycrystalline film 61 above the interlayer insulating film 38.

[0259] In step S210, a second initial metal film 69 is formed on the first initial metal film 67 in the contact hole 54B and above the interlayer insulating film 38. For example, the second initial metal film 69 is a TiN film formed by sputtering. The second initial metal film 69 is formed in a stacked manner with the first initial metal film 67.

[0260] In step S212, the semiconductor substrate 10 is annealed in a nitrogen atmosphere. As a result, at the bottom 54b of the contact hole 54B, the silicon of the semiconductor substrate 10 and the first initial metal film 67 are silicided to form a third alloy layer 68. The third alloy layer 68 in this example is TiSi 2 The first initial metal film 67 formed at the bottom 54b of the contact hole 54B is combined with the silicon of the semiconductor substrate 10 and replaced by the third alloy layer 68. At the bottom 54b of the contact hole 54B, the third alloy layer 68 is formed in contact with the front surface 21 of the semiconductor substrate 10, and the first barrier metal layer 60 is formed in contact with the upper surface of the third alloy layer 68.

[0261] In addition, by the annealing of step S212, the first initial metal film 67 is nitrided to form a TiN film on the side wall 54w of the contact hole 54B. In addition, a portion of the first initial metal film 67 formed on the side wall 54w of the contact hole 54B may remain without being combined with nitrogen or the like. A stacked structure of a Ti layer and a TiN layer may be formed on the side wall 54w of the contact hole 54B. The Ti layer is the remaining first initial metal film 67, and is provided in contact with the interlayer insulating film 38. The TiN layer may be a stacked structure of a TiN film formed by nitriding the second initial metal film 69 and the first initial metal film 67. The Ti layer and the TiN layer in the contact hole 54B are an example of the second barrier metal layer 74.

[0262] It should be noted that step S210 may be omitted, and the second barrier metal layer 74 may be formed only from a TiN film formed by nitriding the first initial metal film 67. Since the TiN film formed by annealing has a denser structure than the TiN film formed by sputtering, the interlayer insulating film 38 and the third alloy layer 68 can be more reliably protected from the influence of the gas during the formation of the plug layer 64 described later.

[0263] In addition, through the annealing in step S212, the initial polycrystalline film 61 and the first initial metal film 67 are silicided on the upper surface of the interlayer insulating film 38 to form a second alloy layer 63. The second alloy layer 63 in this example is TiSi 2. Above the interlayer insulating film 38, the first initial metal film 67 is combined with the initial polycrystalline film 61 and replaced by the second alloy layer 63. Therefore, above the interlayer insulating film 38, the first initial metal film 67 does not remain or the amount of the remaining is small, so the influence caused by the hydrogen storage effect of the first initial metal film 67 can be suppressed, and the hydrogen termination of the dangling bonds of the MOS gate structure can be promoted. As a result, the fluctuation of the threshold voltage can be suppressed.

[0264] In addition, by the annealing in step S212, the first barrier metal layer 60 and the second alloy layer 63 are stacked on the upper surface of the interlayer insulating film 38. The first barrier metal layer 60 may be a TiN film formed by sputtering as the second initial metal film 69. In addition, it may also include a layer in which the first initial metal film 67 for forming the second alloy layer 63 is formed on the upper surface of the interlayer insulating film 38 and remains without being combined with the initial polycrystalline film 61, nitrogen, etc., and a TiN film formed by annealing Ti formed as the first initial metal film 67 on the upper surface of the interlayer insulating film 38 in a nitrogen atmosphere. By providing the first barrier metal layer 60 on the upper surface of the interlayer insulating film 38, it is possible to improve the ion permeation resistance.

[0265] It should be noted that the semiconductor substrate 10 may be annealed before step S210. In this case, the annealing process may be performed twice, after the first initial metal film 67 is formed and after the second initial metal film 69 is formed. The former is an annealing process for forming the third alloy layer 68 and the second alloy layer 63 and for nitriding the remaining first initial metal film 67, and the latter is an annealing process for improving the adhesion of the second initial metal film 69. The conditions of these annealings may be the same or different. In addition, in other examples, only the annealing process before the former step S210 may be performed, and the annealing process after the latter step S210 may not be performed. The annealing process may be performed before the plug layer 64 is formed.

[0266] In step S214, the plug layer 64 is formed. In this example, the plug layer 64 of tungsten is formed by CVD (Chemical Vapor Deposition) to bury the inside of the contact hole 54B. As described above, since the second barrier metal layer 74 and the first barrier metal layer 60 are provided on the inner wall of the contact hole 54, it is possible to avoid the interlayer insulating film 38 and the third alloy layer 68 being corroded by the gas during the formation of the plug layer 64.

[0267] In step S216, the plug layer 64 is etched back. In this way, the unnecessary tungsten film outside the contact hole 54B can be removed. The etch back can be performed by dry etching or CMP (Chemical Mechanical Polishing). It should be noted that step S216 can also be omitted and the plug layer 64 can remain outside the contact hole 54B.

[0268] After step S216, the emitter electrode 52 may be formed above the semiconductor substrate 10. In addition, after step S216, components on the back surface 23 side such as the collector electrode 24 may be formed. After step S216, the back surface lifetime control region 151 and the front surface lifetime control region 152 may be formed. It should be noted that step S216 may be omitted and the plug layer 64 may remain outside the contact hole 54B. In addition, steps S214 and S216 may be omitted and the plug layer 64 may not be formed.

[0269] Thus, according to the manufacturing method of the semiconductor device 200, the second barrier metal layer 74 and the first barrier metal layer 60 having the Ti layer and the TiN layer are formed in the contact hole 54B, so that the ion permeation resistance can be improved. In addition, by forming the second barrier metal layer 74 and the first barrier metal layer 60, it is possible to avoid the interlayer insulating film 38 and the third alloy layer 68 being corroded by the gas when the plug layer 64 is formed.

[0270] In addition, according to the manufacturing method of the semiconductor device 200, before forming the contact hole 54B, the initial polycrystalline film 61 is formed on the upper surface of the interlayer insulating film 38, and the first initial metal film 67 formed on the upper surface of the interlayer insulating film 38 is combined with the initial polycrystalline film 61 and replaced by the second alloy layer 63. In addition, as a result, the Ti layer can be formed in the contact hole 54 to improve the ion permeation resistance obtained by the second barrier metal layer 74, and Ti is removed from the upper surface of the interlayer insulating film 38, suppressing the influence caused by the hydrogen storage effect of Ti, promoting the hydrogen termination of the dangling bond of the MOS gate structure, and improving the ion permeation resistance by the first barrier metal layer 60. As a result, the fluctuation of the threshold voltage can be suppressed.

[0271] Fig.16A , Fig. 16B as well as Fig. 16C FIG. 2 is an enlarged view of a cross section of a modified example of the semiconductor device 200. Fig.16A , Fig. 16B as well as Fig. 16C In the example, the structure of the plug layer 64 is similar to Fig.13A and Fig. 13B The structure of the plug layer 64 in FIG. Fig.16A , Fig. 16B as well as Fig. 16C An enlarged view of a cross section near the contact hole 54B is shown.

[0272] Fig.16A The cross section is an XZ cross section through the emitter region 12 at the front side 21 of the semiconductor substrate 10. Fig.16A In the example, Fig.13A The difference is that the plug layer 64 is arranged outside the contact hole 54B above the interlayer insulating film 38. The plug layer 64 can be arranged outside the contact hole 54 and above the interlayer insulating film 38 to be in contact with the first barrier metal layer 60. It should be noted that in the XZ cross section of the front surface 21 of the semiconductor substrate 10 through the contact region 15, in addition to the contact region 15 being arranged instead of Fig.16A Except for the emission area 12, all Fig.16A The XZ cross sections are the same and therefore are omitted from the illustration.

[0273] Fig. 16B The cross section is an XZ cross section through the emitter region 12 at the front side 21 of the semiconductor substrate 10. Fig. 16B In the example, Fig.13A The difference is that the plug layer 64 is not provided in the contact hole 54B, but an emitter electrode 52 is provided instead. The emitter electrode 52 is connected to the front surface 21 of the semiconductor substrate 10 through the contact hole 54B. It should be noted that in the XZ cross section of the front surface 21 of the semiconductor substrate 10 through the contact area 15, the contact area 15 is provided instead of the emitter electrode 52. Fig. 16B Except for the emission area 12, all Fig. 16B The XZ cross sections are the same and therefore are omitted from the illustration.

[0274] exist Fig. 16C In the example of the present invention, the gate electrode 240 having a planar structure replaces the gate trench portion 40. The cross section of this example is an XZ cross section passing through the source electrode 252, the interlayer insulating film 38, the source region 212 of the first conductivity type, the base region 214 of the second conductivity type, the contact region 215 of the second conductivity type, the plug region 219 of the second conductivity type, and the gate electrode 240 on the front surface 21 of the semiconductor substrate 10. In the contact hole 54B, the third alloy layer 68 and the first barrier metal layer 60 are provided at the bottom 54b, and the second barrier metal layer 74 is provided on the side wall 54w. In addition, the second alloy layer 63 and the first barrier metal layer 60 are provided above the interlayer insulating film 38.

[0275] The semiconductor device 200 of this example may not have the plug layer 64. Compared with the trench structure, the planar structure can be arranged at a wider pitch, so the contact hole 54B can be filled with the source electrode 252. It should be noted that in other examples, the second alloy layer 63, the first barrier metal layer 60, the second barrier metal layer 74, and the plug layer 64 on the upper side or the side wall of the interlayer insulating film 38 may also be formed by using FIG. 13A to FIG. 16AThe gate trench portion 40 may be provided as in the contact hole 54B described in the figure shown in the figure, instead of providing the gate electrode 240 of the planar structure.

[0276] Thus, the semiconductor device 200 of this example can also be applied to Fig.13A and Fig. 13B The structure inside the contact hole 54B and the structure on the upper surface of the interlayer insulating film 38 are described.

[0277] It should be noted that it is also possible to manufacture Fig. 9 , Figure 10A to Figure 10C The semiconductor device 100 shown in the figure is manufactured by performing the following steps. Fig.13A and Fig. 13B The contact hole 54B of the semiconductor device 200 shown in the figure: after the contact hole 54 is opened in step S104 and the initial polycrystalline film 61 is formed in step S106, the initial polycrystalline film 61 inside the contact hole 54B is removed so that it only remains on the upper surface of the interlayer insulating film 38, and the steps after step S108 are performed. In the case where the contact hole 54B is manufactured by such a manufacturing process, the initial polycrystalline film 61 may not remain on the entire upper surface of the interlayer insulating film 38, but the initial polycrystalline film 61 may be removed in part. For example, the boundary where the initial polycrystalline film 61 remains may not coincide with the opening of the contact hole 54B, and the boundary between the second barrier metal layer 74 and the first barrier metal layer 60 and the boundary between the second barrier metal layer 74 and the second alloy layer 63 may exist on the upper surface of the interlayer insulating film 38. In this way, the semiconductor device 100 having the contact hole 54A and the contact hole 54B can be manufactured by partially removing the initial polycrystalline film 61 formed after the contact hole 54 is formed. Figure 7 In the example, with Figure 3A The contact hole 54A and Figure 5A The contact hole 54B shown in FIG. 1 is described above, but is not limited thereto. For example, the contact hole 54B may also have Fig.11A The contact hole 54A and Fig.13A The contact hole 54B shown, or the contact hole 54B having the second barrier metal layer 74 on the upper surface of the interlayer insulating film 38, etc.

[0278] Alternatively, the semiconductor device 200 having only the contact hole 54B may be manufactured by partially removing the initial polycrystalline film 61 formed after the contact hole 54 is formed. Fig.13A , Fig. 13B The contact hole 54B shown in the figure may also have Figure 5A , Figure 5BThe contact hole 54B shown in the figure, the contact hole 54B having a second barrier metal layer 74 on the upper surface of the interlayer insulating film 38, and other contact holes 54B with different structures.

[0279] In addition, it is also possible to Fig. 9 , Figure 10A to Figure 10C In the manufacturing process of the semiconductor device 100 shown in FIG. 1 , the semiconductor device 100 having the contact hole 54A and the contact hole 54B is manufactured by performing the following steps: the contact hole 54A is opened in step S104, and after the initial polycrystalline film 61 is formed in step S106, the contact hole 54B is opened in the interlayer insulating film 38 on which the initial polycrystalline film 61 is formed, and the steps after step S108 are performed. The manufacturing process of the contact hole 54B is similar to that of the contact hole 54B. Fig.14 , Figures 15A to 15C Thus, even if the initial polycrystalline film 61 is not removed in the middle, the semiconductor device 100 having the contact holes 54A and 54B can be manufactured. That is, if the emitter electrode 52 is formed after step S116, a semiconductor device having Fig.11A The contact hole 54A and Fig.13A If the semiconductor device 100 having the contact hole 54B shown in FIG. 1 is further removed after step S116 to form the emitter electrode 52 by removing the first barrier metal layer 60 and the second alloy layer 63, a semiconductor device having a contact hole 54B can be obtained. Figure 3A The contact hole 54A and Figure 5A If the semiconductor device 100 having the contact hole 54B shown in FIG. 1 is omitted and the emitter electrode 52 is formed, a semiconductor device having Fig. 11B The contact hole 54A and Fig.16A If the semiconductor device 100 having the contact hole 54B shown in FIG. 1 is omitted and the emitter electrode 52 is formed, a semiconductor device having Fig. 11C The contact hole 54A and Fig. 16B The semiconductor device 100 is shown with the contact hole 54B.

[0280] In the embodiments so far, the first alloy layer 62 of the bottom 54b of the contact hole 54A is formed by the initial polycrystalline film 61 of the bottom 54b formed after the contact hole is opened, but the invention is not limited thereto. Fig. 9 and Fig. 10BIn the step S106 shown, only the portion of the bottom 54b of the contact hole is removed from the initial polycrystalline film 61, and the first alloy layer 62 is formed from the silicon of the terrace portion of the bottom 54b of the contact hole, that is, the base layer. In this case, by forming the second alloy layer 63 on the side wall 54w of the contact hole and removing or thinning the first initial metal film 67 of the first barrier metal layer 60 on the side wall 54w of the contact hole, the fluctuation of the threshold value can also be suppressed. In addition, for the injection of carriers through the bottom 54b of the contact hole, the amount of silicon in the terrace portion that changes to silicide increases, and the high-concentration area decreases, so that adjustment different from the process described in the embodiments so far can be performed.

[0281] On the other hand, in the embodiments so far, the third alloy layer 68 at the bottom 54b of the contact hole 54B is formed of the silicon of the terrace portion of the bottom 54b of the contact hole, i.e., the base layer, but the invention is not limited thereto. Fig. 9 and Fig. 10B The initial polycrystalline film 61 of step S106 shown in the figure is formed, and the third alloy layer 68 is formed from the initial polycrystalline film 61 of the bottom 54b. In this case, when the second alloy layer 63 is formed on the upper surface of the interlayer insulating film 38 around the contact hole 54B, the first initial metal film 67 of the first barrier metal layer 60 is removed or thinned on the upper surface of the interlayer insulating film 38, thereby suppressing the fluctuation of the threshold value. In addition, for the injection of carriers through the bottom 54b of the contact hole, since the amount of silicon in the terrace portion that changes into silicide is reduced, a high concentration area remains, and since an impurity introduction polycrystalline layer 66 is sometimes provided, it is possible to make adjustments different from the processing described in the embodiments so far.

[0282] In addition, the contact holes 55, 56, etc., which are formed in areas other than the active portion 120 to connect the emitter electrode 52 to the emitter region 12, the contact region 15, the base region 14, the plug region 19, etc., which are the base layers, may also be formed with the same structure as the contact holes 54A and 54B described in the embodiments so far. Figure 1A , Figure 2B As shown in the figure, it is arranged on the connection part 25 as the base layer or as Figure 1A , Figure 2B The contact hole 55 on the gate conductive portion 44 of different examples, such as Figure 1A , Figure 2B As shown in the figure, it is arranged on the dummy conductive part 34 or as Figure 1A , 2BIn the contact hole 56 on the connecting portion 25 of different examples, or the contact hole on the polysilicon diode of the temperature sensing diode not shown, the field plate of the edge terminal structure portion 140, the guard ring, etc., when the second alloy layer 63 is formed on the upper surface of the interlayer insulating film 38 and the side wall of the contact hole, the first initial metal film 67 of the first barrier metal layer 60 that is connected to the second alloy layer 63 is removed or thinned, thereby suppressing the fluctuation of the threshold of the active portion 120.

[0283] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0284] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: With MOS gate structure, The semiconductor device comprises: A base layer, which is disposed on the front surface of the semiconductor substrate or above the semiconductor substrate; an interlayer insulating film disposed above the base layer; a first contact hole provided in the interlayer insulating film and extending from the upper surface of the interlayer insulating film to the base layer; a first alloy layer disposed at the bottom of the first contact hole; as well as The second alloy layer is disposed on the sidewall of the first contact hole.

2. The semiconductor device according to claim 1, wherein: The first alloy layer includes an alloy layer formed by reacting polycrystal deposited inside the first contact hole.

3. The semiconductor device according to claim 1, wherein: The second alloy layer is an alloy layer formed by reacting polycrystal deposited inside the first contact hole.

4. The semiconductor device according to claim 1, wherein: The second alloy layer has a thickness of 0.01 μm or more and 0.2 μm or less.

5. The semiconductor device according to claim 1, wherein: The semiconductor device includes a first barrier metal layer provided inside the first alloy layer and the second alloy layer in the first contact hole.

6. The semiconductor device according to claim 5, wherein: The first barrier metal layer includes a TiN layer.

7. The semiconductor device according to claim 6, wherein: The semiconductor device includes a tungsten plug layer, and the plug layer is provided in the first contact hole in contact with the first barrier metal layer.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that The semiconductor substrate has a transistor portion and a diode portion.

9. The semiconductor device according to claim 1, wherein: The interlayer insulating film further has a second contact hole reaching the base layer from the upper surface of the interlayer insulating film. The second contact hole does not have the second alloy layer on a side wall.

10. The semiconductor device according to claim 1, wherein: The semiconductor device includes an impurity-introduced polycrystalline layer provided in contact with the first alloy layer.

11. The semiconductor device according to claim 1, wherein: The semiconductor device includes an impurity-introduced polycrystalline layer provided at least between the lower surface of the first alloy layer and the base layer, and the conductivity type of the base layer matches the conductivity type of the impurity-introduced polycrystalline layer.

12. The semiconductor device according to claim 9, wherein: A second barrier metal layer is provided on a side wall of the second contact hole in contact with the interlayer insulating film.

13. The semiconductor device according to claim 1, wherein: The semiconductor substrate has a recessed portion provided in the base layer below the first contact hole, and the first alloy layer is provided in the recessed portion.

14. The semiconductor device according to claim 1, wherein: The semiconductor substrate has a lifetime control region containing a lifetime inhibitor on at least a portion of a front surface side of the semiconductor substrate.

15. The semiconductor device according to claim 14, wherein: The semiconductor substrate has a transistor portion and a diode portion, the transistor portion has a main region separated from the diode portion and a boundary region between the main region and the diode portion, and the lifetime control region is provided in the diode portion and the boundary region.

16. A method for manufacturing a semiconductor device, characterized in that: include: The step of forming a MOS gate structure on the front side of the semiconductor substrate; forming an interlayer insulating film on a base layer provided on the front surface of the semiconductor substrate or on the semiconductor substrate; A step of forming, above the base layer, in the interlayer insulating film a first contact hole reaching the base layer from the upper surface of the interlayer insulating film; forming an initial polycrystalline film and a first initial metal film on the inner wall of the first contact hole; as well as The semiconductor substrate is heated to form a first alloy layer at the bottom of the first contact hole, and a second alloy layer is formed on the sidewall of the first contact hole.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The initial polycrystalline film is formed before the first initial metal film is formed.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: The initial polycrystalline film is formed after the first initial metal film is formed.

19. The method for manufacturing a semiconductor device according to claim 16, wherein: The method for manufacturing a semiconductor device includes the step of forming a preliminary first barrier metal layer on the first alloy layer and the second alloy layer.

20. The method for manufacturing a semiconductor device according to claim 16, wherein: The method for manufacturing a semiconductor device includes forming a second initial metal film before heating the semiconductor substrate.

21. A semiconductor device, characterized in that: With MOS gate structure, The semiconductor device comprises: A base layer, which is disposed on the front surface of the semiconductor substrate or above the semiconductor substrate; an interlayer insulating film disposed above the base layer; a second contact hole provided in the interlayer insulating film and extending from the upper surface of the interlayer insulating film to the base layer; a third alloy layer, disposed at the bottom of the second contact hole; as well as The second alloy layer is disposed on the upper surface of the interlayer insulating film.

22. The semiconductor device according to claim 21, wherein: The third alloy layer includes an alloy layer formed by reacting the base layer.

23. The semiconductor device according to claim 21, wherein A second barrier metal layer is provided on a side wall of the second contact hole in contact with the interlayer insulating film.

24. The semiconductor device according to claim 23, wherein: The second barrier metal layer has: A Ti layer in contact with the interlayer insulating film at a side wall of the second contact hole; and A TiN layer is stacked on the Ti layer.

25. The semiconductor device according to claim 22, wherein: The semiconductor device includes a first barrier metal layer provided on an upper surface of the third alloy layer.

26. The semiconductor device according to claim 25, wherein: The first barrier metal layer has a TiN layer disposed on the third alloy layer.

27. The semiconductor device according to claim 22, wherein: The semiconductor device includes a first barrier metal layer provided on an upper surface of the second alloy layer.

28. The semiconductor device according to claim 27, wherein: The first barrier metal layer has a TiN layer disposed on the second alloy layer.

29. A method for manufacturing a semiconductor device, characterized in that: include: The step of forming a MOS gate structure on the front side of the semiconductor substrate; forming an interlayer insulating film on a base layer provided on the front surface of the semiconductor substrate or on the semiconductor substrate; A step of forming an initial polycrystalline film on the upper surface of the interlayer insulating layer; A step of forming a second contact hole in the interlayer insulating film so as to reach the base layer from the upper surface of the interlayer insulating film; forming a first initial metal film on the inner wall of the second contact hole and the upper surface of the initial polycrystalline film; as well as The step of forming a third alloy layer at the bottom of the second contact hole and forming a second alloy layer on the upper surface of the interlayer insulating film by heating the semiconductor substrate.

30. The method for manufacturing a semiconductor device according to claim 29, wherein: The method for manufacturing a semiconductor device includes the step of forming a second initial metal film on the first initial metal film.

Images