Semiconductor device

Abstract

The invention provides a semiconductor device capable of improving reliability. According to one embodiment, a semiconductor device includes: a first electrode; a second electrode facing the first electrode in the first direction; a semiconductor portion provided between the first electrode and the second electrode; a metal silicide layer disposed between the second electrode and the semiconductor portion; and a metal layer. And a metal silicide layer provided between the metal silicide layer and the second electrode, the metal silicide layer having a recess recessed toward the semiconductor portion side. The metal layer is in contact with the bottom surface and the side surface of the recess.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device. Background Art

[0002] In power semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is known that a p-type transistor is provided below a source electrode. + Type semiconductor region and n + In addition, in this structure, a metal silicide layer and a metal layer are sometimes provided between the source electrode and the semiconductor region.

[0003] In the power semiconductor device as described above, when a current flows in the opposite direction between the drain electrode and the source electrode, thermal stress is generated due to the difference in thermal expansion coefficient between the metal silicide layer and the metal layer. When the adhesion between the metal silicide layer and the metal layer is reduced due to the thermal stress, metal peeling and metal cracking are likely to occur. As a result, reliability may be reduced.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 7243094 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] An object of the present invention is to provide a semiconductor device having improved reliability.

[0009] Technical solutions for solving technical problems

[0010] A semiconductor device according to one embodiment includes: a first electrode; a second electrode facing the first electrode in a first direction; a semiconductor portion provided between the first electrode and the second electrode; a metal silicide layer provided between the second electrode and the semiconductor portion; and a metal layer. The metal silicide layer is provided between the metal silicide layer and the second electrode, and has a concave portion that is concave toward the semiconductor portion. The metal layer is in contact with the bottom surface and the side surface of the concave portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment cut along the vertical direction.

[0012] Figure 2 It is a perspective view showing the structure of the main part of the semiconductor device 1 according to the first embodiment.

[0013] Figure 3 It is a cross-sectional view of a semiconductor device of a comparative example cut along a vertical direction.

[0014] Figure 4 It is a perspective view showing the structure of a main part of a semiconductor device according to a comparative example.

[0015] Figure 5 This is a cross-sectional view of the semiconductor device according to the second embodiment cut along the vertical direction.

[0016] Figure 6 It is a perspective view showing the structure of a main part of a semiconductor device according to a second embodiment.

[0017] Figure 7 It is a perspective view showing the structure of a main part of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention.

[0019] (First Embodiment)

[0020] Figure 1 It is a cross-sectional view of the semiconductor device of the first embodiment cut along the vertical direction. The semiconductor device 1 of the present embodiment is a MOSFET with a planar gate structure. In the following description, the X-axis, Y-axis and Z-axis shown in each figure are sometimes used to illustrate the configuration and structure of each part of the semiconductor device. The X-axis, Y-axis and Z-axis are orthogonal to each other, and respectively represent the X direction (second direction), the Y direction (third direction), and the Z direction (first direction). In addition, the Z direction is sometimes described as the top and the opposite direction as the bottom. In the present embodiment, the X direction and the Y direction represent the in-plane directions parallel to the semiconductor device 1 of the present embodiment, and the Z direction represents the out-of-plane direction orthogonal to the semiconductor device 1.

[0021] In addition, p, p + The expression of n means that the p-type impurity concentration increases in this order. - 、n + The expression means that the n-type impurity concentration becomes higher in this order.

[0022] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). In addition, the relative level of the impurity concentration can also be determined, for example, based on the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). In addition, the depth and distance of the semiconductor region can be obtained, for example, by SIMS.

[0023] The semiconductor device 1 of the present embodiment includes a semiconductor portion 10, a drain electrode 20, a source electrode 30, a gate electrode 40, a metal silicide layer 50, and a metal layer 60. The drain electrode 20 and the source electrode 30 correspond to a first electrode and a second electrode, respectively.

[0024] like Figure 1 As shown, the semiconductor portion 10 includes n + Type semiconductor region 11, p + type semiconductor region 12, p-type semiconductor region 13 and n-type semiconductor region 14. - Type semiconductor region 14. + The semiconductor region 11 corresponds to the first semiconductor region. + The p-type semiconductor region 12 corresponds to the second semiconductor region. The p-type semiconductor region 13 corresponds to the third semiconductor region.

[0025] n + The semiconductor region 11 is in contact with the metal silicide 50 on its upper surface or side surface. + The type semiconductor region 11 is electrically connected to the source electrode 30 via the metal silicide 50 and the metal layer 60. + The n-type semiconductor region 11 can be formed, for example, by ion implanting a high-concentration n-type impurity from the surface of the semiconductor portion 10 .

[0026] p + The p-type semiconductor region 12 is in contact with the metal silicide 50 on its upper surface. + The type semiconductor region 12 is electrically connected to the source electrode 30 via the metal silicide 50 and the metal layer 60. + The p-type semiconductor region 12 can be formed, for example, by ion implanting a high-concentration p-type impurity from the surface of the semiconductor portion 10 .

[0027] Here, refer to Figure 2 , for n + type semiconductor region 11 and p + The layout of the semiconductor region 12 will be described below.

[0028] Figure 2 1 is a perspective view showing the structure of the main part of the semiconductor device 1 according to the first embodiment. Figure 2 As shown, n + type semiconductor region 11 and p + The n-type semiconductor regions 12 are arranged along the X direction. + type semiconductor region 11 and p + The type semiconductor regions 12 are alternately arranged adjacent to each other along the Y direction.

[0029] The p-type semiconductor region 13 surrounds the n + type semiconductor region 11 and p + The p-type semiconductor region 12 is in contact with each semiconductor region. The p-type semiconductor region 13 can be formed by, for example, ion implanting a low-concentration p-type impurity from the surface of the semiconductor portion 10 .

[0030] return Figure 1 , n - The type semiconductor region 14 is a drift region arranged at the bottom layer of the semiconductor portion 10. - The type semiconductor region 14 is composed of, for example, epitaxially grown SiC (silicon carbide).

[0031] n - When the semiconductor device 1 is turned off, the n-type semiconductor region 14 is depleted by the drain voltage applied between the drain electrode 20 and the source electrode 30. - The thickness of the semiconductor region 14 is designed to satisfy a predetermined withstand voltage condition.

[0032] In addition, in the semiconductor portion 10, various semiconductor layers may be formed between the p-type semiconductor region 13 and the n-type semiconductor region 14. - type semiconductor region 14. In addition, Figure 1 and Figure 2 In FIG. 1 , although not shown in any figure, the region between the two p-type semiconductor regions 13 arranged side by side along the X direction can be set as a Schottky barrier diode region, for example.

[0033] The drain electrode 20 is provided at n - The back side of the semiconductor region 14 is provided. The source electrode 30 is arranged to face the drain electrode 20 in the Z direction with the semiconductor portion 10 interposed therebetween. The source electrode 30 is electrically insulated from the gate electrode 40 by an interlayer insulating film 70. The drain electrode 20 and the source electrode 30 can be formed using metal such as aluminum, for example. In addition, the interlayer insulating film 70 is, for example, a silicon oxide film (SiO2).

[0034] The gate electrode 40 is opposed to the p-type semiconductor region 13 via a gate insulating film 41. The gate electrode 40 can be formed using polysilicon, for example. In addition, the gate insulating film 41 is, for example, a silicon oxide film (SiO2). In addition, in the present embodiment, the gate electrode 40 is a planar type, but it may also be a trench type.

[0035] The metal silicide layer 50 is disposed on n + In addition, the metal silicide layer 50 is also provided on the p + The metal silicide layer 50 includes nickel silicon (NiSi).

[0036] When forming the metal silicide layer 50, firstly + type semiconductor region 11 and p + A silicon film is formed on the semiconductor region 12. Next, a metal film made of nickel or the like is formed on the silicon film by, for example, sputtering. Then, the silicon and the metal react by annealing treatment or the like to form a metal silicide layer 50. Figure 2 The structure of the metal silicide layer 50 will be described.

[0037] like Figure 2 As shown, the metal silicide layer 50 has a + Type semiconductor region 11, p + The concave portion 51 is recessed on the side of the semiconductor region 12. The concave portion 51 is formed in a groove shape extending continuously along the Y direction. + type semiconductor region 11 and p + In the type semiconductor region 12 , a region in contact with the metal silicide layer 50 is recessed along the shape of the outer peripheral surface of the recess 51 .

[0038] return Figure 1 The metal layer 60 is in contact with the inner side surface and the bottom surface of the above-mentioned recessed portion 51, respectively. That is, the shape of the bottom surface of the metal layer 60 is convex in a manner that it is closely attached to the inner peripheral surface of the recessed portion 51 of the metal silicide 50. In addition, the upper surface of the metal layer 60 is recessed toward the metal silicide 50 side. Therefore, the bottom surface of the source electrode 30 in contact with the metal layer 60 is convex along the recess of the metal layer 60. The metal layer 60 can be formed by evaporating a metal such as titanium.

[0039] Here, refer to Figure 3 and Figure 4 , a comparative example to be compared with the present embodiment will be described.

[0040] Figure 3 It is a cross-sectional view of a semiconductor device of a comparative example cut along a vertical direction. Figure 4 FIG. 1 is a perspective view showing the structure of the main part of a semiconductor device of a comparative example. Figure 3 as well as Figure 4 In the present invention, the same components as those of the semiconductor device 1 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0041] In the semiconductor device 100 of this comparative example, Figure 4 As shown in FIG. 5 , the metal silicide layer 50 is formed in a flat plate shape. Figure 4 As shown, only the upper surface of the metal silicide layer 50 becomes the contact surface with the metal layer 60 .

[0042] In the semiconductor device 100 configured as described above, for example, when a current flows in the reverse direction from the source electrode 30 to the drain electrode 20, in particular, at the p + The p-type semiconductor region 12 concentrates large current. + The semiconductor region 12 generates heat. The generated heat is transferred to the p + A metal silicide layer 50 in contact with the type semiconductor region 12 and a metal layer 60 in contact with the metal silicide layer 50.

[0043] In with p + The metal silicide layer 50 and the metal layer 60 that are in contact with the semiconductor region 12 have different thermal expansion coefficients. Therefore, thermal stress caused by the difference in thermal expansion coefficients is generated at the interface between the metal silicide layer 50 and the metal layer 60. Due to this thermal stress, the adhesion between the metal silicide layer 50 and the metal layer 60 may be reduced. If the adhesion is reduced, it is easy to cause metal peeling, in which the metal layer 60 is peeled off from the metal silicide layer 50, and metal cracking, in which cracks are generated in the metal layer 60.

[0044] Therefore, in this embodiment, etching or the like is performed to n + type semiconductor region 11 or p + The concave portion 51 is formed by sputtering a metal film made of nickel or the like in the semiconductor region 12. In addition, the metal layer 60 is formed in close contact with the inner side surface and the bottom surface of the concave portion 51. As a result, the adhesion between the metal silicide layer 50 and the metal layer 60 is enhanced by the anchoring effect. Therefore, it is not easy to cause metal peeling and metal cracking of the metal layer 60, so the reliability is improved.

[0045] In addition, in the present embodiment, the source electrode 30 includes aluminum. Aluminum is a relatively soft metal. Therefore, the source electrode 30 enters the concave portion 51 side, thereby functioning as a buffer to alleviate the thermal stress caused by the difference in thermal expansion coefficient between the metal silicide layer 50 and the metal layer 60. As a result, metal peeling and metal cracking of the metal layer 60 are less likely to occur, and thus reliability is further improved.

[0046] In the semiconductor device 1 of the present embodiment, when a predetermined voltage is applied between the gate electrode 20 and the source electrode 30, a channel is formed in the p-type semiconductor region 13. As a result, a positive current flows from the drain electrode 20 to the source electrode 30. At this time, if the current value is large, the n + Thermal stress is generated at the interface between the metal silicide layer 50 in contact with the type semiconductor region 11 and the metal layer 60 in contact with the metal silicide layer 50. Therefore, there is a concern that the adhesion between these two layers may be reduced.

[0047] However, in this embodiment, not only +The metal silicide layer 50 is in contact with the n-type semiconductor region 12, and + The metal silicide layer 50 in contact with the n-type semiconductor region 11 also forms a recess 51. Therefore, through the anchor effect, + The adhesion between the metal silicide layer 50 in contact with the p-type semiconductor region 11 and the metal layer 60 in contact with the metal silicide layer 50 is enhanced. + type semiconductor region 12 side, and in n + Metal peeling and metal cracking are also less likely to occur on the semiconductor region 11 side, so the reliability can be further improved.

[0048] (Second Embodiment)

[0049] Figure 5 This is a cross-sectional view of the semiconductor device according to the second embodiment cut along the vertical direction. Figure 6 FIG. 2 is a perspective view showing the structure of the main part of the semiconductor device according to the second embodiment. Figure 5 as well as Figure 6 In the present invention, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

[0050] The shape of the metal silicide layer 50 of the semiconductor device 2 of this embodiment is different from that of the first embodiment. + The first portion 50a connected to the p-type semiconductor region 11 and + The depth from the surface of the semiconductor portion 10 to the lower end of the metal silicide layer 50 is the same between the second portions 50 b that are in contact with the type semiconductor region 12 .

[0051] On the other hand, in the metal silicide layer 50 of the present embodiment, Figure 5 and Figure 6 As shown, the depth from the surface of the semiconductor portion 10 to the lower end of the metal silicide layer 50 is different between the first portion 50a and the second portion 50b. Specifically, the depth d2 of the second portion 50b is greater than the depth d1 of the first portion 50a. As the above-mentioned depth increases, the anchoring effect between the metal silicide layer 50 and the metal layer 60 increases.

[0052] In order to form the metal silicide layer 50 having the first portion 50a and the second portion 50b, in this embodiment, as shown in FIG. Figure 6 As shown, n + The semiconductor region 11 is etched to a depth d1, and the p + The semiconductor region 12 is etched to a depth d2.

[0053] In the semiconductor device 2 of the present embodiment, similarly to the first embodiment, when a current in the opposite direction flows between the drain electrode 20 and the source electrode 30, the current is concentrated on the p + type semiconductor region 12. Therefore, thermal stress may be generated at the interface between the metal silicide layer 50 and the metal layer 60.

[0054] However, in the metal silicide layer 50 of this embodiment, + The depth d2 of the second portion 50b connected to the n-type semiconductor region 12 is greater than that of the n-type semiconductor region 12. + The depth d1 of the first portion 50a in contact with the type semiconductor region 11. Therefore, the anchoring effect of the second portion 50b is higher than that of the first embodiment. Therefore, the adhesion between the metal silicide layer 50 and the metal layer 60 is further enhanced. Therefore, the reliability can be further improved.

[0055] In addition, in the present embodiment, the depth d2 of the second portion 50b is greater than the depth d1 of the first portion 50a, but the depth relationship can also be appropriately changed according to the magnitude of the current. For example, when a large current flows in the forward direction between the drain electrode 20 and the source electrode 30, the adhesion between the first portion 50 and the metal layer 60 is easily reduced.

[0056] In the above case, the depth d1 of the first portion 50a may be greater than the depth d2 of the second portion 50b. This strengthens the adhesion between the first portion 50 and the metal layer 60. Therefore, the reliability can be further improved.

[0057] (Third Embodiment)

[0058] Figure 7 FIG. 1 is a perspective view showing the structure of the main part of the semiconductor device according to the third embodiment. Figure 7 In the embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. Figure 1 The first embodiment shown is the same, so illustration and description are omitted.

[0059] The structure of the metal silicide layer 50 of the semiconductor device 3 of the present embodiment is different from that of the first embodiment. + The first portion 50a connected to the p-type semiconductor region 11 and + The second portions 50b in contact with the type semiconductor region 12 are arranged in a lattice along the X direction and the Y direction. In other words, the first portions 50a and the second portions 50b are alternately arranged intermittently along the X direction and the Y direction.

[0060] The first portion 50a is formed to be n- +The second portion 50b is formed to be concave toward the p-type semiconductor region 11. + The concave shape is recessed on the side of the semiconductor region 12. In addition, the metal layer 60 is buried without a gap along the concave shapes of the first portion 50a and the second portion 50b. Therefore, the adhesion between the metal silicide layer 50 and the metal layer 60 is enhanced by the anchoring effect. Therefore, even if the current flows in the forward and reverse directions between the drain electrode 20 and the source electrode 30, it is not easy to cause the metal layer 60 to peel off or crack.

[0061] Therefore, according to the present embodiment, the reliability can be improved similarly to the first embodiment.

[0062] In addition, in this embodiment, if Figure 7 As shown, n + The type semiconductor region 11 is located between the first portion 50a and the second portion 50b arranged along the Y direction. + The area of ​​the semiconductor region 11 is larger than that of the first embodiment. This can reduce the on-resistance.

[0063] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope or subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

[0064] Description of Reference Numerals

[0065] 1, 2, 3: Semiconductor devices

[0066] 10: Semiconductor Division

[0067] 11:n + Type semiconductor region (first semiconductor region)

[0068] 12: p + Type semiconductor region (second semiconductor region)

[0069] 13: p-type semiconductor region (third semiconductor region)

[0070] 20: Drain electrode (first electrode)

[0071] 30: Source electrode (second electrode)

[0072] 40: Gate electrode

[0073] 50: Metal silicide layer

[0074] 50a: Part I

[0075] 50b: Part 2

[0076] 51: concave part

[0077] 60: Metal layer

Claims

1. A semiconductor device, characterized in that: have: a first electrode; a second electrode, opposite to the first electrode in a first direction; A semiconductor portion disposed between the first electrode and the second electrode; a metal silicide layer disposed between the second electrode and the semiconductor portion; and a metal layer disposed between the metal silicide layer and the second electrode, The metal silicide layer has a recessed portion recessed toward the semiconductor portion. The metal layer is in contact with the bottom surface and the side surface of the concave portion.

2. The semiconductor device according to claim 1, wherein: The semiconductor portion includes a first semiconductor region of a first conductivity type in contact with the metal silicide layer.

3. The semiconductor device according to claim 2, wherein: The semiconductor portion includes a second semiconductor region of a second conductivity type, The metal silicide layer has a first portion in contact with the first semiconductor region and a second portion in contact with the second semiconductor region.

4. The semiconductor device according to claim 3, wherein: The first semiconductor region and the second semiconductor region are arranged side by side along a second direction orthogonal to the first direction.

5. The semiconductor device according to claim 4, wherein: The first semiconductor regions and the second semiconductor regions are alternately arranged adjacent to each other along a third direction that is orthogonal to the first direction and the second direction.

6. The semiconductor device according to claim 5, wherein: The recessed portion is in the shape of a groove extending continuously in the third direction.

7. The semiconductor device according to claim 3, wherein: The depth from the surface of the semiconductor portion to the lower end of the metal silicide layer is different between the first portion and the second portion.

8. The semiconductor device according to claim 5, wherein: The first portion and the second portion are arranged in a lattice shape along the second direction and the third direction.

9. The semiconductor device according to claim 3, wherein: The semiconductor device further comprises: A third semiconductor region of the second conductivity type is in contact with the first semiconductor region and the second semiconductor region; and The gate electrode faces the third semiconductor region via a gate insulating film.

10. The semiconductor device according to claim 1, wherein: The second electrode comprises aluminum, The metal silicide layer comprises nickel silicon, namely NiSi. The metal layer includes titanium.

Images