MEMS device and packaging method thereof

Abstract

The invention relates to an MEMS device and a packaging method thereof, the MEMS device comprises a main body wafer (1) and a substrate wafer (2), the main body wafer (1) comprises an MEMS sensitive structure (11) and a first conductive layer (12), the MEMS sensitive structure (11) comprises a plurality of split parts (111), each split part (111) is provided with a bottom surface (1111), the plurality of bottom surfaces (1111) are flush to form a bottom plane (112) of the MEMS sensitive structure (11), and the first conductive layer (12) is arranged on the substrate wafer (2). The first conductive layer (12) abuts against the bottom plane (112), and the first conductive layer (12) is electrically connected with the substrate wafer (2). According to the technical scheme, the packaging difficulty of the main body wafer and the substrate wafer in the MEMS device provided by the invention is low, and the main body wafer and the substrate wafer are easier to integrate together.

Description

Technical Field

[0001] The present disclosure relates to the technical field of MEMS (micro-electromechanical systems) devices, and in particular, to a MEMS device and a manufacturing method thereof. Background Art

[0002] In the related art, MEMS devices mainly include a main wafer (such as a MEMS chip) and a substrate wafer (such as an ASIC chip). Currently, it is difficult to package the main wafer and the substrate wafer. Summary of the invention

[0003] The purpose of the present disclosure is to provide a MEMS device, in which the packaging difficulty of a main wafer and a substrate wafer is relatively small, and the two are easier to integrate together.

[0004] In order to achieve the above-mentioned purpose, the present disclosure provides a MEMS device, including a main wafer and a substrate wafer, the main wafer including a MEMS sensitive structure and a first conductive layer, the MEMS sensitive structure including a plurality of split parts, the split parts having a bottom surface, the plurality of bottom surfaces are flushly arranged to construct a bottom plane of the MEMS sensitive structure, the first conductive layer abuts against the bottom plane, and the first conductive layer is electrically connected to the substrate wafer.

[0005] Optionally, the main wafer includes a second conductive layer, which is disposed on a side of the first conductive layer close to the substrate wafer, and the second conductive layer electrically connects the first conductive layer and the substrate wafer.

[0006] Optionally, the substrate wafer includes a third conductive layer, the first conductive layer, the second conductive layer and the third conductive layer are stacked in sequence along a first direction, and the second conductive layer is electrically connected to the first conductive layer and the third conductive layer.

[0007] Optionally, the second conductive layer and the third conductive layer are both constructed as metal layers, and the second conductive layer is bonded to the third conductive layer.

[0008] Optionally, the first conductive layer is configured as a polysilicon layer or a metal layer, and the first conductive layer abuts against the second conductive layer.

[0009] Optionally, the first conductive layer includes a plurality of conductors, the conductors having a first section and a second section connected to each other, the first section abutting the section, the second section abutting the second conductive layer, the first section and the second section both having a width in a second direction perpendicular to the first direction, and the width of the second section being greater than the width of the first section.

[0010] Optionally, the first section and the second section are perpendicular to each other.

[0011] Optionally, at least one of the electrical conductors is configured as an L-shaped electrical conductor.

[0012] Optionally, at least one of the conductors is configured as an inverted T-shaped conductor.

[0013] Optionally, the plurality of split parts include a plurality of movable parts, the main wafer includes a first insulating layer arranged on the MEMS sensitive structure, and the first insulating layer forms a first cavity for the movable part to move.

[0014] Optionally, the plurality of split parts include a plurality of fixing parts, the first conductive layer includes a plurality of conductors, and at least one of the conductors extends into the first cavity and abuts against a corresponding fixing part.

[0015] Optionally, the first insulating layer is further formed with a first gap, and the plurality of conductors include a conductor arranged in the first gap.

[0016] Optionally, the main wafer includes a blocking layer and a second insulating layer, the first insulating layer, the blocking layer and the second insulating layer are stacked in sequence in a first direction, the blocking layer is formed with a second notch, the second insulating layer is provided with a third notch arranged in pair with the second notch, and the conductor is arranged in the second notch and the third notch arranged in pair.

[0017] Optionally, the first insulating layer is configured as a silicon dioxide layer, and the barrier layer is configured as a silicon nitride layer.

[0018] Optionally, the second insulating layer is configured as a silicon dioxide layer.

[0019] Optionally, the second insulating layer is further formed with a fourth notch arranged in pair with the third notch, and the second conductive layer is arranged in the fourth notch.

[0020] Optionally, the MEMS device includes a cover wafer, the cover wafer, the main body wafer and the substrate wafer are stacked in sequence in a first direction, and a second cavity for movement of the movable part is formed on the cover wafer.

[0021] Optionally, the main wafer includes a fourth conductive layer, which is arranged on the top surface of the MEMS sensitive structure, and the cover wafer includes a fifth conductive layer, wherein the fourth conductive layer and the fifth conductive layer are both constructed as metal layers, and the fourth conductive layer is bonded to the fifth conductive layer.

[0022] On the basis of the above technical solution, the present disclosure also provides a packaging method for a MEMS device, which is used to package the above MEMS device, and the packaging method includes the following steps: setting a first conductive layer on a wafer substrate; etching the wafer substrate to form a MEMS sensitive structure; molding a substrate wafer; and electrically connecting the first conductive layer to the substrate wafer.

[0023] Optionally, the substrate wafer includes a third conductive layer, and the packaging method includes: providing a second conductive layer abutting against the first conductive layer on the wafer base; and bonding the second conductive layer and the third conductive layer together.

[0024] Optionally, the packaging method includes: setting a first insulating layer on the wafer substrate; setting a first notch on the first insulating layer; making the first conductive layer abut against the MEMS sensitive structure through the first notch; and setting a first cavity on the first insulating layer.

[0025] Optionally, the packaging method includes: disposing a barrier layer on the first insulating layer; forming a second gap on the barrier layer; disposing the first conductive layer in the second gap; and disposing a second insulating layer on the barrier layer.

[0026] Optionally, the packaging method includes: after “etching the wafer substrate to form the MEMS sensitive structure”, etching the first insulating layer so that the first insulating layer forms the first cavity.

[0027] Optionally, the packaging method includes: before “etching the first insulating layer so that the first insulating layer forms the first cavity”, providing a barrier layer on the second insulating layer.

[0028] Optionally, the packaging method includes: forming a fourth gap on the second insulating layer; and disposing a third conductive layer in the fourth gap.

[0029] Optionally, the wafer substrate includes a buried oxide layer, and the packaging method includes: after "bonding the second conductive layer and the third conductive layer together", removing the substrate layer of the wafer substrate outside the buried oxide layer, and removing the buried oxide layer.

[0030] Optionally, the packaging method includes: molding a cover wafer, the cover wafer including a fifth conductive layer; providing a fourth conductive layer on the MEMS sensitive structure; and bonding the fourth conductive layer and the fifth conductive layer together.

[0031] Through the above technical solution, in the MEMS device provided by the present disclosure, the main body wafer includes a MEMS sensitive structure and a first conductive layer, the MEMS sensitive structure includes a plurality of split parts with the bottom surface flushly arranged, the first conductive layer abuts against the bottom surface of the split part and is electrically connected to the substrate wafer at the same time, that is, the first conductive layer and the MEMS sensitive structure are separately arranged, and the first conductive layer and the MEMS sensitive structure are two independent parts. In this way, the present disclosure can reduce the difficulty of etching and forming the MEMS sensitive structure by setting the bottom plane of the MEMS sensitive structure as a plane, and the first conductive layer can be processed separately to reduce the processing restrictions of the etching process on the main body wafer, thereby, while ensuring that the MEMS sensitive structure is electrically connected to the substrate wafer through the first conductive layer, the packaging difficulty of the main body wafer and the substrate wafer can be reduced, so that the main body wafer and the substrate wafer are easier to integrate together. And by setting the bottom plane of the MEMS sensitive structure as a plane, the height of the first conductive layer and the height of the MEMS sensitive structure can also be guaranteed, so that the MEMS sensitive structure has a larger movement space.

[0032] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings: Figure 1 It is a structural schematic diagram of a MEMS device in the related art; Figure 2 is a structural schematic diagram of a MEMS device provided in an embodiment of the present disclosure; Figure 3 is a schematic structural diagram of a main wafer provided by an embodiment of the present disclosure; Figure 4 is a schematic structural diagram of a substrate wafer provided by an embodiment of the present disclosure; Figure 5 is a schematic structural diagram of a cover wafer provided by an embodiment of the present disclosure; Figure 6-25 is a corresponding step diagram of a packaging method for a MEMS device provided in an embodiment of the present disclosure; Fig.26 It is a flowchart of the packaging method of the MEMS device provided in the embodiment of the present disclosure.

[0034] Description of Reference Numerals 1'-main wafer; 11'-MEMS sensitive structure; 12'-bump; 2'-substrate wafer; 1-main wafer; 11-MEMS sensitive structure; 111-divided part; 1111-bottom surface; 112-bottom plane; 113-movable part; 114-fixed part; 12-first conductive layer; 121-conductor; 1211-first subdivision; 1212-second subdivision; 13-second conductive layer; 14-first insulating layer; 141-first cavity; 142-first notch; 15-barrier layer; 151-second notch; 16-second insulating layer; 161-third notch; 162-fourth notch; 17-fourth conductive layer; 18-pin pad; 2-substrate wafer; 21-third conductive layer; 3-cover wafer; 31-second cavity; 32-fifth conductive layer; 100-wafer base; 110-buried oxide layer; 120-substrate layer; 200-silicon wafer. DETAILED DESCRIPTION

[0035] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0036] In the present disclosure, unless otherwise stated, directional words such as "upper" and "lower" generally refer to the relative "upper" and "lower" in the direction of gravity when the corresponding components are in use; "top" and "bottom" generally refer to the "top" and "bottom" in the height direction relative to the corresponding components in use; and "first direction" and "second direction" are based on the Figure 2 The terms "first", "second", etc. used in the present disclosure are intended to distinguish one element from another and do not have order or importance. In addition, in the following description, when referring to the drawings, unless otherwise explained, the same figure numbers in different drawings represent the same or similar elements. The above definitions are only used to explain and illustrate the present disclosure and should not be construed as limitations on the present disclosure.

[0037] In this disclosure, MEMS (Micro-Electro-Mechanical System) devices are an industrial technology that integrates microelectronics technology with mechanical engineering. The internal structure is generally at the micron or even nanometer level. It is an independent intelligent system that focuses on ultra-precision machining and involves many fields such as microelectronics, materials, mechanics, chemistry, and mechanics. SOI (Silicon On Insulator) means that the silicon transistor structure is on top of an insulator. The principle is to add an insulating material between Silicon transistors to reduce the parasitic capacitance between the two by half. CVD (Chemical Vapor Deposition) is a thin film process defined as the deposition of a solid film on a substrate surface due to a gas phase chemical reaction, where the deposited material is usually atoms, molecules, or a combination of the two. PVD (Physical Vapor Deposition) is a thin film process that uses physical methods under vacuum conditions to vaporize the surface of solid or liquid materials into gaseous atoms, molecules or partially ionize them into ions, and deposits a thin film with some special functions on the surface of the substrate through a low-pressure gas (or plasma) process. DIRE (Deep Reactive Ion Etching) is a microelectronic dry etching process. It is the most basic process that can produce directional etching and is a high aspect ratio silicon etching technology based on fluorine-based gases.

[0038] In the related art, reference Figure 1 As shown in the figure, the main wafer 1' includes a MEMS sensitive structure 11', and a protrusion 12' is formed on one side of the MEMS sensitive structure 11' close to the substrate wafer 2', and the main wafer 1' is electrically connected to the substrate wafer 2' through the protrusion 12'. In this way, the protrusion 12' and the MEMS sensitive structure 11' are designed as one body. In the actual production process, the main wafer 1' is usually first etched to form the protrusion 12', and then etched for the second time to form the MEMS sensitive structure 11'. Due to the high aspect ratio in the etching process, the protrusion 12' is limited. The height of the MEMS sensitive structure 11' affects the mechanical movement of the MEMS sensitive structure 11', and due to the setting of the protrusion 12', the etching depth required in the second etching process is relatively large, and the MEMS sensitive structure 11' at the protrusion 12' is difficult to process. As a result, the etching forming of the MEMS sensitive structure 11' is difficult. In addition, since the protrusion 12' usually needs to be bonded to the substrate wafer, the protrusion 12' needs to be designed with a sufficient size to ensure the contact area with the substrate wafer, thereby ensuring the reliability of the bonding, which limits the design space and flexibility of the MEMS sensitive structure 11'.

[0039] In order to solve the above problems, according to the specific implementation methods provided by the present disclosure, reference Figures 2 to 5 As shown in, the present disclosure provides a MEMS device, including a main wafer 1 and a substrate wafer 2, the main wafer 1 includes a MEMS sensitive structure 11 and a first conductive layer 12, the MEMS sensitive structure 11 includes a plurality of split parts 111, the split parts 111 have a bottom surface 1111, the plurality of bottom surfaces 1111 are flushly arranged to construct a bottom plane 112 of the MEMS sensitive structure 11, the first conductive layer 12 abuts against the bottom plane 112, and the first conductive layer 12 is electrically connected to the substrate wafer 2.

[0040] Through the above technical scheme, in the MEMS device provided by the present disclosure, the main wafer 1 includes a MEMS sensitive structure 11 and a first conductive layer 12, the MEMS sensitive structure 11 includes a plurality of split parts 111 flush with the bottom surface 1111, the first conductive layer 12 abuts against the bottom surface 1111 of the split part 111 and is electrically connected to the substrate wafer 2 at the same time, that is, the first conductive layer 12 and the MEMS sensitive structure 11 are separately arranged, and the first conductive layer 12 and the MEMS sensitive structure 11 are two independent components. In this way, the present disclosure can reduce the difficulty of etching the MEMS sensitive structure 11 by setting the bottom plane 112 of the MEMS sensitive structure 11 as a plane, and the first conductive layer 12 can be processed separately to reduce the processing restrictions of the etching process on the main wafer 1, thereby, while ensuring that the MEMS sensitive structure 11 is electrically connected to the substrate wafer 2 through the first conductive layer 12, the packaging difficulty of the main wafer 1 and the substrate wafer 2 can be reduced, so that the main wafer 1 and the substrate wafer 2 are easier to integrate together. Furthermore, by setting the bottom plane 112 of the MEMS sensitive structure 11 as a plane, the height of the first conductive layer 12 can be ensured, so that the MEMS sensitive structure 11 has a larger movement space. In addition, the first conductive layer 12 can also be designed into any suitable shape and size according to actual needs, so as to reduce the area of ​​the bottom surface 1111 of the split part 111 occupied by the first conductive layer 12 as much as possible, while ensuring full contact between the first conductive layer 12 and the substrate wafer 2, reducing the difficulty of packaging the main wafer 1 and the substrate wafer 2, and making it easier to integrate the main wafer 1 and the substrate wafer 2 together.

[0041] In the MEMS device provided in the present disclosure, the main wafer 1 can be electrically connected to the substrate wafer 2 in any suitable manner, and the present disclosure does not impose any specific limitation on this. Figure 2As shown in , the main wafer 1 may include a second conductive layer 13, and the second conductive layer 13 may be arranged on a side of the first conductive layer 12 close to the substrate wafer 2, and the second conductive layer 13 electrically connects the first conductive layer 12 and the substrate wafer 2. Among them, the size of the second conductive layer 13 in the second direction may be larger than the first conductive layer 12, which can improve the reliability of the electrical connection between the second conductive layer 13 and the first conductive layer 12 on the one hand, and the first conductive layer 12 can be electrically connected to the substrate wafer 2 through the second conductive layer 13, which improves the reliability of the electrical connection between the first conductive layer 12 and the substrate wafer 2.

[0042] Based on the above embodiments, as an exemplary embodiment, refer to Figure 2 As shown in , the substrate wafer 2 may include a third conductive layer 21, the first conductive layer 12, the second conductive layer 13 and the third conductive layer 21 may be stacked in sequence along the first direction, and the second conductive layer 13 electrically connects the first conductive layer 12 and the third conductive layer 21. In this way, the arrangement of the first conductive layer 12 and the second conductive layer 13 can facilitate the electrical connection between the main wafer 1 and the substrate wafer 2, wherein the arrangement of the second conductive layer 13 can improve the reliability of the electrical connection between the first conductive layer 12 and the third conductive layer 21. Specifically, one end of the first conductive layer 12 may be connected to the bottom surface 1111 of the split portion 111 of the main wafer 1, and the other end may protrude toward the substrate wafer 2 to facilitate the connection with the second conductive layer 13. The second conductive layer 13 may increase its contact area with the third conductive layer 21 relative to the second conductive layer 13 on the basis of ensuring the electrical connection with the first conductive layer 12, so as to improve the reliability of the conductive connection between the first conductive layer 12 and the third conductive layer 21, thereby improving the reliability of the conductive connection between the main wafer 1 and the substrate wafer 2.

[0043] In some other embodiments, the second conductive layer 13 may not be provided, and the first conductive layer 12 may be directly electrically connected to the third conductive layer 21. For example, the first conductive layer 12 and the third conductive layer 21 are directly abutted together, which can also achieve electrical connection between the main wafer 1 and the substrate wafer 2. The present disclosure does not make any specific restrictions on this.

[0044] In the MEMS device provided in the present disclosure, the first conductive layer 12 and the second conductive layer 13 can be electrically connected to each other in any suitable manner, and the present disclosure does not impose any specific limitation on this. Figure 2 and Figure 4As shown in , the second conductive layer 13 and the third conductive layer 21 can both be constructed as metal layers, and the second conductive layer 13 is bonded to the third conductive layer 21. The second conductive layer 13 and the third conductive layer 21 are both constructed as metal layers. On the one hand, when the second conductive layer 13 and the third conductive layer 21 are in contact, the conductive connection between the two can be achieved. On the other hand, on the basis that the second conductive layer 13 and the third conductive layer 21 are both constructed as metal layers, the bonding connection method can realize the interconnection of electrical signals between the main wafer 1 and the substrate wafer 2 while realizing the electrical connection between the first conductive layer 12 and the second conductive layer 13. Among them, bonding generally includes direct bonding, anodic bonding, eutectic bonding and other methods, and the present disclosure does not make specific restrictions on this.

[0045] In the MEMS device provided in the present disclosure, as an exemplary embodiment, the first conductive layer 12 can be constructed as a polysilicon layer or a metal layer, and the first conductive layer 12 is in contact with the second conductive layer 13. Among them, polysilicon has the properties of both metal and semiconductor, and has good electrical and optical properties, and the polysilicon layer can be deposited on the bottom surface 1111 of the split part 111 by CVD process, so as to facilitate electrical connection with the MEMS sensitive structure 11, and then facilitate the contact between the first conductive layer 12 and the second conductive layer 13. In addition, the first conductive layer can also be constructed as a metal layer, such as Au, Al, W, Mo, Cu, etc., which can also play a conductive role, or the first conductive layer 12 can also be constructed as polysilicon doped with conductive metal, so as to further improve the electrical properties of the first conductive layer 12.

[0046] In the MEMS device provided in the present disclosure, the first conductive layer 12 can be constructed in any suitable form, and the present disclosure does not impose any specific limitation on this. Figure 2 and Figure 3As shown in , the first conductive layer 12 may include a plurality of conductors 121, and the conductor 121 may have a first sub-portion 1211 and a second sub-portion 1212 connected to each other, the first sub-portion 1211 abuts against the split portion 111, and the second sub-portion 1212 abuts against the second conductive layer 13, and the first sub-portion 1211 and the second sub-portion 1212 may both have a width in a second direction perpendicular to the first direction, and the width of the second sub-portion 1212 is greater than the width of the first sub-portion 1211. In other words, the first sub-portion 1211 and the second sub-portion 1212 may be constructed to have different sizes, wherein the first sub-portion 1211 is smaller than the second sub-portion 1212 in the second direction, so as to reduce the area of ​​contact between the conductor 121 and the split portion 111, that is, to reduce the area occupied by the conductor 121 on the bottom surface 1111 of the split portion 111, so as to increase the proportion of the part of the MEMS sensitive structure 11 that can perform mechanical movement, thereby improving the effective design space of the main wafer 1. The second section 1212 is wider than the first section 1211 in the second direction, so as to increase the contact area between the conductor 121 and the second conductive layer 13 , ie, improve the reliability of the conductive connection between the first conductive layer 12 and the second conductive layer 13 .

[0047] The first sub-portion 1211 and the second sub-portion 1212 may be perpendicular to each other. That is, the second sub-portion 1212 may protrude relative to the first sub-portion 1211 in the first direction toward the substrate wafer 2, further facilitating the connection between the conductor 121 and the second conductive layer 13, and facilitating the conductive connection between the first conductive layer 12 and the second conductive layer 13. At the same time, the perpendicular arrangement of the first sub-portion 1211 and the second sub-portion 1212 may also improve the stability of the arrangement of the conductor 121 between the main wafer 1 and the substrate wafer 2.

[0048] In the MEMS device provided in the present disclosure, as an exemplary embodiment, reference is made to Figure 3 As shown in , at least one conductor 121 can be configured as an L-shaped conductor 121. The bottom surface 1111 of the L-shaped conductor 121 abuts against the second conductive layer 13, and the top surface of the L-shaped conductor 121 abuts against the split portion 111, so as to meet the requirements of reducing the area occupied by the conductor 121 on the bottom surface 1111 of the split portion 111 while increasing the contact area between the conductor 121 and the second conductive layer 13.

[0049] In some other embodiments, at least one conductor 121 may also be configured as an inverted T-shaped conductor 121. The bottom surface 1111 of the inverted T-shaped conductor 121 abuts against the second conductive layer 13, and the top surface of the inverted T-shaped conductor 121 abuts against the split portion 111, which can also meet the requirements of reducing the area occupied by the conductor 121 on the bottom surface 1111 of the split portion 111 while increasing the contact area between the conductor 121 and the second conductive layer 13, and the present disclosure does not impose specific restrictions on this.

[0050] In some other embodiments, at least one conductor 121 may also be constructed in a "J" shape, in which case the conductor 121 has a second division 1212 abutting the second conductive layer 13, and two first divisions 1211 abutting the split portion 111, the two first divisions 1211 being perpendicular to the second division 1212, and the ends of the two first divisions 1211 being bent and extended away from each other to further increase the contact area between the first division 1211 and the split portion 111, thereby improving the reliability of the electrical connection between the conductor 121 and the split portion 111.

[0051] In the MEMS device provided in the present disclosure, as an exemplary embodiment, reference is made to Figure 3 As shown in , the multiple split parts 111 may include multiple active parts 113, and the main wafer 1 may include a first insulating layer 14 arranged on the MEMS sensitive structure 11, and the first insulating layer 14 is formed with a first cavity 141 for the active part 113 to move. In this way, the first insulating layer 14 is formed with the first cavity 141, and the split parts 111 can achieve a sealed connection of the substrate wafer 2 in the bottom direction of the MEMS sensitive structure 11 on the one hand, and the setting of the first cavity 141 can provide a movement space for the active part 113 on the other hand.

[0052] In the MEMS device provided in the present disclosure, as an exemplary embodiment, reference is made to Figure 3 As shown in the figure, the multiple split parts 111 may include multiple fixed parts 114, the first conductive layer 12 may include multiple conductors 121, at least one conductor 121 extends into the first cavity 141 and abuts against the corresponding fixed part 114, so that the MEMS sensitive structure 11 realizes a conductive connection with the first conductive layer 12 through the setting of the fixed part 114, and can be fixed to the substrate wafer 2 and conductively connected to the substrate wafer 2 through the cooperation with the second conductive layer 13 and the third conductive layer 21.

[0053] As an exemplary embodiment, reference is made to Figure 3 As shown in , the first insulating layer 14 may also be formed with a first notch 142, and the plurality of conductors 121 may include a conductor 121 disposed in the first notch 142. In this way, the MEMS sensitive structure 11 can pass through the first insulating layer 14 through the conductor 121 to achieve conductive connection with the second conductive layer 13, and further achieve electrical connection with the substrate wafer 2.

[0054] In the MEMS device provided in the present disclosure, as an exemplary embodiment, reference is made to Figure 2As shown in , the main body wafer 1 may also include a barrier layer 15 and a second insulating layer 16. The first insulating layer 14, the barrier layer 15 and the second insulating layer 16 may be stacked in sequence in the first direction. The barrier layer 15 is formed with a second notch 151. The second insulating layer 16 is provided with a third notch 161 arranged in pair with the second notch 151. The conductor 121 is arranged in the second notch 151 and the third notch 161 arranged in pair. The arrangement of the first insulating layer 14, the barrier layer 15 and the third insulating layer can improve the reliability of the connection between the main body wafer 1 and the substrate wafer 2 while further improving the reliability of the sealing of the MEMS sensitive structure 11. The arrangement of the second notch 151 and the third notch 161 can facilitate the conductor 121 to achieve the conductive connection between the MEMS sensitive structure 11 and the second conductive layer 13.

[0055] The first insulating layer 14 can be constructed as a silicon dioxide layer, and the barrier layer 15 can be constructed as a silicon nitride layer. Silicon dioxide has a certain stability and can be used as a temporary support structure to facilitate the formation of MEMS devices, and then removed as the substrate layer 120. Silicon nitride has excellent insulation and stability and is difficult to etch easily. The silicon dioxide layer and the silicon nitride layer can be sequentially deposited on the bottom surface 1111 of the MEMS sensitive structure 11 by a CVD process. Since the first insulating layer 14 needs to form a first cavity 141 by a hydrogen fluoride vapor etching process in the actual production process, the provision of the barrier layer 15 can avoid damage to the second insulating layer 16 in the process.

[0056] The second insulating layer 16 can be constructed as a silicon dioxide layer. In the present disclosure, the first conductive layer 12 protrudes from the barrier layer 15. The second insulating layer 16 can seal the first conductive layer 12 and insulate the conductors 121 from each other. At the same time, the barrier layer 15 can prevent the second insulating layer 16 from being damaged when the first cavity 141 is formed.

[0057] In the MEMS device provided in the present disclosure, as an exemplary embodiment, reference is made to Figure 3 As shown in , the second insulating layer 16 may also be formed with a fourth notch 162 arranged in pair with the third notch 161, and the second conductive layer 13 is arranged in the fourth notch 162. That is, the arrangement of the fourth notch 162 provides an installation space for the second conductive layer 13, and the second conductive layer 13 may be arranged in the fourth notch 162 and the bottom surface 1111 is flush with the second insulating layer 16, so that the second insulating layer 16 can abut against the surface of the substrate wafer 2 to further improve the sealing performance of the MEMS sensitive structure 11.

[0058] In the MEMS device provided in the present disclosure, as an exemplary embodiment, reference is made to Figure 5As shown in , the MEMS device includes a cover wafer 3, and the cover wafer 3, the main body wafer 1 and the substrate wafer 2 are stacked in sequence in the first direction, and a second cavity 31 for the movable part 113 to move is formed on the cover wafer 3. In other words, the cover wafer 3 and the substrate wafer 2 are respectively arranged on the opposite sides of the main body wafer 1 in the first direction to achieve the sealing of the top and bottom of the main body wafer 1. Among them, the setting of the second cavity 31 can provide a movement space for the movable part 113, and the second cavity 31 cooperates with the first cavity 141 to facilitate the movable part 113 to achieve movement in the first direction.

[0059] In the MEMS device provided in the present disclosure, the main body wafer 1 can be electrically connected to the cover wafer 3 in any suitable manner, and the present disclosure does not impose any specific limitation on this. Figure 2 and Figure 5 As shown in , the main body wafer 1 may include a fourth conductive layer 17, and the fourth conductive layer 17 is arranged on the top surface of the MEMS sensitive structure 11, and the cover wafer 3 includes a fifth conductive layer 32, wherein the fourth conductive layer 17 and the fifth conductive layer 32 are both constructed as metal layers, and the fourth conductive layer 17 is bonded to the fifth conductive layer 32. The fourth conductive layer 17 and the fifth conductive layer 32 are both constructed as metal layers. On the one hand, the conductive connection between the fourth conductive layer 17 and the fifth conductive layer 32 can be achieved when they are in contact. On the other hand, on the basis that the fourth conductive layer 17 and the fifth conductive layer 32 are both constructed as metal layers, the bonding connection method can realize the interconnection of electrical signals between the main body wafer 1 and the cover wafer 3 while realizing the electrical connection between the fourth conductive layer 17 and the fifth conductive layer 32. The bonding generally includes multiple methods such as direct bonding, anodic bonding, eutectic bonding, etc., and the present disclosure does not make specific restrictions on this.

[0060] Based on the above technical solution, Fig.26 As shown in , the present disclosure also provides a packaging method for a MEMS device, which is used to package the above-mentioned MEMS device, and the packaging method includes the following steps: arranging a first conductive layer 12 on a wafer substrate 100; etching the wafer substrate 100 to form a MEMS sensitive structure 11; molding a substrate wafer 2; and electrically connecting the first conductive layer 12 to the substrate wafer 2. Through the above method, reference Figure 6 As shown in FIG. 1 , a wafer substrate 100 may be provided. Fig.11 As shown in FIG. 1 , a first conductive layer 12 is provided on a wafer substrate 100, and then a substrate wafer 2 is formed. Fig.15 As shown in FIG. 1 , the first conductive layer 12 is electrically connected to the substrate wafer 2, referring to Fig.19As shown in the figure, the wafer substrate 100 is etched to form a MEMS sensitive structure 11, wherein the first conductive layer 12 can be processed separately to reduce the processing restrictions of the etching process on the MEMS sensitive structure 11, and the difficulty of etching the MEMS sensitive structure 11 can be reduced by setting the bottom plane 112 of the MEMS sensitive structure 11 as a plane, and the first conductive layer 12 can be processed separately to reduce the processing restrictions of the etching process on the main wafer 1. Therefore, while ensuring that the MEMS sensitive structure 11 is electrically connected to the substrate wafer 2 through the first conductive layer 12, the packaging difficulty of the main wafer 1 and the substrate wafer 2 is reduced, making it easier to integrate the main wafer 1 and the substrate wafer 2 together.

[0061] The wafer substrate 100 may be an SOI wafer having a buried oxide layer 110 (see Figure 6 As shown in ), so as to facilitate thinning of the SOI wafer in subsequent processing. In some other embodiments, the wafer substrate 100 can also be an ordinary silicon wafer, and the present disclosure does not make any specific limitation on this.

[0062] It should be noted that the packaging method of the MEMS device provided in the present disclosure can change the order of the steps of the above method in any suitable order based on the above embodiments, and the present disclosure does not impose any specific limitation on this.

[0063] In the packaging method of the MEMS device provided in the present disclosure, the substrate wafer 2 may include a third conductive layer 21, and the packaging method includes: arranging a second conductive layer 13 abutting against the first conductive layer 12 on the wafer base 100; bonding the second conductive layer 13 and the third conductive layer 21 together. Fig.14 As shown in FIG. 1 , the second conductive layer 13 can be deposited on the first conductive layer 12 by a PVD process. Fig.15 As shown in FIG. 1 , the first conductive layer 12 and the second conductive layer 13 are bonded.

[0064] The packaging method of the MEMS device provided in the present disclosure includes: providing a first insulating layer 14 on a wafer substrate 100; providing a first notch 142 on the first insulating layer 14; making the first conductive layer 12 abut against the MEMS sensitive structure 11 through the first notch 142; and providing a first cavity 141 on the first insulating layer 14. Figure 7 As shown in FIG. 1 , a first insulating layer 14 is deposited on top of the wafer substrate 100 by a CVD process. Fig. 9 As shown in , the first insulating layer 14 can be etched by a DRIE process to form a first notch 142 on the first insulating layer 14; Fig.10 As shown in FIG. 1 , the first conductive layer 12 is deposited by a CVD process, and the first conductive layer 12 abuts against the MEMS sensitive structure 11 through the first notch 142. Fig. 20 As shown in , a first cavity 141 can be formed on the first insulating layer 14 by a hydrogen fluoride vapor etching process. The first insulating layer 14 is a silicon dioxide layer.

[0065] The packaging method of the MEMS device provided in the present disclosure includes: arranging a barrier layer 15 on the first insulating layer 14; forming a second notch 151 on the barrier layer 15; arranging the first conductive layer 12 in the second notch 151; and arranging a second insulating layer 16 on the barrier layer 15. Figure 8 As shown in FIG. 1 , a barrier layer 15 is deposited on the first insulating layer 14 by a CVD process. Fig. 9 As shown in , the barrier layer 15 is etched by a DRIE process to form a second notch 151 on the barrier layer 15; Fig.12 As shown in FIG, a second insulating layer 16 is deposited on the barrier layer 15 by a CVD process. The barrier layer 15 is a silicon nitride layer, and the second insulating layer 16 is a silicon dioxide layer.

[0066] The packaging method of the MEMS device provided in the present disclosure includes: after “etching the wafer substrate 100 to form the MEMS sensitive structure 11”, etching the first insulating layer 14 to form a first cavity 141 in the first insulating layer 14. Fig. 20 As shown in FIG. 1 , a first cavity 141 is formed on the first insulating layer 14 by a hydrogen fluoride vapor etching process.

[0067] The packaging method of the MEMS device provided in the present disclosure includes: before "etching the first insulating layer 14 to form the first cavity 141 in the first insulating layer 14", a barrier layer 15 is provided on the second insulating layer 16. By the above method, reference Figure 8 As shown in FIG. 1 , a barrier layer 15 is deposited on the first insulating layer 14 by a CVD process. Fig.12 As shown in FIG. 1 , a second insulating layer 16 is deposited on the barrier layer 15 by a CVD process, referring to Fig.17 As shown in FIG. , the MEMS device is flipped over and referenced Fig. 20 As shown in FIG. 1 , the first insulating layer 14 is etched by a hydrogen fluoride vapor etching process. Thus, the barrier layer 15 can be used to prevent the hydrogen fluoride vapor from damaging the second insulating layer 16 .

[0068] The packaging method of the MEMS device provided in the present disclosure includes: forming a fourth notch 162 on the second insulating layer 16; and arranging a second conductive layer 13 in the fourth notch 162. Fig.13 As shown in FIG. 1 , the second insulating layer 16 is etched by RIE process to form a fourth notch 162 on the second insulating layer 16. Fig.14As shown in , the second conductive layer 13 is deposited on the second insulating layer 16 by a PVD process, and the second conductive layer 13 fills the fourth gap 162 .

[0069] In the packaging method of the MEMS device provided in the present disclosure, the wafer substrate 100 may include a buried oxide layer 110, and the packaging method includes: after "bonding the second conductive layer 13 and the third conductive layer 21 together", removing the substrate layer 120 of the wafer substrate 100 outside the buried oxide layer 110, and removing the buried oxide layer 110. Through the above technical method, reference Fig.16 As shown in FIG. 1 , the side of the wafer base 100 away from the substrate wafer 2 is thinned by a grinding and polishing process until the substrate layer 120 and the buried oxide layer 110 are removed.

[0070] The buried oxide layer 110 is used as the substrate layer 120 to limit the thinning range of the wafer substrate 100 .

[0071] The packaging method of the MEMS device provided in the present disclosure includes: molding a cover wafer 3, the cover wafer 3 includes a fifth conductive layer 32; arranging a fourth conductive layer 17 on the MEMS sensitive structure 11; and bonding the fourth conductive layer 17 and the fifth conductive layer 32 together. Fig.25 As shown in FIG. 1 , a cover wafer 3 is provided, and the cover wafer 3 includes a fifth conductive layer 32, referring to FIG. Fig.18 As shown in FIG. 1 , a fourth conductive layer 17 and a pin pad 18 are deposited on the MEMS sensitive structure 11 by a PVD process, referring to FIG. Fig.21 As shown in FIG. 1 , the fourth conductive layer 17 is bonded to the fifth conductive layer 32 to achieve conductive connection between the cover wafer 3 and the MEMS sensitive structure 11, referring to FIG. Fig. 22 As shown in , the portion of the cover wafer 3 corresponding to the pin pad 18 is cut to expose the pin pad 18 .

[0072] The molding method of the cover wafer 3 includes: referring to Fig.23 As shown in the figure, silicon wafer is provided, reference Fig.24 As shown in FIG. 1 , a fifth conductive layer 32 is deposited on one side of the cover wafer 3 by a PVD process, and a photoresist pattern is made on the fifth conductive layer 32 by a photolithography process. Fig.25 As shown in FIG. 1 , a DRIE process is used to etch the side of the cover wafer 3 where the fifth conductive layer 32 is provided, while avoiding the fifth conductive layer 32 , to form a second cavity 31 .

[0073] In summary, in the packaging method provided in the present disclosure, as an exemplary embodiment, the process flow of MEMS device packaging is as follows: the first step is to refer to Figure 6 As shown in FIG. 1 , a wafer substrate 100 is provided, and the wafer substrate 100 includes a buried oxide layer 110; in the second step, referring to Figure 7As shown in FIG. 1 , a first insulating layer 14 is formed on the top of the wafer substrate 100 by a thermal oxidation process; in the third step, referring to Figure 8 As shown in FIG. 1 , a barrier layer 15 is deposited on the surface of the first insulating layer 14 by a CVD process; in the fourth step, referring to Fig. 9 As shown in FIG, the first insulating layer 14 and the barrier layer 15 are etched by a DRIE process to form a first notch 142 and a second notch 151, respectively; in the fifth step, referring to Fig.10 As shown in FIG. 1 , a conductive layer is deposited on the surface of the barrier layer 15 by a CVD process, and the conductive layer fills the first gap 142 and the second gap 151; Step 6, referring to Fig.11 As shown in FIG. 1 , the conductive layer is etched by RIE process to form a plurality of mutually isolated conductive bodies 121; Step 7, referring to Fig.12 As shown in FIG. 1 , a second insulating layer 16 is deposited on the surface of the barrier layer 15 by a CVD process, and the second insulating layer 16 covers the surface of the conductor 121; in the eighth step, referring to Fig.13 As shown in FIG. 1 , the second insulating layer 16 is etched by RIE process to form a fourth notch 162, at which time the conductor 121 is exposed through the third notch 161; step 9, referring to Fig.14 As shown in FIG. 1 , a second conductive layer 13 is deposited in the third gap 161 by a PVD process, and the second conductive layer 13 is electrically connected to the conductor 121; Step 10, referring to Fig.15 As shown in , a substrate wafer 2 is provided, and the substrate wafer 2 is provided with a third conductive layer 21, and the second conductive layer 13 and the third conductive layer 21 are bonded; in the eleventh step, refer to Fig.16 As shown in , the wafer substrate 100 is polished to remove the buried oxide layer 110 to thin the wafer substrate 100; the twelfth step, referring to Fig.17 As shown in the figure, turn the entire MEMS device upside down; Step 13, refer to Fig.18 As shown in FIG. 1 , a fourth conductive layer 17 and a pin pad 18 are deposited on the wafer substrate 100 by a PVD process; Step 14, referring to Fig.19 As shown in FIG. 1 , the wafer substrate 100 is etched by a DRIE process to form a MEMS sensitive structure 11; step 15, referring to Fig. 20 As shown in FIG. 1 , the first insulating layer 14 is etched by a hydrogen fluoride vapor etching process to form a first cavity 141; step 16, referring to Fig.21 As shown in , a cover wafer 3 is provided, the cover wafer 3 is provided with a fifth conductive layer 32, and the fourth conductive layer 17 and the fifth conductive layer 32 are bonded; Step 17, reference Fig. 22 As shown in , the cover wafer 3 is cut to expose the pin pad 18, and the MEMS device is packaged by the above packaging method.

[0074] It should be noted here that the processes used in the above-mentioned packaging method, such as PVD process, CVD process, DRIE process, etc., can be replaced by any suitable process known in the relevant technology. For example, the DRIE process can be replaced by the RIE process. The present disclosure does not make any specific restrictions on this.

[0075] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0076] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.

[0077] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.

Claims

1. A MEMS device, characterized in that: It includes a main wafer and a substrate wafer, the main wafer includes a MEMS sensitive structure and a first conductive layer, the MEMS sensitive structure includes a plurality of split parts, the split parts have a bottom surface, and the plurality of bottom surfaces are flushly arranged to construct a bottom plane of the MEMS sensitive structure, the first conductive layer abuts against the bottom plane, and the first conductive layer is electrically connected to the substrate wafer.

2. The MEMS device according to claim 1, characterized in that: The main wafer includes a second conductive layer, which is disposed on a side of the first conductive layer close to the substrate wafer, and the second conductive layer electrically connects the first conductive layer and the substrate wafer.

3. The MEMS device according to claim 2, characterized in that: The substrate wafer includes a third conductive layer, the first conductive layer, the second conductive layer and the third conductive layer are stacked in sequence along a first direction, and the second conductive layer is electrically connected to the first conductive layer and the third conductive layer.

4. The MEMS device according to claim 3, characterized in that: The second conductive layer and the third conductive layer are both configured as metal layers, and the second conductive layer is bonded to the third conductive layer.

5. The MEMS device according to claim 4, characterized in that: The first conductive layer is configured as a polysilicon layer or a metal layer, and the first conductive layer abuts against the second conductive layer.

6. The MEMS device according to any one of claims 2 to 5, characterized in that: The first conductive layer includes a plurality of conductors, each of which has a first section and a second section connected to each other, the first section abuts against the section, the second section abuts against the second conductive layer, the first section and the second section both have a width in a second direction perpendicular to the first direction, and the width of the second section is greater than the width of the first section.

7. The MEMS device according to claim 6, characterized in that: The first section and the second section are perpendicular to each other.

8. The MEMS device according to claim 7, characterized in that: At least one of the electrical conductors is configured as an L-shaped electrical conductor.

9. The MEMS device according to claim 7, characterized in that: At least one of the conductors is configured as an inverted T-shaped conductor.

10. The MEMS device according to any one of claims 1 to 5, characterized in that: The plurality of split parts include a plurality of movable parts, the main wafer includes a first insulating layer arranged on the MEMS sensitive structure, and the first insulating layer forms a first cavity for the movable part to move.

11. The MEMS device according to claim 10, characterized in that: The plurality of split parts include a plurality of fixing parts, the first conductive layer includes a plurality of conductors, at least one of the conductors extends into the first cavity and abuts against the corresponding fixing part.

12. The MEMS device according to claim 11, characterized in that: The first insulating layer is further formed with a first gap, and the plurality of conductors include a conductor disposed in the first gap.

13. The MEMS device according to claim 11, characterized in that: The main wafer includes a blocking layer and a second insulating layer, the first insulating layer, the blocking layer and the second insulating layer are stacked in sequence in a first direction, the blocking layer is formed with a second notch, the second insulating layer is provided with a third notch arranged in pair with the second notch, and the conductor is arranged in the second notch and the third notch arranged in pair.

14. The MEMS device according to claim 13, characterized in that: The first insulating layer is configured as a silicon dioxide layer, and the barrier layer is configured as a silicon nitride layer.

15. The MEMS device according to claim 14, characterized in that: The second insulating layer is configured as a silicon dioxide layer.

16. The MEMS device according to claim 13, characterized in that: The second insulating layer is further formed with a fourth notch arranged in pair with the third notch, and the second conductive layer is arranged in the fourth notch.

17. The MEMS device according to claim 10, characterized in that: The MEMS device comprises a cover wafer. The cover wafer, the main body wafer and the substrate wafer are stacked in sequence in a first direction. A second cavity for the movable part to move is formed on the cover wafer.

18. The MEMS device according to claim 17, characterized in that: The main wafer includes a fourth conductive layer, which is arranged on the top surface of the MEMS sensitive structure. The cover wafer includes a fifth conductive layer, wherein the fourth conductive layer and the fifth conductive layer are both constructed as metal layers, and the fourth conductive layer is bonded to the fifth conductive layer.

19. A packaging method for a MEMS device, characterized in that: The packaging method is used to package the MEMS device according to any one of claims 1 to 18, and the packaging method comprises the following steps: Disposing a first conductive layer on the wafer substrate; Etching the wafer substrate to form a MEMS sensitive structure; forming substrate wafers; The first conductive layer is electrically connected to the substrate wafer.

20. The packaging method of a MEMS device according to claim 19, characterized in that: The substrate wafer includes a third conductive layer, and the packaging method includes: Disposing a second conductive layer on the wafer substrate in contact with the first conductive layer; The second conductive layer and the third conductive layer are bonded together.

21. The packaging method of a MEMS device according to claim 19 or 20, characterized in that: The packaging method comprises: Disposing a first insulating layer on the wafer substrate; A first notch is provided on the first insulating layer; and the first conductive layer is brought into contact with the MEMS sensitive structure through the first notch; A first cavity is disposed on the first insulating layer.

22. The packaging method of a MEMS device according to claim 21, characterized in that: The packaging method comprises: Disposing a barrier layer on the first insulating layer; forming a second notch on the barrier layer; and disposing the first conductive layer in the second notch; A second insulating layer is disposed on the barrier layer.

23. The packaging method of a MEMS device according to claim 22, characterized in that: The packaging method comprises: after “etching the wafer substrate to form a MEMS sensitive structure”, etching the first insulating layer so that the first insulating layer forms the first cavity.

24. The packaging method of a MEMS device according to claim 23, characterized in that: The packaging method comprises: before "etching the first insulating layer so that the first insulating layer forms the first cavity wafer substrate MEMS sensitive structure", setting a barrier layer on the second insulating layer.

25. The packaging method of a MEMS device according to claim 22, characterized in that: The packaging method comprises: forming a fourth notch on the second insulating layer; A second conductive layer is disposed in the fourth gap.

26. The packaging method of a MEMS device according to claim 20, characterized in that: The wafer substrate includes a buried oxide layer, and the packaging method includes: After "bonding the second conductive layer and the third conductive layer together", the substrate layer of the wafer base outside the buried oxide layer is removed, and the buried oxide layer is removed.

27. The packaging method of a MEMS device according to claim 20, characterized in that: The packaging method comprises: forming a cover wafer, wherein the cover wafer comprises a fifth conductive layer; Disposing a fourth conductive layer on the MEMS sensitive structure; The fourth conductive layer and the fifth conductive layer are bonded together.

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