Conductive structure preparation method, conductive structure and micro electro mechanical system

Abstract

The invention provides a conductive structure preparation method, a conductive structure and a micro electro mechanical system, and relates to the technical field of semiconductors. At least two crystalline metal layers are sequentially sputtered on the side, away from the substrate layer, of the amorphous adhesion layer at different pre-configured sputtering powers, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is smaller than a set first size threshold value, the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than a set second size threshold; metal wires arranged in an array mode are formed on the side, away from the substrate layer, of the crystalline metal layer farthest from the amorphous adhesion layer, and the grain sizes of the metal wires are larger and larger from the side close to the crystalline metal layer to the side away from the crystalline metal layer. And the grain size of one side, close to the crystalline metal layer, of the metal wire is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer, so that the metal wire is not easy to fall off from the substrate layer, and the reliability is high.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a conductive structure, a conductive structure and a micro-electromechanical system. Background Art

[0002] Micro-Electro-Mechanical System (MEMS) is a micro device that combines electrical and mechanical properties, with the advantages of small size, low power consumption, good performance, and good compatibility with IC manufacturing processes. Metals can be used to prepare conductive structures in MEMS due to their good conductivity and chemical stability.

[0003] Generally, the conductive structure includes a base layer, a crystalline metal layer disposed on one side of the amorphous adhesive layer, and an array of metal wires disposed on one side of the crystalline metal layer. In the current conductive structure, the metal wires are easily separated from the base layer and the amorphous adhesive layer, causing damage to the MEMS, thereby affecting the use of the MEMS. Summary of the invention

[0004] The present application provides a conductive structure preparation method, a conductive structure and a micro-electromechanical system, which are used to solve the problem in the prior art that metal wires are easily detached from a base layer and an amorphous adhesion layer, causing damage to the micro-electromechanical system.

[0005] In a first aspect, the present application provides a method for preparing a conductive structure, comprising:

[0006] sputtering an amorphous adhesion layer on one side of the substrate layer;

[0007] At least two crystalline metal layers are sequentially sputtered on a side of the amorphous adhesion layer away from the base layer with different pre-configured sputtering powers, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is smaller than a set first size threshold, and the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is larger than a set second size threshold, and the second size threshold is larger than the first size threshold, wherein each sputtering power is used to sputter one crystalline metal layer;

[0008] On a side of the crystalline metal layer farthest from the amorphous adhesion layer and away from the base layer, an array of metal wires is formed, wherein the grain size of the metal wire increases from the side close to the crystalline metal layer to the side far from the crystalline metal layer, and the grain size of the metal wire on the side close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer;

[0009] The portions of the orthographic projections of the amorphous adhesion layer and the at least two crystalline metal layers on the base layer that do not overlap with the orthographic projections of the metal wires on the base layer are removed.

[0010] In a possible implementation manner, the sputtering power of the amorphous adhesion layer ranges from 500 W to 40 kW, and the sputtering power of each sputtering of the crystalline metal layer ranges from 100 W to 10 kW.

[0011] In one possible implementation, the crystalline metal layer includes two layers.

[0012] The sputtering power of the amorphous adhesion layer is 25kW, the power of the first sputtering of the crystalline metal layer is 2KW, and the power of the second sputtering of the crystalline metal layer is 1KW;

[0013] Alternatively, the sputtering power of the amorphous adhesion layer is 1 kW, the power of the first sputtering of the crystalline metal layer is 10 kW, and the power of the second sputtering of the crystalline metal layer is 100 W;

[0014] Alternatively, the sputtering power of the amorphous adhesion layer is 40 kW, the power of the first sputtering of the crystalline metal layer is 100 W, and the power of the second sputtering of the crystalline metal layer is 10 kW;

[0015] Alternatively, the sputtering power of the amorphous adhesion layer is 20 kW, the power of the first sputtering of the crystalline metal layer is 5 kW, and the power of the second sputtering of the crystalline metal layer is 500W.

[0016] In a possible implementation manner, the second size threshold is set in a range of 25 nm-50 nm.

[0017] In one possible embodiment, when sputtering the amorphous adhesion layer and at least two crystalline metal layers, the pressure range of the sputtering reactor is 5×10 -9 mTorr~5×10 -5 mTorr.

[0018] In a possible implementation manner, the thickness of the amorphous adhesion layer is in a range of 2 nm to 50 nm, and the total thickness of the at least two crystalline metal layers is in a range of 50 nm to 500 nm.

[0019] In a possible implementation, removing a portion that does not overlap with the orthographic projection of the amorphous adhesion layer and the at least two crystalline metal layers on the base layer and the orthographic projection of the metal wire on the base layer includes:

[0020] Ion beam etching is used to remove the portion where the orthographic projections of the amorphous adhesion layer and at least two crystalline metal layers on the base layer do not overlap with the orthographic projections of the metal wires on the base layer.

[0021] In a possible implementation, an array of metal wires is formed on a side of the crystalline metal layer farthest from the amorphous adhesion layer and away from the base layer, including:

[0022] Forming an array of spaced photoresists on a side of the crystalline metal layer farthest from the amorphous adhesion layer away from the base layer to form an electroplating pattern;

[0023] Electroplating a metal conductor in an exposed area between each two adjacent photoresists;

[0024] A scrubber is used to remove the photoresist arranged in an array to form metal wires arranged in an array.

[0025] In a second aspect, the present application provides a conductive structure, which is prepared using the conductive structure preparation method provided in the first aspect of the present application.

[0026] In a third aspect, the present application further provides a micro-electromechanical system, comprising a plurality of conductive elements, wherein the conductive elements are electrically connected to each other using the conductive structure provided in the second aspect of the present application.

[0027] The present application provides a method for preparing a conductive structure, a conductive structure and a micro-electromechanical system, wherein at least two crystalline metal layers are sequentially sputtered on a side of an amorphous adhesion layer away from a base layer with different pre-configured sputtering powers, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is smaller than a set first size threshold. In this way, the crystalline metal layer closest to the amorphous adhesion layer can be better connected with the amorphous adhesion layer, so that the metal wires subsequently grown on the at least two crystalline metal layers are not easily detached from the amorphous adhesion layer.

[0028] In addition, on the side of the crystalline metal layer farthest from the amorphous adhesion layer and far away from the base layer, an array of metal wires is formed. Since the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than the set second size threshold, the grain size of the metal wire on the side close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer, and the grain size of the metal wire increases from the side close to the crystalline metal layer to the side far away from the crystalline metal layer. In this way, the grain size of at least two crystalline metal layers can be larger as a whole. According to the Hall-Petch law, the larger the grain size, the lower the hardness. It can be seen that the metal wire has a lower hardness as a whole. When the metal wire with lower hardness is formed, the impact force on at least two crystalline metal layers, the amorphous adhesion layer, and the base layer is smaller, so it is not easy to destroy the connection between the base layer and the amorphous adhesion layer, so that the metal wire is not easy to fall off from the base layer, thereby improving the product quality and service life of the micro-electromechanical system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0030] Figure 1 A flowchart of the steps of the method for preparing a conductive structure provided in an embodiment of the present application;

[0031] Figure 2 A process flow chart of a method for preparing a conductive structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0033] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0034] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0035] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0036] See also Figure 1 and Figure 2 , the present application embodiment provides a method for preparing a conductive structure, comprising:

[0037] S101 : sputtering an amorphous adhesion layer 202 on one side of the base layer 201 .

[0038] Among them, the process of S101 is as follows Figure 2 As shown in (a)-(b) in the figure; the sputtering method can be but not limited to magnetron sputtering. The material of the base layer 201 can be but not limited to single crystal Si wafer or SiO2 wafer; the material of the amorphous adhesion layer 202 can include Ti or Cr.

[0039] S102: At least two crystalline metal layers 203 are sputtered in sequence on the side of the amorphous adhesion layer 202 away from the base layer 201 with different pre-configured sputtering powers, so that the grain size of the crystalline metal layer 203 closest to the amorphous adhesion layer 202 is smaller than a set first size threshold, and the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 is larger than a set second size threshold.

[0040] The second size threshold is greater than the first size threshold, and each sputtering power is used to sputter a layer of crystalline metal layer 203 .

[0041] Among them, the process of S101 is as follows Figure 2 As shown in (b)-(c) in FIG. 2 . The material of the crystalline metal layer 203 may be, but is not limited to, metal Au. The crystalline metal layer 203 may be 2 layers, 3 layers, or 4 layers, etc. ( Figure 2 There are 2 layers in the middle).

[0042] Further, the sputtering power of the amorphous adhesion layer 202 ranges from 500W to 40kW. For example, the sputtering power of the amorphous adhesion layer 202 may be, but is not limited to, 25kw, 1kw, 20kw, or 40kw. The sputtering power of each sputtering of the crystalline metal layer 203 ranges from 100W to 10kW, and the sputtering power of the sputtering of the crystalline metal layer 203 may be, but is not limited to, 100W, 500W, 1kw, 2kw, 5kw, or 10kw. When the sputtering power of the sputtering of the crystalline metal layer 203 ranges from 100W to 10kW, different sputtering powers may be selected between 100W and 10kW, so that the grain size of the crystalline metal layer 203 closest to the amorphous adhesion layer 202 is smaller than the set first size threshold, and the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 is larger than the set second size threshold. The second size threshold may be set in the range of 25nm-50nm. For example, the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 may be, but is not limited to, 25nm, 37.9nm, 41.8nm, 45.9nm, and 39.3nm.

[0043] It should be noted that the method of sputtering at least two crystalline metal layers 203 may also be magnetron sputtering; the combination of the amorphous adhesion layer 202 and the at least two crystalline metal layers 203 may be called a metal seed layer.

[0044] In addition, when sputtering the amorphous adhesion layer 202 and the at least two crystalline metal layers 203, the pressure range of the sputtering reactor is 5×10 -9 mTorr~5×10 -5 mTorr, for example, the pressure of the sputtering reactor can be 2×10- 6 mTorr, 5×10 -5 mTorr, or 5×10 -9 mTorr.

[0045] In addition, the thickness of the amorphous adhesion layer 202 is in the range of 2nm to 50nm, for example, the thickness of the amorphous adhesion layer 202 is 2nm, 10nm or 50nm; the total thickness of the at least two crystalline metal layers 203 is in the range of 50nm to 500nm. For example, the total thickness of the at least two crystalline metal layers 203 is in the range of 50nm, 200nm or 500nm, which is not limited here. It can be understood that the thickness of the sputtered amorphous adhesion layer 202 and the thickness of the at least two crystalline metal layers 203 can be controlled by controlling the sputtering time of the amorphous adhesion layer 202 and the at least two crystalline metal layers 203, respectively. The longer the sputtering time, the greater the thickness of the amorphous adhesion layer 202 and the thickness of the at least two crystalline metal layers 203.

[0046] S103 : forming an array of metal wires 205 on a side of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 and away from the base layer 201 .

[0047] The grain size of the metal wire 205 increases from the side close to the crystalline metal layer 203 to the side far away from the crystalline metal layer 203 , and the grain size of the metal wire 205 close to the crystalline metal layer 203 is equal to the grain size of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 .

[0048] It can be understood that, since the grain size of the metal wire 205 increases from the side close to the crystalline metal layer 203 to the side away from the crystalline metal layer 203, the grain size of the metal wire 205 on the side away from the crystalline metal layer 203 is larger. For example, the grain size of the metal wire 205 on the side away from the crystalline metal layer 203 may be, but is not limited to, 56.9 nm, 63.1 nm, 67.1 nm, or 75.7 nm.

[0049] Exemplarily, S103 may be specifically implemented as follows:

[0050] Step 1: forming an array of spaced photoresists 204 on a side of the crystalline metal layer 203 farthest from the amorphous adhesion layer 202 and away from the base layer 201 to form an electroplating pattern.

[0051] Wherein, the process of step 1 is as follows Figure 2 As shown in (c)-(d) in .

[0052] Step 2: Electroplating a metal wire 205 in the exposed area between each two adjacent photoresists 204 .

[0053] Wherein, the process of step 2 is as follows Figure 2 Specifically, a direct current electroplating method can be used to electroplate the metal wire 205 in the exposure area between each two adjacent photoresists 204 .

[0054] Step 3: Use a scrubber to remove the photoresist 204 arranged in an array to form metal wires 205 arranged in an array.

[0055] S104 : removing the portion that does not overlap with the orthographic projection of the amorphous adhesion layer 202 and the at least two crystalline metal layers 203 on the base layer 201 and the orthographic projection of the metal wire 205 on the base layer 201 .

[0056] Specifically, ion beam etching may be used to remove portions of the non-overlapping orthographic projections of the amorphous adhesion layer 202 and the at least two crystalline metal layers 203 on the base layer 201 and the orthographic projections of the metal wires 205 on the base layer 201 .

[0057] Among them, the process of step 3-S104 is as follows Figure 2 As shown in (e)-(f) in the figure.

[0058] According to experiments conducted by the inventors, the grain size of the second crystalline metal layer 203 of the conductive structure obtained in the process flow of the previous related art is 24.1 nm; the grain size of the metal wire 205 is 46.6 nm, and the scratch depth of the metal wire 205 is 4793 nm.

[0059] Four specific examples are used below to illustrate the method for preparing the conductive structure of the embodiment of the present application.

[0060] Embodiment 1:

[0061] Use 6 inches <110> A silicon wafer of 655±10 μm thick (i.e., substrate layer 201) is prepared by magnetron sputtering. A 10 nm amorphous Cr layer (i.e., amorphous adhesion layer 202) is first deposited on the silicon wafer at a power of 20 kW. Then, a 150 nm crystalline Au layer (i.e., first crystalline metal layer 203) is deposited at a power of 5 kW. Subsequently, a 50 nm crystalline Au layer (i.e., second crystalline metal layer 203) is deposited at a power of 500 W. During the deposition, the pressure in the reactor chamber is 5×10 -9 mTorr, a photoresist 204 layer arranged in an array is made on the second crystalline metal layer 203 using a photolithography process, a gold layer is electroplated in the exposure area using a direct current electroplating method, a scrubber is used to remove the residual photoresist 204, and the excess metal seed layer is removed by ion beam etching to obtain a conductive structure 1. After testing, the grain size of the second crystalline metal layer 203 of the conductive structure 1 is 39.3nm; the grain size of the metal wire 205 is 63.1nm, and the scratch depth of the metal wire 205 is 6560nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. The overall hardness of the metal wire 205 is lower. When the metal wire 205 with lower hardness is formed, the impact force on the amorphous adhesion layer 202, the crystalline metal layers 203 on both sides and the base layer 201 is smaller. In this way, it is not easy to destroy the connection between the base layer 201 and the amorphous adhesion layer 202, so that the base layer 201 is not easy to fall off from the amorphous adhesion layer 202, thereby improving the product quality and service life of the micro-electromechanical system.

[0062] Embodiment 2:

[0063] Use 8 inches <110> A 1 μm thick SiO2 film is grown on the SiO2 film by chemical vapor deposition (CVD) to obtain a base layer 201. A 2 nm amorphous Cr layer (i.e., amorphous adhesion layer 202) is first deposited on the SiO2 film by magnetron sputtering at a power of 1 kW, and then a 150 nm crystalline Au layer (i.e., the first crystalline metal layer 203) is deposited at a power of 10 kW, and then a 30 nm crystalline Au layer (i.e., the second crystalline metal layer 203) is deposited at a power of 100 W. During the deposition, the pressure in the reactor chamber is 5×10 -5mTorr, a photoresist 204 layer arranged in an array is made on the second crystalline metal layer 203 using a photolithography process, a gold layer is electroplated in the exposure area using a direct current electroplating method, a scrubber is used to remove the residual photoresist 204, and the excess metal seed layer is removed by ion beam etching to obtain a conductive structure 2. After testing, the grain size of the second crystalline metal layer 203 of the conductive structure 2 is 45.9nm; the grain size of the metal wire 205 is 75.17nm, and the scratch depth of the metal wire 205 is 7546nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. The overall hardness of the metal wire 205 is lower. When the metal wire 205 with lower hardness is formed, the impact force on the amorphous adhesion layer 202, the crystalline metal layers 203 on both sides and the base layer 201 is smaller. In this way, it is not easy to destroy the connection between the base layer 201 and the amorphous adhesion layer 202, so that the base layer 201 is not easy to fall off from the amorphous adhesion layer 202, thereby improving the product quality and service life of the micro-electromechanical system.

[0064] Embodiment 3:

[0065] Use 8 inches <110> A 1 μm thick SiO2 film is grown on the SiO2 film by chemical vapor deposition (CVD) to obtain a base layer 201. A 250 nm amorphous Ti layer (i.e., amorphous adhesion layer 202) is first deposited on the SiO2 film by magnetron sputtering at a power of 40 kW, and then a 200 nm crystalline Au layer (i.e., the first crystalline metal layer 203) is deposited at a power of 100 W, and then a 300 nm crystalline Au layer (i.e., the second crystalline metal layer 203) is deposited at a power of 10 kW. During the deposition, the pressure in the reactor chamber is 5×10 -9mTorr, a photoresist 204 layer arranged in an array is made on the second crystalline metal layer 203 using a photolithography process, a gold layer is electroplated in the exposure area using a direct current electroplating method, a scrubber is used to remove the residual photoresist 204, and the excess metal seed layer is removed by ion beam etching to obtain a conductive structure 3. After testing, the grain size of the second crystalline metal layer 203 of the conductive structure 3 is 37.9nm; the grain size of the metal wire 205 is 56.9nm, and the scratch depth of the metal wire 205 is 6267nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. The overall hardness of the metal wire 205 is lower. When the metal wire 205 with lower hardness is formed, the impact force on the amorphous adhesion layer 202, the crystalline metal layers 203 on both sides and the base layer 201 is smaller. In this way, it is not easy to destroy the connection between the base layer 201 and the amorphous adhesion layer 202, so that the base layer 201 is not easy to fall off from the amorphous adhesion layer 202, thereby improving the product quality and service life of the micro-electromechanical system.

[0066] Embodiment 4:

[0067] Use 8 inches <110> A silicon wafer of 655±10 μm thick (i.e., substrate layer 201) is prepared by magnetron sputtering. A 10 nm amorphous Cr layer (i.e., amorphous adhesion layer 202) is first deposited on the silicon wafer at a power of 20 kW. Then, a 150 nm crystalline Au layer (i.e., first crystalline metal layer 203) is deposited at a power of 5 kW. Subsequently, a 50 nm crystalline Au layer (i.e., second crystalline metal layer 203) is deposited at a power of 500 W. During the deposition, the pressure in the reactor chamber is 5×10 -9 mTorr, a photoresist 204 layer arranged in an array is made on the second crystalline metal layer 203 using a photolithography process, a gold layer is electroplated in the exposure area using a direct current electroplating method, a scrubber is used to remove the residual photoresist 204, and the excess metal seed layer is removed by ion beam etching to obtain a conductive structure 4. After testing, the grain size of the second crystalline metal layer 203 of the conductive structure 4 is 39.3nm; the grain size of the metal wire 205 is 63.1nm, and the scratch depth of the metal wire 205 is 6560nm. It can be seen that the scratch depth of the metal wire 205 is deeper than that of the prior art. The deeper the scratch depth, the lower the hardness of the metal wire 205. The overall hardness of the metal wire 205 is lower. When the metal wire 205 with lower hardness is formed, the impact force on the amorphous adhesion layer 202, the crystalline metal layers 203 on both sides and the base layer 201 is smaller. In this way, it is not easy to destroy the connection between the base layer 201 and the amorphous adhesion layer 202, so that the base layer 201 is not easy to fall off from the amorphous adhesion layer 202, thereby improving the product quality and service life of the micro-electromechanical system.

[0068] In addition, an embodiment of the present application provides a conductive structure, which is prepared using the conductive structure preparation method provided in the above embodiment of the present application.

[0069] In addition, the present application also provides a micro-electromechanical system, including a plurality of conductive elements, wherein the conductive elements are electrically connected to each other using the conductive structure provided in the above-mentioned embodiment of the present application.

[0070] In summary, the embodiments of the present application provide a method for preparing a conductive structure, a conductive structure, and a micro-electromechanical system, which sputters at least two crystalline metal layers in sequence on the side of the amorphous adhesion layer away from the base layer with pre-configured different sputtering powers, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is smaller than a set first size threshold. In this way, the crystalline metal layer closest to the amorphous adhesion layer can be better connected with the amorphous adhesion layer, so that the metal wires subsequently grown on the at least two crystalline metal layers are not easily detached from the amorphous adhesion layer.

[0071] In addition, on the side of the crystalline metal layer farthest from the amorphous adhesion layer away from the base layer, an array of metal wires is formed. Since the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is greater than the set second size threshold, the grain size of the metal wire on the side close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer, and the grain size of the metal wire increases from the side close to the crystalline metal layer to the side far from the crystalline metal layer. In this way, the grain size of at least two crystalline metal layers can be larger as a whole. According to the Hall-Petch law, the larger the grain size, the lower the hardness. It can be seen that the hardness of at least two crystalline metal layers is lower as a whole. When at least two crystalline metal layers with lower hardness are formed, the impact force on the amorphous adhesion layer and the base layer is smaller. In this way, it is not easy to destroy the connection between the base layer and the amorphous adhesion layer, so that the metal wire is not easy to fall off from the base layer, thereby improving the product quality and service life of the micro-electromechanical system.

[0072] In the above description, the technical details such as the patterning of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0073] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0074] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for preparing a conductive structure, characterized in that: The method comprises: sputtering an amorphous adhesion layer on one side of the substrate layer; At least two crystalline metal layers are sequentially sputtered on a side of the amorphous adhesion layer away from the base layer with different pre-configured sputtering powers, so that the grain size of the crystalline metal layer closest to the amorphous adhesion layer is smaller than a set first size threshold, and the grain size of the crystalline metal layer farthest from the amorphous adhesion layer is larger than a set second size threshold, and the second size threshold is larger than the first size threshold, wherein each sputtering power is used to sputter one layer of the crystalline metal layer; On a side of the crystalline metal layer farthest from the amorphous adhesion layer and away from the base layer, an array of metal wires is formed, wherein the grain size of the metal wire increases from the side close to the crystalline metal layer to the side far from the crystalline metal layer, and the grain size of the metal wire on the side close to the crystalline metal layer is equal to the grain size of the crystalline metal layer farthest from the amorphous adhesion layer; The portions of the orthographic projections of the amorphous adhesion layer and the at least two crystalline metal layers on the base layer that do not overlap with the orthographic projections of the metal wires on the base layer are removed.

2. The method according to claim 1, characterized in that The sputtering power of the amorphous adhesion layer ranges from 500W to 40kW, and the sputtering power of the crystalline metal layer each time is ranged from 100W to 10kW.

3. The method according to claim 2, characterized in that The crystalline metal layer includes two layers. The sputtering power of the amorphous adhesion layer is 25 kW, the power of the first sputtering of the crystalline metal layer is 2 kW, and the power of the second sputtering of the crystalline metal layer is 1 kW; Alternatively, the sputtering power of the amorphous adhesion layer is 1 kW, the power of the first sputtering of the crystalline metal layer is 10 kW, and the power of the second sputtering of the crystalline metal layer is 100 W; Alternatively, the sputtering power of the amorphous adhesion layer is 40 kW, the power of the first sputtering of the crystalline metal layer is 100 W, and the power of the second sputtering of the crystalline metal layer is 10 kW; Alternatively, the sputtering power of the amorphous adhesion layer is 20 kW, the power of the first sputtering of the crystalline metal layer is 5 kW, and the power of the second sputtering of the crystalline metal layer is 500 W.

4. The method according to claim 1, characterized in that: The set second size threshold ranges from 25 nm to 50 nm.

5. The method according to claim 1, characterized in that: When sputtering the amorphous adhesion layer and the at least two crystalline metal layers, the pressure range of the sputtering reactor is 5×10 -9 mTorr~5×10 -5 mTorr.

6. The method according to claim 1, characterized in that The thickness of the amorphous adhesion layer is in the range of 2nm to 50nm, and the total thickness of the at least two crystalline metal layers is in the range of 50nm to 500nm.

7. The method according to claim 1, characterized in that The removing of the portion where the orthographic projections of the amorphous adhesion layer and the at least two crystalline metal layers on the base layer do not overlap with the orthographic projections of the metal wire on the base layer comprises: Ion beam etching is used to remove portions of the amorphous adhesion layer and the at least two crystalline metal layers whose orthographic projections on the base layer do not overlap with the orthographic projections of the metal wires on the base layer.

8. The method according to claim 1, characterized in that The metal wires arranged in an array on a side of the crystalline metal layer farthest from the amorphous adhesion layer and away from the base layer include: Forming an array of spaced photoresists on a side of the crystalline metal layer farthest from the amorphous adhesion layer away from the base layer to form an electroplating pattern; Electroplating a metal conductor in the exposed area between each two adjacent photoresists; A scrubber is used to remove the array-like spaced photoresist to form array-like arranged metal wires.

9. A conductive structure, characterized in that: The conductive structure is prepared by the conductive structure preparation method according to any one of claims 1 to 8.

10. A micro-electromechanical system, characterized in that: It comprises a plurality of conductive elements, each of which is electrically connected by using the conductive structure as claimed in claim 9.

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