Chip waveform de-embedding method and device, electronic equipment and storage medium

Abstract

The invention discloses a chip waveform de-embedding method and device, electronic equipment and a storage medium, and relates to the technical field of chip testing. The method comprises the following steps: welding a first LPDDR5 chip on a first test circuit board through an adapter plate; a second LPDDR5 chip is welded to a second test circuit; obtaining a first chip waveform and a second chip waveform of the first test circuit board and the second test circuit board through an oscilloscope, and carrying out fast Fourier calculation on the first chip waveform and the second chip waveform to obtain a first frequency domain signal and a second frequency domain signal; obtaining a first transfer function of the adapter plate according to the first frequency domain signal and the second frequency domain signal; obtaining a third frequency domain signal according to the first frequency domain signal and a first transfer function; and performing inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip. According to the method provided by the embodiment of the invention, the accuracy of the chip waveform test can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip waveform de-embedding method, device, electronic equipment, and storage medium. Background Art

[0002] In the signal test of DDR chips, it is necessary to introduce a fixture to assist in measuring waveforms. The fixture serves as an intermediary between the test circuit board and the chip to be tested, and is used to achieve the connection between the test circuit board and the chip to be tested. When the test circuit board is testing the chip to be tested, the oscilloscope probe is brought into contact with the fixture to achieve waveform measurement of the chip. However, the fixture is usually equipped with structures such as through holes and traces. The complex structure inside the fixture can cause signal loss and reflection, making the waveform measured by the oscilloscope inconsistent with the actual waveform of the chip, resulting in inaccurate measurement results. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a chip waveform de-embedding method, device, electronic device, and storage medium, which can improve the accuracy of chip waveform measurement.

[0004] In a first aspect, a chip waveform de-embedding method according to an embodiment of the present invention includes: According to the layout of the LPDDR5 chip, an adapter board is designed; a surface pad is provided on the surface of the adapter board, a bottom pad is provided on the bottom surface of the adapter board, and the surface pad is connected to the bottom pad through a via hole; Acquire a first test circuit board and a second test circuit board; Soldering the first LPDDR5 chip to the surface pads of the adapter board, and soldering the bottom pads of the adapter board to the first test circuit board, so that the first LPDDR5 chip is connected to the first test circuit board through the adapter board; Soldering a second LPDDR5 chip on the surface of the second test circuit board; Acquire a first chip waveform of the first test circuit board through an oscilloscope, and perform fast Fourier calculation on the first chip waveform to obtain a first frequency domain signal; Acquire a second chip waveform of the second test circuit board through an oscilloscope, and perform fast Fourier calculation on the second chip waveform to obtain a second frequency domain signal; Obtaining a first transfer function of the adapter board according to the first frequency domain signal and the second frequency domain signal; Obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function; Perform an inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip. According to some embodiments of the present invention, the calculation formula of the first transfer function is: ; in, represents the first chip waveform, represents the first frequency domain signal, represents the second chip waveform, represents the second frequency domain signal, and H represents the first transfer function. According to some embodiments of the present invention, obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function includes: performing an inverse operation on the first transfer function to obtain an inverse transfer function; A convolution operation is performed on the first frequency domain signal and the inverse transfer function to obtain the third frequency domain signal. According to some embodiments of the present invention, the method further comprises: Import the design file of the adapter board into the simulation software and select the circuit routing to be tested; Obtaining the S parameters of the adapter plate through the simulation software; Inputting the S parameter into the oscilloscope, so that the oscilloscope obtains the second transfer function of the adapter board according to the S parameter; performing a deconvolution operation on the first frequency domain signal and the second transfer function to obtain a fourth frequency domain signal; Perform an inverse Fourier transform on the fourth frequency domain signal to obtain a second test waveform of the LPDDR5 chip. According to some embodiments of the present invention, the method further comprises: Calculating a first error between the first test waveform and the second chip waveform; Calculating a second error between the second test waveform and the second chip waveform; The first test waveform or the second test waveform is determined as a final test waveform according to the first error and the second error.

[0005] According to some embodiments of the present invention, the calculation formula of the first error is: ; in, represents the first test waveform, represents the second chip waveform, N is the total number of samples, is the first error. According to some embodiments of the present invention, the adapter board is a six-layer board, including a top board, four inner-layer boards and a bottom board, the thickness of the bottom board is greater than the sum of the thicknesses of the top board and the four inner-layer boards, and a circuit is arranged in the inner-layer board; the method further includes: According to a preset depth and a preset width, grooves are milled around the bottom of the bottom plate, so that the bottom of the bottom plate serves as the lower layer, and the top of the bottom plate, the top plate, and the four inner layers serve as the upper layer; wherein the preset depth is less than the thickness of the bottom plate; Four extension plates are formed on the portion of the surface of the upper layer portion protruding from the surface of the lower layer portion; A test pad is arranged on the surface of each of the extension plates, and a gap is formed between any two adjacent extension plates; Lead the test points of the line routing to the surface of the adapter board and connect them to the corresponding test pads. In the second aspect, a chip waveform de-embedding device according to an embodiment of the present invention includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the chip waveform de-embedding method as described in the embodiment of the first aspect.

[0006] In a third aspect, an electronic device according to an embodiment of the present invention includes: the chip waveform de-embedding device described in the embodiment of the second aspect above.

[0007] In a fourth aspect, according to a storage medium of an embodiment of the present invention, the storage medium stores computer executable instructions, and the computer executable instructions are used to enable a computer to execute the chip waveform de-embedding method described in the embodiment of the first aspect.

[0008] The chip waveform de-embedding method, device, electronic device, and storage medium according to the embodiments of the present invention have at least the following beneficial effects: by introducing an adapter board, it is possible to complete the test of the LPDDR5 chip and de-embed the measured waveform, thereby avoiding signal loss and reflection caused by the structure inside the adapter board, so that the waveform measured by the oscilloscope is consistent with the actual waveform of the chip, thereby ensuring the accuracy of the measurement result.

[0009] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A flowchart of the steps of a chip waveform de-embedding method according to an embodiment of the present invention; Figure 2 It is a structural schematic diagram of an adapter board according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal wiring of the adapter board according to an embodiment of the present invention; Figure 4 is a schematic top view of an adapter plate according to an embodiment of the present invention; Figure 5 It is a front view schematic diagram of an adapter plate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0012] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0013] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0014] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0015] In the signal test of DDR chips, it is necessary to introduce a fixture to assist in measuring waveforms. The fixture serves as an intermediary between the test circuit board and the chip to be tested, and is used to achieve the connection between the test circuit board and the chip to be tested. When the test circuit board is testing the chip to be tested, the oscilloscope probe is brought into contact with the fixture to achieve waveform measurement of the chip. However, the fixture is usually equipped with structures such as through holes and traces. The complex structure inside the fixture can cause signal loss and reflection, making the waveform measured by the oscilloscope inconsistent with the actual waveform of the chip, resulting in inaccurate measurement results.

[0016] To this end, the embodiments of the present invention provide a chip waveform de-embedding method, device, electronic device, and storage medium, which can complete the test of the LPDDR5 chip and de-embed the measured waveform when an adapter board is introduced, thereby avoiding signal loss and reflection caused by the internal structure of the adapter board, and making the waveform measured by the oscilloscope consistent with the actual waveform of the chip, thereby ensuring the accuracy of the measurement result.

[0017] The chip waveform de-embedding method, device, electronic device, and storage medium according to the embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0018] On the one hand, an embodiment of the present invention provides a chip waveform de-embedding method, such as Figure 1 As shown, the method comprises the following steps: Step S100: designing an adapter board 100 according to the layout of the LPDDR5 chip; a surface pad 200 is disposed on the surface of the adapter board 100, and a bottom pad (not shown) is disposed on the bottom surface of the adapter board 100, and the surface pad 200 is connected to the bottom pad via a via hole; Step S200: Acquire a first test circuit board and a second test circuit board; Step S300: soldering the first LPDDR5 chip to the surface pad 200 of the adapter board 100, and soldering the bottom pad of the adapter board 100 to the first test circuit board, so that the first LPDDR5 chip is connected to the first test circuit board through the adapter board 100; Step S400: soldering a second LPDDR5 chip to a surface of a second test circuit board; Step S500: acquiring a first chip waveform of a first test circuit board through an oscilloscope, and performing fast Fourier transformation on the first chip waveform to obtain a first frequency domain signal; Step S600: acquiring a second chip waveform of a second test circuit board through an oscilloscope, and performing fast Fourier transformation on the second chip waveform to obtain a second frequency domain signal; Step S700: obtaining a first transfer function of the adapter board 100 according to the first frequency domain signal and the second frequency domain signal; Step S800: obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function; Step S900: Perform an inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip.

[0019] Specifically, Figure 2 As shown, since the surface of the adapter board 100 is provided with a surface pad 200, the bottom surface of the adapter board 100 is provided with a bottom pad (not shown), and the surface pad 200 is connected to the bottom pad through a via hole, the first LPDDR5 chip is soldered to the surface pad 200 of the adapter board 100, and after the bottom pad of the adapter board 100 is soldered to the first test circuit board, the first LPDDR5 chip can be connected to the first test circuit board through the surface pad 200, the via hole and the bottom pad.

[0020] like Figure 5 As shown, in some embodiments of the present application, the adapter board 100 adopts a six-layer board design, including a top board 110, four inner-layer boards 120 and a bottom board 130, wherein the thickness of the bottom board 130 is greater than the sum of the thicknesses of the top board 110 and the four inner-layer boards 120. The inner-layer board 120 of the adapter board 100 is provided with circuit routing, such as Figure 3 The adapter plate 100 is divided into an upper portion 140 and a lower portion 150. The surface area of ​​the upper portion 140 is larger than that of the lower portion 150. The surface of the upper portion 140 protrudes from the surface of the lower portion 150 to form four extension plates 400 (such as Figure 4 As shown in the figure), a test pad 300 is provided on the surface of each extension board 400; the test points of the line routing are led out to the surface of the adapter board 100 and connected to the corresponding test pad 300.

[0021] It should be noted that the surface pads 200 and the bottom pads of the adapter board 100 correspond one to one, and the two are connected through a via hole to achieve the conduction of the circuits of each layer of the adapter board 100. At the same time, the design of the surface pads 200 and the bottom pads corresponds to the layout of the LPDDR5 chip. The circuit routing inside the adapter board 100 includes various circuits required by the LPDDR5 chip, such as power lines, data lines, clock lines, control lines, ground lines, etc. For the circuits that need to be tested, the test points of the corresponding circuit routing are led out to the surface of the adapter board 100 and connected to the corresponding test pads 300, such as Figure 2 As shown. The surface pad 200 is connected to the bottom pad by a through hole to achieve the effect of electrical interconnection, and the signal test line segment of the line routing is led out in the middle layer to the surface test pad 300, that is, a T-shaped topology is adopted. The signal test line segment led out needs to be as short as possible to reduce the reflection caused by the T-shaped topology. When the LPDDR5 chip is to be tested, the first LPDDR5 chip is first soldered to the surface of the adapter board 100, and then the adapter board 100 is soldered to the first test circuit board, so that the first test circuit board can drive the first LPDDR5 chip to start working. During the operation of the first LPDDR5 chip, for the items to be tested, the corresponding test pad 300 is connected to the oscilloscope, and the various waveforms in the working process of the LPDDR5 chip can be displayed and measured through the oscilloscope, thereby realizing various parameter tests of the LPDDR5 chip, such as testing whether the eye width and eye height of the eye diagram of the LPDDR5 chip meet the design standards, and testing whether the signal integrity of the LPDDR5 chip meets the requirements. At the same time, since the first test circuit board is designed with a test circuit, components such as capacitors, resistors, and MOS tubes are required. In order to avoid collision between the adapter board 100 and the components on the test circuit board when the adapter board 100 is installed on the test circuit board, such as Figure 4 As shown, the depth-controlled milling process is used to mill grooves around the bottom of the adapter plate 100, so that the adapter plate 100 is divided into an upper portion 140 and a lower portion 150, and the surface area of ​​the upper portion 140 is larger than the surface area of ​​the lower portion 150, forming a T shape as a whole. In this example, the total thickness of the adapter plate 100 is 2.4 mm, and the bottom is milled by 1.6 mm of thickness using the depth-controlled milling process, so as to avoid collision between the adapter plate 100 and the parts on the test circuit board after welding. It should be noted that the total thickness of the adapter plate 100 and the milled thickness can be adjusted according to actual needs, and are not limited to this.

[0022] Although the introduction of the adapter board 100 can make the testing of the LPDDR5 chip more convenient and comprehensive, the adapter board 100 is provided with vias, line routing, etc. inside, which may cause signal loss and reflection, making the waveform measured by the oscilloscope inconsistent with the actual waveform of the chip, resulting in inaccurate measurement results. For this reason, in addition to obtaining the first chip waveform of the first test circuit board through the oscilloscope, the second chip waveform of the second test circuit board is also obtained through the oscilloscope. Unlike the first test circuit board, the second test circuit board does not introduce the adapter board 100, but directly solders the second LPDDR5 chip to the surface of the second test circuit board, thereby avoiding the signal loss and reflection caused by the adapter board 100.

[0023] After obtaining the first chip waveform of the first test circuit board and the second chip waveform of the second test circuit board through an oscilloscope, fast Fourier calculation is performed on the first chip waveform and the second chip waveform respectively, and the first chip waveform and the second chip waveform are converted from time domain signals to frequency domain signals to obtain first frequency domain signals and second frequency domain signals. Then, according to the first frequency domain signals and the second frequency domain signals, the first transfer function of the adapter board 100 is obtained, wherein the calculation formula of the first transfer function is as follows: ; in, represents the first chip waveform, represents a first frequency domain signal obtained after fast Fourier transform of the first chip waveform, represents the second chip waveform, represents a second frequency domain signal obtained after fast Fourier transform is performed on the second chip waveform, and H represents the first transfer function.

[0024] After the first transfer function is obtained, a third frequency domain signal may be obtained according to the first frequency domain signal and the first transfer function, specifically comprising the following steps: Step S810: performing an inverse operation on the first transfer function to obtain an inverse transfer function; Step S820: performing a convolution operation on the first frequency domain signal and the inverse transfer function to obtain a third frequency domain signal.

[0025] Specifically, the transfer inverse function is: , then the third frequency domain signal is the result of convolving the first frequency domain signal with the inverse transfer function. Finally, the third frequency domain signal is inversely Fourier transformed to obtain the first test waveform of the LPDDR5 chip. It should be noted that since the second frequency domain signal is not affected by the adapter board 100, the first transfer function of the adapter board 100 can be obtained based on the first frequency domain signal and the second frequency domain signal, and then the first frequency domain signal is convolved with the inverse transfer function of the first transfer function to obtain the third frequency domain signal, which is the signal obtained by removing the interference of the adapter board 100 from the first frequency domain signal.

[0026] According to the chip waveform de-embedding method of the embodiment of the present application, it is possible to complete the test of the LPDDR5 chip and de-embed the measured waveform when the adapter board 100 is introduced, thereby avoiding signal loss and reflection caused by the internal structure of the adapter board 100, so that the waveform measured by the oscilloscope is consistent with the actual waveform of the chip, thereby ensuring the accuracy of the measurement result.

[0027] Further, in some embodiments of the present application, the chip waveform de-embedding method of the embodiment of the present application further includes the following five steps: (1) Import the design file of the adapter board 100 into the simulation software and select the circuit routing to be tested; (2) Obtaining S parameters of the adapter board 100 through simulation software; (3) inputting the S parameter into the oscilloscope, so that the oscilloscope obtains the second transfer function of the adapter board 100 according to the S parameter; (4) performing a deconvolution operation on the first frequency domain signal and the second transfer function to obtain a fourth frequency domain signal; (5) Perform an inverse Fourier transform on the fourth frequency domain signal to obtain a second test waveform of the LPDDR5 chip.

[0028] Among them, the simulation software can use common software such as Spice, ADS or Proteus. By importing the design file of the adapter board 100 in the simulation software and selecting the line routing to be tested, the corresponding S parameters can be obtained. Then, the S parameters are exported from the simulation file and saved as an S2P file. The file is imported into the oscilloscope so that the oscilloscope obtains the S parameters, and the second transfer function of the adapter board 100 is obtained according to the S parameters. The calculation method of the second transfer function is as follows: ; in, is the second transfer function, is the forward transmission coefficient of the adapter plate 100, is the transmission delay of the adapter board 100.

[0029] After obtaining the second transfer function, the first frequency domain signal and the second transfer function are deconvolved to obtain a fourth frequency domain signal, which is the signal obtained by removing the interference of the adapter board 100 from the first frequency domain signal. In this example, the S parameters of the adapter board 100 are obtained by using simulation software, and then the second transfer function of the adapter board 100 is obtained according to the S parameters of the adapter board 100 through an oscilloscope, so as to obtain the chip signal measured after removing the interference of the adapter board 100 by deconvolving the first frequency domain signal and the second transfer function. Finally, the fourth frequency domain signal is inversely Fourier transformed to obtain the second test waveform of the LPDDR5 chip.

[0030] Furthermore, in some embodiments of the present application, the chip waveform de-embedding method further includes the following three steps: Calculating a first error between a first test waveform and a second chip waveform; Calculating a second error between a second test waveform and a second chip waveform; According to the first error and the second error, the first test waveform or the second test waveform is determined to be the final test waveform.

[0031] Among them, the first test waveform is a waveform obtained by removing the interference of the adapter board 100 according to the second chip waveform obtained by the second test circuit board; and the second test waveform is a waveform obtained by removing the interference of the adapter board 100 according to the S parameter obtained by the simulation software. By comparing the errors between the two test waveforms and the second chip waveform, it is possible to determine which waveform is closer to the actual waveform of the LPDDR5 chip, thereby determining the final de-embedding method. If the first error between the first test waveform and the second chip waveform is less than the second error between the second test waveform and the second chip waveform, the first test waveform is used as the final test waveform of the LPDDR5 chip; if the first error between the first test waveform and the second chip waveform is greater than the second error between the second test waveform and the second chip waveform, the first test waveform is used as the final test waveform of the LPDDR5 chip, and the second test waveform is used as the final test waveform of the LPDDR5 chip. In this way, the most effective de-embedding method can be determined, the interference of the adapter board 100 on the chip waveform can be accurately removed, and the accuracy of the measured chip waveform can be improved.

[0032] In some embodiments of the present application, the calculation formula of the first error is: ; in, represents the first test waveform, represents the second chip waveform, N is the total number of samples, It should be noted that the calculation formula of the second error is similar to the calculation formula of the first error.

[0033] Furthermore, if Figure 5 As shown, in some embodiments of the present application, the chip waveform de-embedding method further includes the following three steps: According to the preset depth and preset width, the bottom of the bottom plate 130 is milled around, so that the bottom of the bottom plate 130 is used as the lower layer 150, and the top of the bottom plate 130, the top plate 110, and the four inner layer plates 120 are used as the upper layer 140; wherein the preset depth is less than the thickness of the bottom plate 130; Four extension plates 400 are formed on the portion of the surface of the upper layer 140 protruding from the surface of the lower layer 150. A test pad 300 is disposed on the surface of each extension plate 400 , and a gap 410 is formed between any two adjacent extension plates 400 ; The test points of the line routing are led out of the surface of the adapter board 100 and connected to the corresponding test pads 300 .

[0034] Specifically, the adapter board 100 adopts a six-layer board design, including a top plate 110, four inner layers 120 and a bottom plate 130, wherein the thickness of the bottom plate 130 is greater than the sum of the thicknesses of the top plate 110 and the four inner layers 120; when the bottom of the adapter board 100 is milled, the bottom of the bottom plate 130 is milled, and the depth of the milling groove does not exceed the thickness of the bottom plate 130, so that the top plate 110 and the four inner layers 120 are both located in the upper part 140 of the adapter board 100 to avoid affecting the line routing in the inner layer 120. At the same time, the stacking spacing between the top plate 110 and the four inner layers 120 is as small as possible to achieve good signal shielding and impedance reference when testing the line routing. In terms of the board selection of the adapter board 100, a high-speed board with a good low dielectric constant and low dielectric loss tangent should be selected to reduce the loss during signal transmission. In this example, the dielectric constant of the plate material of the adapter board 100 is lower than 3.71, and the dielectric loss factor is lower than 0.002 at a frequency of 1 GHz, which meets the requirements of high-speed transmission and low loss of signals. In this example, the total thickness of the adapter board 100 is 2.4 mm, and the bottom is milled by a controlled depth milling process to remove 1.6 mm of thickness, so as to avoid collision between the adapter board 100 and the parts on the test circuit board after welding. A gap 410 is formed between any two adjacent extension boards 400, so that four corners correspond to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter board 100 when welding the adapter board 100 to the first test circuit board. In order to conduct a comprehensive test of the LPDDR5 chip, it is necessary to select the key signals of the LPDDR5 chip as test points. In this example, the following signals are used as test points: For data lines: the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip are brought out as the first signal test point; In terms of clock and address / control lines: the clock differential signal (CK), two random CA signals, and two random CS signals of each channel of the LPDDR5 chip are brought out as the second signal test point.

[0035] Power test point: Bring out the VDDQ, VDD1, VDD2H, and VDD2L of the LPDDR5 chip as power test points.

[0036] After selecting the above test points, connect all the test points to the corresponding test pads 300 through routing. After selecting the first signal test point, the second signal test point and the power test point, the first signal test point, the second signal test point and the power test point also need to be connected to the ground test point as a basis to lead out the GND signal of the LPDDR5 chip as a ground test point. To this end, GND ground holes are evenly arranged around the WCK differential signal, RDQS differential signal, data single-ended signal, clock differential signal, CA signal, CS signal, VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal to achieve grounding; the signal of the GND ground hole is led out as a ground test point; the ground test point is connected to the corresponding test pad 300.

[0037] It should be noted that for the wiring that needs to be tested, GND grounding treatment is adopted, and GND ground holes are evenly drilled around the signal to achieve the effect of signal shielding and reduce the crosstalk effect between high-speed signals.

[0038] like Figure 2As shown, in some embodiments of the present application, the signal test pad 310 corresponding to the first signal test point, the second signal test point and the power test point is designed as an elliptical pad, and the ground test pad 320 corresponding to the GND test point is designed as a rectangular pad design, which is convenient for distinguishing and processing during later testing. It should be noted that the signal test pad 310 and the ground test pad 320 can also be designed as other shapes, as long as the shapes of the two are different. At the same time, each ground test pad 320 and the signal test pad 310 are equally spaced around the four extension plates 400, and a spacing of more than 0.75mm is maintained to avoid collision of the test pens during testing. At the same time, a gap 410 is formed between any two adjacent extension plates 400, thereby leaving four corners corresponding to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter board 100 when the adapter board 100 is soldered to the first test circuit board. Due to the high thickness of the adapter board 100, the via hole connecting the surface pad 200 and the bottom pad needs to use a through hole with a maximum aperture to meet the diameter-to-depth ratio requirement in machining. The connecting vias at the test pad 300 (i.e., vias for WCK differential signals, RDQS differential signals, data single-ended signals, clock differential signals, CA signals, CS signals, VDDQ signals, VDD1 signals, VDD2H signals, VDD2L signals, etc.) use 1-3 layers of blind vias to connect the test pads to the inner layer traces to eliminate the reflection effect caused by the via stub. The differential signals of the adapter board 100 (such as WCK differential signals, RDQS differential signals and clock differential signals, etc.) are controlled within 100Ω impedance, the single-ended signals (such as data single-ended signals, CA signals, CS signals, etc.) are controlled within 50Ω impedance, and the power supply lines (such as VDDQ signals, VDD1 signals, VDD2H signals, VDD2L signals, etc.) are kept at a line width of more than 12 mils.

[0039] On the other hand, an embodiment of the present application also proposes a chip waveform de-embedding device, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the above-mentioned chip waveform de-embedding method.

[0040] The processor may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application; The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory can store an operating system and other applications. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory, and the processor calls and executes the chip waveform de-embedding method of the embodiment of the present application; the memory and the processor can be connected through a bus or the like.

[0041] On the other hand, an embodiment of the present invention further provides an electronic device, comprising the above-mentioned chip waveform de-embedding device.

[0042] On the other hand, an embodiment of the present invention further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned chip waveform de-embedding method is implemented.

[0043] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0044] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0045] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0046] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0047] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0048] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0049] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0050] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A chip waveform de-embedding method, characterized in that: include: According to the layout of the LPDDR5 chip, an adapter board is designed; a surface pad is provided on the surface of the adapter board, a bottom pad is provided on the bottom surface of the adapter board, and the surface pad is connected to the bottom pad through a via hole; Acquire a first test circuit board and a second test circuit board; Soldering the first LPDDR5 chip to the surface pads of the adapter board, and soldering the bottom pads of the adapter board to the first test circuit board, so that the first LPDDR5 chip is connected to the first test circuit board through the adapter board; Soldering a second LPDDR5 chip on the surface of the second test circuit board; Acquire a first chip waveform of the first test circuit board through an oscilloscope, and perform fast Fourier calculation on the first chip waveform to obtain a first frequency domain signal; Acquire a second chip waveform of the second test circuit board through an oscilloscope, and perform fast Fourier calculation on the second chip waveform to obtain a second frequency domain signal; Obtaining a first transfer function of the adapter board according to the first frequency domain signal and the second frequency domain signal; Obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function; Perform an inverse Fourier transform on the third frequency domain signal to obtain a first test waveform of the LPDDR5 chip.

2. The chip waveform de-embedding method according to claim 1, characterized in that: The calculation formula of the first transfer function is: ； in, represents the first chip waveform, represents the first frequency domain signal, represents the second chip waveform, represents the second frequency domain signal, and H represents the first transfer function.

3. The chip waveform de-embedding method according to claim 1, characterized in that: The step of obtaining a third frequency domain signal according to the first frequency domain signal and the first transfer function comprises: performing an inverse operation on the first transfer function to obtain an inverse transfer function; A convolution operation is performed on the first frequency domain signal and the inverse transfer function to obtain the third frequency domain signal.

4. The chip waveform de-embedding method according to claim 1, characterized in that: The method further comprises: Import the design file of the adapter board into the simulation software and select the circuit routing to be tested; Obtaining the S parameters of the adapter plate through the simulation software; Inputting the S parameter into the oscilloscope, so that the oscilloscope obtains the second transfer function of the adapter board according to the S parameter; performing a deconvolution operation on the first frequency domain signal and the second transfer function to obtain a fourth frequency domain signal; Perform an inverse Fourier transform on the fourth frequency domain signal to obtain a second test waveform of the LPDDR5 chip.

5. The chip waveform de-embedding method according to claim 4, characterized in that: The method further comprises: Calculating a first error between the first test waveform and the second chip waveform; Calculating a second error between the second test waveform and the second chip waveform; The first test waveform or the second test waveform is determined as a final test waveform according to the first error and the second error.

6. The chip waveform de-embedding method according to claim 5, characterized in that: The calculation formula of the first error is: ; in, represents the first test waveform, represents the second chip waveform, N is the total number of samples, is the first error.

7. The chip waveform de-embedding method according to claim 1, characterized in that: The adapter board is a six-layer board, including a top board, four inner-layer boards and a bottom board, the thickness of the bottom board is greater than the sum of the thicknesses of the top board and the four inner-layer boards, and the inner-layer boards are provided with circuit routing; the method further includes: According to a preset depth and a preset width, grooves are milled around the bottom of the bottom plate, so that the bottom of the bottom plate serves as the lower layer, and the top of the bottom plate, the top plate, and the four inner layers serve as the upper layer; wherein the preset depth is less than the thickness of the bottom plate; Four extension plates are formed on the portion of the surface of the upper layer portion protruding from the surface of the lower layer portion; A test pad is arranged on the surface of each of the extension plates, and a gap is formed between any two adjacent extension plates; Lead the test points of the line routing to the surface of the adapter board and connect them to the corresponding test pads.

8. A chip waveform de-embedding device, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the chip waveform de-embedding method as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: It includes the chip waveform de-embedding device as described in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the chip waveform de-embedding method as described in any one of claims 1 to 7.

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