A composite waveguide structure and a method of manufacturing the same

Abstract

The application provides a composite waveguide structure and a preparation method thereof, and belongs to the technical field of electro-optical modulators. The composite waveguide structure comprises a first waveguide wafer and a waveguide film. The first waveguide wafer comprises a first substrate, a passivation layer, a first waveguide structure in the passivation layer and a metal electrode. The metal electrode is arranged on both sides of the first waveguide structure. The first waveguide structure is covered with a first waveguide cladding layer on the upside. The upside of the metal electrode is provided with a first pad hole. The waveguide film comprises a second substrate, a buried oxygen layer arranged on the second substrate and a second waveguide structure arranged on the upside of the buried oxygen layer. The second waveguide structure is provided with second pad holes on both sides. The second waveguide structure is covered with a second waveguide cladding layer on the upside. The second waveguide cladding layer is bonded with the first waveguide cladding layer. The position of the second waveguide structure corresponds to the position of the first waveguide structure. The position of the second pad hole corresponds to the position of the first pad hole. The application improves the compatibility of the W2W heterogeneous integration mode with the CMOS process.

Description

Technical Field

[0001] The present application relates to the technical field of electro-optic modulators, and in particular to a composite waveguide structure and a preparation method thereof. Background Art

[0002] Optical communications, radio frequency photonic systems, millimeter wave measuring instruments and other devices using optical devices have increasingly higher bandwidth requirements. In semiconductor photonic modulators, the limitation of electron carrier transmission time fundamentally affects the high-frequency operating characteristics of diode-based electro-optical modulators (EOMs), which has aroused great interest in the research of materials with high-frequency electro-optical modulation properties. Lithium niobate (LN) has attracted widespread attention in integrated optics due to its superior electro-optical and nonlinear optical properties. Mach-Zehnder modulators (MZMs) heterojunctionally integrated with silicon or silicon nitride waveguides have been proven to achieve very high modulation bandwidths, supporting high-frequency modulation far exceeding 100 GHz.

[0003] Ideally, the fabrication of this electro-optic modulator should be compatible with conventional CMOS processes used in silicon photonics, resulting in higher performance, lower cost, and improved manufacturing scalability. Electro-optic modulator (composite waveguide) structures composed of thin-film lithium niobate and silicon nitride are typically fabricated using die-to-wafer (D2W) or wafer-to-wafer (W2W) bonding.

[0004] The W2W bonding process for LN-SiNx composite waveguides typically involves front-end processes such as LN and metal electrode photolithography and thin film preparation, making it incompatible with CMOS processes. Furthermore, the LN process relies on the processing of the SiNx waveguide chip, limiting the flexibility of the LN process and reducing process efficiency. In fact, a fabrication method that places a metal electrode (Al) beneath the SiNx to form a buried electrode structure and then bonds the LN-cut single chip to a SiNx waveguide wafer or a single SiNx waveguide chip via D2W or D2D bonding can address the CMOS incompatibility issue. However, the LN Si substrate removal process faces significant risks and challenges. For example, the D2W method: ① There is a risk of LN chip detachment during Si grinding; ② The risk of etchant damage to the SiNx waveguide device during wet etching of residual Si after grinding. The D2D method typically uses dry etching to remove the Si substrate, which is also incompatible with CMOS processes and unsuitable for mass production. Summary of the Invention

[0005] In view of this, an embodiment of the present application provides a composite waveguide structure and a method for preparing the same, which at least partially solves the problem in the prior art that the process flow is incompatible with the CMOS process and has low process efficiency.

[0006] In a first aspect, an embodiment of the present application provides a composite waveguide structure, comprising a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, wherein the first waveguide wafer comprises a first substrate, a passivation layer arranged on the first substrate, and a first waveguide structure and a metal electrode arranged in the passivation layer, the metal electrodes are arranged on both sides of the first waveguide structure, the upper side of the first waveguide structure is covered with a first waveguide cladding, and the upper side of the metal electrode is provided with a first pad hole; the waveguide film comprises a second substrate, a buried oxide layer arranged on the second substrate, and a second waveguide structure arranged on the upper side of the buried oxide layer, second pad holes are provided on both sides of the second waveguide structure, the upper side of the second waveguide structure is covered with a second waveguide cladding, the second waveguide cladding is bonded to the first waveguide cladding, the position of the second waveguide structure corresponds to the position of the first waveguide structure, and the position of the second pad hole corresponds to the position of the first pad hole.

[0007] In a second aspect, an embodiment of the present application further provides a method for preparing a composite waveguide structure, for preparing the composite waveguide structure as described in the first aspect, the method comprising:

[0008] Sequentially preparing a metal electrode and a first waveguide structure on the passivation layer of the first substrate, with the metal electrodes being arranged on both sides of the first waveguide structure;

[0009] preparing and planarizing a first waveguide cladding layer on the first waveguide structure;

[0010] Opening a hole above the metal electrode to form a first pad hole to obtain a first waveguide wafer;

[0011] preparing an electro-optical material substrate wafer, wherein the electro-optical material substrate wafer comprises a second substrate, a buried oxide layer and an electro-optical material film arranged in a stacked manner;

[0012] Patterning the electro-optical material film to form a second waveguide structure, and making the position of the second waveguide structure correspond to the position of the first waveguide structure through layout design;

[0013] preparing and planarizing a second waveguide cladding for the second waveguide structure;

[0014] Opening holes in the second waveguide cladding layer and the buried oxide layer to form second pad holes, and making the positions of the second pad holes correspond to the positions of the first pad holes through layout design to obtain a second waveguide wafer;

[0015] bonding the first waveguide wafer and the second waveguide wafer through the first waveguide cladding and the second waveguide cladding;

[0016] The second substrate is removed.

[0017] According to a specific implementation of the embodiment of the present application, the step of sequentially preparing a metal electrode and a first waveguide structure on the passivation layer of the first substrate includes:

[0018] depositing a first passivation layer on the first substrate;

[0019] depositing a metal thin film on the first passivation layer;

[0020] Patterning the metal film through a patterning process to form the metal electrode;

[0021] Depositing a second passivation layer and planarizing it, and depositing a SiNx thin film on the second passivation layer;

[0022] The SiNx film is processed by a patterning process to form the first waveguide structure.

[0023] According to a specific implementation of the embodiment of the present application, preparing and planarizing the first waveguide cladding of the first waveguide structure includes:

[0024] Depositing the first waveguide cladding based on a CVD process;

[0025] A chemical mechanical polishing process is used to perform a planarization process, so that the thickness of the first waveguide cladding layer above the first waveguide structure is reduced to a first preset thickness.

[0026] According to a specific implementation of the embodiment of the present application, the step of opening a hole above the metal electrode to form a first pad hole includes:

[0027] The second passivation layer and the first waveguide cladding layer above the metal electrode are opened by dry etching to form the first pad hole.

[0028] According to a specific implementation of the embodiment of the present application, patterning the electro-optical material film to form the second waveguide structure includes:

[0029] The electro-optical material film is patterned by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure.

[0030] According to a specific implementation of the embodiment of the present application, preparing and planarizing the second waveguide cladding of the second waveguide structure includes:

[0031] Depositing the second waveguide cladding based on a CVD process;

[0032] A chemical mechanical polishing process is used to perform a planarization process, so that the thickness of the second waveguide cladding layer above the second waveguide structure is reduced to a second preset thickness.

[0033] According to a specific implementation of the embodiment of the present application, the sum of the first preset thickness and the second preset thickness is less than 150 nm.

[0034] According to a specific implementation of the embodiment of the present application, bonding the first waveguide wafer to the second waveguide wafer includes:

[0035] performing cleaning and plasma activation on the first waveguide wafer and the second waveguide wafer in sequence;

[0036] Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device;

[0037] The pre-bonded device is annealed to complete the bonding.

[0038] According to a specific implementation of the embodiment of the present application, removing the second substrate includes:

[0039] The second substrate is removed by grinding or chemical mechanical polishing.

[0040] Beneficial effects:

[0041] The composite waveguide structure and preparation method in the embodiments of the present application indirectly align the pad windows on the first waveguide wafer and the second waveguide wafer through layout design according to the W2W bonding alignment relationship, thereby achieving the elimination of front-end processing such as photolithography etching and thin film preparation after W2W, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process; fully utilizing the flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer, and improving the process structure compatibility between the bonding area and the non-bonding area. For example, the thickness of the waveguide cladding between the LN-Si Nx layers in the bonding area and the thickness of the Si Nx waveguide cladding in the non-bonding area can be differentiated according to design requirements.

[0042] In addition, compared with the D2W bonding method, the present application reduces the risk of LN chip falling off during the removal of the Si substrate of LN, and can directly remove the Si substrate through chemical mechanical polishing, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow; compared with the D2W bonding method, the LN chip size of the present application can be smaller, thereby improving the integration of the optical chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 is a schematic diagram of a composite waveguide structure according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a process for preparing a composite waveguide structure according to an embodiment of the present invention;

[0046] Figure 3 Schematic diagram of preparing a first passivation layer according to one embodiment of the present invention;

[0047] Figure 4 Schematic diagram of preparing a metal electrode according to one embodiment of the present invention;

[0048] Figure 5 Schematic diagram of preparing a second passivation layer according to one embodiment of the present invention;

[0049] Figure 6 Schematic diagram of fabricating a Si Nx waveguide structure according to one embodiment of the present invention;

[0050] Figure 7 Schematic diagram of preparing a first waveguide cladding according to one embodiment of the present invention;

[0051] Figure 8 A schematic diagram of preparing a first pad hole according to an embodiment of the present invention;

[0052] Figure 9 Schematic diagram of preparing an electro-optical material substrate wafer according to one embodiment of the present invention;

[0053] Figure 10 Schematic diagram of preparing an LN waveguide structure according to one embodiment of the present invention;

[0054] Figure 11 Schematic diagram of preparing a second waveguide cladding according to one embodiment of the present invention;

[0055] Figure 12 A schematic diagram of preparing a second pad hole according to an embodiment of the present invention;

[0056] Figure 13 FIG. 4 is a schematic diagram of bonding a first waveguide wafer and a second waveguide wafer according to an embodiment of the present invention.

[0057] In the figure: 1. first substrate; 2. silicon dioxide film; 3. metal electrode; 4. first waveguide structure; 5. first pad hole; 6. electro-optical material film; 7. second substrate; 8. buried oxide layer; 9. second waveguide structure; 10. second pad hole. DETAILED DESCRIPTION

[0058] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0059] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0060] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0061] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0062] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0063] In a first aspect, the present invention provides a composite waveguide structure, referring to Figure 1The composite waveguide structure includes a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, wherein the first waveguide wafer includes a first substrate 1, a passivation layer arranged on the first substrate 1, and a first waveguide structure 4 and a metal electrode 3 arranged in the passivation layer, the metal electrodes 3 are arranged on both sides of the first waveguide structure 4, the upper side of the first waveguide structure 4 is covered with a first waveguide cladding, and the upper side of the metal electrode 3 is provided with a first pad hole 5; the waveguide film includes a second substrate 7, a buried oxide layer 8 arranged on the second substrate 7, and a second waveguide structure 9 arranged on the upper side of the buried oxide layer 8, second pad holes 10 are provided on both sides of the second waveguide structure 9, the upper side of the second waveguide structure 9 is covered with a second waveguide cladding, the second waveguide cladding is bonded to the first waveguide cladding, the position of the second waveguide structure 9 corresponds to the position of the first waveguide structure 4, and the position of the second pad hole 10 corresponds to the position of the first pad hole 5.

[0064] In a specific implementation, the waveguide film bonded to the first waveguide wafer can be a film formed by removing the second substrate from the second waveguide wafer. For example, the first waveguide wafer can be set as a SiNx waveguide wafer, and the second waveguide wafer can be set as an LN waveguide wafer.

[0065] In this embodiment, the upper and lower pad holes are set correspondingly. During actual preparation, indirect alignment can be performed through photolithography layout design, so that W2W is realized without the need for front-end processing such as photolithography etching and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process.

[0066] Secondly, refer to Figure 2 The present invention also provides a method for preparing a composite waveguide structure, which is used to prepare the composite waveguide structure as described in the first aspect. The method comprises the following steps:

[0067] Step S101: preparing a metal electrode 3 and a first waveguide structure 4 in sequence on a passivation layer of a first substrate 1, wherein the metal electrodes 3 are provided on both sides of the first waveguide structure 4;

[0068] Step S102: preparing and planarizing a first waveguide cladding layer on the first waveguide structure 4;

[0069] Step S103: drilling a hole above the metal electrode 3 to form a first pad hole 5 to obtain a first waveguide wafer;

[0070] Step S104: preparing an electro-optical material substrate wafer, wherein the electro-optical material substrate wafer includes a second substrate 7, a buried oxide layer 8, and an electro-optical material film 6 that are stacked;

[0071] Step S105 , patterning the electro-optical material film 6 to form a second waveguide structure 9 , and making the position of the second waveguide structure 9 correspond to the position of the first waveguide structure 4 through layout design;

[0072] Step S106: preparing a second waveguide cladding layer for the second waveguide structure 9 and planarizing the second waveguide cladding;

[0073] Step S107: drilling the second waveguide cladding layer and the buried oxide layer 8 to form a second pad hole 10, and making the position of the second pad hole 10 correspond to the position of the first pad hole 5 through layout design to obtain a second waveguide wafer;

[0074] Step S108: bonding the first waveguide wafer to the second waveguide wafer, and bonding the first waveguide cladding to the second waveguide cladding;

[0075] Step S109 , removing the second substrate 7 .

[0076] In a specific implementation, the structure after removing the second substrate 7 from the second waveguide wafer is a waveguide film bonded to the first waveguide wafer. In practical applications, the first waveguide wafer can be, for example, a SiNx waveguide wafer, and the first waveguide structure is a SiNx waveguide structure. The second waveguide wafer can be, for example, an LN waveguide wafer, and the second waveguide structure is an LN waveguide structure.

[0077] In this embodiment, according to the W2W bonding alignment relationship, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, thereby achieving the W2W without the need for front-end processing such as photolithography, etching, and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process; fully utilizing the flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer, and improving the process structure compatibility between the bonding area and the non-bonding area. For example, the waveguide cladding thickness between the LN-SiNx layers in the bonding area and the SiNx waveguide cladding thickness in the non-bonding area can be differentiated according to design requirements.

[0078] In addition, compared with the D2W bonding method, the present application reduces the risk of LN chip falling off during the removal of the Si substrate of LN, and can directly remove the Si substrate through chemical mechanical polishing, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow; compared with the D2W bonding method, the LN chip size of the present application can be smaller, thereby improving the integration of the optical chip.

[0079] During specific implementation, the first substrate 1 and the second substrate 7 may be configured as silicon substrates.

[0080] In one embodiment, referring to Figures 3 to 6The metal electrode 3 and the first waveguide structure 4 are sequentially prepared on the passivation layer of the first substrate 1, comprising:

[0081] A first passivation layer is deposited on the first substrate 1, such as Figure 3 As shown;

[0082] depositing a metal thin film on the first passivation layer;

[0083] The metal film is processed by a patterning process to form the metal electrode 3, such as Figure 4 As shown;

[0084] Deposit a second passivation layer and planarize it, e.g. Figure 5 As shown, a SiNx film is deposited on the second passivation layer;

[0085] The SiNx film is processed by a patterning process to form the first waveguide structure 4, as shown in FIG. Figure 6 shown.

[0086] During specific implementation, the patterning process may adopt processes such as photolithography and etching.

[0087] In a specific implementation, the first passivation layer and the second passivation layer can be respectively set as a silicon dioxide film 2. The specific preparation process of the metal electrode 3 and the first waveguide structure 4 includes:

[0088] First, a silicon dioxide film 2 is prepared on a silicon substrate, including: preparing a silicon dioxide film 2 with a thickness of 1 to 8 μm on the Si substrate by CVD or thermal oxidation growth;

[0089] The metal electrode 3 is prepared, specifically including: PVD deposition of a metal film with a thickness of 0.5 to 1.5 μm; and then forming a lead electrode structure through a patterning process such as photolithography and etching;

[0090] Prepare and planarize the second passivation layer: deposit silicon dioxide by CVD, and then planarize it by CMP until the thickness of the silicon dioxide film 2 above the metal electrode 3 is 200-500 nm;

[0091] SiNx film preparation and waveguide patterning: CVD deposits a SiNx film with a thickness of 100 to 500 nm and a refractive index of 1.9 to 2.2, and then forms the first waveguide structure 4 through patterning processes such as photolithography and etching.

[0092] In one embodiment, preparing and planarizing the first waveguide cladding of the first waveguide structure 4 includes:

[0093] Depositing the first waveguide cladding based on a CVD process;

[0094] A chemical mechanical polishing process is used to perform a planarization process, so that the thickness of the first waveguide cladding layer above the first waveguide structure 4 is reduced to a first preset thickness h1.

[0095] In a specific implementation, the first waveguide cladding is configured as a silicon dioxide film 2 , that is, the first passivation layer, the second passivation layer and the first waveguide cladding can all be configured as a silicon dioxide film 2 .

[0096] In one embodiment, the step of opening a hole above the metal electrode 3 to form the first pad hole 5 includes:

[0097] The second passivation layer and the first waveguide cladding layer above the metal electrode 3 are opened by dry etching to form the first pad hole 5 .

[0098] In specific implementation, the operation of opening a hole above the metal electrode 3 is called a pad window, and the metal pad can be exposed by dry etching of silicon dioxide. Generally, at least two first pad holes 5 are provided, for example, Figure 8 As shown in the figure, two first pad holes 5 are provided. In the actual process, the number of holes can be adjusted according to demand.

[0099] During specific implementation, the processing of the first waveguide wafer in the above embodiment can be compatible with the CMOS process, thereby improving the CMOS process compatibility of the W2W heterogeneous integration method.

[0100] The processing of the second waveguide wafer is described in detail below. The processing of the second waveguide wafer can be carried out using an external dedicated line in a CMOS process environment. For details, please refer to the following embodiment.

[0101] In specific implementation, the electro-optical material substrate wafer is set as a thin film LN substrate wafer, which is a commercially mature thin film LN substrate, wherein the electro-optical material film 6 is an LN thin film with a thickness of 100nm to 500nm. It is prepared using the Smart-cut process, which is a process technology that forms a damage layer by ion implanting the bulk LN and annealing it at 200 to 300°C, and then splits and falls off along the damage layer. The second substrate 7 is a Si base, wherein the buried oxide layer 8 has a thickness of 0.1 to 2μm. The buried oxide layer 8 is a SiO2 thin film prepared by thermal oxidation growth. The specific structure of the thin film LN substrate wafer is referred to. Figure 9 .

[0102] In one embodiment, referring to Figure 10 The electro-optical material film 6 is patterned to form a second waveguide structure 9, comprising:

[0103] The electro-optical material film 6 is patterned by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure 9 .

[0104] In practice, inductively coupled plasma-reactive ion etching is performed on the electro-optical material film 6 to form the second waveguide structure 9. It should be noted that during the patterned photolithography layout design of this step, the position of the second waveguide structure 9 must be determined based on the flip alignment relationship for subsequent W2W bonding with the first waveguide wafer, thereby achieving indirect alignment of the second waveguide structure 9 with the first waveguide structure 4 on the layout.

[0105] In one embodiment, referring to Figure 11 The step of preparing and flattening the second waveguide cladding of the second waveguide structure 9 includes:

[0106] Depositing the second waveguide cladding based on a CVD process;

[0107] A chemical mechanical polishing process is used to perform a planarization process, so that the thickness of the second waveguide cladding layer above the second waveguide structure 9 is reduced to a second preset thickness.

[0108] In specific implementation, the second waveguide cladding can be set to a SiO2 film, the SiO2 film is deposited by CVD, and is flattened by CMP until the thickness of the SiO2 film above the second waveguide structure 9 reaches a second preset thickness h2, and satisfies h1+h2<150nm, where h1 is the first preset thickness of the first waveguide cladding above the first waveguide structure 4 after the first waveguide cladding is flattened.

[0109] In one embodiment, the sum of the first preset thickness and the second preset thickness is less than 150 nm.

[0110] In one embodiment, for the formation of the second pad hole 10, refer to Figure 12 , dry-etch the second waveguide cladding and buried oxide layer 8 onto the Si substrate. The second pad hole 10 in this step needs to be indirectly aligned with the pad window on the first waveguide wafer according to the W2W bonding alignment relationship during the photolithography layout design.

[0111] In the above embodiment, the second waveguide wafer processing is realized. According to the W2W bonding alignment relationship, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, thereby realizing W2W without the need for front-end processing such as photolithography etching and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process.

[0112] The processing process of the LN-Si Nx composite waveguide is described in detail below, including the following contents.

[0113] In one embodiment, referring to Figure 13 , bonding the first waveguide wafer to the second waveguide wafer, comprising:

[0114] performing cleaning and plasma activation on the first waveguide wafer and the second waveguide wafer in sequence;

[0115] Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device;

[0116] The pre-bonded device is annealed to complete the bonding.

[0117] In specific implementation, the bonding strength can be improved by annealing. The temperature during annealing can be set to be less than 250°C. The second waveguide wafer is combined with the first waveguide wafer. Figure 13 The first pad hole 5 above the metal electrode 3 corresponds to the position of the second pad holes 10 on both sides of the second waveguide structure 9, and the second waveguide structure 9 corresponds to the first waveguide structure 4 in the bonding area.

[0118] In one embodiment, removing the second substrate 7 includes:

[0119] The second substrate 7 is removed by grinding or chemical mechanical polishing. The structure after removing the second substrate 7 is shown in FIG. Figure 1 shown.

[0120] Compared to D2W bonding, this embodiment reduces the risk of LN chips falling off during the removal of the Si substrate from the second waveguide wafer. The Si substrate can be removed directly via CMP, avoiding the issues of low processing efficiency and damage to SiNx waveguide devices associated with wet etching, while also simplifying the process. Furthermore, compared to D2W bonding, LN chips can be smaller, increasing the integration density of optical chips.

[0121] In the embodiment provided by the present invention, according to the W2W bonding alignment relationship, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, thereby achieving the W2W without the need for front-end processing such as photolithography etching and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process; fully utilizing the flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer, and improving the process structure compatibility between the bonding area and the non-bonding area. For example, the thickness of the waveguide cladding between the LN-SiNx layers in the bonding area and the thickness of the Si Nx waveguide cladding in the non-bonding area can be differentiated according to design requirements.

[0122] In addition, compared with the D2W bonding method, the present application reduces the risk of LN chip falling off during the removal of the Si substrate of LN, and can directly remove the Si substrate through chemical mechanical polishing, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow; compared with the D2W bonding method, the LN chip size of the present application can be smaller, thereby improving the integration of the optical chip.

[0123] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A composite waveguide structure, characterized in that: The invention comprises a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, wherein the first waveguide wafer comprises a first substrate (1), a passivation layer arranged on the first substrate (1), and a first waveguide structure (4) and a metal electrode (3) arranged in the passivation layer, the metal electrodes (3) being arranged on both sides of the first waveguide structure (4), the upper side of the first waveguide structure (4) being covered with a first waveguide cladding, and the upper side of the metal electrode (3) being provided with a first pad hole (5); the waveguide film comprises a second substrate (7), a buried oxide layer (8) arranged on the second substrate (7), and a second waveguide structure (9) being arranged on the upper side of the buried oxide layer (8), the second waveguide structure (9) being provided with second pad holes (10) on both sides, the upper side of the second waveguide structure (9) being covered with a second waveguide cladding, the second waveguide cladding being bonded to the first waveguide cladding, the position of the second waveguide structure (9) corresponding to the position of the first waveguide structure (4), and the position of the second pad hole (10) corresponding to the position of the first pad hole (5).

2. A method for preparing a composite waveguide structure, for preparing the composite waveguide structure according to claim 1, characterized in that: The method comprises: A metal electrode (3) and a first waveguide structure (4) are sequentially prepared on the passivation layer of the first substrate (1), wherein the metal electrodes (3) are arranged on both sides of the first waveguide structure (4); Preparing and flattening a first waveguide cladding layer on the first waveguide structure (4); Opening a hole above the metal electrode (3) to form a first pad hole (5) to obtain a first waveguide wafer; preparing an electro-optical material substrate wafer, the electro-optical material substrate wafer comprising a stacked second substrate (7), a buried oxide layer (8), and an electro-optical material film (6); Patterning the electro-optical material film (6) to form a second waveguide structure (9), and making the position of the second waveguide structure (9) correspond to the position of the first waveguide structure (4) through layout design; Preparing and flattening a second waveguide cladding layer on the second waveguide structure (9); The second waveguide cladding layer and the buried oxide layer (8) are opened to form a second pad hole (10), and the position of the second pad hole (10) is made to correspond to the position of the first pad hole (5) through layout design to obtain a second waveguide wafer; bonding the first waveguide wafer and the second waveguide wafer through the first waveguide cladding and the second waveguide cladding; The second substrate (7) is removed.

3. The method for preparing a composite waveguide structure according to claim 2, wherein: The metal electrode (3) and the first waveguide structure (4) are sequentially prepared on the passivation layer of the first substrate (1), comprising: Depositing a first passivation layer on the first substrate (1); depositing a metal thin film on the first passivation layer; Processing the metal film through a patterning process to form the metal electrode (3); Depositing a second passivation layer and planarizing it, and depositing a SiNx film on the second passivation layer; The SiNx film is patterned by a patterning process to form the first waveguide structure (4).

4. The method for preparing a composite waveguide structure according to claim 2, wherein: The step of preparing and flattening the first waveguide cladding of the first waveguide structure (4) comprises: Depositing the first waveguide cladding based on a CVD process; A chemical mechanical polishing process is used to perform a flattening process, so that the thickness of the first waveguide cladding layer above the first waveguide structure (4) is reduced to a first preset thickness.

5. The method for preparing a composite waveguide structure according to claim 3, wherein: The step of opening a hole above the metal electrode (3) to form a first pad hole (5) comprises: The second passivation layer and the first waveguide cladding layer above the metal electrode (3) are opened by dry etching to form the first pad hole (5).

6. The method for preparing a composite waveguide structure according to claim 2, wherein: The electro-optical material film (6) is patterned to form a second waveguide structure (9), comprising: The electro-optical material film (6) is patterned by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure (9).

7. The method for preparing a composite waveguide structure according to claim 4, wherein: The step of preparing and flattening the second waveguide cladding of the second waveguide structure (9) comprises: Depositing the second waveguide cladding based on a CVD process; A planarization process is performed through a chemical mechanical polishing process, so that the thickness of the second waveguide cladding layer above the second waveguide structure (9) is reduced to a second preset thickness.

8. The method for preparing a composite waveguide structure according to claim 7, wherein: The sum of the first preset thickness and the second preset thickness is less than 150 nm.

9. The method for preparing a composite waveguide structure according to claim 2, wherein: Bonding the first waveguide wafer to the second waveguide wafer includes: performing cleaning and plasma activation on the first waveguide wafer and the second waveguide wafer in sequence; Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device; The pre-bonded device is annealed to complete the bonding.

10. The method for preparing a composite waveguide structure according to claim 2, wherein: The removing of the second substrate (7) comprises: The second substrate (7) is removed by grinding or chemical mechanical polishing.

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