Method for determining error compensation, semiconductor structure and manufacturing method thereof

Abstract

Embodiments of the present application provide a method for determining error compensation, a semiconductor structure, and a manufacturing method thereof. The method for determining error compensation is applied to the manufacturing process of a semiconductor structure. The semiconductor structure includes a substrate, at least two measurement photolithography layers formed on the substrate, and an alignment photolithography layer formed on the side of the measurement photolithography layer away from the substrate. The method for determining error compensation includes: assigning measurement compensation weights to the measurement error compensations of each measurement photolithography layer according to the process window corresponding to each measurement photolithography layer; the measurement compensation weight is determined according to the ratio of the process window corresponding to a measurement photolithography layer to the process windows corresponding to all measurement photolithography layers; performing weighted summation on the measurement error compensations of at least two measurement photolithography layers, and using the weighted summation result as the measurement alignment error compensation of the alignment photolithography layer. Through the embodiments of the present application, the compensation ability of the measurement alignment error compensation is improved, and the alignment accuracy between different photolithography layers is increased.

Description

Technical Field

[0001] Embodiments in the present application relate to the field of semiconductor manufacturing technology, and particularly to a method for determining error compensation, a semiconductor structure, and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor devices towards high integration and miniaturization of dimensions, during the semiconductor processing, it may be necessary to stack multiple photolithography layers with different photolithography patterns to achieve multiple exposures of different photolithography patterns on the same wafer. To improve the performance of highly integrated semiconductor devices, precise alignment between multiple photolithography layers is required.

[0003] The alignment accuracy between multiple photolithography layers can be measured by overlay (OVL) error. Specifically, in a multi-layer photolithography process, the overlay error can be the alignment error of the photolithography layer being processed relative to the photolithography layer that has been processed. To meet the alignment accuracy requirements of advanced process nodes, it is necessary to compensate for the overlay error.

[0004] In the prior art, the overlay error compensation is usually determined based on measurement alignment error compensation and process alignment error compensation. However, the R & D personnel found that during the processing of some special semiconductor structures, applying the overlay error compensation determined by the existing method to the photolithography layer being processed still cannot make the processed semiconductor structure meet the alignment accuracy requirements. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application provide a method for determining error compensation, a semiconductor structure, and a manufacturing method thereof to improve the alignment accuracy during the manufacturing process of semiconductor structures.

[0006] In one aspect, an embodiment of the present application provides a method for determining error compensation, which is applied to the manufacturing process of a semiconductor structure; the semiconductor structure includes a substrate, at least two measurement photolithography layers formed on the substrate, and a alignment photolithography layer formed on the side of the measurement photolithography layer away from the substrate; the method includes: assigning a measurement compensation weight to the measurement error compensation of each measurement photolithography layer according to the process window corresponding to each measurement photolithography layer; wherein the measurement compensation weight is determined according to the ratio of the process window corresponding to one measurement photolithography layer to the process windows corresponding to all measurement photolithography layers; performing weighted summation on the measurement error compensations of the at least two measurement photolithography layers, and taking the weighted summation result as the measurement alignment error compensation of the alignment photolithography layer.

[0007] Optionally, the measurement compensation weight corresponding to each measurement photolithography layer is negatively correlated with the size of the process window corresponding to each measurement photolithography layer.

[0008] Optionally, the semiconductor structure is fabricated according to a structural coordinate system; wherein the structural coordinate system includes a first direction and a second direction that are perpendicular to each other; correspondingly, the process window includes a first process window along the first direction and a second process window along the second direction; the measurement error compensation includes a first measurement error compensation along the first direction and a second measurement error compensation along the second direction; the measurement compensation weight includes a first measurement compensation weight along the first direction and a second measurement compensation weight along the second direction; the step of assigning a measurement compensation weight to the measurement error compensation for each measurement photolithography layer according to the process window corresponding to each measurement photolithography layer includes: assigning a first measurement compensation weight to the first measurement error compensation corresponding to one measurement photolithography layer according to the ratio of one first process window to all the first process windows; assigning a second measurement compensation weight to the second measurement error compensation corresponding to one measurement photolithography layer according to the ratio of one second process window to all the second process windows.

[0009] Optionally, the method further includes: using an advanced process control model to assign a process compensation weight to the process error compensation for each measurement photolithography layer; performing weighted summation on the process error compensations of the at least two measurement photolithography layers, and using the weighted summation result as the process alignment error compensation for the alignment photolithography layer; determining the overlay error compensation for the alignment photolithography layer according to the measurement alignment error compensation and the process alignment error compensation.

[0010] In another aspect, an embodiment of the present application provides a semiconductor structure, including: a substrate; wherein the substrate includes a substrate and at least two measurement photolithography layers formed on the substrate; an alignment photolithography layer formed on a side of the measurement photolithography layer away from the substrate; wherein the measurement alignment error compensation of the alignment photolithography layer is determined by the error compensation determination method as described in the above embodiment.

[0011] Optionally, each measurement photolithography layer includes an alignment mark; during the exposure of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

[0012] Optionally, the distance between the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction is less than 1 um.

[0013] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate; wherein, the substrate includes a substrate and at least two measurement photolithography layers formed on the substrate; forming a registration photolithography layer on a side of the measurement photolithography layer away from the substrate; wherein, the measurement alignment error compensation of the registration photolithography layer is determined by the error compensation determination method as described in the above embodiment.

[0014] Optionally, the step of providing a substrate includes: providing a substrate; sequentially forming the at least two measurement photolithography layers on one side of the substrate; wherein, each of the measurement photolithography layers includes an alignment mark; during the exposure of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

[0015] Optionally, the step of sequentially forming the at least two measurement photolithography layers on one side of the substrate includes: repeatedly executing the following sub-steps until the at least two measurement photolithography layers are formed; wherein, the spacing distance of the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction is less than 1um; the sub-steps include: forming a photolithography material layer; preparing an alignment mark in the photolithography material layer to obtain a measurement photolithography layer.

[0016] Optionally, the photolithography material layer includes a bottom anti-reflection coating close to the substrate and a photoresist layer away from the substrate; the step of preparing an alignment mark in the photolithography material layer to obtain a measurement photolithography layer formed on the surface of the substrate includes: exposing the photoresist layer to form an alignment mark in the photoresist layer; transferring the pattern of the alignment mark from the photoresist layer to the bottom anti-reflection coating; removing the photoresist layer, and using the bottom anti-reflection coating formed with the alignment mark as the measurement photolithography layer.

[0017] In multiple embodiments of the present application, for a semiconductor structure including a substrate, at least two measurement photolithography layers formed on the substrate, and a registration photolithography layer formed on a side of the measurement photolithography layer away from the substrate, according to the ratio of the process window corresponding to a single measurement photolithography layer to the process window corresponding to all measurement photolithography layers, a measurement compensation weight is assigned to the measurement error compensation of the measurement photolithography layer, and then the measurement error compensations of at least two measurement photolithography layers are weighted and summed, and the weighted sum result is used as the measurement alignment error compensation of the registration photolithography layer. The unexpected effects achieved include: during the process of determining the measurement alignment error compensation, the influence of the process windows of multiple measurement photolithography layers on the measurement alignment error compensation is introduced, the compensation ability of the measurement alignment error compensation is improved, and the alignment accuracy between different photolithography layers in the semiconductor structure is improved. Description of the Drawings

[0018] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for describing the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0019] Figure 1 A schematic block diagram of a method for determining overlay error compensation provided by the related art.

[0020] Figure 2 A schematic flowchart of a method for determining error compensation provided by an embodiment of the present application.

[0021] Figure 3 A schematic block diagram of a method for determining overlay error compensation provided by an embodiment of the present application.

[0022] Figure 4 A schematic flowchart of a manufacturing method for a semiconductor structure provided by an embodiment of the present application.

[0023] Figure 5 A schematic flowchart of providing a substrate provided by an embodiment of the present application.

[0024] Figure 6 A schematic diagram of forming a first photolithography material layer on a substrate provided by an embodiment of the present application.

[0025] Figure 7 A schematic diagram of exposing and forming a first alignment mark on the first photoresist layer provided by an embodiment of the present application.

[0026] Figure 8 A schematic diagram of transferring the first alignment mark to the first bottom anti-reflection coating provided by an embodiment of the present application.

[0027] Figure 9 A schematic diagram of forming a second photolithography material layer on the first metrology photolithography layer provided by an embodiment of the present application.

[0028] Figure 10 A schematic diagram of exposing and forming a second alignment mark on the second photoresist layer provided by an embodiment of the present application.

[0029] Figure 11 A schematic diagram of transferring the second alignment mark to the second bottom anti-reflection coating provided by an embodiment of the present application.

[0030] Figure 12 A schematic diagram of forming a registration photolithography layer on the second metrology photolithography layer provided by an embodiment of the present application.

[0031] Structure label description

[0032] 10. Exposure machine; 11. Alignment marks of the second processed photolithography layer; 12. Measured alignment error of the second processed photolithography layer; 13. Measured alignment error compensation; 14. APC model; 15. Process error compensation of the first processed photolithography layer; 16. Process compensation weight of the first processed photolithography layer; 17. Process error compensation of the second processed photolithography layer; 18. Process compensation weight of the second processed photolithography layer; 19. Process alignment error compensation; 20. Alignment marks of the first measured photolithography layer; 21. Measured alignment error of the first measured photolithography layer; 22. Measured error compensation of the first measured photolithography layer; 23. Alignment marks of the second measured photolithography layer; 24. Measured alignment error of the second measured photolithography layer; 25. Measured error compensation of the second measured photolithography layer; 26. Process window of the first measured photolithography layer; 27. Measured compensation weight of the first measured photolithography layer; 28. Process window of the second measured photolithography layer; 29. Measured compensation weight of the second measured photolithography layer; 30. Solving model for overlay error compensation; 31. Overlay error compensation; 41. Process error compensation of the first measured photolithography layer; 42. Process compensation weight of the first measured photolithography layer; 43. Process error compensation of the second measured photolithography layer; 44. Process compensation weight of the second measured photolithography layer; 100. Substrate; 110. Substrate; 120. First photolithography material layer; 121. First bottom anti-reflection coating; 122. First photoresist layer; 130. First alignment marks; 140. Second photolithography material layer; 141. Second bottom anti-reflection coating; 142. Second photoresist layer; 150. Second alignment marks; 160. Alignment photolithography layer; 161. Alignment bottom anti-reflection coating; 162. Alignment photoresist layer. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0034] The accompanying drawings provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. The components shown in the drawings only show the components related to the present application, rather than being drawn according to the number, shape, and size of the components in actual implementation. The forms, quantities, and proportions of the components in actual implementation may be changed, and the layout form of the components may also be more complex.

[0035] In the description of the embodiments of the present application, it should be understood that terms such as "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. Terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the said features.

[0036] As the semiconductor process node continues to shrink, during the process of achieving alignment between multiple lithography layers, the range allowing alignment offset between different lithography layers continues to narrow, that is, the overlay error window between different lithography layers continues to decrease. Especially in advanced process nodes below 40nm, even a tiny overlay error may lead to a significant decrease in production yield or a significant reduction in the performance of semiconductor devices. Therefore, in related technologies, based on multiple lithography layers that have been processed, it is necessary to use overlay error compensation to compensate for the overlay error of the lithography layer being processed to improve the alignment accuracy of semiconductor devices.

[0037] In related technologies, generally, an exposure machine determines overlay error compensation based on measurement alignment error compensation and process alignment error compensation. Taking the process alignment error compensation calculated based on the process alignment errors of two processed lithography layers as an example, where the first processed lithography layer is the first processed lithography layer and the processed lithography layer adjacent to the lithography layer being processed is the second processed lithography layer, the exposure machine can determine the overlay error compensation through the following process.

[0038] Please refer to Figure 1 . Since each processed lithography layer has an alignment mark, the exposure machine 10 can measure the alignment mark 11 of the second processed lithography layer to obtain the measured position information of the alignment mark 11 of the second processed lithography layer on the second processed lithography layer. Based on this measured position information and the designed position of the alignment mark 11 of the second processed lithography layer on the second processed lithography layer, the measured alignment error 12 of the second processed lithography layer is obtained, and then the measurement alignment error compensation 13 is calculated based on the measured alignment error 12 of the second processed lithography layer.

[0039] Moreover, the exposure machine 10 can calculate the process error compensation 15 of the first completed processed photolithography layer and the process error compensation 17 of the second completed processed photolithography layer by using a preset APC (Advanced Process Control) model 14, and assign process compensation weights to the process error compensations of the two completed processed photolithography layers according to a preset weighting algorithm, that is, the process compensation weight 16 of the first completed processed photolithography layer and the process compensation weight 18 of the second completed processed photolithography layer, perform weighted summation on the process error compensation 15 of the first completed processed photolithography layer and the process error compensation 17 of the second completed processed photolithography layer, and use the weighted summation result as the process alignment error compensation 19.

[0040] Finally, the measurement alignment error compensation 13 and the process alignment error compensation 19 can be jointly input into a preset overlay error compensation solving model 30, and the output result of the overlay error compensation solving model 30 is used as the overlay error compensation 31.

[0041] For some semiconductor devices that need to implement special functions, their structural design requires the exposure machine to control the overlay error between the photolithography layer being processed and multiple completed processed photolithography layers. However, from the above determination process of the overlay error compensation, it can be seen that the process alignment error compensation can be calculated based on the process alignment errors of multiple completed processed photolithography layers, while the measurement alignment error compensation can only be calculated based on the measurement alignment error of a single completed processed photolithography layer, and it is impossible to calculate the measurement alignment error compensation based on the measurement alignment errors of multiple completed processed photolithography layers, resulting in a weak compensation ability of the measurement alignment error compensation, reducing the control ability of the exposure machine for the overlay error, and further resulting in the alignment accuracy of the semiconductor device manufactured after performing overlay error compensation using the above process still not meeting the alignment accuracy requirements of the device.

[0042] Therefore, it is necessary to provide a method for determining error compensation. For a semiconductor structure including a substrate, at least two measurement photolithography layers formed on the substrate, and a alignment photolithography layer formed on the side of the measurement photolithography layer away from the substrate, according to the ratio of the process window corresponding to a single measurement photolithography layer to the process window corresponding to all measurement photolithography layers, assign a measurement compensation weight to the measurement error compensation of the measurement photolithography layer, and then perform weighted summation on the measurement error compensations of at least two measurement photolithography layers, and use the weighted summation result as the measurement alignment error compensation of the alignment photolithography layer, so as to introduce the influence of the process windows of multiple measurement photolithography layers on the measurement alignment error compensation during the determination of the measurement alignment error compensation, improve the compensation ability of the measurement alignment error compensation, and improve the alignment accuracy of the semiconductor structure.

[0043] An embodiment of the present application provides a method for determining error compensation, which can be applied to the manufacturing process of a semiconductor structure. The semiconductor structure may include a substrate, at least two measurement photolithography layers formed on the substrate, and an alignment photolithography layer formed on a side of the measurement photolithography layer away from the substrate.

[0044] In this embodiment, the substrate can serve as the basis for forming the semiconductor structure. Specifically, the substrate can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate can be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), etc. The substrate can be a single-layer structure or a multi-layer structure. In this embodiment, considering factors such as dielectric loss requirements, manufacturing processes, and manufacturing costs, a silicon wafer is used as the substrate.

[0045] In this embodiment, the measurement photolithography layer can be an already formed photolithography layer. Specifically, a photolithography pattern can be formed in the measurement photolithography layer. The photolithography pattern can include a circuit pattern and an alignment mark. The circuit patterns formed on different measurement photolithography layers can be different, and the alignment marks can be the same. The number of measurement photolithography layers is at least two, and the specific number can be determined according to the design requirements of the semiconductor structure.

[0046] In this embodiment, the alignment photolithography layer can be a photolithography layer being processed. Specifically, to meet the design requirements of the semiconductor structure, the alignment accuracy between the alignment photolithography layer and at least two measurement photolithography layers needs to meet the specified alignment accuracy requirements.

[0047] Please refer to Figure 2 . The method for determining the error compensation may include S110 and S120.

[0048] S110: Assign a measurement compensation weight to the measurement error compensation of each measurement photolithography layer according to the process window corresponding to each measurement photolithography layer.

[0049] Limited by the accuracy of the photolithography process, the actual position of the photolithography pattern on the measurement photolithography layer will deviate from the reference position determined according to the design requirements on the measurement photolithography layer. In this embodiment, the process window corresponding to the measurement photolithography layer can represent the allowable deviation range of the photolithography pattern on the measurement photolithography layer under the process node corresponding to the semiconductor structure.

[0050] In this embodiment, the measurement error compensation can be calculated by the exposure machine based on the measurement alignment error. Specifically, for each measurement photolithography layer, the exposure machine can first measure the alignment marks in the measurement photolithography layer to obtain the measurement position information of the alignment marks in the measurement photolithography layer, compare the measurement position represented by the measurement position information with the designed position of the alignment marks on the measurement photolithography layer, and use the offset of the measurement position relative to the designed position as the measurement alignment error of the measurement photolithography layer. Subsequently, the exposure machine can use a preset measurement error compensation solving algorithm to calculate the measurement error compensation based on the measurement alignment error.

[0051] To introduce the influence of the process window of different measurement photolithography layers into the measurement alignment error compensation, in this embodiment, the measurement compensation weight can be determined according to the ratio of the process window corresponding to a measurement photolithography layer to the process windows corresponding to all measurement photolithography layers.

[0052] The process window can be used as a measure of the dimensional accuracy requirement. The smaller the process window, the higher the dimensional accuracy requirement. Therefore, to improve the compensation ability of the measurement alignment error compensation and the alignment accuracy of the semiconductor structure, in some embodiments, the measurement compensation weight corresponding to each measurement photolithography layer is negatively correlated with the size of the process window corresponding to each measurement photolithography layer. Specifically, the measurement compensation weight corresponding to the measurement photolithography layer with a smaller process window is larger, and conversely, the measurement compensation weight corresponding to the measurement photolithography layer with a larger process window is smaller.

[0053] To improve the manufacturing process quality of the semiconductor result, in some embodiments, the semiconductor structure can be manufactured according to the structure coordinate system. Specifically, the structure coordinate system can use a selected point on the wafer, such as the center point of the wafer, as the coordinate origin, and extend the first direction and the second direction perpendicular to each other from the coordinate origin. Limited by the lithography process accuracy and the measurement accuracy, the dimensional deviations of the lithography pattern in different directions are different. For example, the lithography pattern includes a circle with a designed diameter of 10 nm. After measurement by the R & D personnel, it is found that the actual diameter of the circle in the first direction is 9.8 nm, and the actual diameter in the second direction is 10.5 nm.

[0054] Since the dimensional deviations of the lithography pattern in different directions are different, to control the dimensional accuracy and alignment accuracy of the lithography pattern in different directions, in this embodiment, the process window can include a first process window in the first direction and a second process window in the second direction. The measurement error compensation can include a first measurement error compensation in the first direction and a second measurement error compensation in the second direction. The measurement compensation weight can include a first measurement compensation weight in the first direction and a second measurement compensation weight in the second direction.

[0055] Correspondingly, in this embodiment, the step of assigning measurement compensation weights to the measurement error compensation of each measurement photolithography layer according to the process window corresponding to each measurement photolithography layer may include: assigning a first measurement compensation weight to the first measurement error compensation corresponding to a measurement photolithography layer according to the ratio of a first process window to all first process windows; assigning a second measurement compensation weight to the second measurement error compensation corresponding to a measurement photolithography layer according to the ratio of a second process window to all second process windows. Specifically, in each direction, the sum of the measurement compensation weights of all measurement photolithography layers is 1, that is, the sum of the first measurement compensation weights of all measurement photolithography layers is 1, and the sum of the second measurement compensation weights of all measurement photolithography layers is 1.

[0056] Taking the case where there are two measurement photolithography layers formed on the substrate, where the measurement photolithography layer close to the substrate is the first measurement photolithography layer and the measurement photolithography layer far from the substrate is the second measurement photolithography layer as an example, the first measurement compensation weight and the second measurement compensation weight can be assigned to the first measurement photolithography layer according to the following Formula 1 and Formula 2, and the first measurement compensation weight and the second measurement compensation weight can be assigned to the second measurement photolithography layer according to the following Formula 3 and Formula 4.

[0057] Formula 1

[0058] Formula 2

[0059] Formula 3

[0060] Formula 4

[0061] Wherein, is the first measurement compensation weight of the first measurement photolithography layer, is the second measurement compensation weight of the first measurement photolithography layer, is the first measurement compensation weight of the second measurement photolithography layer, is the second measurement compensation weight of the second measurement photolithography layer, is the first process window of the first measurement photolithography layer, is the second process window of the first measurement photolithography layer, is the first process window of the second measurement photolithography layer, is the second process window of the second measurement photolithography layer.

[0062] In the case where there are three or more measurement photolithography layers formed on the substrate, the above formulas can be adjusted, and the first measurement compensation weight and the second measurement compensation weight of different measurement photolithography layers can be calculated according to the adjusted formulas.

[0063] S120: Perform weighted summation on the measurement error compensations of at least two measurement photolithography layers, and use the result of the weighted summation as the measurement alignment error compensation for the alignment photolithography layer.

[0064] By assigning measurement compensation weights to the measurement error compensations corresponding to each measurement photolithography layer, then performing weighted summation, and using the result of the weighted summation as the measurement alignment error compensation for the alignment photolithography layer, it is possible to determine the overall measurement alignment error compensation based on the measurement alignment errors of each measurement photolithography layer, thereby improving the compensation ability of the measurement alignment error compensation.

[0065] In some embodiments, the method for determining the error compensation further includes: using an advanced process control model to assign process compensation weights to the process error compensations of each measurement photolithography layer; performing weighted summation on the process error compensations of at least two measurement photolithography layers, and using the result of the weighted summation as the process alignment error compensation for the alignment photolithography layer; determining the overlay error compensation for the alignment photolithography layer based on the measurement alignment error compensation and the process alignment error compensation.

[0066] In this embodiment, the methods for determining the process alignment error compensation and the overlay error compensation are similar to those used in the related art, and will not be elaborated here.

[0067] Please refer to Figure 3 ... Taking the case where both the measurement alignment error compensation and the process alignment error compensation are calculated based on two measurement photolithography layers, where the measurement photolithography layer close to the substrate is the first measurement and processing photolithography layer, and the measurement photolithography layer far from the substrate is the second measurement photolithography layer as an example, in this embodiment, the exposure machine can determine the overlay error compensation applied to the alignment photolithography layer through the following process.

[0068] First, the exposure machine 10 can measure the alignment mark 20 of the first measurement photolithography layer to obtain the measured position information of the alignment mark 20 of the first measurement photolithography layer on the first measurement photolithography layer. Based on this measured position information and the designed position of the alignment mark 20 of the first measurement photolithography layer on the first measurement photolithography layer, the measurement alignment error 21 of the first measurement photolithography layer is obtained, and then the measurement error compensation 22 of the first measurement photolithography layer is calculated based on the measurement alignment error 21 of the first measurement photolithography layer. The exposure machine 10 can use a similar method to obtain the measurement alignment error 24 of the second measurement photolithography layer according to the measurement of the alignment mark 23 of the second measurement photolithography layer, and then calculate the measurement error compensation 25 of the second measurement photolithography layer based on the measurement alignment error 24 of the second measurement photolithography layer.

[0069] Subsequently, the exposure machine 10 can determine the measurement compensation weight 27 of the first measured photolithography layer and the measurement compensation weight 29 of the second measured photolithography layer according to the process window 26 of the first measured photolithography layer and the process window 28 of the second measured photolithography layer. Perform weighted summation on the measurement error compensation 22 of the first measured photolithography layer and the measurement error compensation 25 of the second measured photolithography layer, and use the weighted summation result as the measurement alignment error compensation 13.

[0070] Moreover, the exposure machine 10 can calculate the process error compensation 41 of the first measured photolithography layer and the process error compensation 43 of the second measured photolithography layer by using the APC model 14, and assign process compensation weights to the process error compensations of the two measured photolithography layers according to a preset weighting algorithm, that is, the process compensation weight 42 of the first measured photolithography layer and the process compensation weight 44 of the second measured photolithography layer. Perform weighted summation on the process error compensation 41 of the first measured photolithography layer and the process error compensation 43 of the second measured photolithography layer, and use the weighted summation result as the process alignment error compensation 19.

[0071] Finally, the measurement alignment error compensation 13 and the process alignment error compensation 19 can be jointly input into the overlay error compensation solving model 30, and the output result of the overlay error compensation solving model 30 is used as the overlay error compensation 31.

[0072] Compare Figure 1 and Figure 3 It can be seen that since the influence of the process windows of all measured photolithography layers is introduced into the measurement alignment error compensation 13, the compensation ability of the measurement alignment error compensation 13 is improved, and further the compensation ability of the overlay error compensation 31 determined based on the measurement alignment error compensation 13 is improved, and the alignment accuracy between different photolithography layers in the semiconductor structure is improved.

[0073] Please refer to Figure 4 . An embodiment of the present application provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure can be used to manufacture a semiconductor structure including at least two measured photolithography layers and a registration photolithography layer.

[0074] The manufacturing method of the semiconductor structure may include steps S210 and S220.

[0075] S210: Provide a substrate.

[0076] In this embodiment, the substrate may include a substrate and at least two measured photolithography layers formed on the substrate. To reduce the process complexity, each measured photolithography layer can be formed by the same process.

[0077] Please refer to Figure 5 . In some embodiments, the step of providing a substrate may include S211 and S212.

[0078] S211: Provide a substrate.

[0079] S212: Sequentially form at least two measurement photolithography layers on one side of the substrate.

[0080] In some embodiments, the step of sequentially forming at least two measurement photolithography layers on one side of the substrate may include: repeatedly performing the following sub-steps until at least two measurement photolithography layers are formed; the sub-steps may include: forming a photolithography material layer; preparing alignment marks in the photolithography material layer to obtain a measurement photolithography layer.

[0081] To reduce the standing wave effect and other optical interferences caused by the reflection of the wafer surface during the photolithography process and improve the photolithography accuracy, in this embodiment, the photolithography material layer may include a bottom anti-reflective coating (BARC) close to the substrate and a photoresist layer (PR) far from the substrate. Specifically, the thickness of the photoresist layer and the thickness of the bottom anti-reflective coating may match each other, and the embodiments of the present application do not specifically limit the thicknesses of the photoresist layer and the bottom anti-reflective coating.

[0082] In this embodiment, the alignment marks can be used to assist the exposure machine in obtaining the measurement alignment errors of each measurement photolithography layer. Specifically, to reduce the recognition difficulty of the alignment marks by the exposure machine, the structure of the alignment marks can be different from the structure of the circuit pattern. For example, the alignment marks can be composed of multiple bar-shaped structures arranged at intervals, or the alignment marks can be an irregular structure. The embodiments of the present application do not specifically limit the structure of the alignment marks.

[0083] To reduce the number of exposures of the exposure machine and lower the process cost, in this embodiment, each measurement photolithography layer may include alignment marks. During the exposure of the substrate, the alignment marks in different measurement photolithography layers can be located in the same exposure window, so that the measurement position information of the alignment marks in all measurement photolithography layers can be obtained by using a single exposure. Specifically, the exposure window can be the range that can be covered by a single exposure of the exposure machine. The size of the exposure window can be determined by the equipment parameters of the exposure machine. To adapt to the equipment parameters of various exposure machines, the spacing distances of the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction can be less than 1 um.

[0084] To facilitate the exposure machine to identify the alignment marks in different measurement photolithography layers during a single exposure, in this embodiment, the structures of the alignment marks in different measurement photolithography layers can be the same. In some cases, to meet the design requirements of special structures, the structures of the alignment marks in different measurement photolithography layers can also be different.

[0085] To improve the fidelity of lithographic patterns during the manufacturing process of semiconductor structures, reduce the damage to lithographic patterns in subsequent processes, and mitigate the adverse effects of lithographic pattern damage on the alignment accuracy of multiple lithographic layers, in some embodiments, the step of fabricating alignment marks in a lithographic material layer to obtain a measurement lithographic layer formed on the surface of a substrate may include: exposing a photoresist layer to form alignment marks in the photoresist layer; transferring the pattern of the alignment marks from the photoresist layer to a bottom anti-reflection coating; removing the photoresist layer, and using the bottom anti-reflection coating with the formed alignment marks as the measurement lithographic layer.

[0086] Taking the formation of two measurement lithographic layers on a substrate as an example, the formation process of the substrate will be briefly introduced.

[0087] Please refer to Figure 6 . First, a first lithographic material layer 120 can be formed on a substrate 110. Specifically, the first lithographic material layer 120 may include a first bottom anti-reflection coating 121 adjacent to the substrate 110 and a first photoresist layer 122.

[0088] Please refer to Figure 7 . Subsequently, the first photoresist layer 122 can be exposed to form a first alignment mark 130 in the first photoresist layer 122. Specifically, during the exposure of the first photoresist layer 122, a lithographic pattern including the pattern of the first alignment mark 130 can be transferred from a mask to the first photoresist layer 122.

[0089] Please refer to Figure 8 . Then, the first photoresist layer 122 can be used as a mask for the first bottom anti-reflection coating 121, and the lithographic pattern on the first photoresist layer 122 can be transferred to the first bottom anti-reflection coating 121, thereby forming a first alignment mark 130 in the first bottom anti-reflection coating 121. The first photoresist layer 122 is removed by a dry etching process or a wet etching process, and the remaining first bottom anti-reflection coating 121 with the formed first alignment mark 130 is used as the first measurement lithographic layer.

[0090] Please refer to Figures 9 to 11 . A second lithographic material layer 140 including a second bottom anti-reflection coating 141 and a second photoresist layer 142 can be formed on the side of the first measurement lithographic layer away from the substrate 110. The second photoresist layer 142 is exposed to form a second alignment mark 150 in the second photoresist layer 142, and the pattern of the second alignment mark 150 is transferred to the second bottom anti-reflection coating 141. The second photoresist layer 142 is removed, and the second bottom anti-reflection coating 141 with the formed second alignment mark 150 is used as the second measurement lithographic layer, obtaining a substrate 100 with two measurement lithographic layers formed on the substrate 110.

[0091] In this embodiment, the process parameters used to form the first measurement photolithography layer may be the same as those used to form the second measurement photolithography layer.

[0092] S220: Form a alignment photolithography layer on the side of the measurement photolithography layer away from the substrate.

[0093] Please refer to Figure 12 . In this embodiment, the alignment photolithography layer 160 may include an alignment bottom anti-reflection coating 161 close to the substrate 110 and an alignment photoresist layer 162 away from the substrate 110. The measurement alignment error compensation of the alignment photolithography layer 160 can be determined by the error compensation determination method described in any of the above embodiments.

[0094] An embodiment of the present application provides a semiconductor structure, which may include: a substrate; wherein, the substrate may include a substrate and at least two measurement photolithography layers formed on the substrate; an alignment photolithography layer formed on the side of the measurement photolithography layer away from the substrate. Wherein, the measurement alignment error compensation of the alignment photolithography layer can be determined by the error compensation determination method described in any of the above embodiments.

[0095] To reduce the number of exposures of the exposure machine, in some embodiments, each measurement photolithography layer may include alignment marks. During the exposure of the substrate, the alignment marks in different measurement photolithography layers may be located in the same exposure window.

[0096] To adapt to the equipment parameters of different exposure machines, in some embodiments, the spacing distances of the alignment marks in different measurement photolithography layers along the horizontal or vertical direction may be less than 1um.

[0097] Regarding the manufacturing method of the semiconductor structure described in the above embodiments and other technical effects of the semiconductor structure, reference can be made to other embodiments of the present application for comparison and explanation, which will not be elaborated here.

[0098] In the embodiment of the present application, for a semiconductor structure including a substrate, at least two measurement photolithography layers formed on the substrate, and an alignment photolithography layer formed on the side of the measurement photolithography layer away from the substrate, according to the ratio of the process window corresponding to a single measurement photolithography layer to the process window corresponding to all measurement photolithography layers, a measurement compensation weight is assigned to the measurement error compensation of the measurement photolithography layer, and then the measurement error compensations of at least two measurement photolithography layers are weighted and summed, and the weighted sum result is used as the measurement alignment error compensation of the alignment photolithography layer. The unexpected effects achieved include: during the process of determining the measurement alignment error compensation, the influence of the process windows of multiple measurement photolithography layers on the measurement alignment error compensation is introduced, thereby improving the compensation ability of the measurement alignment error compensation and the overall compensation ability of the overlay error compensation, and improving the alignment accuracy of the semiconductor structure.

[0099] In some embodiments of the present application, the overlay error determined by the method for determining error compensation according to the above embodiments can be applied to the manufacturing processes of multiple batches of the semiconductor structures described in the above embodiments.

[0100] It can be understood that the specific examples in the present application are only for helping those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the present application.

[0101] It can be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the various processes do not mean the sequence of execution. The execution sequence of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0102] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0103] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meaning as commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the embodiments of the present application and the appended claims includes any and all combinations of one or more of the related listed items. The singular forms "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0104] In several embodiments provided by the present application, it should be understood that the disclosed pixel structures and image sensors can be implemented in other ways. For example, the embodiments of the pixel structures and image sensors described above are merely illustrative.

[0105] As described above, only the specific embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the technical field of the present application can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for determining error compensation, characterized in that, The method is applied to the manufacturing process of a semiconductor structure; the semiconductor structure includes a substrate, at least two measurement photolithography layers formed on the substrate, and an alignment photolithography layer formed on a side of the measurement photolithography layers away from the substrate; the method includes: According to the process window corresponding to each of the measurement photolithography layers, assign a measurement compensation weight to the measurement error compensation of each of the measurement photolithography layers; wherein, the measurement compensation weight is determined according to the ratio of the process window corresponding to one of the measurement photolithography layers to the process windows corresponding to all of the measurement photolithography layers; the measurement compensation weight corresponding to each of the measurement photolithography layers is negatively correlated with the size of the process window corresponding to each of the measurement photolithography layers; Perform weighted summation on the measurement error compensations of the at least two measurement photolithography layers, and use the weighted summation result as the measurement alignment error compensation of the alignment photolithography layer.

2. The method according to claim 1, characterized in that Manufacture the semiconductor structure according to a structure coordinate system; wherein, the structure coordinate system includes a first direction and a second direction perpendicular to each other; correspondingly, the process window includes a first process window along the first direction and a second process window along the second direction; the measurement error compensation includes a first measurement error compensation along the first direction and a second measurement error compensation along the second direction; the measurement compensation weight includes a first measurement compensation weight along the first direction and a second measurement compensation weight along the second direction; the step of assigning a measurement compensation weight to the measurement error compensation of each of the measurement photolithography layers according to the process window corresponding to each of the measurement photolithography layers includes: Assign a first measurement compensation weight to the first measurement error compensation corresponding to one of the measurement photolithography layers according to the ratio of one of the first process windows to all of the first process windows; Assign a second measurement compensation weight to the second measurement error compensation corresponding to one of the measurement photolithography layers according to the ratio of one of the second process windows to all of the second process windows.

3. The method according to claim 1, characterized in that The method further includes: Use an advanced process control model to assign a process compensation weight to the process error compensation of each of the measurement photolithography layers; Perform weighted summation on the process error compensations of the at least two measurement photolithography layers, and use the weighted summation result as the process alignment error compensation of the alignment photolithography layer; Determine the overlay error compensation of the alignment photolithography layer according to the measurement alignment error compensation and the process alignment error compensation.

4. A semiconductor structure, characterized in that, Includes: A substrate; wherein, the substrate includes a substrate and at least two measurement photolithography layers formed on the substrate; An alignment photolithography layer formed on a side of the measurement photolithography layers away from the substrate; wherein, the measurement alignment error compensation of the alignment photolithography layer is determined by the error compensation determination method described in any one of claims 1 to 3.

5. The semiconductor structure according to claim 4, wherein Each of the measurement photolithography layers includes an alignment mark; during the exposure of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

6. The semiconductor structure according to claim 5, characterized in that The interval distance of the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction is less than 1um.

7. A manufacturing method of a semiconductor structure, characterized in that, Includes: Provide a substrate; wherein, the substrate includes a substrate and at least two measurement photolithography layers formed on the substrate; Form an alignment photolithography layer on a side of the measurement photolithography layer away from the substrate; wherein, the measurement alignment error compensation of the alignment photolithography layer is determined by the error compensation determination method as described in any one of claims 1 to 3.

8. The method according to claim 7, wherein The step of providing a substrate includes: Provide a substrate; Form the at least two measurement photolithography layers in sequence on one side of the substrate; wherein, each of the measurement photolithography layers includes an alignment mark; during the exposure of the substrate, the alignment marks in different measurement photolithography layers are located in the same exposure window.

9. The method according to claim 8, wherein The step of forming the at least two measurement photolithography layers in sequence on one side of the substrate includes: Repeatedly execute the following sub-steps until the at least two measurement photolithography layers are formed; wherein, the spacing distance of the alignment marks in different measurement photolithography layers along the horizontal direction or the vertical direction is less than 1um; the sub-steps include: Form a photolithography material layer; Prepare an alignment mark in the photolithography material layer to obtain a measurement photolithography layer.

10. The method according to claim 9, wherein The photolithography material layer includes a bottom anti-reflection coating close to the substrate and a photoresist layer away from the substrate; the step of preparing an alignment mark in the photolithography material layer to obtain a measurement photolithography layer formed on the surface of the substrate includes: Expose the photoresist layer to form an alignment mark in the photoresist layer; Transfer the pattern of the alignment mark from the photoresist layer to the bottom anti-reflection coating; Remove the photoresist layer, and use the bottom anti-reflection coating with the alignment mark formed thereon as the measurement photolithography layer.

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