Read data receiving method for PSRAM controller

Abstract

The invention discloses a read data receiving method for a PSRAM controller. The read data receiving method comprises the steps that a gating signal of dqs is designed and achieved; directly adopting dqs delay to sample a dq signal according to the gating signal; a dq signal obtained through sampling is isolated through a register and finally enters a chip, and read data receiving of the PSRAM controller is completed. According to the read data receiving method for the PSRAM controller, through innovative reading process design and mechanism innovation, read data receiving of the PSRAM controller is achieved, and the read data receiving method is low in cost, good in practicability, stable and reliable.

Description

Technical Field

[0001] The invention belongs to the field of digital signal processing, and in particular relates to a read data receiving method for a PSRAM controller. Background Art

[0002] In large-scale SoC chips such as satellite navigation baseband processing and computer vision, large-capacity memory is required to run firmware programs and process intermediate data. PSRAM has become a suitable choice with its low cost, low power consumption, large capacity and high performance.

[0003] The operating frequency of PSRAM can generally reach 400Mbps. At such a high operating frequency, during the read operation, it is particularly important for the chip controller to know when and how to receive the returned data.

[0004] In actual applications, there are many variables such as different chips, different PSRAM particles, different circuit boards, different temperatures, and different voltages. In addition, temperature and voltage change dynamically in real time. This creates great difficulties for the controller's read operation design.

[0005] At present, there are generally two solutions for the read operation process of the PSRAM controller:

[0006] Solution 1: Use multiple phases of the local clock for data collection;

[0007] Directly use the local clock to collect the dq data returned by the PSRAM particles. However, the local clock has multiple phases, such as clk_0, clk_90, clk_180 and clk_270; these four clock phases are all 1x phases; use these four clock phases for data collection, and then use registers for buffering. Among these four phases, there may be one or two phases with appropriate data collected, and then select one of the two appropriate phases as the final collected data. This is equivalent to oversampling.

[0008] After the data is collected locally through oversampling, it is necessary to further determine whether to use the rising edge half beat or the falling edge half beat of dqs to receive the dq data cached in the local register, and then store it in the asynchronous fifo cache.

[0009] In the above process, there are two selection processes, namely, the selection of clock phase and the selection of receiving timing. In actual application, both selections need to be tested to summarize and find the appropriate selection results. In specific implementation, software or hardware train operation is generally used to perform simulation and make selections.

[0010] However, the existing technology still has the following problems:

[0011] When receiving data with a local multi-phase clock, among the two valid settings that are actually available, one setting may be relatively stable, while the other setting may be in a more critical state (that is, stable at times, and unstable at times). This setting in a more critical state can pass the test in the training stage, but it will go wrong when applied to large amounts of data in the subsequent stage. However, among these two valid settings, which one is the more critical state setting and which one is the relative setting, the designer cannot know. Similarly, there is a similar situation in the selection of the receiving timing in the later stage. This situation will greatly reduce the reliability of the chip.

[0012] In addition, when choosing the appropriate settings, there is also the following situation: in actual use, environmental parameters such as temperature and voltage change. Then there is such a possibility: in the training stage, the final appropriate settings are selected at the set temperature; but in actual application, the actual temperature, voltage and other parameters are not within the set temperature range of the training stage, which causes the delay of the Soc chip and PSRAM particle devices to change. For example, the delay from the PSRAM particle receiving the read request to the data arriving at the port may be 2ns at low temperature and 6.5ns at high temperature; or, the IO delay is 0.7ns at low temperature and 1.3ns at high temperature. Such a situation will make the previously selected settings invalid in actual application, so that the chip samples and obtains wrong data in actual application.

[0013] Solution 2: Use hard core PHY to achieve data collection;

[0014] The method of using hard core PHY to implement acquisition is often used in DDR systems. The rate of DDR SDRAM is relatively high; there are very fine-grained delay units in the hard core of DDR PHY, such as delay units of the order of 10ps. This delay unit can be adjusted in extremely fine granularity to find the appropriate delay.

[0015] However, DDRPHY is extremely expensive, large in area, high in power consumption, complex to implement, and requires an additional hard IP core. This approach is not suitable for PSRAM systems that have high requirements on cost, area, and power consumption. Summary of the invention

[0016] The object of the present invention is to provide a method for receiving read data of a PSRAM controller which is low in cost, good in practicability, stable and reliable.

[0017] The method for receiving read data of a PSRAM controller provided by the present invention comprises the following steps:

[0018] S1. Design and implement the gating signal of dqs;

[0019] S2. According to the gating signal obtained in step S1, directly use dqs delayed sampling dq signal;

[0020] S3. The sampled dq signals are isolated using registers so that they eventually enter the chip and complete the read data reception of the PSRAM controller.

[0021] The step S1 specifically includes the following steps:

[0022] The dqs signal is input from the IO pin, and then the dqs_i_cg signal is obtained through the gate signal; then the dqs_i_cg signal is delayed 90 degrees to obtain the dqs_i_90 signal;

[0023] The dqs_i_90 signal is turned on by the local clock; a register with an asynchronous set is used, the clock of the register is connected to the gated output dqs_i_90 signal, and the asynchronous set terminal of the register is connected to the signal generated by the local circuit; it is turned on before the read data is returned;

[0024] The counter using the dqs_i_90 signal as the clock counts the number of beats of the received data; when the required number of beats is received, the register output is 0, prompting the clock to be turned off; the signal output by the register is combined with the original clock to be gated to obtain the required gated clock output;

[0025] The dqs_i_90 signal passes through a gated clock device and is then connected to the wclk terminals of the two FIFO buffers; the input terminal of the gated clock device is connected to the dqs_i_90 signal, and the en terminal of the gated clock device is connected to the valid level signal generated by the local clock and generated when the read data is returned.

[0026] The step S1 further comprises the following steps:

[0027] If there is no register with asynchronous set, two levels and logic OR operation are used to obtain the gate enable signal: one level is used to turn on the clock, generated by the local circuit, and turned on before the valid data is returned; the other level is used to turn off the clock, generated by the gated output dqs_i_90 signal, and the clock is turned off immediately after counting the number of data beats to be received; the gate enable signal is obtained by logic OR operation, and then logically ANDed with the original clock that needs to be gated to obtain a gated clock output that meets the rules.

[0028] The step S2 specifically includes the following steps:

[0029] The dqs signal is input from the IO pin, and then the dqs_i_cg signal is obtained through the gate signal; then the dqs_i_cg signal is delayed 90 degrees to obtain the dqs_i_90 signal;

[0030] Use the dqs_i_90 signal to sample the dq signal that enters the chip through the IO pin: sample the rising edge once to get the dq_i_r signal, and sample the falling edge once to get the dq_i_f signal;

[0031] Use two asynchronous FIFOs to receive the sampled data, where the write data of FIFO_R is dq_i_r, and the write clock is the rising edge of the dqs_i_90 signal; the write data of FIFO_F is dq_i_f, and the write clock is the falling edge of the dqs_i_90 signal; the output of the two FIFO buffers is the local clock, which is the whole beat data spliced ​​from two half-beat data; finally, the reception of the read return data is completed;

[0032] Add delay devices to the dqs clock path to meet the timing constraints.

[0033] The step S3 specifically includes the following steps:

[0034] Use the dqs_i_90 signal to sample the dq signal that enters the chip through the IO pin: sample the rising edge once to obtain the dq_i_r signal and store it in the register, sample the falling edge once to obtain the dq_i_f signal and store it in the register;

[0035] The outputs of the two registers are used and then connected to the din end of the asynchronous FIFO buffer.

[0036] The method for receiving read data of a PSRAM controller provided by the present invention not only realizes the receiving of read data of a PSRAM controller through innovative reading process design and mechanism innovation, but also has low cost, good practicability, stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the method flow of the present invention. DETAILED DESCRIPTION

[0038] like Figure 1 The method flow chart of the present invention is shown as follows: The method for receiving read data for a PSRAM controller provided by the present invention comprises the following steps:

[0039] The method of the present invention is based on the following conditions:

[0040] The skew of dq and dqs returned by PSRAM reading is very small, or has a fixed range; although the specific PSRAM particle subdivision type or manufacturer may have a little difference in this regard, it is basically that dq and dqs are completely aligned, or the dq signal is delayed by 0.4 to 0.6ns more than the dqs signal;

[0041] In terms of line delay on the board, the delay difference between the dq signal and the dqs signal can be controlled within the order of 0.01ns; this requirement is more in line with the current actual situation;

[0042] In terms of chip design, the dq signal and dqs signal input parts use the same IO device type to ensure that the delay difference is very small;

[0043] With the above conditions, plus the characteristics of a PSRAM particle itself, the dq signal is updated once every half beat when reading the returned data, and the dqs signal flips once when the dq signal is updated; although the delay of the device will change with temperature and voltage, the delay of the dq signal and the dqs signal will change together. For example, the IO delay of the dq signal and the dqs signal is different at high and low temperatures (for example, 0.7ns at low temperature and 1.3ns at high temperature), but under the same temperature condition, the delay is the same, or the difference is very small; in this way, the returned dqs signal and dq signal can be regarded as synchronized;

[0044] Based on the above conditions, the method of the present invention is as follows:

[0045] S1. Design and implement the gating signal of dqs;

[0046] After the dqs signal passes through the IO from the pin, it cannot be delayed to obtain the dqs_i_90 signal and use it as a valid clock all the time. This is because the asynchronous FIFO cache used is always valid for write enable, and data is written when the time is valid; in the later stage of the controller reading PSRAM data, some dqs signals will be redundant; in the non-read data stage, the dqs signal level may also jump; the dqs signal may also have a high-impedance state; these aspects require that the dqs signal needs to be gated, and only the truly valid clock is selected to connect to the wclk end of the asynchronous FIFO cache, and the rest should be shielded;

[0047] The specific steps include:

[0048] The dqs signal is input from the IO pin, and then the dqs_i_cg signal is obtained through the gate signal; then the dqs_i_cg signal is delayed 90 degrees to obtain the dqs_i_90 signal;

[0049] The dqs_i_90 signal is turned on by the local clock; a register with an asynchronous set is used, the clock of the register is connected to the gated output dqs_i_90 signal, and the asynchronous set terminal of the register is connected to the signal generated by the local circuit; it is turned on before the read data is returned;

[0050] The counter using the dqs_i_90 signal as the clock counts the number of beats of the received data; when the required number of beats is received, the register output is 0, prompting the clock to be turned off; the signal output by the register is combined with the original clock to be gated to obtain the required gated clock output;

[0051] The dqs_i_90 signal passes through a gated clock device and then connects to the wclk terminals of the two FIFO buffers; the input terminal of the gated clock device is connected to the dqs_i_90 signal, and the en terminal of the gated clock device is connected to the valid level signal generated by the local clock when the read data is returned; this is because the first beat of the dqs_i_90 signal is used to receive the dq signal to the dq_i_r signal and the dq_i_f signal, so that the data input terminal din of the FIFO buffer is delayed by one beat, so the first beat clock sent to the FIFO buffer should also be shielded;

[0052] In specific implementation, if there is no register with asynchronous set, two levels and logic OR operation are used to obtain the gated enable signal: one level is used to turn on the clock, which is generated by the local circuit and turned on before the valid data is returned; the other level is used to turn off the clock, which is generated by the dqs_i_90 signal output by the gate, and the clock is turned off immediately after counting the number of data beats to be received; the gated enable signal is obtained by logic OR operation, and then logically ANDed with the original clock to be gated to obtain the gated clock output that meets the rules;

[0053] S2. According to the gate signal obtained in step S1, directly use dqs to delay sampling of dq signal; specifically comprising the following steps:

[0054] The dqs signal is input from the IO pin, and then the dqs_i_cg signal is obtained through the gate signal; then the dqs_i_cg signal is delayed 90 degrees to obtain the dqs_i_90 signal; if the data is 400Mbps, the clock is 200MHz, the whole cycle is 5ns, and the 90-degree delay is 1.25ns (for the case where the dq signal and the dqs signal are aligned, if the dq signal is delayed 0.4ns more than the dqs signal, an additional 0.4ns is required);

[0055] The dqs_i_90 signal is used to sample the dq signal that enters the chip through the IO pin: the rising edge is sampled once to obtain the dq_i_r signal, and the falling edge is sampled once to obtain the dq_i_f signal; in this way, the data is received locally safely and stably;

[0056] Use two asynchronous FIFOs to receive the sampled data, where the write data of FIFO_R is dq_i_r, and the write clock is the rising edge of the dqs_i_90 signal; the write data of FIFO_F is dq_i_f, and the write clock is the falling edge of the dqs_i_90 signal; the output of the two FIFO buffers is the local clock, which is the whole beat data spliced ​​from two half-beat data; finally, the reception of the read return data is completed;

[0057] Add delay devices to the clock path of the dqs signal to meet the timing constraints;

[0058] The delay is achieved by setting the clock during synthesis and STA (static timing analysis):

[0059] create_clock-period 5.000-name dqs_clk[get_ports dqs]-waveform[2.55]

[0060] set_clock_uncertainty 0.5[get_clocks dqs_clk]

[0061] On the dqs pin, set a clock dqs_clk, the clock period is 5ns, the frequency is 200MHz, the duty cycle is 50%, and the clock deviation uncertainty is 0.5ns.

[0062] And the constraints of the dq signal data ports:

[0063] set_input_delay-min 0.00-clock dqs_clk-fall[get_ports dq*]

[0064] set_input_delay-min 2.50-clock dqs_clk-rise[get_ports dq*]

[0065] set_input_delay-max 3.75-clock dqs_clk-fall[get_ports dq*]

[0066] set_input_delay-max 6.25-clock dqs_clk-rise[get_ports dq*]

[0067] Each dq port acts as a data path and enters the sampling registers dq_i_r and dq_i_f. The timing must be calculated and checked according to their actual paths. The clock checked is the rising edge or falling edge of dqs_i_90.

[0068] The key is the -max option, which is used to calculate and check the setup time. When the data path delay of the dq input is large and cannot meet the requirements, the delay of the dqs_clk input clock path will be increased to meet the requirements. Here, the -max of the input delay is larger than the usual setting. For example, from the rising edge to the rising edge, it is 1.25ns longer than a full cycle. The purpose is to assume that the dq has a 6.25ns delay before entering the chip during calculation, and the clock dqs_clk must be delayed by at least 1.25ns to meet the setup time requirements.

[0069] The -min option is used to calculate and check the hold time, and the clock delay should not be too large and should be within a reasonable range.

[0070] In the settings, -fall is half a clock cycle less than -rise: 2.5ns. This is because the rising edge to the rising edge of dqs_clk is a full cycle of 5ns, while the rising edge to the falling edge is half a cycle of 2.5ns, so half a cycle is reduced.

[0071] In this way, during synthesis and STA, in order to meet this timing, a string of delay devices will be added to the clock path of the dqs signal to meet these two timing constraints. The back-end tool will implement this requirement when making the clock tree and modifying the timing. During the specific implementation, a string of clock tree devices may be inserted, or it may be a string of ordinary inverters. Generally, there will be no buf, because the delay of buf for the rising edge and the falling edge is different. After passing through buf, the duty of the clock will change; therefore, in the specific implementation, two pairs of inv of the same model are generally used to achieve the delay; it may be an LVT type device, because the difference between the max delay and min delay of the LVT type is small, while the max delay and min delay of the HVT have larger delays;

[0072] Another implementation method is to find the timinglib file of the corresponding process standard unit, obtain the cells with driving capability, suitable delay, and small difference between max delay and min delay, estimate the required delay level, and directly instantiate a series of delay devices and place them in the rtl code; during synthesis, set the set_dont_touch operation;

[0073] S3. The sampled dq signals are isolated by registers, and finally enter the chip to complete the read data reception of the PSRAM controller; specifically, the steps include:

[0074] Use the dqs_i_90 signal to sample the dq signal that enters the chip through the IO pin: sample the rising edge once to obtain the dq_i_r signal and store it in the register, sample the falling edge once to obtain the dq_i_f signal and store it in the register;

[0075] Use the output of two registers and then connect to the din end of the asynchronous FIFO buffer;

[0076] This is done to make the timing path clear and facilitate convergence. If the dq input signal enters the asynchronous FIFO cache directly after passing through the IO, there will be a mem (register or on-chip memory hard core) from the dq end to the FIFO cache, and many data paths and logical wptr will participate in the operation. Each storage unit path needs to calculate input_delay, setup, hold, etc. There are many paths that need to be balanced from the input port to each internal register node. However, the method of first going through the 1-level register transition method does not have any logical operation from the port to the data input end of the register, and the timing path is very clear. Each data signal has only two paths, the rising edge of dqs_i_90 enters one register, and the falling edge of dqs_i_90 enters one register.

[0077] The addition of one level of latency has minimal impact on performance in cache pre-reading and large data burst operations; however, the process can converge quickly and the function implementation is very stable.

[0078] Compared with the traditional method, the method of the present invention has the following advantages:

[0079] Stable and reliable

[0080] By adopting the method of the present invention, as long as the chip design meets the requirements and the timing constraints are met, and the board line delay skew constraints are also within a reasonable range, it can be ensured that the system can work stably, normally and correctly for a long time; even if there are scenarios where temperature, voltage and the like change, the related signal delays change together, although a part of the delay specially constructed may be affected by the scenario so that the delay changes a little, but the range of this change can ensure that the process of receiving the read data will not go wrong;

[0081] Easy to use

[0082] The method of the present invention can be directly used in a chip or a PSRAM system without performing other operations such as phase calibration before the read and write operations; the method of the present invention can also be used normally in the case of frequency reduction below the target frequency.

[0083] The method of the present invention cleverly utilizes a condition of PSRAM, that is, the dqs read return preamble (preamble code) is large enough; compared with the DDR-SDRAM particle type, the dqs read return preamble of DDR_SDRAM has only one full cycle, and the local circuit needs to strictly grasp when to put the returned dqs in. If it is too early, it will encounter a high impedance state, and if it is too late, a part of the effective clock will be cut off, so fine-grained calibration is required, and changes in temperature, voltage, etc. must also be considered. The dqs preamble returned by the PSRAM read is at least 3 or 4 cycles, and the dqs returned during this period are all low level. The local circuit can put dqs in during this period; then wait for dqs to change from low to high, and then start the effective clock.

[0084] Save resources

[0085] The method of the present invention does not use the hard core of PHY, but only uses a small number of standard units, gates and registers to achieve the desired effect; IO, FIFO buffer, etc. are essential. The delay device and two gated clock devices added by the present invention occupy less resources.

[0086] Save power

[0087] Because fewer resources are required, power consumption is also lower.

[0088] In addition, the present invention adopts a low-power design technology of a gated clock. In other states other than read operations, the clock of this part of the circuit does not flip, which can significantly save a part of dynamic power consumption.

[0089] Short development cycle, easy to implement

[0090] The method of the present invention uses fewer circuits and then adds a few timing constraint settings, and the remaining work can be automatically implemented by the tool.

[0091] In addition, because the returned dq directly enters the register after the IO input, this register is used to isolate the path from the internal circuit; the timing path of the IO port is very clear, and each data line only needs to pay attention to two paths when inputting: one is to enter the register at the rising edge of the clock, and the other is to enter the register at the falling edge of the clock; the path is very clear, without any other logic. Therefore, the balancing process of each port and timing of dq is very easy to implement.

Claims

1. A method for receiving read data of a PSRAM controller, comprising the following steps: S1. Design and implement the gating signal of dqs; S2. According to the gating signal obtained in step S1, directly use dqs delayed sampling dq signal; S3. The sampled dq signals are isolated using registers so that they eventually enter the chip and complete the read data reception of the PSRAM controller.

2. The method for receiving read data of a PSRAM controller according to claim 1, wherein The step S1 specifically includes the following steps: The dqs signal is input from the IO pin, and then the dqs_i_cg signal is obtained through the gate signal; then the dqs_i_cg signal is delayed 90 degrees to obtain the dqs_i_90 signal; The dqs_i_90 signal is turned on by the local clock; a register with an asynchronous set is used, the clock of the register is connected to the gated output dqs_i_90 signal, and the asynchronous set terminal of the register is connected to the signal generated by the local circuit; it is turned on before the read data is returned; The counter using the dqs_i_90 signal as the clock counts the number of beats of the received data; when the required number of beats is received, the register output is 0, prompting the clock to be turned off; the signal output by the register is combined with the original clock to be gated to obtain the required gated clock output; The dqs_i_90 signal passes through a gated clock device and is then connected to the wclk terminals of the two FIFO buffers; the input terminal of the gated clock device is connected to the dqs_i_90 signal, and the en terminal of the gated clock device is connected to the valid level signal generated by the local clock and generated when the read data is returned.

3. The method for receiving read data of a PSRAM controller according to claim 2, wherein The step S1 further comprises the following steps: If there is no register with asynchronous set, two levels and logic OR operation are used to obtain the gate enable signal: one level is used to turn on the clock, generated by the local circuit, and turned on before the valid data is returned; the other level is used to turn off the clock, generated by the gated output dqs_i_90 signal, and the clock is turned off immediately after counting the number of data beats to be received; the gate enable signal is obtained by logic OR operation, and then logically ANDed with the original clock that needs to be gated to obtain a gated clock output that meets the rules.

4. The method for receiving read data of a PSRAM controller according to claim 3, wherein The step S2 specifically includes the following steps: The dqs signal is input from the IO pin, and then the dqs_i_cg signal is obtained through the gate signal; then the dqs_i_cg signal is delayed 90 degrees to obtain the dqs_i_90 signal; Use the dqs_i_90 signal to sample the dq signal that enters the chip through the IO pin: sample the rising edge once to get the dq_i_r signal, and sample the falling edge once to get the dq_i_f signal; Use two asynchronous FIFOs to receive the sampled data, where the write data of FIFO_R is dq_i_r, and the write clock is the rising edge of the dqs_i_90 signal; the write data of FIFO_F is dq_i_f, and the write clock is the falling edge of the dqs_i_90 signal; the output of the two FIFO buffers is the local clock, which is the whole beat data spliced ​​from two half-beat data; finally, the reception of the read return data is completed; Add delay devices on the dqs clock path to meet the timing constraints.

5. The method for receiving read data of a PSRAM controller according to claim 4, characterized in that The step S3 specifically includes the following steps: Use the dqs_i_90 signal to sample the dq signal that enters the chip through the IO pin: sample the rising edge once to obtain the dq_i_r signal and store it in the register, sample the falling edge once to obtain the dq_i_f signal and store it in the register; The outputs of the two registers are used and then connected to the din end of the asynchronous FIFO buffer.

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