Voltage reference circuit, method for generating reference voltage, and electronic equipment.

Abstract

This invention provides a voltage reference circuit, a method for generating a reference voltage, and an electronic device. The voltage reference circuit includes: a bias sub-circuit, a negative temperature coefficient sub-circuit, a positive temperature coefficient sub-circuit, a first node, a power supply terminal, a ground terminal, and a reference voltage output terminal. The bias sub-circuit is coupled to the first node, the power supply terminal, and the ground terminal to generate a bias current. The negative temperature coefficient sub-circuit is coupled to the power supply terminal, the ground terminal, and the first node to generate a first voltage with a negative temperature coefficient. The positive temperature coefficient sub-circuit is coupled to the power supply terminal, the first node, and the reference voltage output terminal to generate a second voltage with a positive temperature coefficient. It also generates a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmits the reference voltage to the reference voltage output terminal. This invention features a simple circuit structure and a small layout area.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit design technology, and in particular to a voltage reference circuit, a method for generating a reference voltage, and an electronic device. Background Technology

[0002] A voltage reference circuit typically refers to a highly stable voltage source used as a voltage reference in a circuit.

[0003] With the continuous increase in the scale of integrated circuits, especially the development of system-on-a-chip (SoC) technology, they have become an indispensable basic circuit in large-scale and very-large-scale integrated circuits and almost all digital and analog systems.

[0004] In existing voltage reference circuit designs, the base-emitter voltage (VBE) of BJT (bipolar junction transistor) devices is typically designed using the negative temperature coefficient and the fact that the base-emitter difference is proportional to the absolute temperature. This approach results in complex structures and large layout areas. Summary of the Invention

[0005] This invention provides a voltage reference circuit, a method for generating a reference voltage, and an electronic device to solve the problems of complex structure and large layout area in existing voltage reference circuits.

[0006] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0007] In a first aspect, embodiments of the present invention provide a voltage reference circuit, comprising: a bias sub-circuit, a negative temperature sub-circuit, a positive temperature sub-circuit, a first node, a power supply terminal, a ground terminal, and a reference voltage output terminal;

[0008] A bias sub-circuit is coupled to the first node, the power supply terminal, and the ground terminal respectively, and is used to generate a bias current;

[0009] A negative temperature coefficient circuit is coupled to the power supply terminal, the ground terminal and the first node respectively, and is used to generate a first voltage with a negative temperature coefficient.

[0010] The positive temperature coefficient circuit is coupled to the power supply terminal, the first node and the reference voltage output terminal respectively, and is used to generate a second voltage with a positive temperature coefficient, and to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and to transmit the reference voltage to the reference voltage output terminal.

[0011] Optionally,

[0012] The negative temperature sub-circuit includes: a first transistor and a second transistor;

[0013] The positive temperature circuit includes: a third transistor and a fourth transistor;

[0014] The gate of the first transistor is coupled to the power supply, the first terminal of the first transistor is coupled to the ground terminal, and the second terminal of the first transistor is coupled to the first node.

[0015] The gate and drain of the second transistor are both coupled to the power supply; the source of the second transistor is coupled to the first node.

[0016] The gate of the third transistor is coupled to the power supply; the source of the third transistor is coupled to the first node; and the drain of the third transistor is coupled to the reference voltage output terminal.

[0017] The gate and drain of the fourth transistor are both coupled to the power supply; the source of the fourth transistor is coupled to the reference voltage output terminal.

[0018] Wherein, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor, and the threshold voltage of the third transistor is equal to the threshold voltage of the fourth transistor; the aspect ratio of the second transistor is less than that of the first transistor; the aspect ratio of the fourth transistor is greater than that of the third transistor; and the first transistor, the second transistor, the third transistor, and the fourth transistor are in a subthreshold state.

[0019] Optionally,

[0020] The channel length of the first transistor is smaller than the channel length of the second transistor.

[0021] And / or,

[0022] The channel length of the third transistor is equal to the channel length of the fourth transistor.

[0023] Optionally,

[0024] The channel length d1 of the first transistor satisfies: 0.15μm ≤ d1 ≤ 0.35μm; and / or,

[0025] The channel length d2 of the second transistor satisfies: 0.9μm ≤ d2 ≤ 1.1μm; and / or,

[0026] The channel length d3 of the third transistor and the fourth transistor satisfies: 0.9μm≤d3≤1.1μm.

[0027] Optionally,

[0028] At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor includes an enhancement-mode gallium nitride (HEMT) transistor.

[0029] Optionally,

[0030] The bias sub-circuit includes: a fifth transistor;

[0031] The gate of the fifth transistor is coupled to the power supply; the first terminal of the fifth transistor is coupled to the ground terminal; and the second terminal of the fifth transistor is coupled to the first node.

[0032] Optionally,

[0033] The bias sub-circuit includes: a resistor unit;

[0034] The first end of the resistor unit is coupled to the power supply and the first node respectively; the second end of the resistor unit is coupled to the ground terminal.

[0035] Optionally, it may also include: a first resistor unit and a second resistor unit;

[0036] The first end of the first resistor unit is coupled to the gate of the first transistor, the gate of the second transistor, and the second terminal of the second transistor, respectively, and the second end of the first resistor unit is coupled to the power supply.

[0037] The first end of the second resistor unit is coupled to the gate of the third transistor, the gate of the fourth transistor, and the second terminal of the fourth transistor, respectively, and the second end of the second resistor unit is coupled to the power supply.

[0038] Secondly, embodiments of the present invention provide a method for generating a reference voltage, which is applied to a voltage reference circuit as described in any one of the first aspects.

[0039] The bias sub-circuit generates bias current;

[0040] The negative temperature coefficient circuit generates a first voltage with a negative temperature coefficient.

[0041] The positive temperature coefficient circuit generates a second voltage, and is also used to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal.

[0042] Thirdly, embodiments of the present invention provide an electronic device including a voltage reference circuit as described in any one of the first aspects.

[0043] In this embodiment of the invention, the voltage reference circuit includes: a bias sub-circuit, a negative temperature sub-circuit, a positive temperature sub-circuit, a first node, a power supply terminal, a ground terminal, and a reference voltage output terminal; by superimposing the first voltage generated by the negative temperature sub-circuit and the second voltage generated by the positive temperature sub-circuit, a reference voltage with zero temperature coefficient can be obtained. The circuit structure is simple and the layout area is small. Attached Figure Description

[0044] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0045] Figure 1 This is a schematic block diagram of the voltage reference circuit according to an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of the layout of the voltage reference circuit according to an embodiment of the present invention;

[0047] Figure 3 To and Figure 2 A schematic diagram of the voltage reference circuit in the corresponding embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram showing the relationship between the threshold voltage and temperature coefficient of a transistor.

[0049] Figure 5 This is a schematic diagram showing the relationship between the difference in threshold voltage of a transistor and its temperature coefficient. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] It should be noted that the collection, gathering, updating, analysis, processing, use, transmission, and storage of user personal information involved in this disclosed technical solution all comply with relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. Necessary measures are taken to prevent unauthorized access to user personal information data and to safeguard user personal information security and network security.

[0052] In the technical solutions disclosed herein, terms such as “connection,” “coupling,” or “linking” are not limited to physical or mechanical connections, but may include electrical connections.

[0053] This invention provides a voltage reference circuit, see [link to relevant documentation]. Figure 1 As shown, Figure 1 This is a block diagram of the voltage reference circuit according to an embodiment of the present invention. The voltage reference circuit includes: a bias sub-circuit, a negative temperature sub-circuit, a positive temperature sub-circuit, a first node 102, a power supply terminal VDD, a ground terminal GND, and a reference voltage output terminal 101.

[0054] The bias sub-circuit is coupled to the first node 102, the power supply terminal VDD, and the ground terminal GND, respectively, and is used to generate bias current.

[0055] The negative temperature coefficient circuit is coupled to the power supply terminal VDD, the ground terminal GND and the first node 102 respectively, and is used to generate a first voltage with a negative temperature coefficient.

[0056] The positive temperature coefficient circuit is coupled to the power supply terminal VDD, the first node 102 and the reference voltage output terminal 101, respectively. It is used to generate a second voltage with a positive temperature coefficient, and also to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal 101.

[0057] In this embodiment of the invention, the positive Wenzi circuit is used to superimpose the first voltage and the second voltage to obtain a reference voltage.

[0058] In this embodiment of the invention, the voltage reference circuit includes: a bias sub-circuit, a negative temperature sub-circuit, a positive temperature sub-circuit, a first node 102, a power supply terminal VDD, a ground terminal GND, and a reference voltage output terminal 101; by superimposing the first voltage generated by the negative temperature sub-circuit and the second voltage generated by the positive temperature sub-circuit, a reference voltage with zero temperature coefficient can be obtained. The circuit structure is simple and the layout area is small.

[0059] In some embodiments of the present invention, see optionally, see Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram of the layout of the voltage reference circuit according to an embodiment of the present invention. Figure 3 To and Figure 2 A schematic diagram of the voltage reference circuit in the corresponding embodiment of the present invention.

[0060] The negative temperature circuit includes: a first transistor M1 and a second transistor M2;

[0061] The positive Wenzi circuit includes: the third transistor M3 and the fourth transistor M4;

[0062] The gate of the first transistor M1 is coupled to the power supply, the first terminal of the first transistor M1 is coupled to the ground terminal GND, and the second terminal of the first transistor M1 is coupled to the first node 102.

[0063] The gate and drain of the second transistor M2 are both coupled to the power supply; the source of the second transistor M2 is coupled to the first node 102.

[0064] The gate of the third transistor M3 is coupled to the power supply; the source of the third transistor M3 is coupled to the first node 102; and the drain of the third transistor M3 is coupled to the reference voltage output terminal 101.

[0065] The gate and drain of the fourth transistor M4 are both coupled to the power supply; the source of the fourth transistor M4 is coupled to the reference voltage output terminal 101.

[0066] Among them, the threshold voltage of the first transistor M1 is less than the threshold voltage of the second transistor M2, and the threshold voltage of the third transistor M3 is equal to the threshold voltage of the fourth transistor M4; the aspect ratio of the second transistor M2 is less than that of the first transistor M1; the aspect ratio of the fourth transistor M4 is greater than that of the third transistor M3; the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are in a subthreshold state.

[0067] In this embodiment of the invention, the first electrode includes a source electrode, and the second electrode includes a drain electrode.

[0068] Specifically, the reference voltage V REF Based on the following formula:

[0069] V REF =V GS1 -V GS2 +V GS3 -V GS4

[0070] Among them, V GS1 V is the driving voltage of the first transistor M1; GS2 V is the driving voltage of the second transistor M2; GS3 V is the driving voltage of the third transistor M3; GS4 This is the driving voltage for the fourth transistor M4.

[0071] In the subthreshold state, V GS1 -V GS2 That is, the first voltage with a negative temperature coefficient, V GS3 -V GS4 That is, the second voltage with a positive temperature coefficient, and the first voltage V. GS1 -V GS2 With the second voltage V GS3 -V GS4 The reference voltage V is obtained by superposition. REF .

[0072] In the subthreshold state, the driving voltage V of the transistorGS It conforms to the following formula:

[0073]

[0074] Where, K is the width-to-length ratio of the transistor; I0 is a parameter determined by the transistor process; I D is the subthreshold current; V T is the thermal voltage, which is proportional to the temperature; V TH is the threshold voltage of the transistor; I0 is a parameter determined by the transistor process, I0 = μ0Cox(η - 1)V T 2 : μ0 is the electron mobility; Cox is the gate oxide capacitance per unit area; η is the subthreshold slope factor, that is, the slope of the transistor current rise in the subthreshold region.

[0075] Combining the specific expression of the subthreshold current I D we can obtain: we can get: Where, V TH1 is the threshold voltage of the first transistor; V TH2 is the threshold voltage of the second transistor; K1 is the width-to-length ratio of the first transistor; K2 is the width-to-length ratio of the second transistor.

[0076] In the embodiment of the present invention, the threshold voltage value of the first transistor M1 is less than the threshold voltage value of the second transistor M2, V TH1 < V TH2 , we can get V TH1 - V TH2 < 0; the width-to-length ratio of the second transistor M2 is less than the width-to-length ratio of the first transistor M1, K2 < K1, and by derivation, we can get

[0077] According to Since V TH1 - V TH2 < 0 and < <0, we can get V GS1 - V GS2 < 0, that is, the first voltage V GS1 - V GS2 has a negative temperature coefficient.

[0078] Combining the specific expression of the subthreshold current I D we can obtain: we can get: Where, v<00000, we can get: is the threshold voltage of the third transistor; V TH4 is the threshold voltage of the fourth transistor; K4 is the width-to-length ratio of the fourth transistor; K3 is the width-to-length ratio of the third transistor.

[0079] In this embodiment of the invention, the threshold voltage value of the third transistor M3 is equal to the threshold voltage value of the fourth transistor M4, V TH3 =V TH4 V can be obtained TH3 -V TH4 =0; the aspect ratio of the fourth transistor M4 is greater than that of the third transistor M3, K4>K3, and it can be deduced that...

[0080] according to Due to V TH3 -V TH4 =0 and V can be obtained GS3 -V GS4 >0, meaning the second voltage V GS3 -V GS4 It exhibits a positive temperature coefficient.

[0081] In summary, when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are in a subthreshold state, the first voltage has a negative temperature coefficient, the second voltage has a positive temperature coefficient, and the superposition of the first voltage and the second voltage can obtain a reference voltage with zero temperature coefficient.

[0082] In this embodiment of the invention, the layout of the negative and positive thermoelectric circuits is achieved by combining the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, and the reference voltage is obtained by utilizing the physical characteristics of each transistor in a subthreshold state. This embodiment of the invention does not require the use of existing BJT (bipolar junction transistor) devices, resulting in a simple circuit structure and small layout area.

[0083] In some embodiments of the present invention, optionally,

[0084] The channel length of the first transistor M1 is smaller than the channel length of the second transistor M2.

[0085] It should be noted that in transistor manufacturing processes, the threshold voltage of a transistor exhibits a negative temperature coefficient, and the smaller the channel length of the transistor, the larger the negative temperature coefficient. Therefore, the temperature coefficient can be controlled by controlling the channel length of the transistor. In this embodiment of the invention, by setting the channel length of the first transistor M1 to be smaller than the channel length of the second transistor M2, the threshold voltage value of the first transistor M1 is made smaller than the threshold voltage value of the second transistor M2, i.e., V TH1 <V TH2 .

[0086] In some embodiments of the present invention, optionally,

[0087] The channel length of the third transistor M3 is equal to the channel length of the fourth transistor M4.

[0088] It should be noted that in transistor manufacturing processes, the threshold voltage of a transistor exhibits a negative temperature coefficient, and the smaller the channel length of the transistor, the larger the negative temperature coefficient. Therefore, the temperature coefficient can be controlled by controlling the channel length of the transistor. In this embodiment of the invention, by setting the channel length of the third transistor M3 to be less than the channel length of the fourth transistor M4, the threshold voltage value of the third transistor M3 is made equal to the threshold voltage value of the fourth transistor M4, i.e., V. TH3 =v TH4 .

[0089] In some embodiments of the present invention, optionally,

[0090] The channel length d1 of the first transistor M1 satisfies: 0.15μm≤d1≤0.35μm;

[0091] In some embodiments of the present invention, optionally,

[0092] The channel length d2 of the second transistor M2 satisfies: 0.9μm≤d2≤1.1μm;

[0093] In some embodiments of the present invention, optionally, the channel length d1 of the first transistor M1 is 0.25 μm, and the channel length d2 of the second transistor M2 is 1 μm.

[0094] See Figure 4 As shown, Figure 4 This diagram illustrates the relationship between the threshold voltage and temperature coefficient of a transistor. It shows two curves for enhancement-mode gallium nitride (GaN) HEMT (High Electron Mobility Transistor) transistors with different channel lengths (0.25 μm and 1 μm). The curve for 0.25 μm channel length is dashed, and the curve for 1 μm channel length is solid. Each curve represents the negative temperature coefficient of the corresponding transistor. It can be concluded that the smaller the channel length, the more drastically the threshold voltage of the GaN HEMT transistor decreases with increasing temperature, i.e., the larger the negative temperature coefficient. (See also...) Figure 5 As shown, Figure 5 This diagram illustrates the relationship between the threshold voltage difference of a transistor and its temperature coefficient, showing the difference in threshold voltage between enhancement-mode gallium nitride (HEMT) transistors with a channel length of 0.25 μm and 1 μm.

[0095] In some embodiments of the present invention, optionally,

[0096] The channel length d3 of the third transistor M3 and the fourth transistor M4 satisfies: 0.9μm≤d3≤1.1μm.

[0097] The channel lengths of d1 and d2 described above are such that by setting the channel length of the first transistor M1 to be less than the channel length of the second transistor M2, the threshold voltage value of the first transistor M1 is less than the threshold voltage value of the second transistor M2 (i.e., V). TH1 <V TH2 Under the condition of ensuring stable physical performance and low manufacturing cost of transistors, the channel length of d3 is such that by setting the channel length of the third transistor M3 to be less than the channel length of the fourth transistor M4, the threshold voltage value of the third transistor M3 is equal to the threshold voltage value of the fourth transistor M4, i.e., V. TH3 =V TH4 .

[0098] In some embodiments of the present invention, see optionally, see Figure 3 As shown, at least one of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 includes an enhancement-mode (E-mode) gallium nitride (HEMT) transistor.

[0099] See Figure 3 As shown, enhancement-mode gallium nitride (HEMT) transistors can be formed by stacking p-GaN / gate-metal. The first resistor unit R1 and the second resistor unit R2 can be metal resistors or active region resistors, such as TiN, AlCu, 2DEG, etc.

[0100] In existing voltage reference circuit designs, the negative temperature coefficient of the base-emitter voltage (VBE) and the proportionality between the base and emitter voltage difference and absolute temperature are utilized to design the reference voltage using BJT (bipolar junction transistor) devices. BJTs are traditional silicon-based transistors, employing BiCMOS (bimetallic oxide semiconductor) or BCD (monolithographic integration) processes, resulting in complex voltage reference circuit structures, large layouts, and high power consumption. Therefore, this invention employs enhancement-mode gallium nitride (HEMT) transistors, specifically the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, which achieve a simpler structure, smaller layout area, and lower power consumption compared to traditional silicon-based transistors. Actual test results show a quiescent current of 0.67 μA, an input voltage of 5 V, and a power consumption of 3.35 μW, demonstrating superior performance compared to voltage reference circuits based on traditional silicon-based transistors.

[0101] Furthermore, by employing enhancement-mode gallium nitride (HEMT) transistors to arrange the voltage reference circuit, this embodiment of the invention achieves superior low-temperature drift characteristics compared to conventional silicon-based transistor-based voltage reference circuits. Specifically, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all enhancement-mode gallium nitride (HEMT) transistors. Actual test results show that with an output reference voltage of 0.743V at room temperature, the reference voltage drift is ≤5.4mV within the range of -50℃ to 150℃, with a temperature coefficient of 36ppm / ℃, demonstrating significantly superior low-temperature drift characteristics compared to voltage reference circuits based on conventional silicon-based crystals.

[0102] Furthermore, the reference voltage designed using BJT devices requires operational amplifiers for voltage clamping. The use of operational amplifiers for voltage clamping also results in a complex voltage reference circuit structure and a large layout area. In this embodiment of the invention, when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all enhancement-mode gallium nitride (HEMT) transistors, no operational amplifier is needed for voltage clamping, resulting in a simpler structure. Eliminating the operational amplifier also reduces the failure rate, and the voltage reference circuit of this embodiment has a long service life.

[0103] In some embodiments of the present invention, see optionally, see Figure 2 and Figure 3 As shown, the bias sub-circuit includes: the fifth transistor M5;

[0104] The gate of the fifth transistor M5 is coupled to the power supply; the first terminal of the fifth transistor M5 is coupled to the ground terminal GND; and the second terminal of the fifth transistor M5 is coupled to the first node 102.

[0105] In this embodiment of the invention, the fifth transistor M5 is used to provide the bias current, which ensures high stability of the bias current and facilitates a stable reference voltage output by the voltage reference circuit. Furthermore, in some embodiments, the fifth transistor M5 is an enhancement-mode gallium nitride (HEMT) transistor, which helps reduce the layout area and power consumption of the voltage reference circuit; and it can also mitigate the interference of temperature on the bias current, ensuring that the reference voltage output by the voltage reference circuit has low temperature drift characteristics.

[0106] In some embodiments of the present invention, optionally,

[0107] The bias sub-circuit includes: a resistor unit;

[0108] The first end of the resistor unit is coupled to the power supply and the first node 102 respectively; the second end of the resistor unit is coupled to the ground terminal GND.

[0109] In this embodiment of the invention, a resistor unit is used to provide bias current, which can effectively reduce the layout cost of the voltage reference circuit. Low cost is conducive to the large-scale application of voltage reference circuits.

[0110] In some embodiments of the present invention, see optionally, see Figure 2 and Figure 3 As shown, the voltage reference circuit also includes: a first resistor unit R1 and a second resistor unit R2;

[0111] The first end of the first resistor unit R1 is coupled to the gate of the first transistor M1, the gate of the second transistor M2, and the second terminal of the second transistor M2, respectively. The second end of the first resistor unit R1 is coupled to the power supply.

[0112] The first end of the second resistor unit R2 is coupled to the gate of the third transistor M3, the gate of the fourth transistor M4, and the second terminal of the fourth transistor M4, respectively. The second end of the second resistor unit R2 is coupled to the power supply.

[0113] In this embodiment of the invention, by arranging the first resistor unit R1 and the second resistor unit R2, and combining the high resistance settings of the first resistor unit R1 and the second resistor unit R2, it can be ensured that the current connected to the first transistor, the second transistor, the third transistor, and the fourth transistor is within the subthreshold current range, that is, the first transistor, the second transistor, the third transistor, and the fourth transistor are in a subthreshold state. The high resistance refers to the resistance value that ensures the current connected to the first transistor, the second transistor, the third transistor, and the fourth transistor is within the subthreshold current range. Because transistors vary due to differences in manufacturing processes and tolerances, and because the reference voltage to be output in actual applications of this embodiment of the invention varies depending on the requirements, specific resistance value ranges for the first resistor unit R1 and the second resistor unit R2 cannot be given here. It should be noted that the lack of specific resistance value ranges should not be considered as a lack of clarity.

[0114] This invention provides a method for generating a reference voltage, applicable to any voltage reference circuit of this invention. The method includes:

[0115] The bias sub-circuit generates bias current;

[0116] The negative temperature coefficient circuit generates a first voltage with a negative temperature coefficient.

[0117] The positive temperature coefficient circuit generates a second voltage and is also used to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmits the reference voltage to the reference voltage output terminal 101.

[0118] This invention provides an electronic device, including any of the voltage reference circuits described in this invention.

[0119] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A voltage reference circuit, characterized in that, include: Bias sub-circuit, negative temperature sub-circuit, positive temperature sub-circuit, first node, power supply terminal, ground terminal and reference voltage output terminal; A bias sub-circuit is coupled to the first node, the power supply terminal, and the ground terminal respectively, and is used to generate a bias current; A negative temperature coefficient circuit is coupled to the power supply terminal, the ground terminal and the first node respectively, and is used to generate a first voltage with a negative temperature coefficient. A positive temperature coefficient circuit is coupled to the power supply terminal, the first node and the reference voltage output terminal respectively, and is used to generate a second voltage with a positive temperature coefficient, and to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and to transmit the reference voltage to the reference voltage output terminal. The negative temperature sub-circuit includes: a first transistor and a second transistor; The positive temperature circuit includes: a third transistor and a fourth transistor; The gate of the first transistor is coupled to the power supply terminal, the first electrode of the first transistor is coupled to the ground terminal, and the second electrode of the first transistor is coupled to the first node. The gate and drain of the second transistor are both coupled to the power supply terminal; the source of the second transistor is coupled to the first node. The gate of the third transistor is coupled to the power supply terminal; the source of the third transistor is coupled to the first node; and the drain of the third transistor is coupled to the reference voltage output terminal. The gate and drain of the fourth transistor are both coupled to the power supply terminal; the source of the fourth transistor is coupled to the reference voltage output terminal. Wherein, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor, and the threshold voltage of the third transistor is equal to the threshold voltage of the fourth transistor; the aspect ratio of the second transistor is less than that of the first transistor; the aspect ratio of the fourth transistor is greater than that of the third transistor; the first transistor, the second transistor, the third transistor, and the fourth transistor are in a subthreshold state. The first transistor, the second transistor, the third transistor, and the fourth transistor are enhancement-mode gallium nitride (HEMT) transistors. The bias sub-circuit includes: a fifth transistor; The gate of the fifth transistor is coupled to the power supply terminal; the first terminal of the fifth transistor is coupled to the ground terminal; the second terminal of the fifth transistor is coupled to the first node. The fifth transistor is an enhancement-gallium nitride (HEMT) transistor.

2. The voltage reference circuit according to claim 1, characterized in that: The channel length of the first transistor is smaller than the channel length of the second transistor. And / or, The channel length of the third transistor is equal to the channel length of the fourth transistor.

3. The voltage reference circuit according to claim 2, characterized in that: The channel length d1 of the first transistor satisfies: 0.15μm≤d1≤0.35μm; And / or, The channel length d2 of the second transistor satisfies: 0.9μm ≤ d2 ≤ 1.1μm; and / or, The channel length d3 of the third transistor and the fourth transistor satisfies: 0.9μm≤d3≤1.1μm.

4. The voltage reference circuit according to claim 1, characterized in that: The bias sub-circuit includes: a resistor unit; The first end of the resistor unit is coupled to the power supply terminal and the first node respectively; the second end of the resistor unit is coupled to the ground terminal.

5. The voltage reference circuit according to claim 1, characterized in that, Also includes: First resistor unit and second resistor unit; The first end of the first resistor unit is coupled to the gate of the first transistor, the gate of the second transistor, and the second terminal of the second transistor, respectively, and the second end of the first resistor unit is coupled to the power supply terminal. The first end of the second resistor unit is coupled to the gate of the third transistor, the gate of the fourth transistor, and the second terminal of the fourth transistor, respectively, and the second end of the second resistor unit is coupled to the power supply terminal.

6. A method for generating a reference voltage, applied to a voltage reference circuit as described in any one of claims 1 to 5, characterized in that: The bias sub-circuit generates bias current; The negative temperature coefficient circuit generates a first voltage with a negative temperature coefficient. The positive temperature coefficient circuit generates a second voltage, and is also used to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal.

7. An electronic device, characterized in that: Includes the voltage reference circuit as described in any one of claims 1 to 5.

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