A method and apparatus for polynomial computation

Abstract

The embodiment of the application provides a polynomial calculation method and device, the method comprises the following steps: obtaining a plurality of to-be-calculated polynomials in a polynomial calculation application; dividing the plurality of to-be-calculated polynomials to obtain a plurality of to-be-calculated groups; the plurality of to-be-calculated groups comprise a first to-be-calculated group; loading common variables corresponding to at least one to-be-calculated polynomial in the first to-be-calculated group into at least one first register group, loading variable coefficients into at least one second register group, and loading reference variables into at least one third register group; controlling the common variables in the at least one first register group to perform outer product calculation with the variable coefficients in the at least one second register group to obtain a first result; and controlling the first result to perform inner product calculation with the reference variables in the at least one third register group to obtain a second result. Through the above method, the polynomial calculation can be converted into matrix calculation between register groups, and the calculation speed is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a polynomial calculation method and apparatus. Background Technology

[0002] In mathematics, a polynomial is a sum / difference of multiple monomials, where each monomial is an expression derived from variables, coefficients, and multiplication / exponentiation (non-negative integer powers) between them. Currently, when calculating polynomials, the general approach is to first calculate the result of each monomial, and then obtain the polynomial result from the sum / difference of the monomials. When calculating a large number of polynomials, this method incurs a significant time overhead. Therefore, improving the calculation speed of polynomials is a pressing issue that needs to be addressed. Summary of the Invention

[0003] This application provides a polynomial calculation method and apparatus to improve the calculation speed of polynomials.

[0004] Firstly, this application provides a polynomial calculation method. This method can be executed by a device with data processing capabilities (such as a computing device) or by a component within that device (such as a processor). Taking a computing device as an example, in this method, multiple polynomials to be calculated in a polynomial calculation application are obtained. These multiple polynomials are then divided into multiple calculation groups. Each calculation group includes at least one polynomial to be calculated. The coefficients of the at least one polynomial in each calculation group are the same. The multiple calculation groups include a first calculation group, which is any one of the multiple calculation groups. The common variables and coefficients corresponding to at least one polynomial in the first calculation group are determined. In addition to reference variables, the common variables corresponding to at least one polynomial to be calculated are loaded into at least one first register group, the coefficients of the variables corresponding to at least one polynomial to be calculated are loaded into at least one second register group, and the reference variables corresponding to at least one polynomial to be calculated are loaded into at least one third register group. The common variables in at least one first register group and the coefficients of the variables in at least one second register group are then subjected to an outer product calculation to obtain a first result corresponding to at least one polynomial to be calculated. The first result corresponding to at least one polynomial to be calculated is then subjected to an inner product calculation with the reference variables in at least one third register group to obtain a second result corresponding to at least one polynomial to be calculated. When calculating a large number of polynomials, this method can transform polynomial loop calculations into matrix calculations between register groups, improving calculation speed.

[0005] In one possible design, determining the common variables, variable coefficients, and reference variables corresponding to at least one polynomial in the first set of polynomials to be calculated may include: for the first polynomial in the at least one set of polynomials to be calculated, where the first polynomial is any polynomial in the at least one set of polynomials to be calculated, performing the following steps: extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, wherein the M N-order polynomials correspond one-to-one with the M reference variables, each N-order polynomial includes N common variables and N variable coefficients, the N common variables correspond one-to-one with the N variable coefficients, the M N-order polynomials each include the same N common variables, M is a positive integer, N is an integer greater than 1, and based on the M N-order polynomials, determining the N common variables and M*N variable coefficients.

[0006] In one possible design, before extracting M N-order polynomials and the M reference variables corresponding to the M N-order polynomials from the first polynomial, the design may further include: if the orders of the monomials included in the first polynomial are determined to be discontinuous, supplementing the first polynomial with monomials corresponding to the missing orders, wherein the coefficients of the variable corresponding to the missing orders of the monomials are zero. This design yields a supplemented first polynomial where the orders of the monomials are continuous, facilitating subsequent polynomial calculations.

[0007] In one possible design, before extracting M N-order polynomials and the M reference variables corresponding to the M N-order polynomials from the first polynomial, the following step can be taken: if the number of monomials in the first polynomial is determined to be odd, an odd number of monomials are added to the first polynomial, with all coefficients of the odd number of monomials being zero. This design yields a supplemented first polynomial where the monomials have continuous orders and an even number of monomials, facilitating subsequent polynomial calculations.

[0008] In one possible design, extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial can include: first, treating every N consecutive monomials of the first polynomial as a second polynomial, resulting in M ​​second polynomials; then, determining the M reference variables corresponding to the M second polynomials by the ratio of the k-th variable in each of the M second polynomials to the k-th variable in the second polynomial with the lowest order, where k is a non-negative integer less than N; finally, determining the M N-order polynomials by the ratio between each of the M second polynomials and its corresponding reference variables. This design provides a method for obtaining M N-order polynomials and M reference variables.

[0009] In one possible design, loading the common variables corresponding to at least one polynomial to be calculated into at least one first register group, loading the variable coefficients corresponding to at least one polynomial to be calculated into at least one second register group, and loading the reference variables corresponding to at least one polynomial to be calculated into at least one third register group may include: for the first polynomial among the at least one polynomial to be calculated, where the first polynomial is any one of the at least one polynomial to be calculated, performing the following steps: loading the N common variables corresponding to the first polynomial into a first target register group, where the first target register group is any one of at least one first register group; loading the M*N variable coefficients corresponding to the first polynomial into a second target register group, where the second target register group is any one of at least one second register group; and loading the M reference variables corresponding to the first polynomial into a third target register group, where the third target register group is any one of at least one third register group.

[0010] In one possible design, the first target register group includes multiple first registers, each of which includes multiple storage locations. Loading the N common variables corresponding to the first polynomial into the first target register group can include: loading the i-th common variable among the N common variables into the j-th storage location of the (b+i)-th first register of the first target register group, where i is an integer taking values ​​from [0, N-1], j is a non-negative integer, and b is a non-negative integer. This design provides a method for loading common variables.

[0011] In one possible design, the second target register group includes multiple second registers, each with multiple storage locations. Loading the M*N variable coefficients corresponding to the first polynomial into the second target register group can include: loading the i-th variable coefficient corresponding to the m-th N-th polynomial among the M N-th polynomials into the b+i-th storage location of the (b+m)-th second register of the second target register group, where m is an integer ranging from [0, M-1], i is an integer ranging from [0, N-1], and b is a non-negative integer. This design provides a method for loading variable coefficients.

[0012] In one possible design, the third target register group includes multiple third registers, each with multiple storage locations. Loading the M reference variables corresponding to the first polynomial into the third target register group can include: loading the m-th reference variable among the M reference variables into the j-th storage location of the (b+m)-th third register of the third target register group, where m is an integer taking values ​​from [0, M-1], b is a non-negative integer, and j is a non-negative integer. This design provides a method for loading reference variables.

[0013] In one possible design, controlling the cross product calculation of the common variables in at least one first register group with the coefficients of the variables in at least one second register group to obtain the first result corresponding to at least one polynomial to be calculated may include: for the first polynomial in at least one polynomial to be calculated, where the first polynomial is any polynomial in at least one polynomial to be calculated, performing the following steps: controlling the cross product calculation of the common variables in the first target register group with the coefficients of the variables in the second target register group to obtain the first result corresponding to the first polynomial.

[0014] In one possible design, controlling the first result corresponding to at least one polynomial to be calculated and the reference variable in at least one third register group to perform an inner product calculation to obtain the second result corresponding to at least one polynomial to be calculated may include: for the first polynomial among the at least one polynomial to be calculated, where the first polynomial is any polynomial among the at least one polynomial to be calculated, performing the following steps: controlling the first result corresponding to the first polynomial to perform an inner product calculation with the reference variable in the third target register group to obtain the second result corresponding to the first polynomial.

[0015] Secondly, embodiments of this application provide a polynomial computing device that has the function of implementing the computing device behavior in the first aspect and any possible implementation method examples of the first aspect. The beneficial effects are described in the first aspect and will not be repeated here. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function. In one possible design, the device structure includes an acquisition module and a processing module. These modules can perform the functions of the computing device behavior in the first aspect and any possible implementation method examples of the first aspect, as detailed in the method examples, and will not be repeated here.

[0016] Thirdly, embodiments of this application provide a computing device that has the functionality to implement the computing device behavior described in the first aspect and any possible implementation method example of the first aspect. The beneficial effects are described in the first aspect and will not be repeated here. The computing device includes a processor and a memory. The processor is configured to support the device in executing the corresponding functions of the computing device in the method example of the first aspect. The memory is coupled to the processor and stores necessary program instructions and data for the communication device. The communication device also includes a communication interface for communicating with other devices.

[0017] Fourthly, this application also provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the methods described in the first aspect and various possible embodiments of the first aspect, or cause the computer to perform the methods described in the first aspect and various possible embodiments of the first aspect.

[0018] Fifthly, this application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods described in the first aspect and various possible implementations of the first aspect, or cause the computer to perform the methods described in the first aspect and various possible implementations of the first aspect.

[0019] In a sixth aspect, this application also provides a computer chip connected to a memory, the chip being used to read and execute software programs stored in the memory, to execute the methods described in the first aspect and various possible designs of the first aspect, or to cause a computer to execute the methods described in the first aspect and various possible implementations of the first aspect. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0021] Figure 2 A flowchart illustrating a polynomial calculation method provided in an embodiment of this application;

[0022] Figure 3 A flowchart illustrating a polynomial calculation method provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the structure of a first register group provided in an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure of a first register group provided in an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the structure of a second register group provided in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the structure of a second register group provided in an embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of a third register group provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram of the structure of a third register group provided in an embodiment of this application;

[0029] Figure 10 This is a schematic diagram of the structure of a first register group provided in an embodiment of this application;

[0030] Figure 11 This is a schematic diagram of the structure of a second register group provided in an embodiment of this application;

[0031] Figure 12 This is a schematic diagram of the structure of a third register group provided in an embodiment of this application;

[0032] Figure 13 This application provides a schematic diagram of the structure of a fourth register group according to an embodiment of the present application.

[0033] Figure 14 This application provides a schematic diagram of the structure of a fourth register group according to an embodiment of the present application.

[0034] Figure 15 This is a schematic diagram of the structure of a fifth register group provided in an embodiment of this application;

[0035] Figure 16 This is a schematic diagram of the structure of a fifth register group provided in an embodiment of this application;

[0036] Figure 17 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the application will be described in further detail below with reference to the accompanying drawings. The specific operating methods and functional descriptions in the method embodiments can also be applied to the device embodiments or system embodiments.

[0038] To better explain the embodiments of this application, the relevant terms or technologies used in this application will be explained first:

[0039] I. Row Vectors

[0040] A row vector is a 1×p matrix, where p is any positive integer, for example: x = [x1 x2 … x p ].

[0041] II. Column Vectors

[0042] The column vector is a q×1 matrix, where q is any positive integer, for example:

[0043] III. Matrix Size / Scale

[0044] A p×q matrix is ​​a rectangular array consisting of p rows and q columns of elements. For example:

[0045]

[0046] In a matrix, each number that makes up the matrix is ​​called an element of the matrix. For example, A 11 A 12 A pq All of these are elements of matrix A. The index (or coordinate) of an element indicates its position within the matrix; it can be the row number (or row coordinate) or column number (or column coordinate). For example, A 11 The subscript "11" indicates that the element is located in the first row and first column of matrix A. 21 This indicates that the element is located in the second row and first column of matrix A. Additionally, the element's subscript can have different representations, such as A... 11 It can also be written as A 1，1 A 21 It can also be written as A 2，1 Similar details will not be repeated below.

[0047] It should be noted that the row number of the first row of a matrix is ​​not limited to 1, but can also be other values, such as 0. Similarly, the column number of the first column of a matrix is ​​not limited to 1, but can also be 0 or other data. For example, if the row number of the first row and the column number of the first column of the matrix above are 0 and 0 respectively, then the index of the first element in the matrix is ​​"00", which means that the element is in the 0th row and 0th column of the matrix.

[0048] IV. Matrix addition

[0049] Matrix addition refers to the addition of two matrices of the same size (i.e., the two matrices have the same number of rows and columns), such as A and B, which are both p×q matrices, and matrix C = A + B.

[0050]

[0051]

[0052] Similarly, matrix subtraction refers to subtracting the elements at the same positions in two matrices of the same size.

[0053] V. Matrix multiplication

[0054] For two matrices to be multiplied (such as matrices D and E), the number of columns in D must be the same as the number of rows in E. For example, if D is a p×q matrix and E is a q×s matrix, then their product will be a p×s matrix.

[0055]

[0056]

[0057] The technical solutions provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0058] Figure 1 This is a schematic diagram of a computing device 100 provided in this application. The computing device 100 includes a processor 101 and a memory 102. Optionally, the computing device 100 may further include a communication interface 104 and a matrix arithmetic unit 106, wherein the processor 101, memory 102, matrix arithmetic unit 106, and communication interface 104 can be interconnected via a communication line 105; the communication line 105 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication line 105 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 1 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0059] The processor 101 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an artificial intelligence (AI) chip, a system-on-chip (SoC), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, or one or more integrated circuits used to control the execution of the program of the present application.

[0060] Please note, Figure 1Only one processor 101 is shown in this embodiment. In practical applications, there can be multiple processors 101. These multiple processors 101 may include multiple processors of the same type or multiple processors of different types. For example, the multiple processors 101 may include multiple CPUs. Alternatively, the multiple processors 101 may include at least one CPU and at least one GPU. Each CPU may have one or more CPU cores. This embodiment does not limit the number of processors 101 or the number of CPU cores.

[0061] Specifically, the processor 101 is used to process data access requests from outside the computing device 100 (such as other computing devices), and also to process requests generated internally by the computing device 100. For example, the request may be a write data request, which includes a polynomial. After receiving the write data request, the processor 101 can execute the polynomial calculation method provided in this embodiment to process the polynomial and store the processed data in the memory 102. Alternatively, the request may be a read data request, which requests to read polynomial data. The polynomial data may include part or all of the polynomial. After receiving the read data request, the processor 101 reads the polynomial data from the memory 102.

[0062] In addition to the above, processor 101 is also used for other data calculations or processing, such as matrix operations, which are not specifically limited. Optionally, the aforementioned matrix operations can also be assigned to matrix operation unit 106 for execution. In some cases, when processor 101 has multiple cores, or computing device 100 includes multiple processors 101, or computing device 100 includes multiple matrix operation units 106, multiple cores, multiple processors 101, or multiple matrix operation units 106 can execute matrix operations in parallel, which will not be discussed in detail here.

[0063] The matrix operator 106 can be used to process matrix operations, as described above in the introduction to matrix operations, and will not be repeated here. The matrix operator 106 may include, but is not limited to, vector processors (VP), vector processor systems (VPS), matrix processors, matrix accelerators, etc., without specific limitations.

[0064] Communication interface 104 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), wired access network, etc. For example, it can receive read data requests, write data requests, etc.

[0065] Memory 102 is used to store data and computer-executable program code. Data includes, but is not limited to, polynomial data. The executable program code may include the program code for the polynomial calculation method provided in this embodiment. Processor 101 executes the executable program code to implement the polynomial calculation method provided in this embodiment. That is, memory 102 stores computer execution instructions for executing the solution of this application, and the processor 101 controls the execution. Processor 101 is used to execute the computer execution instructions stored in memory 102 to implement the polynomial calculation method provided in the above embodiments of this application.

[0066] The memory 102 can exist independently and be connected to the processor via communication line 105. Alternatively, the memory 102 can be integrated with the processor. Specifically, the memory 102 may include RAM or a hard disk. RAM refers to the internal storage that directly exchanges data with the processor 101. It can read and write data at any time and is very fast, serving as temporary data storage for the operating system or other running programs. Unlike RAM, the hard disk reads and writes data more slowly and is typically used for persistent data storage. In some applications, the processor 101 can temporarily store data in RAM. When the total amount of data in RAM reaches a certain threshold, the processor 101 sends the data stored in RAM to the hard disk for persistent storage. This data can be obtained from external devices, input by the user, or generated by the computing device 100; there are no specific limitations. Alternatively, the processor 101 can read data from RAM. If a memory cache miss occurs, the processor 101 reads the data from the hard disk into RAM and then reads the data from RAM again.

[0067] The memory includes at least two types of storage, such as random access memory (RAM) and read-only memory (ROM). For example, RAM can be dynamic random access memory (DRAM) or storage class memory (SCM). Memory can also include other types of RAM, such as static random access memory (SRAM). For read-only memory, examples include programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM). Additionally, the memory can be a dual in-line memory module (DIMM), i.e., a module composed of DRAM. In practical applications, the computing device 100 can be configured with multiple memory modules of different types. This embodiment does not limit the number or type of memory.

[0068] A hard drive can specifically be a disk or other type of storage medium, such as a solid-state drive (SSD), a hard disk drive (HDD), a shingled magnetic recording hard disk, a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0069] It should be noted that, Figure 1 The structure of the computing device 100 shown is merely an example. In actual applications, the computing device 100 may have more or fewer components. For example, the computing device 100 may also include input / output devices such as a keyboard, mouse, and display screen. This application embodiment does not limit this.

[0070] Next, let's apply it to... Figure 1 Taking the computing device shown as an example, the polynomial calculation method provided in the embodiments of this application will be described in detail.

[0071] Figure 2This is a flowchart illustrating the polynomial calculation method provided in the embodiments of this application. The method can be executed by a computing device with data processing capabilities (such as computing device 100), or by a component of that computing device, such as processor 101 or matrix arithmetic unit 106. For ease of explanation, the following description uses computing device 100 as an example. Figure 2 As shown, the method includes:

[0072] S201, Obtain multiple polynomials to be calculated in the polynomial calculation application.

[0073] In this embodiment, the polynomial to be calculated includes a basic variable. The polynomial to be calculated includes at least two monomials. The basic variable included in each monomial of the polynomial to be calculated is the same. The polynomial to be calculated may consist of the sum / difference of at least two monomials, wherein each monomial is an expression obtained by the basic variable, the variable coefficients, and the multiplication and exponentiation operations (non-negative integer powers) between them.

[0074] For example, the polynomial to be calculated is a1x 1 +a2x 2 +a4x 4 , where a1x 1 a2x 2 and a4x 4 All are monomials, with a1, a2, and a4 as variable coefficients and x as the basic variable. a1, a2, a4, and x can be any known values.

[0075] For ease of description later, when the polynomial to be calculated consists of the sum / difference of at least two monomials, the polynomial can be adjusted so that the adjusted polynomial consists of the sum of at least two monomials. The adjusted polynomial facilitates subsequent polynomial calculations. For example, the polynomial to be calculated is 2x. 1 +3x 2 -4x 3 The polynomial to be calculated can be adjusted, and the adjusted polynomial is 2x. 1 +3x 2 +(-4x 3 ).

[0076] S202, divide the multiple polynomials to be calculated into multiple groups to be calculated.

[0077] In this embodiment, polynomials with the same variable coefficients can be grouped into a calculation group. Each calculation group includes at least one polynomial, and the variable coefficients of at least one polynomial in each calculation group are the same.

[0078] The multiple groups to be calculated include a first group to be calculated, wherein the first group to be calculated is any one of the multiple groups to be calculated. The following explanation will use the first group to be calculated as an example.

[0079] S203, determine the common variables, variable coefficients and reference variables corresponding to at least one polynomial to be calculated in the first group to be calculated.

[0080] In the embodiments of this application, at least one polynomial to be calculated includes a first polynomial, wherein the first polynomial is any polynomial among the at least one polynomial to be calculated, and the following description uses the first polynomial as an example.

[0081] Before determining the common variables, coefficients, and reference variables of the first polynomial, we can first determine whether the orders of the monomials included in the first polynomial are continuous. If the orders of the monomials are not continuous, we add monomials corresponding to the missing orders to the first polynomial, with the coefficients of the missing monomials being zero. Next, we determine whether the number of monomials in the first polynomial is odd. If the number of monomials is odd, we add an odd number of monomials to the first polynomial, with the coefficients of all odd-numbered monomials being zero. After adding an odd number of monomials, the orders of the monomials in the supplemented first polynomial are still continuous. Through this method, we can obtain a supplemented first polynomial where the orders of the monomials are continuous and the number of monomials is even, facilitating subsequent polynomial calculations.

[0082] It should be understood that, in order to improve the speed of subsequent polynomial calculations, when the number of monomials in the first polynomial is determined to be odd, a monomial is added to the first polynomial, and the coefficient of this added monomial is zero. For the sake of convenience in subsequent discussions, the following explanation will use the example of adding a monomial to the first polynomial.

[0083] For example, if the first polynomial obtained is a1x 1 +a3x 3 The first polynomial contains two monomials of orders 1 and 3, respectively. Therefore, the orders of these two monomials are not consecutive, and a second-order monomial is missing. Thus, a second-order monomial is used to supplement the first polynomial, updating it to a1x. 1 +a2x 2 +a3x 3 , where a2 is 0.

[0084] First polynomial a1x 1 +a2x 2 +a3x 3It contains 3 monomials, and the number of monomials is odd. It can be expressed as a1x 1 +a2x 2 +a3x 3 Add a monomial to a1x. In one case, this can be done by adding a monomial to a1x. 1 +a2x 2 +a3x 3 Supplement a0x 0 The first polynomial is updated to a0x 0 +a1x 1 +a2x 2 +a3x 3 Where a0 is 0. In another case, it can be expressed as a1x. 1 +a2x 2 +a3x 3 Supplement a4x 4 The first polynomial is updated to a1x 1 +a2x 2 +a3x 3 +a4x 4 , where a4 is 0.

[0085] Given that the monomials in the first polynomial are of continuous order and the number of monomials is even, perform the following steps: First, extract M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial. Then, based on the M N-order polynomials, determine N common variables and M*N variable coefficients, where M is a positive integer and N is an integer greater than 1.

[0086] In the embodiments of this application, M N-order polynomials and M reference variables corresponding to the M N-order polynomials can be extracted from the first polynomial through the following possible implementation methods, including: Figure 3 The following steps are shown:

[0087] S301, take every N consecutive monomials of the first polynomial as a second polynomial, and obtain M second polynomials.

[0088] In this embodiment, the number of monomials in the first polynomial is N*M, where N can be an integer greater than 1 and less than the number of monomials in the first polynomial, M is a positive integer, and * represents multiplication, which will not be elaborated further below. For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6Let N be 3. Based on the first polynomial above, we can obtain two second polynomials. Each second polynomial includes three monomials of adjacent orders, namely a1x 1 +a2x 2 +a3x 3 a4x 4 +a5x 5 +a6x 6 .

[0089] In this embodiment, given a fixed first polynomial, the number M of the resulting second polynomials differs depending on the value of N. The value of N can be determined through the following two possible implementation methods.

[0090] The first possible implementation is to randomly select one value from the possible values ​​corresponding to N as the value of N.

[0091] For example, if N can take the values ​​2 and 3, then 2 is randomly selected as the value of N.

[0092] The second possible implementation involves determining the partitioning results corresponding to the possible values ​​of N, where each partitioning result includes M second polynomials. After determining the execution time corresponding to different partitioning results, the value corresponding to the partitioning result with the shortest execution time is selected as the value of N. The execution time corresponding to each partitioning result includes the execution time required to obtain the results corresponding to the M second polynomials individually, and the execution time required to obtain the sum of the M second polynomials.

[0093] In the M second polynomials, the result of each second polynomial is obtained through inner product calculation. Therefore, the execution time required to obtain the result of each second polynomial is the time required for the inner product calculation. The sum of the M second polynomials requires M-1 accumulations, so the execution time required to obtain the sum of the M second polynomials is the time required for the M-1 accumulations. Specifically, the execution time to obtain the sum of the M second polynomials is equal to (M-1) * the time required for the accumulation calculation.

[0094] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 The first polynomial has 6 monomials, and N can be 2 or 3. The time for the first inner product calculation is set to t1, which can be understood as the inner product of two 2×2 matrices. The time for the second inner product calculation is set to t2, which can be understood as the inner product of two 3×3 matrices. The time for the cumulative calculation is set to t3.

[0095] When N is 2, the first polynomial is partitioned to obtain the first partition result, which includes three second polynomials, namely a1x. 1 +a2x 2 a3x 3 +a4x 4 a5x 5 +a6x 6 The result of each second polynomial is obtained through inner product calculation, so the execution time required to obtain the result of each second polynomial is t1. The execution time required to obtain the results of the above three second polynomials is 3*t1. The sum of the three second polynomials requires two accumulation calculations, so the execution time to obtain the sum of the three second polynomials is 2*t3. Therefore, the execution time corresponding to the first partition result is equal to 3*t1 + 2*t3.

[0096] When N is 3, the first polynomial is partitioned to obtain a second partition result, which includes two second polynomials, namely a1x. 1 +a2x 2 +a3x 3 and a4x 4 +a5x 5 +a6x 6 The result of each second polynomial is obtained through inner product calculation, so the execution time required to obtain the result of each second polynomial is t2. The execution time required to obtain the results of the above two second polynomials is 2*t2. The sum of the two second polynomials requires one accumulation, so the execution time to obtain the sum of the two second polynomials is t3. Therefore, the execution time corresponding to the second partition result is equal to 2*t2 + t3.

[0097] The execution time corresponding to the first partition result is 3*t1+2*t3, and the execution time corresponding to the second partition result is 2*t2+t3. Based on the comparison of the two execution times, if 3*t1+2*t3 is less than 2*t2+t3, then N is 2; if 3*t1+2*t3 is greater than 2*t2+t3, then N is 3; if 3*t1+2*t3 is equal to 2*t2+t3, then N can be either 2 or 3.

[0098] S302, the ratio of the k-th variable included in each of the M second polynomials to the k-th variable included in the second polynomial with the lowest order is determined as the M reference variables corresponding to the M second polynomials; k is a non-negative integer less than N.

[0099] S303, determine the ratio between each of the M second polynomials and its corresponding reference variable as M N-order polynomials.

[0100] In the embodiments of this application, based on Figure 3 From the steps in the diagram, it can be seen that the first polynomial can be decomposed into M N-order polynomials and M reference variables, where the M N-order polynomials correspond one-to-one with the M reference variables.

[0101] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 The first polynomial has 6 monomials. Let N be 2. Obtain 3 second polynomials from the first polynomial, i.e., a1x 1 +a2x 2 a3x 3 +a4x 4 a5x 5 +a6x 6 Each second polynomial includes two variables, the 0th variable and the 1st variable, where k takes the value 0 or 1. The second polynomial with the lowest order is a1x. 1 +a2x 2 .

[0102] In this embodiment, k takes the value of 0 or 1. The following explanation uses the value of k as 0, referring to the 0th second polynomial a1x. 1 +a2x 2 The 0th variable in the second polynomial is x. 1 The second polynomial with the lowest order, a1x 1 +a2x 2 The 0th variable is x 1 Then the reference variable corresponding to the 0th second polynomial is x. 1 / x 1 =1. The 0th second polynomial a1x 1 +a2x 2 The ratio a1x between the reference variable 1 and the reference variable 1 1 +a2x 2 , as the 0th second-order polynomial.

[0103] For the first second polynomial a3x 3 +a4x 4 The 0th variable x in the second polynomial 3 The second polynomial with the lowest order, a1x 1 +a2x 2 The 0th variable is x 1 Then the reference variable corresponding to the first second polynomial is x. 3 / x1 =x 2 The first second polynomial a3x 3 +a4x 4 With the corresponding reference variable x 2 The ratio between a3x 1 +a4x 2 , as the first second-order polynomial.

[0104] For the second second polynomial a5x 5 +a6x 6 The 0th variable x in the second polynomial 5 The second polynomial with the lowest order, a1x 1 +a2x 2 The 0th variable is x 1 Then the reference variable corresponding to the second polynomial is x. 5 / x 1 =x 4 The second polynomial a5x 5 +a6x 6 With the corresponding reference variable x 4 The ratio between a5x 1 +a6x 2 , as the second second-order polynomial.

[0105] In summary, from the first polynomial a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 The three extracted second-order polynomials are a1x 1 +a2x 2 a3x 1 +a4x 2 a5x 1 +a6x 2 The three reference variables corresponding to the three second-order polynomials are 1, x, and x. 2 and x 4 Therefore, the first polynomial a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 It can be broken down into the following structure.

[0106] a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x5 +a6x 6

[0107] =1*(a1x 1 +a2x 2 )+x 2 *(a3x 1 +a4x 2 )+x 4 *(a5x 1 +a6x 2 )

[0108] In the embodiments of this application, each Nth-order polynomial includes N common variables and N variable coefficients, with each of the N common variables corresponding to one of the N variable coefficients. The M Nth-order polynomials each include the same N common variables.

[0109] Based on the above examples, each second-order polynomial includes two common variables x. 1 and x 2 The 0th second-order polynomial includes two common variables x. 1 and x 2 The coefficients of the two shared variables are a1 and a2, respectively. The first second-order polynomial includes two shared variables x. 1 and x 2 The coefficients of the two shared variables are a3 and a4, respectively. The second second-order polynomial includes the shared variable x. 1 and x 2 The coefficients of the two shared variables are a5 and a6, respectively.

[0110] S204, load the common variables corresponding to at least one polynomial to be calculated into at least one first register group, load the variable coefficients corresponding to at least one polynomial to be calculated into at least one second register group, and load the reference variables corresponding to at least one polynomial to be calculated into at least one third register group.

[0111] For the first polynomial in at least one of the polynomials to be computed, perform the following steps:

[0112] Load the N common variables corresponding to the first polynomial into the first target register group, which can be any one of at least one first register group; load the M*N variable coefficients corresponding to the first polynomial into the second target register group, which can be any one of at least one second register group; load the M reference variables corresponding to the first polynomial into the third target register group, which can be any one of at least one third register group.

[0113] In this embodiment, the first register group includes multiple first registers, and each first register includes multiple storage locations. Generally, the first register group includes eight first registers. Each first register can store 512 bits (binary digits) of data. Since each first register is configured to include eight storage locations, each storage location in the first register can store 64 bits of data. The first register can be a scalable vector extension (SVE) register.

[0114] like Figure 4 As shown, for ease of description later, each of the eight first registers in the first register group can be numbered as V0, V1, V2, V3, V4, V5, V6, and V7. Each memory location within each first register can also be numbered as 0, 1, 2, 3, 4, 5, 6, and 7. Each memory location in the first register group can be initialized with 0.

[0115] In one possible implementation, loading the N common variables corresponding to the first polynomial into the first target register group can be achieved through the following steps: loading the i-th common variable among the N common variables into the j-th storage location of the (b+i)-th first register in the first target register group, where i is an integer ranging from [0, N-1], j is a non-negative integer, and b is a non-negative integer. In this embodiment, since the first register group includes 8 first registers, and each first register includes 8 storage locations, the value range of b+i is any integer in [0, 7], and the value range of j is any integer in [0, 7].

[0116] In the embodiments of this application, the loading method of the N common variables corresponding to the first polynomial may include the following methods.

[0117] For the 0th common variable corresponding to the first polynomial, the 0th common variable can be loaded in the following way: for example, the 0th common variable can be directly obtained from the N common variables and loaded into the first target register group.

[0118] For the shared variables corresponding to the first polynomial, excluding the 0th shared variable, there are two possible ways to load them. One possible way is to directly obtain the other shared variables from the N shared variables and load them into the first destination register set. Another possible way is to calculate based on the 0th shared variable in the first destination register set to obtain the other shared variables. For example, if the 0th shared variable is x... 1 The other common variables are x2 , in x 1 After being loaded into the first target register set, calculations are performed within the first target register set, and x is... 1 *x 1 As a common variable, x 2 and obtain x 2 Add it to the first target register group.

[0119] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 Its three corresponding second-order polynomials are a1x 1 +a2x 2 a3x 1 +a4x 2 and a5x 1 +a6x 2 The three reference variables corresponding to the three second-order polynomials are 1, x, and y. 2 and x 4 .

[0120] All three second-order polynomials include two common variables x. 1 and x 2 The 0th common variable is x 1 The first common variable is x. 2 Let j = 0, b = 0, as follows Figure 5 As shown, the 0th common variable x 1 Load the first public variable x into the 0th storage location of the 0th (0+0=0) first register of the first target register group. 2 Load into the 0th storage location of the 1st (0+1=1) first register in the first target register group, where the 0th first register is the first register V0 and the 1st first register is the first register V1.

[0121] It should be understood that the shared variables located in the (b+i)th first register of the first destination register group should have the same variable coefficients. When shared variables have the same coefficients, they can be loaded into different storage locations within the same first register. For example, the shared variable x might be stored in the 0th storage location of the 0th first register of the first destination register group. 1 The corresponding variable coefficient is a1, and the common variable y is stored in the first storage location of the 0th register of the first target register group. 1 The corresponding variable coefficient is still a1, and there are a total of variables x.1 and y 1 The corresponding variable coefficients are the same.

[0122] In this embodiment, the second register group includes multiple second registers, each of which includes multiple storage locations. Generally, the second register group includes eight second registers. Each second register can store 512 bits of data. Since each second register is configured to include eight storage locations, each storage location in the second register can store 64 bits of data. The second registers can be scalable matrix extension (SME) registers.

[0123] like Figure 6 As shown, for ease of description later, each second register in the second register group can be numbered, with the eight second registers numbered e0, e1, e2, e3, e4, e5, e6, and e7 respectively. Each storage location within each second register can also be numbered, with the eight storage locations of each second register numbered 0, 1, 2, 3, 4, 5, 6, and 7 respectively. Each storage location in the second register group can be initialized with 0. To facilitate a more intuitive understanding of polynomial calculations later, each second register in the second register group uses... Figure 6 The structure shown is as described. Other arrangements of the second registers in the second register group are not limited here.

[0124] In one possible implementation, loading the M*N variable coefficients corresponding to the first polynomial into the second target register group can be achieved through the following steps: loading the i-th variable coefficient corresponding to the m-th N-th polynomial among the M N-th polynomials into the b+i-th storage location of the second second register in the second target register group, where m is an integer ranging from [0, M-1], i is an integer ranging from [0, N-1], and b is a non-negative integer. In this embodiment, since the second register group includes 8 second registers, and each second register includes 8 storage locations, the value range of b+i is any integer in [0, 7], and the value range of b+m is any integer in [0, 7].

[0125] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 Its three corresponding second-order polynomials are a1x 1 +a2x 2 a3x 1 +a4x 2and a5x 1 +a6x 2 The coefficients of the three second-order polynomials are a1, a2, a3, a4, a5, and a6, respectively.

[0126] Set b = 0, such as Figure 7 As shown, the 0th second-order polynomial a1x 1 +a2x 2 The corresponding variable coefficients are a1 and a2. In the 0th second-order polynomial, the 0th variable coefficient is a1, and the 1st variable coefficient is a2. When m = 0 and i = 0, the 0th variable coefficient a1 of the 0th second-order polynomial is loaded into the 0th (0+0=0)th storage location of the 0th (0+0=0)th second register in the second destination register group. When m = 0 and i = 1, the 1st variable coefficient a2 of the 0th second-order polynomial is loaded into the 0th (0+0=0)th storage location of the 1st (0+1=0)th second register in the second destination register group. The 0th second register is the second register e0, and the 1st second register is the second register e1.

[0127] The first second-order polynomial a3x 1 +a4x 2 The corresponding variable coefficients are a3 and a4. In the first second-order polynomial, the 0th variable coefficient is a3, and the 1st variable coefficient is a4. When m = 1 and i = 0, the 0th variable coefficient a3 of the first second-order polynomial is loaded into the 1st (0+1=1) storage location of the 0th (0+0=0) second register in the second destination register group; when m = 1 and i = 1, the 1st (0+1=1) variable coefficient a4 of the first second-order polynomial is loaded into the 1st (0+1=0) second register in the second destination register group. The 0th second register is the second register e0, and the 1st second register is the second register e1.

[0128] The second second-order polynomial a5x 1 +a6x 2The corresponding variable coefficients are a5 and a6. In the second second-order polynomial, the 0th variable coefficient is a5, and the 1st variable coefficient is a6. When m=2 and i=0, the 0th variable coefficient a5 of the second second-order polynomial is loaded into the 2nd (0+2=0) storage location of the 0th (0+0=0)th second register in the second destination register group; when m=2 and i=1, the 1st variable coefficient a6 of the second second-order polynomial is loaded into the 2nd (0+2=2) storage location of the 1st (0+1=0)th second register in the second destination register group. The 0th second register is the second register e0, and the 1st second register is the second register e1.

[0129] In this embodiment, the third register group includes multiple third registers, and each third register includes multiple storage locations. Generally, the third register group includes eight third registers. Each third register can store 512 bits of data. Since each third register is configured to include eight storage locations, each storage location in the third register can store 64 bits of data. The third register can be an SVE register.

[0130] like Figure 8 As shown, for ease of description later, each third register in the third register group can be numbered, with the eight third registers numbered U0, U1, U2, U3, U4, U5, U6, and U7 respectively. Each storage location within each third register can also be numbered, with the eight storage locations of each third register numbered 0, 1, 2, 3, 4, 5, 6, and 7 respectively. Each storage location in the third register group can be initialized with 0.

[0131] In one possible implementation, loading the M reference variables corresponding to the first polynomial into the third target register group can be achieved through the following steps: loading the m-th reference variable among the M reference variables into the j-th storage location of the (b+m)-th third register in the third target register group, where m is an integer ranging from [0, M-1], b is a non-negative integer, and j is a non-negative integer. In this embodiment, since the third register group includes 8 third registers, and each third register includes 8 storage locations, the value range of b+m is any integer in [0, 7], and the value range of j is any integer in [0, 7].

[0132] For example, the first polynomial is a1x 1 +a2x 2 +a3x 3 +a4x 4 +a5x 5 +a6x 6 Its three corresponding second-order polynomials are a1x 1+a2x 2 a3x 1 +a4x 2 and a5x 1 +a6x 2 The three reference variables corresponding to the three second-order polynomials are 1, x, and y. 2 and x 4 .

[0133] Set j=0, b=0, such as Figure 9 As shown, when m=0, the 0th reference variable 1 is loaded into the 0th storage location of the 0th (0+0=0)th third register in the third target register group. The 0th third register is the third register U0.

[0134] When m=1, the first reference variable x 2 Load the data into the 0th storage location of the 1st (0+1=1)th third register in the third target register group. The 1st third register is the third register U1.

[0135] When m=2, the second reference variable x 4 Loaded into the 0th storage location of the 0th (0+2=2)th third register in the third target register group. The 2nd third register is the third register U2.

[0136] When multiple first polynomials are obtained, the above method can be used to determine the N common variables, M*N variable coefficients, and M reference variables corresponding to each first polynomial. The N common variables corresponding to each first polynomial are loaded into the first target register group, the M*N variable coefficients corresponding to each first polynomial are loaded into the second target register group, and the M reference variables corresponding to each first polynomial are loaded into the third target register group.

[0137] Let's take 24 first polynomials as an example. The 0th to 7th first polynomials are respectively...

[0138]

[0139]

[0140]

[0141]

[0142]

[0143]

[0144]

[0145]

[0146] Among them, x0, x1, x2, x3, x4, x5, x6 and x7 are basic variables with different values.

[0147] Taking the 0th first polynomial as an example, the 0th first polynomial can be expressed as follows:

[0148]

[0149] The 0th first polynomial consists of three second-order polynomials, with each of the three reference variables being 1. and The three second-order polynomials include the following common variables: and The coefficients of the three second-order polynomials are a1, a2, a3, a4, a5, and a6.

[0150] The method for obtaining the reference variables, common variables, and coefficients of the first to seventh first polynomials is similar to the method for obtaining the reference variables, common variables, and coefficients of the zeroth first polynomial, and will not be elaborated here.

[0151] The 8th to 15th first polynomials are respectively

[0152]

[0153]

[0154]

[0155]

[0156]

[0157]

[0158]

[0159]

[0160] Among them, y0, y1, y2, y3, y4, y5, y6 and y7 are basic variables with different values.

[0161] Taking the 8th first polynomial as an example, the 8th first polynomial can be expressed as follows:

[0162]

[0163] The eighth first polynomial consists of two second-order polynomials, with the two reference variables corresponding to these two second-order polynomials being 1 and 2. The common variables included in the two second-order polynomials are and The coefficients of the two second-order polynomials are b1, b2, b3, and b4.

[0164] The method for obtaining the reference variables, common variables, and coefficients of the 9th to 15th first polynomials is similar to the method for obtaining the reference variables, common variables, and coefficients of the 8th first polynomial, and will not be repeated here.

[0165] The 16th to 23rd first polynomials are respectively

[0166]

[0167]

[0168]

[0169]

[0170]

[0171]

[0172]

[0173]

[0174] Among them, z0, z1, z2, z3, z4, z5, z6 and z7 are basic variables with different values.

[0175] Taking the 16th first polynomial as an example, the 16th first polynomial can be expressed as follows:

[0176]

[0177] The 16th first polynomial consists of two 3rd-order polynomials, with 1 and 2 corresponding to two reference variables. The common variables included in the two third-order polynomials are and The coefficients of the two third-order polynomials are c1, c2, c3, c4, c5, and c6.

[0178] like Figure 10 As shown, the common variables corresponding to the above 24 first polynomials are added to the first target register group, as follows. Figure 11As shown, the coefficients of the variables corresponding to the above 24 first polynomials are loaded into the second target register group, as follows. Figure 12 As shown, the reference variables corresponding to the above 24 first polynomials are loaded into the third target register group.

[0179] S205, control at least one common variable in the first register group to perform an outer product calculation with the coefficients of the variables in at least one second register group to obtain the first result corresponding to at least one polynomial to be calculated.

[0180] For the first polynomial in at least one polynomial to be calculated, the coefficients of the common variables in the first target register group and the variable coefficients in the second target register group are used to perform an outer product calculation to obtain the first result corresponding to the first polynomial.

[0181] In this embodiment, the first result corresponding to the first polynomial can be stored in the fourth destination register group. The fourth destination register group includes multiple fourth registers, and each fourth register includes multiple storage locations. Generally, the fourth register group includes 8 fourth registers. Each fourth register can store 512 bits of data. Since each fourth register is set to include 8 storage locations, each storage location in the fourth register can store 64 bits of data. The fourth register can be an SVE register.

[0182] like Figure 13 As shown, for ease of description later, each of the eight fourth registers in the fourth register group can be numbered as W0, W1, W2, W3, W4, W5, W6, and W7. Each memory location within each fourth register can also be numbered as 0, 1, 2, 3, 4, 5, 6, and 7. Each memory location in the fourth register group can be initialized with 0.

[0183] Specifically, the m-th first result among the M first results corresponding to the first polynomial can be loaded into the j-th storage location of the (b+m)-th fourth target register, where m is an integer taking values ​​in the range [0, M-1], b is a non-negative integer, and j is a non-negative integer. In this embodiment, since the fourth register group includes 8 fourth registers, and each fourth register includes 8 storage locations, the value range of b+m is any integer in the range [0, 7], and the value range of j is any integer in the range [0, 7].

[0184] In one possible implementation, the outer product of the b-th storage location of each first register in the first target register group and the q-th storage location of each second register in the second target register group is calculated to obtain the first result corresponding to the first polynomial, where b is an integer taking all values ​​in [0,7] and q is an integer taking all values ​​in [0,7].

[0185] Using the 24 first polynomials mentioned earlier as an example, the common variables corresponding to the 24 first polynomials are stored in... Figure 10 The first target register group shown stores the variable coefficients corresponding to the 24 first polynomials in... Figure 11 The second target register group shown illustrates how to calculate the first results corresponding to the 24 first polynomials by performing an outer product between the common variables in the first target register group and the variable coefficients in the second target register group. The first results corresponding to the 24 first polynomials are stored in... Figure 14 In the fourth target register group shown.

[0186] The first result is obtained by performing an outer product calculation between the 0th storage location of each first register in the first target register group and the 0th storage location of each second register in the second target register group. and the first result Load into the 0th fourth destination register at the 0th storage location.

[0187] The first result is obtained by performing an outer product calculation between the 0th storage location of each first register in the first target register group and the 1st storage location of each second register in the second target register group. and the first result Load into the 0th storage location of the 1st fourth destination register.

[0188] The first result is obtained by performing an outer product calculation between the 0th storage location of each first register in the first target register group and the 2nd storage location of each second register in the second target register group. and the first result Load into the 0th storage location of the 2nd fourth destination register.

[0189] The first result is obtained by performing an outer product calculation between the 0th storage location of each first register in the first target register group and the 3rd storage location of each second register in the second target register group. and the first result Load into the 0th storage location of the 3rd fourth destination register.

[0190] The outer product of the 0th storage location of each first register in the first target register group and the 4th storage location of each second register in the second target register group is calculated to obtain the first result. and the first result Load into the 0th storage location of the 4th target register.

[0191] The first result is obtained by performing an outer product calculation between the 0th storage location of each first register in the first target register group and the 5th storage location of each second register in the second target register group. and the first result Load into the 0th storage location of the 5th fourth destination register.

[0192] The first result is obtained by performing an outer product calculation on the 0th storage location of each first register in the first target register group and the 6th storage location of each second register in the second target register group. and the first result Load into the 0th storage location of the 6th fourth destination register.

[0193] The outer product of the 0th storage location of each first register in the first target register group and the 7th storage location of each second register in the second target register group is calculated to obtain a first result of 0, and the first result 0 is loaded into the 0th storage location of the 7th fourth target register.

[0194] The above steps are repeated for the first 1-7 storage locations of each first register in the first target register group, which will not be elaborated here.

[0195] S206, control at least one polynomial to be calculated to perform inner product calculation with the first result corresponding to each of the at least one polynomial to be calculated and the reference variable in at least one third register group to obtain the second result corresponding to each of the at least one polynomial to be calculated.

[0196] For the first polynomial in at least one polynomial to be calculated, the inner product of the first result corresponding to the first polynomial and the reference variable in the third target register group is calculated to obtain the second result corresponding to the first polynomial.

[0197] In this embodiment, the second result of the first polynomial can be stored in the fifth destination register group. The fifth destination register group includes multiple fifth registers, each of which includes multiple storage locations. Generally, the fifth register group includes eight fifth registers. Each fifth register can store 512 bits of data. Since each fifth register is configured to include eight storage locations, each storage location in the fifth register can store 64 bits of data. The fifth register can be an SVE register.

[0198] like Figure 15As shown, for ease of description later, each of the eight fifth registers in the fifth register group can be numbered, with Z0, Z1, Z2, Z3, Z4, Z5, Z6, and Z7 respectively. Each memory location within each fifth register can also be numbered, with the eight memory locations of each fifth register numbered 0, 1, 2, 3, 4, 5, 6, and 7 respectively. Each memory location in the fifth register group can be initialized with 0.

[0199] It should be understood that before performing the inner product calculation, the number of first results corresponding to the first polynomial and the number of reference variables need to be determined. In the embodiments of this application, the number of first results corresponding to the first polynomial is M, and the number of reference variables is M. The number of first results corresponding to the first polynomial and the number of reference variables can be stored in the sixth target register group before the inner product calculation.

[0200] by Figure 12 The third target register group shown, Figure 14 Taking the fourth target register group as an example, this illustrates how to perform an inner product calculation between the first result in the fourth target register group and the reference variable in the third target register group to obtain the second result of 24 first polynomials. The second result of the 24 first polynomials is stored in... Figure 16 The fifth target register group is shown.

[0201] The number of temporary values ​​corresponding to the 0th first polynomial is determined to be 3, and the number of reference variables is 3. The inner product of the 0th storage location of the fourth registers W0~W2 in the fourth target register group and the 0th storage location of the third registers U0~U2 in the third target register group is calculated to obtain the second result of the first polynomial. and the second result of the first polynomial Load into the 0th storage location of the 0th register in the 0th target register group.

[0202] The calculation process for the second result corresponding to the 1st to 7th first polynomials is similar to that for the 0th first polynomial, and will not be repeated here.

[0203] The number of temporary values ​​corresponding to the 8th first polynomial is determined to be 2, and the number of reference variables is 2. The inner product of the 0th storage location of the fourth register W3~W4 in the fourth target register group and the 0th storage location of the third register U3~U4 in the third target register group is calculated to obtain the second result of the first polynomial. and the second result of the first polynomial Load into the 0th storage location of the 1st fifth destination register in the 5th register group.

[0204] The calculation process for the second result corresponding to the 9th to 15th first polynomials is similar to that for the 8th first polynomial, and will not be repeated here.

[0205] The number of temporary values ​​corresponding to the 16th first polynomial is determined to be 2, and the number of reference variables is also determined to be 2. The inner product of the 0th storage location of registers W5-W6 in the fourth target register group and the 0th storage location of registers U5-U6 in the third target register group is calculated to obtain the second result of the first polynomial. and the second result of the first polynomial Load into the 0th storage location of the 2nd fifth register in the fifth target register group.

[0206] The calculation process for the second result corresponding to the 17th to 23rd first polynomials is similar to that for the 16th first polynomial, and will not be repeated here.

[0207] When calculating a large number of polynomials, the above method can transform polynomial loop calculations into matrix calculations between register groups, thereby improving calculation speed.

[0208] Based on the same inventive concept as the method embodiments, this application also provides a polynomial calculation device for performing the above-described... Figure 2 The method of the method embodiment. For example... Figure 17 As shown, the polynomial calculation device 1700 includes an acquisition module 1701 and a processing module 1702. Specifically, in this polynomial calculation device 1700, the modules are connected through a communication path. In one application scenario, the memory 102 stores executable program code, and the processor 101 executes the executable program code to implement the functions of the aforementioned acquisition module 1701 and processing module 1702, thereby realizing the polynomial calculation method provided in this embodiment.

[0209] The acquisition module 1701 is used to acquire multiple polynomials to be calculated in polynomial calculation applications.

[0210] Processing module 1702 is used to divide multiple polynomials to be calculated into multiple groups to be calculated. Each group to be calculated includes at least one polynomial to be calculated. The at least one polynomial to be calculated in each group has the same type. The multiple groups to be calculated include a first group to be calculated, which is any one of the multiple groups to be calculated. The module determines the common variables, variable coefficients, and reference variables corresponding to at least one polynomial to be calculated in the first group to be calculated. The at least one polynomial to be calculated in the first group to be calculated has the same variable coefficients. The module loads the common variables corresponding to at least one polynomial to be calculated into at least one first register group, loads the variable coefficients corresponding to at least one polynomial to be calculated into at least one second register group, and loads the reference variables corresponding to at least one polynomial to be calculated into at least one third register group. The module controls the common variables in at least one first register group to perform an outer product calculation with the variable coefficients in at least one second register group to obtain a first result corresponding to at least one polynomial to be calculated. The module controls the first result corresponding to at least one polynomial to be calculated to perform an inner product calculation with the reference variables in at least one third register group to obtain a second result corresponding to at least one polynomial to be calculated.

[0211] In one possible implementation, when the processing module 1702 determines the common variables, variable coefficients, and reference variables corresponding to at least one polynomial in the first group to be calculated, it may include: for the first polynomial in the at least one group to be calculated, where the first polynomial is any polynomial in the at least one group to be calculated, the following steps are performed: extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, where the M N-order polynomials correspond one-to-one with the M reference variables, each N-order polynomial including N common variables and N variable coefficients, where the N common variables correspond one-to-one with the N variable coefficients, and the M N-order polynomials each include the same N common variables, where M is a positive integer and N is an integer greater than 1; and determining the N common variables and M*N variable coefficients based on the M N-order polynomials.

[0212] In one possible implementation, before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the processing module 1702 is further configured to supplement the first polynomial with the monomials corresponding to the missing orders when it is determined that the orders of the monomials included in the first polynomial are not continuous, and the variable coefficients of the monomials corresponding to the missing orders are zero.

[0213] In one possible implementation, before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the processing module 1702 is further configured to supplement the first polynomial with an odd number of monomials if the number of monomials included in the first polynomial is determined to be odd. The coefficients of the odd number of monomials are all zero.

[0214] In one possible implementation, when processing module 1702 extracts M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, it specifically performs the following steps: taking each N-order adjacent monomial in the first polynomial as a second polynomial to obtain M second polynomials; determining the ratio of the k-th variable included in each of the M second polynomials to the k-th variable included in the second polynomial with the lowest order as the M reference variables corresponding to the M second polynomials; k is a non-negative integer less than N; and determining the ratio between each of the M second polynomials and its corresponding reference variable as M N-order polynomials.

[0215] In one possible implementation, when processing module 1702 loads the common variables corresponding to at least one polynomial to be calculated into at least one first register group, loads the variable coefficients corresponding to at least one polynomial to be calculated into at least one second register group, and loads the reference variables corresponding to at least one polynomial to be calculated into at least one third register group, it may include: for the first polynomial among the at least one polynomial to be calculated, where the first polynomial is any one of the at least one polynomial to be calculated, performing the following steps: loading the N common variables corresponding to the first polynomial into a first target register group, where the first target register group is any one of the at least one first register group; loading the M*N variable coefficients corresponding to the first polynomial into a second target register group, where the second target register group is any one of the at least one second register group; and loading the M reference variables corresponding to the first polynomial into a third target register group, where the third target register group is any one of the at least one third register group.

[0216] In one possible implementation, the first target register group includes multiple first registers, each of which includes multiple storage locations; when the processing module 1702 loads the N common variables corresponding to the first polynomial into the first target register group, it is specifically used to: load the i-th common variable among the N common variables into the j-th storage location of the b+i-th first register of the first target register group, where i is an integer taking values ​​from [0, N-1], j is a non-negative integer, and b is a non-negative integer.

[0217] In one possible implementation, the second target register group includes multiple second registers, each of which includes multiple storage locations; when the processing module 1702 loads the M*N variable coefficients corresponding to the first polynomial into the second target register group, it is specifically used to: load the i-th variable coefficient corresponding to the m-th N-th polynomial among the M N-th polynomials into the b+i-th storage location of the second target register group, where m is an integer taking values ​​from [0, M-1], i is an integer taking values ​​from [0, N-1], and b is a non-negative integer.

[0218] In one possible implementation, the third target register group includes multiple third registers, each of which includes multiple storage locations; when the processing module 1702 loads the M reference variables corresponding to the first polynomial into the third target register group, it is specifically used to: load the m-th reference variable among the M reference variables into the j-th storage location of the (b+m)-th third register of the third target register group, where m is an integer taking values ​​from [0, M-1], b is a non-negative integer, and j is a non-negative integer.

[0219] In one possible implementation, when the processing module 1702 controls the common variables in at least one first register group to perform an outer product calculation with the variable coefficients in at least one second register group to obtain the first result corresponding to at least one polynomial to be calculated, it is specifically used to: for the first polynomial in at least one polynomial to be calculated, where the first polynomial is any polynomial in at least one polynomial to be calculated, perform the following steps: control the common variables in the first target register group to perform an outer product calculation with the variable coefficients in the second target register group to obtain the first result corresponding to the first polynomial.

[0220] In one possible implementation, when the processing module 1702 controls the first result corresponding to at least one polynomial to be calculated to perform an inner product calculation with the reference variable in at least one third register group to obtain the second result corresponding to at least one polynomial to be calculated, it is specifically used to: for the first polynomial among the at least one polynomial to be calculated, where the first polynomial is any polynomial among the at least one polynomial to be calculated, perform the following steps: control the first result corresponding to the first polynomial to perform an inner product calculation with the reference variable in the third target register group to obtain the second result corresponding to the first polynomial.

[0221] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computer device, it causes the at least one computer device to perform the above-described... Figure 2The method described in the embodiments is the same as the one described above, and will not be repeated here.

[0222] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device or a data storage device containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform the above-described... Figure 2 The methods performed in the embodiments are described in the preceding text and will not be repeated here.

[0223] Optionally, the computer execution instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not specifically limit this.

[0224] Those skilled in the art will understand that the various numerical designations, such as "first," "second," etc., used in this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, nor do they indicate a sequential order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" refers to one or more. "At least two" refers to two or more. "At least one," "any one," or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. "Multiple" refers to two or more, and other quantifiers are similar. Furthermore, for elements appearing in the singular forms "a," "an," and "the," unless the context explicitly specifies otherwise, they do not imply "one or only one," but rather "one or more." For example, "a device" implies one or more such devices.

[0225] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0226] The various illustrative logic units and circuits described in the embodiments of this application can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0227] The steps of the methods or algorithms described in the embodiments of this application can be directly embedded in hardware, software units executed by a processor, or a combination of both. The software units can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC.

[0228] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0229] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative descriptions of the application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of the claims and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A polynomial calculation method, characterized in that, The method includes: To obtain multiple polynomials to be computed in a polynomial computation application; The plurality of polynomials to be calculated are divided into a plurality of groups to be calculated. Each group to be calculated includes at least one polynomial to be calculated. The variable coefficients of at least one polynomial to be calculated in each group to be calculated are the same. The plurality of groups to be calculated includes a first group to be calculated. The first group to be calculated is any one of the plurality of groups to be calculated. Determine the common variables, variable coefficients, and reference variables corresponding to at least one polynomial to be calculated in the first group to be calculated; The common variables corresponding to the at least one polynomial to be calculated are loaded into at least one first register group, the variable coefficients corresponding to the at least one polynomial to be calculated are loaded into at least one second register group, and the reference variables corresponding to the at least one polynomial to be calculated are loaded into at least one third register group. The common variables in the at least one first register group are controlled to perform an outer product calculation with the variable coefficients in the at least one second register group to obtain the first result corresponding to the at least one polynomial to be calculated; The first result corresponding to the at least one polynomial to be calculated is controlled to perform an inner product calculation with the reference variable in the at least one third register group to obtain the second result corresponding to the at least one polynomial to be calculated.

2. The method as described in claim 1, characterized in that, The step of determining the common variables, variable coefficients, and reference variables corresponding to at least one polynomial in the first set of polynomials to be calculated includes: For the first polynomial among the at least one polynomials to be calculated, where the first polynomial is any one of the at least one polynomials to be calculated, the following steps are performed: M N-order polynomials and M reference variables corresponding to the M N-order polynomials are extracted from the first polynomial. The M N-order polynomials correspond one-to-one with the M reference variables. Each N-order polynomial includes N common variables and N variable coefficients. The N common variables correspond one-to-one with the N variable coefficients. The N common variables included in the M N-order polynomials are the same. M is a positive integer and N is an integer greater than 1. Based on the M N-order polynomials, determine N common variables and M*N variable coefficients.

3. The method as described in claim 2, characterized in that, Before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the process further includes: If it is determined that the orders of the monomials included in the first polynomial are not continuous, the first polynomial is supplemented with monomials corresponding to the missing orders, and the variable coefficients of the monomials corresponding to the missing orders are zero.

4. The method as described in claim 2 or 3, characterized in that, Before extracting M N-order polynomials and M reference variables corresponding to the M N-order polynomials from the first polynomial, the process further includes: If the number of monomials included in the first polynomial is determined to be odd, an odd number of monomials are added to the first polynomial, wherein the coefficients of the odd number of monomials are all zero.

5. The method as described in claim 2, characterized in that, The extraction of M N-order polynomials from the first polynomial and the M reference variables corresponding to the M N-order polynomials includes: Take every N consecutive monomials of the first polynomial as a second polynomial, and obtain M second polynomials; The ratio of the k-th variable in each of the M second polynomials to the k-th variable in the second polynomial with the lowest order is determined as the M reference variables corresponding to the M second polynomials; where k is a non-negative integer less than N. The ratio between each of the M second polynomials and its corresponding reference variable is used to determine the M N-order polynomials.

6. The method as described in claim 2, characterized in that, The step of loading the common variables corresponding to the at least one polynomial to be calculated into at least one first register group, loading the variable coefficients corresponding to the at least one polynomial to be calculated into at least one second register group, and loading the reference variables corresponding to the at least one polynomial to be calculated into at least one third register group includes: For the first polynomial among the at least one polynomials to be calculated, where the first polynomial is any one of the at least one polynomials to be calculated, the following steps are performed: The N common variables corresponding to the first polynomial are loaded into the first target register group, where the first target register group is any one of the at least one first register group; The M*N variable coefficients corresponding to the first polynomial are loaded into the second target register group, where the second target register group is any one of the at least one second register group; The M reference variables corresponding to the first polynomial are loaded into the third target register group, which is any one of the at least one third register group.

7. The method as described in claim 6, characterized in that, The first target register group includes a plurality of first registers, and each first register includes a plurality of storage locations; The step of loading the N common variables corresponding to the first polynomial into the first target register group includes: The i-th common variable among the N common variables is loaded into the j-th storage location of the (b+i)-th first register in the first target register group, where i is an integer taking values ​​from [0, N-1], j is a non-negative integer, and b is a non-negative integer.

8. The method as described in any one of claims 6-7, characterized in that, The second target register group includes multiple second registers, and each second register includes multiple storage locations; The step of loading the M*N variable coefficients corresponding to the first polynomial into the second target register group includes: The coefficient of the i-th variable corresponding to the m-th N-th polynomial among the M N-th polynomials is loaded into the b+m-th storage location of the b+i-th second register in the second target register group, where m is an integer taking values ​​from [0, M-1], i is an integer taking values ​​from [0, N-1], and b is a non-negative integer.

9. The method as described in claim 6, characterized in that, The third target register group includes multiple third registers, and each third register includes multiple storage locations; The step of loading the M reference variables corresponding to the first polynomial into the third target register group includes: The m-th reference variable among the M reference variables is loaded into the j-th storage location of the (b+m)-th third register in the third target register group, where m is an integer taking values ​​from [0, M-1], b is a non-negative integer, and j is a non-negative integer.

10. The method as described in claim 6, characterized in that, The step of controlling the outer product calculation of the common variables in the at least one first register group and the variable coefficients in the at least one second register group to obtain the first result corresponding to the at least one polynomial to be calculated includes: For the first polynomial among the at least one polynomials to be calculated, where the first polynomial is any one of the at least one polynomials to be calculated, the following steps are performed: The common variables in the first target register group are controlled to perform an outer product calculation with the variable coefficients in the second target register group to obtain the first result corresponding to the first polynomial.

11. The method as described in claim 10, characterized in that, The step of controlling the first result corresponding to each of the at least one polynomial to be calculated to perform an inner product calculation with the reference variables in each of the at least one third register group to obtain the second result corresponding to each of the at least one polynomial to be calculated includes: For the first polynomial among the at least one polynomials to be calculated, where the first polynomial is any one of the at least one polynomials to be calculated, the following steps are performed: The first result corresponding to the first polynomial is controlled to perform an inner product calculation with the reference variable in the third target register group to obtain the second result corresponding to the first polynomial.

12. A polynomial computing device, characterized in that, The polynomial computing device includes an acquisition module and a processing module: The acquisition module is used to acquire multiple polynomials to be calculated in the polynomial calculation application; The processing module is used to divide the plurality of polynomials to be calculated into a plurality of groups to be calculated. Each group to be calculated includes at least one polynomial to be calculated. The at least one polynomial to be calculated in each group to be calculated has the same type. The plurality of groups to be calculated includes a first group to be calculated, which is any one of the plurality of groups to be calculated. The processing module is further configured to determine the common variables, variable coefficients and reference variables corresponding to at least one polynomial to be calculated in the first group to be calculated, wherein at least one polynomial to be calculated in the first group to be calculated corresponds to the same variable coefficients. The processing module is further configured to load the common variables corresponding to the at least one polynomial to be calculated into at least one first register group, load the variable coefficients corresponding to the at least one polynomial to be calculated into at least one second register group, and load the reference variables corresponding to the at least one polynomial to be calculated into at least one third register group. The processing module is also used to control the common variables in the at least one first register group to perform an outer product calculation with the variable coefficients in the at least one second register group to obtain the first result corresponding to the at least one polynomial to be calculated. The processing module is further configured to control the first result corresponding to the at least one polynomial to be calculated to perform an inner product calculation with the reference variable in the at least one third register group to obtain the second result corresponding to the at least one polynomial to be calculated.

13. A computing device, characterized in that, The computing device includes a processor and a memory; The memory is used to store computer program instructions; The processor executes computer program instructions in the memory to perform the method as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, When the computer-readable storage medium is executed by the storage device, the storage device performs the method according to any one of claims 1 to 11.

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