DPU (Data Processing Unit) equipment initialization method

Abstract

The invention provides a DPU equipment initialization method, and relates to the field of computer equipment. According to the method, a BAR space mapping process, a PCI device initialization process, a PF data channel initialization process and a VP data channel initialization process are executed respectively; the method comprises the following steps: firstly, carrying out IO remap mapping operation on a BAR register, and mapping a physical address of the BAR register to a virtual address space of a Linux kernel to obtain a BAR space; then PCI device initialization is carried out through the BAR space; secondly, initializing a PCI driver and a kernel timer, and on the basis, maintaining a work queue task and periodically executing port state polling; and finally, distributing an interrupt vector to the VP data channel, and managing the on-off of the VP data channel through the interrupt vector. The invention provides a complete and systematized initialization processing scheme of the DPU high-speed daughter card based on the domestic chip, which is beneficial to improving the development efficiency of domestic equipment.

Description

Technical Field

[0001] The present invention relates to the field of computer equipment, and in particular to a DPU equipment initialization method. Background Art

[0002] DPU (Data Processing unit) is a dedicated processor that provides data center infrastructure virtualization services such as network, storage, security, and management around data processing. It is usually a computing architecture composed of a CPU based on ARM / X86 architecture and dedicated hardware acceleration engines such as ASIC / NP / FPGA, forming a physical network card that provides virtualization functions.

[0003] The DPU high-speed daughter card is a form of DPU network card, which is set up as an independent small board. It has the technical advantages of low power consumption, low cost and high reliability. At present, the high-performance network, simulation, acquisition, monitoring and other scenarios in the field of avionics are rapidly growing in demand for massive storage and computing in airborne and laboratory environments, and the demand for diversified communication products is growing, which is also accompanied by the increasingly frequent and extensive use of DPU high-speed daughter cards in the field of avionics.

[0004] In the context of military industry, avionics equipment requires domestic substitution, and research on domestic chip daughter cards has become an important option for occupying market share in the future military industry. Because the DPU high-speed daughter cards of international brands were often used in the past, their related firmware programs were packaged and used directly, which brought convenience while also limiting the development of technology.

[0005] Therefore, when initializing the DPU device, a DPU high-speed daughter card based on domestic chips has not yet proposed a complete and systematic initialization processing solution; therefore, it is necessary to provide a DPU device initialization method to solve the above technical problems. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a DPU device initialization method, which aims to provide a complete and systematic initialization processing solution for the DPU high-speed daughter card based on domestic chips to fill the gaps in the prior art.

[0007] The present invention provides a DPU device initialization method, which is used for a DPU high-speed daughter card based on a single DPU chip, wherein the DPU chip is connected to a PCI device, and the PCI device is provided with a plurality of BAR registers. The Linux kernel is loaded into the DPU chip, and a BAR space mapping process, a PCI device initialization process, a PF data channel initialization process, and a VP data channel initialization process are respectively executed; wherein,

[0008] BAR space mapping process: perform IO remap mapping operation on the BAR register, map the physical address of the BAR register to the virtual address space of the Linux kernel, and obtain the BAR space;

[0009] PCI device initialization process: PCI device initialization is performed through BAR space;

[0010] PF data channel initialization process: Initialize the PCI driver and kernel timer, and on this basis, maintain the work queue tasks and periodically perform port status polling;

[0011] VP data channel initialization process: set and assign interrupt vectors to VP data channels, and manage the on and off of VP data channels through interrupt vectors.

[0012] As a further solution, when performing the BAR space mapping process: the BAR register stores the physical base address of the MEM / IO space, and after enabling the PCI device, the IO remap mapping operation is performed on the BAR register interval, and the mapped BAR registers are combined into a BAR space; wherein, mbus messages are sent and received through the shared memory space of the BAR space.

[0013] As a further solution, the PCI device initialization process proceeds through the following steps:

[0014] Send an mbus message through the BAR4 space to command the chip eeprom information to be read; if the acquisition fails, the default configuration information is used;

[0015] Clear the vport channel data in BAR4 space and reset the vport channel data;

[0016] Get the port parameter configuration of the port map;

[0017] Obtain mbus messages through BAR4 space and read the NIC status settings of the DPU high-speed daughter card;

[0018] Determine the NIC status setting; if there is a NIC status setting, jump to setting the network card feature information;

[0019] Send mbus message through BAR4 space to command the port parameter configuration to be written into DPU chip;

[0020] Read the write status; if the write times out or fails, an alarm is triggered and the BAR space device initialization process ends;

[0021] Set the network card feature information and complete the PCI device initialization process.

[0022] As a further solution, the network card feature information includes enabling PF functions and configuring function parameters; wherein the PF functions include PF RSS, PF SRIOV, PF IP checksum, PF TSO and PF LRO, and the function parameters include RSS table size, RSS table entry width, RSS hash key block size and NIC CQsize.

[0023] As a further solution, the PF data channel initialization process is performed through the following steps:

[0024] Initialize the core timer of the DPU chip and bind the timer timeout task;

[0025] Set the timer timeout period and activate the kernel timer;

[0026] Initialize the work queue task and bind the work task;

[0027] Set the number of PF queues and PF number;

[0028] Create a debugfs file; the debugfs file is used to record historical operation records.

[0029] As a further solution, after completing the PF data channel initialization process, the timer timeout task starts timing, and determines whether it is a timeout task based on the timer timeout period; if so, the timer timeout period of the timeout task is modified, re-timing is performed and added to the work queue task; the work queue task is implemented according to the bound work task, and port status polling is performed periodically.

[0030] As a further solution, port status polling is performed through the following steps:

[0031] Save the original link settings and read the link status;

[0032] If the read is successful or link_status.link is empty, the phy information is initialized to the default value and the phy link status is set to link down;

[0033] If the read fails and link_status.link is not empty, set the phy link status to link up, get link_status.speed gear, and set phy type and link_speed;

[0034] Read the optical module status and determine whether it is the same as the original value;

[0035] If they are the same, determine whether the optical module status is empty; if so, unplug the printing optical module; if not, plug the printing optical module in; and execute the next step;

[0036] If they are different, proceed directly to the next step;

[0037] Determine whether the current link status is the same as old_link;

[0038] If they are the same, a port status poll is completed;

[0039] If they are different, determine whether the current state is link up; if so, execute the link up process; if not, execute the link down process.

[0040] As a further solution, the link up process is performed through the following steps:

[0041] Notify the Linux kernel to start the protocol stack link;

[0042] Wake up the protocol stack transmission queue;

[0043] Update vsi link status and link_speed;

[0044] Synchronous optical module link_speed parameter;

[0045] Print link up information, actual port speed, and auto-negotiation status.

[0046] As a further solution, the link down process is performed through the following steps:

[0047] Notify the Linux kernel to disconnect the protocol stack link;

[0048] Stop the protocol stack transmission queue;

[0049] Update vsi link status and link_speed;

[0050] Print link down information.

[0051] As a further solution, the VP data channel initialization process:

[0052] Allocate the msix_entry array, and after successful allocation, write the entry of the msix_entry array;

[0053] pf->state sets the MSIX flag;

[0054] Apply for MSI-x interrupt vector; the requested interrupt vector number is written into the vector of the msix_entry array, the memory of pf->irq_pile is allocated, and the actual allocated interrupt vector number is stored in pf->irq_pile;

[0055] If successful, pf->state sets the INTX DOWN flag;

[0056] If it fails, pf->state clears the MSIX flag and enables the INTX interrupt;

[0057] If the interrupt is successful, pf->state sets the INTX DOWN flag, otherwise, the VP data channel initialization process ends;

[0058] Write the configuration to the register of the DPU chip to end the VP data channel initialization process.

[0059] Compared with the prior art, the DPU device initialization method provided by the present invention has the following advantages:

[0060] The present invention first performs an IO remap operation on a BAR register, maps the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space; then initializes the PCI device through the BAR space; then initializes the PCI driver and the kernel timer, and on this basis, maintains the work queue task and periodically executes port status polling; finally, allocates an interrupt vector to a VP data channel, and manages the on and off of the VP data channel through the interrupt vector; the present invention provides a complete and systematic initialization processing solution for a DPU high-speed daughter card based on a domestic chip, which is helpful to improve the development efficiency of domestic equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 A schematic diagram of a DPU device initialization method provided by the present invention;

[0062] Figure 2 A schematic diagram of the BAR space mapping process provided by the present invention;

[0063] Figure 3 A schematic diagram of the PCI device initialization process provided by the present invention;

[0064] Figure 4 A schematic diagram of the PF data channel initialization process provided by the present invention;

[0065] Figure 5 A schematic diagram of the port status polling process provided by the present invention;

[0066] Figure 6This is a schematic diagram of the VP data channel initialization process provided by the present invention. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0068] See also Figure 1 The present invention provides a DPU device initialization method for a DPU high-speed daughter card based on a single DPU chip, wherein the DPU chip is connected to a PCI device, the PCI device is provided with a plurality of BAR registers, a Linux kernel is loaded into the DPU chip, and a BAR space mapping process, a PCI device initialization process, a PF data channel initialization process and a VP data channel initialization process are respectively executed; wherein,

[0069] BAR space mapping process: perform IO remap mapping operation on the BAR register, map the physical address of the BAR register to the virtual address space of the Linux kernel, and obtain the BAR space;

[0070] PCI device initialization process: PCI device initialization is performed through BAR space;

[0071] PF data channel initialization process: Initialize the PCI driver and kernel timer, and on this basis, maintain the work queue tasks and periodically perform port status polling;

[0072] VP data channel initialization process: set and assign interrupt vectors to VP data channels, and manage the on and off of VP data channels through interrupt vectors.

[0073] It should be noted that: the present invention first performs an IO remap mapping operation on the BAR register, maps the physical address of the BAR register to the virtual address space of the Linux kernel to obtain the BAR space; then initializes the PCI device through the BAR space; then initializes the PCI driver and the kernel timer, and on this basis, maintains the work queue task and periodically executes port status polling; finally, allocates an interrupt vector to the VP data channel, and manages the on and off of the VP data channel through the interrupt vector; the present invention provides a complete and systematic initialization processing solution for the DPU high-speed daughter card based on the domestic chip, which helps to improve the development efficiency of domestic equipment.

[0074] When performing the BAR space mapping process: the BAR register stores the physical base address of the MEM / IO space. After enabling the PCI device, the IO remap mapping operation is performed on the BAR register interval, and the mapped BAR registers are combined into a BAR space; wherein, mbus messages are sent and received through the shared memory space of the BAR space.

[0075] It should be noted that: Figure 2 As shown, the PCI device connected to the domestic DPU chip has at least 256 bytes of address space, and the first 64 bytes are standard; in a specific embodiment, the PCI device includes 6 BAR registers, which store the physical base addresses of 6 MEM / IO spaces. Here we only use BAR0, BAR2, and BAR4, and they are all base addresses of MEM space. After enabling the PCI device, we map the physical addresses in BAR0, BAR2, and BAR4 to the kernel virtual address space;

[0076] After the BAR space is mapped successfully, the software can read and write registers through the BAR space, and send and receive mbus messages through the shared memory space of the BAR space.

[0077] like Figure 3 As shown, the PCI device initialization process is carried out through the following steps:

[0078] Send an mbus message through the BAR4 space to command the chip eeprom information to be read; if the acquisition fails, the default configuration information is used;

[0079] Clear the vport channel data in BAR4 space and reset the vport channel data;

[0080] Get the port parameter configuration of the port map;

[0081] Obtain mbus messages through BAR4 space and read the NIC status settings of the DPU high-speed daughter card;

[0082] Determine the NIC status setting; if there is a NIC status setting, jump to setting the network card feature information;

[0083] Send mbus message through BAR4 space to command the port parameter configuration to be written into DPU chip;

[0084] Read the write status; if the write times out or fails, an alarm is triggered and the BAR space device initialization process ends;

[0085] Set the network card feature information and complete the PCI device initialization process.

[0086] It should be noted that: this embodiment sends a command through the BAR space to read the chip eeprom information. If the acquisition fails, the default configuration information is used to clear the vport channel data to ensure that the vport channel data is reset during the driver probe phase.

[0087] Then, according to the obtained device type, the port parameters are set; the status of the device as a standard Ethernet card is obtained. If the NIC status is not set, the port parameters are written to the chip through the mbus message, and it is determined whether the writing is effective.

[0088] The network card feature information includes enabling PF functions and configuring function parameters; wherein the PF functions include PFRSS, PF SRIOV, PF IP checksum, PF TSO and PF LRO, and the function parameters include RSS table size, RSStable entry width, RSS hash key block size and NIC CQ size.

[0089] It should be noted that: PF RSS: receive-side scaling function; PF SRIOV: single-root I / O virtualization function; PF IPchecksum: interface IP header check function; PF TSO: network card batch forwarding function, used to reduce the load of sending data packets; function parameters are some specific specification restrictions, which will not be repeated here.

[0090] like Figure 4 As shown, the PF data channel initialization process is performed through the following steps:

[0091] Initialize the core timer of the DPU chip and bind the timer timeout task;

[0092] Set the timer timeout period and activate the kernel timer;

[0093] Initialize the work queue task and bind the work task;

[0094] Set the number of PF queues and PF number;

[0095] Create a debugfs file; the debugfs file is used to record historical operation records.

[0096] It should be noted that the data structure type of pf is struct nce_pf, which is the private driver handle of the driver, in which all global information of the device driver is maintained. The driver configuration file includes pci_dev, hw, (interrupt vector table, timer, scheduled task) and mutex locks and spin locks for race protection of these resources. Among them, the scheduled task will enter the polling state only when the timer setting timeout takes effect, and will not enter the polling state during the initialization stage.

[0097] like Figure 4 As shown, after completing the PF data channel initialization process, the timer timeout task starts timing, and determines whether it is a timeout task based on the timer timeout period; if so, the timer timeout period of the timeout task is modified, re-timing is performed and added to the work queue task; the work queue task is implemented according to the bound work task, and periodic port status polling is performed.

[0098] like Figure 5 As shown in the figure, port status polling is performed through the following steps:

[0099] Save the original link settings and read the link status;

[0100] If the read is successful or link_status.link is empty, the phy information is initialized to the default value and the phy link status is set to link down;

[0101] If the read fails and link_status.link is not empty, set the phy link status to link up, get link_status.speed gear, and set phy type and link_speed;

[0102] Read the optical module status and determine whether it is the same as the original value;

[0103] If they are the same, determine whether the optical module status is empty; if so, unplug the printing optical module; if not, plug the printing optical module in; and execute the next step;

[0104] If they are different, proceed directly to the next step;

[0105] Determine whether the current link status is the same as old_link;

[0106] If they are the same, a port status poll is completed;

[0107] If they are different, determine whether the current state is link up; if so, execute the link up process; if not, execute the link down process.

[0108] The link up process is performed through the following steps:

[0109] Notify the Linux kernel to start the protocol stack link;

[0110] Wake up the protocol stack transmission queue;

[0111] Update vsi link status and link_speed;

[0112] Synchronous optical module link_speed parameter;

[0113] Print link up information, actual port speed, and auto-negotiation status.

[0114] The link down process is performed through the following steps:

[0115] Notify the Linux kernel to disconnect the protocol stack link;

[0116] Stop the protocol stack transmission queue;

[0117] Update vsi link status and link_speed;

[0118] Print link down information.

[0119] like Figure 6 As shown, the VP data channel initialization process:

[0120] Allocate the msix_entry array, and after successful allocation, write the entry of the msix_entry array;

[0121] pf->state sets the MSIX flag;

[0122] Apply for MSI-x interrupt vector; the requested interrupt vector number is written into the vector of the msix_entry array, the memory of pf->irq_pile is allocated, and the actual allocated interrupt vector number is stored in pf->irq_pile;

[0123] If successful, pf->state sets the INTX DOWN flag;

[0124] If it fails, pf->state clears the MSIX flag and enables the INTX interrupt;

[0125] If the interrupt is successful, pf->state sets the INTX DOWN flag, otherwise, the VP data channel initialization process ends;

[0126] Write the configuration to the register of the DPU chip to end the VP data channel initialization process.

[0127] It should be noted that: since the device supports a maximum of 72 VP data channels, 72 interrupt vectors need to be applied for to meet the data processing of different channels. The Linux kernel maintains the allocated interrupt vectors through the data structure struct msix_entry. Therefore, before applying for the MSI-x interrupt vector, the memory space of the data structure must be pre-allocated. Here we need 72 interrupt vectors, so the driver is responsible for allocating an array with 72 elements of the data structure.

[0128] There are two data members in struct msix_entry, namely vector and entry. The entry is filled by the driver, which only specifies an entry number to distinguish different interrupt vectors. The vector member is the interrupt vector number available to the software allocated by the kernel after the interrupt vector is successfully applied. Based on this interrupt vector number, request_irq can be used to register the interrupt processing function to the interrupt vector.

[0129] The actual application and allocation of interrupt vectors is implemented through the kernel interface pci_enable_msix_range(). This function requires 4 parameters. The first parameter is the pci_dev data structure pointer passed in when the probe function of pci_driver is entered. The second parameter is the address of the allocated struct msix_entry type array. The third parameter is the minimum number of interrupt vectors required to be applied for, and the fourth parameter is the maximum number of interrupt vectors expected to be applied, that is, 72. If the number of interrupt vectors allocated is less than the minimum number of interrupt vectors, the interface returns -ENOSPC and successfully returns the total number of interrupt vectors actually allocated.

[0130] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A DPU device initialization method, for a DPU high-speed daughter card based on a single DPU chip, wherein the DPU chip is connected to a PCI device, and the PCI device is provided with a plurality of BAR registers, characterized in that: Load the Linux kernel into the DPU chip, and execute the BAR space mapping process, PCI device initialization process, PF data channel initialization process, and VP data channel initialization process respectively; among them, BAR space mapping process: perform IO remap mapping operation on the BAR register, map the physical address of the BAR register to the virtual address space of the Linux kernel, and obtain the BAR space; PCI device initialization process: PCI device initialization is performed through BAR space; PF data channel initialization process: Initialize the PCI driver and kernel timer, and on this basis, maintain the work queue tasks and periodically perform port status polling; VP data channel initialization process: set and assign interrupt vectors to VP data channels, and manage the on and off of VP data channels through interrupt vectors.

2. A DPU device initialization method according to claim 1, characterized in that: When performing the BAR space mapping process: the BAR register stores the physical base address of the MEM / IO space. After enabling the PCI device, the IO remap mapping operation is performed on the BAR register interval, and the mapped BAR registers are combined into a BAR space; wherein, mbus messages are sent and received through the shared memory space of the BAR space.

3. A DPU device initialization method according to claim 2, characterized in that: The PCI device initialization process is carried out through the following steps: Send an mbus message through the BAR4 space to command the chip eeprom information to be read; if the acquisition fails, the default configuration information is used; Clear the vport channel data in BAR4 space and reset the vport channel data; Get the port parameter configuration of the port map; Obtain mbus messages through BAR4 space and read the NIC status settings of the DPU high-speed daughter card; Determine the NIC status setting; if there is a NIC status setting, jump to setting the network card feature information; Send mbus message through BAR4 space to command the port parameter configuration to be written into DPU chip; Read the write status; if the write times out or fails, an alarm is triggered and the BAR space device initialization process ends; Set the network card feature information and complete the PCI device initialization process.

4. A DPU device initialization method according to claim 3, characterized in that: The network card feature information includes enabling PF functions and configuring function parameters; wherein the PF functions include PF RSS, PF SRIOV, PF IP checksum, PF TSO and PF LRO, and the function parameters include RSS table size, RSS table entry width, RSS hashkey block size and NIC CQ size.

5. A DPU device initialization method according to claim 4, characterized in that: The PF data channel initialization process is performed through the following steps: Initialize the core timer of the DPU chip and bind the timer timeout task; Set the timer timeout period and activate the kernel timer; Initialize the work queue task and bind the work task; Set the number of PF queues and PF number; Create a debugfs file; the debugfs file is used to record historical operation records.

6. A DPU device initialization method according to claim 5, characterized in that: After completing the PF data channel initialization process, the timer timeout task starts timing, and determines whether it is a timeout task based on the timer timeout period; if so, the timer timeout period of the timeout task is modified, re-timing is performed and added to the work queue task; the work queue task is implemented according to the bound work task, and port status polling is performed periodically.

7. A DPU device initialization method according to claim 6, characterized in that: Port status polling is performed through the following steps: Save the original link settings and read the link status; If the read is successful or link_status.link is empty, the phy information is initialized to the default value and the phy link status is set to link down; If the read fails and link_status.link is not empty, set the phy link status to link up, get link_status.speed gear, and set phy type and link_speed; Read the optical module status and determine whether it is the same as the original value; If they are the same, determine whether the optical module status is empty; if so, unplug the printing optical module; if not, plug the printing optical module in; and execute the next step; If they are different, proceed directly to the next step; Determine whether the current link status is the same as old_link; If they are the same, a port status poll is completed; If they are different, determine whether the current state is link up; if so, execute the link up process; if not, execute the link down process.

8. A DPU device initialization method according to claim 7, characterized in that: The link up process is performed through the following steps: Notify the Linux kernel to start the protocol stack link; Wake up the protocol stack transmission queue; Update vsi link status and link_speed; Synchronous optical module link_speed parameter; Print link up information, actual port speed, and auto-negotiation status.

9. A DPU device initialization method according to claim 7, characterized in that: The link down process is performed through the following steps: Notify the Linux kernel to disconnect the protocol stack link; Stop the protocol stack transmission queue; Update vsi link status and link_speed; Print link down information.

10. A DPU device initialization method according to claim 1, characterized in that: VP data channel initialization process: Allocate the msix_entry array, and after successful allocation, write the entry of the msix_entry array; pf->state sets the MSIX flag; Apply for MSI-x interrupt vector; the requested interrupt vector number is written into the vector of the msix_entry array, the memory of pf->irq_pile is allocated, and the actual allocated interrupt vector number is stored in pf->irq_pile; If successful, pf->state sets the INTX DOWN flag; If it fails, pf->state clears the MSIX flag and enables the INTX interrupt; If the interrupt is successful, pf->state sets the INTX DOWN flag, otherwise, the VP data channel initialization process ends; Write the configuration to the register of the DPU chip to end the VP data channel initialization process.

Images