Printed circuit board (PCB) and PCB processing method

Abstract

The invention provides a printed circuit board (PCB) and a PCB processing method. The invention provides a printed circuit board (PCB), the PCB comprises a first daughter board provided with a high-speed wiring layer and a grounding layer and a second daughter board provided with a non-high-speed wiring layer, the first daughter board comprises via hole points arranged according to an array mode, and any via hole point represents a differential pair of via holes; differential pair via holes represented by via hole points in each array are connected with the high-speed wiring layer in the first daughter board in sequence; a shielding groove along the row direction is configured between adjacent rows in the array, or a shielding groove along the column direction is configured between adjacent columns in the array, the shielding grooves arranged between the adjacent rows or between the adjacent columns are connected with a grounding layer in the first daughter board, the depth of the shielding grooves is in a step shape, and step grooves are formed through the shielding grooves. On the basis of not influencing the fan-out of the differential signal wire, the crosstalk between the differential pair via holes between adjacent rows or columns is isolated.

Description

Technical Field

[0001] The present application relates to the field of PCB processing, and in particular to a printed circuit board PCB and a PCB processing method. Background Art

[0002] At present, printed circuit boards (PCBs) usually use a ball grid array (BGA) packaging method, that is, the differential pair vias corresponding to the pins are arranged in an array on the PCB. Under this packaging method, the differential pair vias are arranged very closely, and crosstalk is easily generated when high-speed signals are transmitted through the differential pair vias between adjacent rows or columns. Summary of the invention

[0003] In view of this, the present application provides a printed circuit board PCB and a PCB processing method to reduce the crosstalk between signal vias of a differential pair.

[0004] The technical solutions provided by this application are as follows:

[0005] According to an embodiment of the first aspect of the present application, a printed circuit board PCB is provided, wherein the PCB comprises a first sub-board and a second sub-board, wherein a high-speed routing layer and a ground layer are deployed on the first sub-board, and a non-high-speed routing layer is deployed on the second sub-board;

[0006] The first sub-board also includes via points arranged in an array, and any via point represents a differential pair of vias; shielding grooves along the row direction are arranged between adjacent rows in the array, and the shielding grooves are connected to the ground layer in the first sub-board; wherein the depth of the shielding grooves arranged between adjacent rows in the array is stepped, so that each shielding groove on the first sub-board presents a stepped groove; or, shielding grooves along the column direction are arranged between adjacent columns in the array, and the shielding grooves are connected to the ground layer in the first sub-board; wherein the depth of the shielding grooves arranged between adjacent columns in the array is stepped, so that each shielding groove on the first sub-board presents a stepped groove;

[0007] The differential pair vias represented by each via point in the array are sequentially connected to the high-speed routing layer in the first sub-board to fan out the differential signals through the differential pair vias represented by the via point through the connected high-speed routing layer.

[0008] Optionally, in the case where shielding grooves along the row direction are arranged between adjacent rows in the array, the depth of the shielding grooves along the row direction arranged between adjacent rows in the array is between the depths of the high-speed routing layers connected by the differential pair vias represented by each via point in the adjacent rows; a plurality of grounding blind holes are arranged between adjacent columns in the array, and the grounding blind holes penetrate the first sub-board and are connected to each grounding layer in the first sub-board; wherein the high-speed routing layers connected by the differential pair vias represented by each via point in the same row are the same, and the high-speed routing layers connected by the differential pair vias represented by each via point in different rows are different;

[0009] In the case where shielding grooves along the column direction are arranged between adjacent columns in the array, the depth of the shielding grooves along the column direction arranged between adjacent columns in the array is between the depths of the high-speed routing layers connected by the differential pair vias represented by each via point in the adjacent columns; a plurality of grounding blind holes are arranged between adjacent rows in the array, and the grounding blind holes penetrate the first sub-board and are connected to each grounding layer in the first sub-board; wherein the high-speed routing layers connected by the differential pair vias represented by each via point in the same column are the same, and the high-speed routing layers connected by the differential pair vias represented by each via point in different columns are different.

[0010] Optionally, each via included in any differential pair of vias is connected to a signal pad of the via;

[0011] When the shielding grooves arranged along the row direction between adjacent rows in the array pass between the via points of adjacent rows in the array, the direction of the shielding grooves is perpendicular to the connection line of the signal pads of every two matching vias between the adjacent rows; wherein the signal pads of the matching vias between adjacent rows refer to the signal pads of the vias close to one side of the adjacent row in the differential pair of vias represented by each via point in the array and the signal pads closest to the adjacent row;

[0012] When the shielding grooves along the column direction arranged between adjacent columns in the array pass between the via points of adjacent columns in the array, the direction of the shielding grooves is perpendicular to the connection line of the signal pads of every two matching vias between the adjacent columns; wherein, the signal pads of the matching vias between adjacent columns refer to the signal pads of the vias close to the adjacent column side in the differential pair of vias represented by each via point in the array and the signal pads closest to the adjacent column.

[0013] Optionally, both ends of the shielding slot and the turning connections of the shielding slot in different directions are rounded.

[0014] Optionally, the first sub-board further includes at least one grounding blind hole, the grounding blind hole passes through the first sub-board and is connected to each grounding layer in the first sub-board; the surface of the first sub-board further includes a grounding copper foil, the grounding copper foil is connected to the at least one grounding blind hole;

[0015] The shielding slot also includes a shielding ring, which is located on the surface of the first sub-board and connected to the slot wall of the shielding slot. The shielding ring is also connected to the grounding copper foil.

[0016] Optionally, there is a spacing between the signal pad of each via in the differential pair of vias represented by any via point and the shielding ring to avoid a short circuit.

[0017] Optionally, one or more grounding blind holes are provided inside the shielding slot, and the grounding blind holes penetrate through the first sub-board from inside the shielding slot and are connected to at least one grounding layer in the first sub-board.

[0018] According to an embodiment of the second aspect of the present application, a PCB processing method is provided, wherein the PCB includes a first sub-board and a second sub-board, the first sub-board is deployed with a high-speed routing layer and a ground layer, and the second sub-board is deployed with a non-high-speed routing layer; the method includes:

[0019] The first sub-board and the second sub-board are pressed together to obtain the PCB; via points are arranged on the PCB in an array manner; any via point represents a differential pair of vias; the differential pair of vias represented by each via point in the array are sequentially connected to the high-speed routing layer in the PCB to fan out the differential signal of the differential pair of vias represented by the via point through the connected high-speed routing layer;

[0020] Shielding grooves along the row direction are arranged between adjacent rows of the array; wherein the shielding grooves are connected to the grounding layer in the PCB, and the depths of the shielding grooves arranged between adjacent rows in the array are stepped, so that each shielding groove on the PCB presents a stepped groove; or, shielding grooves along the column direction are arranged between adjacent columns of the array; wherein the shielding grooves are connected to the grounding layer in the PCB, and the depths of the shielding grooves arranged between adjacent columns in the array are stepped, so that each shielding groove on the PCB presents a stepped groove.

[0021] Optionally, the method of arranging the via points in an array manner on the PCB includes:

[0022] After the first sub-board and the second sub-board are pressed together to obtain the PCB, the PCB is drilled to set various via points on the PCB in an array manner; wherein the drilling direction is the direction from the first sub-board to the second sub-board;

[0023] The method of providing shielding slots along the row direction between adjacent rows of the array includes:

[0024] Controlled depth milling is performed between adjacent rows of the array in the PCB to set shielding grooves along the row direction between adjacent rows of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent rows of the array;

[0025] The method of providing shielding slots along the column direction between adjacent columns of the array includes:

[0026] Controlled depth milling is performed between adjacent columns of the array in the PCB to set shielding grooves along the column direction between adjacent columns of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent columns of the array;

[0027] After performing controlled depth milling between adjacent rows of the array in the PCB, or performing controlled depth milling between adjacent columns of the array in the PCB, the method further comprises:

[0028] The PCB is electroplated and back-drilled so that the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the PCB in sequence, so as to fan out the differential signals of the differential pair vias represented by the via points through the connected high-speed routing layer.

[0029] Optionally, the method of arranging the via points in an array manner on the PCB includes:

[0030] Before pressing the first sub-board and the second sub-board together to obtain the PCB, drilling holes in the first sub-board to set various via points in an array manner on the first sub-board;

[0031] The method of providing shielding slots along the row direction between adjacent rows of the array includes:

[0032] Controlled depth milling is performed between adjacent rows in the array in the first sub-board to set shielding grooves along the row direction between adjacent rows of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent rows of the array;

[0033] The method of providing shielding slots along the column direction between adjacent columns of the array includes:

[0034] Performing controlled depth milling between adjacent columns of the array in the first sub-board to set shielding grooves along the column direction between adjacent columns of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent columns of the array;

[0035] Before pressing the first sub-board and the second sub-board together to obtain the PCB, the method further includes:

[0036] The first sub-board is electroplated and back-drilled so that the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the first sub-board in sequence, so as to fan out the differential signals of the differential pair vias represented by the via points through the connected high-speed routing layer.

[0037] As can be seen from the above technical scheme, the present application proposes a printed circuit board PCB, which includes a first sub-board on which a high-speed routing layer and a ground layer are deployed, and a second sub-board on which a non-high-speed routing layer is deployed, wherein the first includes via points arranged in an array, and any via point represents a differential pair of vias; the differential pair of vias represented by each via point in each array are connected to the high-speed routing layer in the first sub-board in sequence to fan out the differential signal of the differential pair of vias represented by the via point through the connected high-speed routing layer; shielding grooves along the row direction are configured between adjacent rows in the array, or shielding grooves along the column direction are configured between adjacent columns, wherein the shielding grooves arranged between adjacent rows or adjacent columns are connected to the ground layer in the first sub-board, and the depth is stepped, so that each shielding groove in the PCB forms a stepped groove, and the crosstalk between the differential pair vias between adjacent rows or columns is isolated by the stepped groove without affecting the fan-out of the differential signal routing. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0039] Figure 1A A schematic diagram of the BGA area in a PCB provided in an embodiment of the present application;

[0040] Figure 1B A schematic diagram of shallow routing crosstalk between adjacent column differential pairs provided in an embodiment of the present application;

[0041] Figure 1C A schematic diagram of deep routing crosstalk between adjacent column differential pairs provided in an embodiment of the present application;

[0042] Figure 1D A schematic diagram of providing a shielding slot between adjacent column differential pairs provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of a PCB structure provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of a pad array arranged in columns provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of an eccentric disk structure provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of an area for setting shielding slots in adjacent columns provided in an embodiment of the present application;

[0047] Figure 6 An overall schematic diagram of an arrangement of adjacent columns of shielding slots provided in an embodiment of the present application;

[0048] Figure 7 A schematic diagram of the position of a ground pad covered by shielding slots in adjacent columns provided in an embodiment of the present application;

[0049] Figure 8 A schematic diagram of providing shielding slots in adjacent columns provided in an embodiment of the present application;

[0050] Fig. 9 A schematic diagram of a PCB structure in which adjacent rows of shielding slots form a stepped slot as a whole, provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of adding grounding blind holes to adjacent rows of shielding slots provided in an embodiment of the present application;

[0052] Fig.11 A schematic diagram of a pad array arranged in rows provided in an embodiment of the present application;

[0053] Fig.12 A schematic diagram of a grounding blind via between adjacent rows of differential pair vias provided in an embodiment of the present application;

[0054] Fig.13 A schematic diagram of the position of a ground pad covered by adjacent rows of shielding slots provided in an embodiment of the present application;

[0055] Fig.14 A schematic diagram of adding grounding blind holes to adjacent rows of shielding slots provided in an embodiment of the present application;

[0056] Fig.15 A flow chart of a PCB processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application and to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0058] At present, printed circuit boards (PCBs) usually use a ball grid array (BGA) packaging method, that is, the differential pair vias corresponding to the pins are arranged in an array on the PCB. Under this packaging method, the differential pair vias are arranged very closely, and crosstalk is easily generated when high-speed signals are transmitted through the differential pair vias between adjacent rows or columns.

[0059] Please refer to Figure 1A , Figure 1A A schematic diagram of the BGA area in a PCB provided in an embodiment of the present application.

[0060] like Figure 1A As shown, the blue concentric circles represent signal vias, where the inner circular area of ​​the concentric circles represents the diameter of the via, and the outer circular area is the via pad, that is, the area expanded by metal to connect to the inside of the via, so as to facilitate the electrical connection between the pad and the internal routing of the via; the red circle represents the pad of the signal via; the yellow concentric circles represent ground vias, and the yellow circle marked with GND represents the ground pad.

[0061] exist Figure 1A In the figure, two adjacent signal vias (blue concentric circles) are a pair of differential vias, and the differential vias are arranged in an array. The differential vias corresponding to the A1 pad and the differential vias corresponding to the A2 pad are differential vias in the same column (column A); the differential vias corresponding to the A1 pad and the differential vias corresponding to the B1 pad are differential vias in the same row (row 1).

[0062] exist Figure 1A In the figure, the differential pair vias corresponding to A1 and A2, the differential pair vias corresponding to B1 and B2, the differential pair vias corresponding to A1 and B1, and the differential pair vias corresponding to A2 and B1 are very close to each other, and crosstalk may exist. For the differential pair vias corresponding to A1 and A2, the differential pair vias corresponding to B1 and B2, and the differential pair vias corresponding to A2 and B1, ground vias can be added between each differential pair via to isolate the crosstalk, so as to reduce the impact of the crosstalk; however, between the differential pair vias corresponding to A1 and B1, and the differential pair vias corresponding to A2 and B2, in order to enable the signals fanned out of the differential pair vias in the B column to be routed normally on the corresponding routing layer, a routing channel needs to be reserved, and it is impossible to drill a shielding ground via in the middle. Therefore, there is no available ground via for isolation between the differential pair vias corresponding to A1 and B1, and the differential pair vias corresponding to A2 and B2.

[0063] Since different signal through-holes fan out (transmit the signal to the target routing layer) in different routing layers, the corresponding via lengths are also different. The closer the fan-out routing layer is to the BOTTOM surface (bottom surface) of the PCB, the longer its via length.

[0064] Please refer to Figure 1B , Figure 1B A schematic diagram of shallow routing crosstalk between adjacent column differential pairs provided in an embodiment of the present application.

[0065] like Figure 1B As shown in the figure, the routing is shallow, the coupling length (via length) is short, and the crosstalk is not obvious.

[0066] Please refer to Figure 1C , Figure 1C A schematic diagram of deep routing crosstalk between adjacent column differential pairs provided in an embodiment of the present application.

[0067] like Figure 1C As shown in the figure, the routing is deep, the coupling length (via length) is long, and the crosstalk is more serious.

[0068] When the signal is transmitted at a low rate, the impact of this type of crosstalk is small. However, as the signal rate continues to increase, the length of the vias gradually increases. At the same time, in order to achieve better integration, the spacing between adjacent differential pair vias is shrinking. The crosstalk between adjacent differential pair vias has already affected the signal quality. Therefore, it is necessary to solve the crosstalk problem caused by long via coupling in such scenarios.

[0069] Based on this, the present application proposes a printed circuit board PCB for isolating crosstalk between signal vias, and a shielding groove is set in the PCB to reduce the impact of the crosstalk.

[0070] Please refer to Figure 1D , Figure 1D A schematic diagram of providing a shielding groove between adjacent differential pair vias provided in an embodiment of the present application.

[0071] like Figure 1D As shown, a shielding slot can be set between adjacent differential pairs. The interior of the shielding slot is a hollow slot body. The effect of the shielding slot is equivalent to a metal wall, and the signal can hardly penetrate, which can better achieve the effect of shielding crosstalk.

[0072] The printed circuit board PCB for isolating crosstalk between signal vias proposed in the present application is described in detail below.

[0073] In this embodiment, the PCB includes a first sub-board and a second sub-board, the first sub-board is deployed with a high-speed routing layer and a ground layer, and the second sub-board is deployed with a non-high-speed routing layer.

[0074] The PCB board structure proposed in this embodiment will interrupt the power layer plane channel between the differential pair vias, so the power layer in the PCB cannot be above the routing layer.

[0075] As an embodiment, the first sub-board included in the PCB may be set with n layers, the n layers are located on the TOP surface of the PCB, and may include a first sub-board and a second sub-board. The first sub-board is set with n layers, the n layers are located on the TOP surface of the PCB; the n layers may include multiple high-speed routing layers and multiple ground layers.

[0076] The second sub-board included in the PCB is provided with m layers, and the m layer is located below the n layer, serving as the BOTTOM surface of the PCB. The m layer includes a non-high-speed routing layer. Specifically, the non-high-speed routing layer may include a power layer and / or a ground layer and / or a low-speed routing layer.

[0077] By setting the first sub-board and the second sub-board, the PCB can present an n-layer + m-layer stacked structure, wherein the first sub-board and the second sub-board can be different sub-boards, that is, the first sub-board includes n layers, and the second sub-board includes m layers; the first sub-board and the second sub-board can also be the same sub-board (in this case, they can be collectively referred to as the first sub-board), that is, the first sub-board includes n+m layers (that is, n layers located on the TOP surface and m layers located on the BOTTOM surface), and the present application does not impose any restrictions on this.

[0078] In this embodiment, the first sub-board further includes via points arranged in an array, and any via point represents a differential pair of vias. The arrangement of the via points and the selection of their positions will be described in detail below and will not be repeated here.

[0079] In this embodiment, the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the first sub-board (i.e., in the nth layer) in sequence to fan out the differential signals of the differential pair vias represented by the via point through the connected high-speed routing layer.

[0080] Specifically, the differential pair vias all use blind holes from the first layer to the nth layer. There are several high-speed routing layers and ground layers between the first layer to the nth layer. Each blind hole is back-drilled to the depth of the corresponding high-speed routing layer to obtain each differential pair via.

[0081] Among them, according to the different arrangements of the differential pair vias, the differential pair vias in different rows or columns are fanned out from different high-speed routing layers in order from the outside to the inside. The closer the row or column where the differential pair vias are located is to the inside of the array, the greater the depth of the high-speed routing layer of the fan-out.

[0082] As an embodiment, taking the arrangement of differential pair vias in columns as an example, the differential signals passing through the first column of differential pair vias from the outside to the inside fan out from the first routing layer, the differential signals passing through the second column of differential pair vias fan out from the second routing layer, and so on.

[0083] In this embodiment, shielding grooves along the row direction are arranged between adjacent rows in the above-mentioned array, and the shielding grooves are connected to the ground layer in the first sub-board; wherein, the depth of the shielding grooves arranged between adjacent rows in the array is stepped, so that each shielding groove on the first sub-board presents a stepped groove; or, shielding grooves along the column direction are arranged between adjacent columns in the array, and the shielding grooves are connected to the ground layer in the first sub-board; wherein, the depth of the shielding grooves arranged between adjacent columns in the array is stepped, so that each shielding groove on the first sub-board presents a stepped groove.

[0084] In this embodiment, the shielding slot can be connected to at least one grounding layer in the first sub-board. Specifically, it can be connected to the grounding copper foil on the surface of the first sub-board, or it can be linked to at least one grounding layer in the first sub-board. Preferably, the shielding slot can be linked to all grounding layers it passes through to ensure the crosstalk shielding effect.

[0085] At the same time, the depth of the shielding grooves arranged between adjacent rows or adjacent columns is stepped, so that each shielding groove in the PCB forms a stepped groove. On the basis that the differential signals of each row or column can be routed and fanned out normally, the crosstalk between the differential pair vias between adjacent rows or columns is isolated by the stepped groove.

[0086] Below through Figures 2 to 14 The specific structure and related principles of the printed circuit board PCB proposed in this application are described.

[0087] First, the overall structure of the printed circuit board PCB is described.

[0088] Please refer to Figure 2 , Figure 2 A schematic diagram of a PCB structure provided for an embodiment of the present application.

[0089] like Figure 2 As shown, a PCB with differential pair vias arranged in columns is shown, wherein the PCB includes a first sub-board with n layers (denoted as N sub-board) and a second sub-board with m layers (denoted as M sub-board), the total number of stacked layers is n+m layers, and there are 4 columns of differential pair vias.

[0090] Among them, the N sub-board is located on the TOP surface, and there are 4 routing layers for fanning out the 4 columns of differential vias. On both sides of these 4 routing layers, there are several ground layers. The nth layer of the N sub-board can be used as a power supply, ground, and low-speed routing layer, and this application does not limit this.

[0091] The M daughter board is located on the BOTTOM surface and has m layers, specifically including the N+1th layer to the n+mth layer in the PCB, which can be used for the power layer and / or the ground layer and / or the low-speed routing layer

[0092] In this embodiment, high-speed signals are transmitted in the differential pair vias. In the subsequent description, if it is not explicitly stated that the routing layer is the low-speed routing layer in the m-layer, the routing layers mentioned below all refer to the high-speed routing layer in the n-layer.

[0093] In the stackup corresponding to the N sub-board, the 1st, 2nd, 3rd, and 4th columns of differential pair vias are arranged from the outside to the inside, and fan out from the 1st, 2nd, 3rd, and 4th routing layers respectively. The vias connected from the TOP surface to the routing layer are blind vias from the TOP to the nth layer, and are back-drilled from the nth layer to the routing layer. For fan-out methods with more columns, the above arrangement and fan-out methods of differential pair vias can also be used.

[0094] In this embodiment, between adjacent differential pair vias, several grounding blind vias connected from the TOP surface to the nth layer can be designed to isolate signals between differential pairs in adjacent rows or columns to reduce crosstalk. The grounding vias in this figure only indicate their function, and do not mean that they are between two columns of differential vias, nor do they indicate the number of such vias.

[0095] exist Figure 2 There are also several power / ground / signal through holes on the left side, as well as blind holes on the M daughter board. The connection method of these through holes is irrelevant to the technical solution proposed in this application and will not be repeated here.

[0096] It should be noted that in this embodiment, a secondary pressing stack of an N sub-board and an M sub-board (i.e. a PCB formed by pressing an N sub-board including n layers and an M sub-board including m layers) can be used; it can also be a single pressing through-hole board with n+m layers. If a stack of n+m layers of through-hole boards pressed once is used, all differential pair vias and ground vias are through holes, which has no impact on subsequent solutions.

[0097] In addition, in this embodiment, bus bars, VPD (Vertical Power Delivery) and other methods can also be used to power the PCB. The PCB using these power supply methods does not need to set up a power layer, and this application does not impose any restrictions on this.

[0098] The following briefly introduces the via points arranged in an array manner in the ball grid array (BGA) area of ​​the PCB. In this embodiment, each via included in any differential pair of vias is connected to the signal pad of the via.

[0099] Please refer to Figure 3 , Figure 3A schematic diagram of a pad array arranged in columns provided in an embodiment of the present application.

[0100] like Figure 3 As shown, each circular area represents a pad, which is connected to its corresponding through hole (not shown in the figure). For the differential pair pads in the same column, their horizontal coordinates are the same, for example, A1P and A1N are a pair of differential pair pads, A2P, A2N and A1P, A1N are differential pair pads in the same column (i.e., column A); and the differential pair pads in adjacent columns are staggered in the horizontal direction, for example, A1P and A1N are a pair of differential pair pads, and B1P, B1N are differential pair pads in adjacent columns (i.e., column B). There can also be several ground pads (i.e., GND pads in the figure) around the differential pair pads.

[0101] In this embodiment, the arrangement of the pad array is determined according to the arrangement of the pins of the electronic component connected to the PCB, and each pad corresponds to a pin of the electronic component connected to the PCB.

[0102] In the process of designing a PCB, it is first necessary to determine the arrangement of the pad array according to the arrangement of the pins of the electronic components connected to the PCB. Further, the corresponding via point array can be determined based on the pad array. In the via point array, one element in the array, i.e., a via point, represents a pair of differential vias.

[0103] In order to match impedance and expand routing channels, when determining the via positions corresponding to each pad, an eccentric disk method can be used, that is, the centers of the via and the pad do not overlap, so that the via positions are more compact to avoid as large a routing area as possible.

[0104] Please refer to Figure 4 , Figure 4 A schematic diagram of an eccentric disk structure provided in an embodiment of the present application.

[0105] like Figure 4 As shown, Figure 3 Taking the arrangement of the pad array as an example, the differential pair vias in column A can be moved upward by a certain distance relative to the corresponding differential pair pads, and the differential pair vias in column B can be moved downward by the same distance relative to the corresponding differential pair pads.

[0106] At the same time, between the first row and the second row, a number of ground blind vias can be densely arranged according to the positions of the ground pads. By moving the positions of the differential pair via holes and the ground holes, a routing channel is formed between the two rows of vias for the differential pair routing to fan out further inside.

[0107] After the positions of the differential pair vias are determined according to the differential pair pads, the arrangement of the entire differential pair vias can be determined, that is, the via point array is determined. The arrangement of the via point array is similar to that of the differential pair pad array.

[0108] It should be noted that the routing channel formed between the two rows of vias means that the routing layers included in the above n layers will not be affected by the punching in this area and can be routed normally.

[0109] In this embodiment, these grounding blind vias have formed shielding for differential pair vias between adjacent rows. It should be noted that the number and position of the grounding vias are not completely designed according to the diagram, and can be adjusted according to the signal simulation results to ensure sufficient distance between the grounding blind vias and the signal vias.

[0110] It can be seen that in the above BGA array signal arrangement, the differential pair vias between adjacent rows can be directly shielded by providing ground blind vias.

[0111] In this embodiment, for the differential pair vias between adjacent columns, if they are directly shielded by setting ground blind holes, since the ground blind holes are vias that directly penetrate the first sub-board (that is, penetrate the n layer), they will affect the routing path in the routing layer, that is, routing cannot be performed in the area where the vias exist. At this time, crosstalk shielding between the differential pair vias between adjacent columns can be achieved by setting shielding grooves.

[0112] Please refer to Figure 5 , Figure 5 A schematic diagram of a shielding slot setting area between adjacent columns of via points provided in an embodiment of the present application.

[0113] like Figure 5 As shown, shielding grooves are designed between adjacent columns of via points (such as differential pair vias A1P, A1N and differential pair vias B1P, B1N) (differential pad labels A1P, A1N are used here to refer to the corresponding differential pair via labels and will be used in the following text).

[0114] In this embodiment, when the shielding grooves along the column direction are arranged between adjacent columns in the array and pass between the via points of adjacent columns in the array, the direction of the shielding grooves is perpendicular to the connection line of the signal pads of every two matching vias between adjacent columns; wherein, the signal pads of the matching vias between adjacent columns refer to the signal pads of the vias on the side of the adjacent column in the differential pair of vias represented by each via point in the array and the signal pads closest to the adjacent column.

[0115] Since the larger the width D1 of the shielding groove is, the lower the processing difficulty is, in order to increase the width D1 of the shielding groove as much as possible to reduce the processing difficulty of controlled depth milling and electroplating, the direction of the shielding groove when passing through the via points of adjacent columns should be perpendicular to the minimum width between the signal pads of adjacent columns to obtain the maximum shielding groove width.

[0116] Specifically, in Figure 5 In determining the specific direction of the shielding groove between the A column and the B column, for the first via point in the A column, namely the differential pair vias A1P and A1N, the signal pad of the via close to the adjacent column (column B) side, namely the signal pad A1N, can be determined. After determining the signal pad A1N, based on the distance between the pads of each via in the differential pair vias included in the B column, the pad in the B column (namely the signal pad B1P) closest to the signal pad A1N is determined as the signal pad that matches the signal pad A1N.

[0117] Furthermore, the shielding groove can be set at the center position of two matching signal pads, with equal distance to the signal pads on both sides. The direction of the shielding groove in this area is perpendicular to the connection direction of the above two matching signal pads, that is, perpendicular to the connection direction of signal pad A1N and signal pad B1P.

[0118] As an embodiment, the width of the shielding groove can be determined based on the minimum processing diameter supported by the depth-controlled milling cutter and the distance between the two matching signal pads, that is, it is greater than or equal to the minimum processing diameter supported by the depth-controlled milling cutter, ensuring that the shielding groove can be processed through the depth-controlled milling technology, and it is smaller than the distance between the two matching signal pads, avoiding contact between the shielding groove and the signal pad and causing a short circuit.

[0119] In this embodiment, in order to process a shielding slot with a width of D1, a depth-controlled milling cutter with a diameter of D1 can be used for processing. The two ends of the shielding slot and the turning connection of the shielding slot in different directions are rounded. The radius R of the fillet can be determined according to the width of the shielding slot, such as the fillet radius To ensure that the depth-controlled milling cutter can complete the processing of the fillet area.

[0120] As an embodiment, the shielding slot further includes a shielding ring, which is located on the surface of the first sub-board (ie, the TOP surface) and connected to the slot wall of the shielding slot. The shielding ring is also connected to the grounding copper foil.

[0121] Specifically, the shielding ring is a metal ring located at the outermost side of the shielding slot (the area with a width of D2 in the figure), and the shielding ring is connected to the grounding copper foil (not shown in the figure) on the surface of the PCB to replace the grounding pad between two adjacent columns, and is connected to the grounding pin corresponding to the electronic component connected to the PCB at this position. Among them, the first sub-board also includes at least one grounding blind hole (such as the via corresponding to the GND pad in the figure), the grounding blind hole runs through the first sub-board and is connected to each grounding layer in the first sub-board, and the grounding copper foil is connected to at least one grounding blind hole.

[0122] In this embodiment, there is a spacing (the area shown by D3 in the figure) between the signal pad of each via hole in the differential pair of via holes represented by any via point and the shielding ring to avoid short circuit.

[0123] Illustratively, the width D2 of the shielding ring in the shielding groove and the shortest distance D3 between the shielding ring and the signal pad can be determined according to the PCB processing capability, and the present application does not impose any limitation on this.

[0124] In this embodiment, there may be dozens of rows of via points in the same column, that is, the same column includes multiple groups of differential pair vias, so the shielding groove can be continuously extended until the last group of differential pair vias in the column. During the extension process, the direction of the shielding groove is always determined according to the above method.

[0125] Please refer to Figure 6 , Figure 6 An overall schematic diagram of the arrangement of adjacent columns of shielding slots provided in an embodiment of the present application.

[0126] like Figure 6 As shown, the shielding slot can be extended to the last set of differential pair vias in the same column.

[0127] It should be noted that the direction of the shielding slot may change during the continuous extension process, and the signal pad A1N may be matched with one or more signal pads, for example, Figure 6 In the embodiment, the distances between the signal pad A1N, the signal pad B1P and the signal pad B2P are equal. At this time, the signal pad B1P and the signal pad B2P are both signal pads that match the signal pad A1N.

[0128] When the shielding groove extends between signal pad A1N and signal pad B1P, its direction can be perpendicular to the line connecting signal pad A1N and signal pad B1P; when the shielding groove extends between signal pad A1N and signal pad B2P, its direction can be perpendicular to the line connecting signal pad A1N and signal pad B2P.

[0129] At the connection between two sections of shielding slots in different directions, a rounded corner R can be made to provide a smooth transition.

[0130] In this embodiment, the depth of the shielding grooves set between adjacent columns can be determined according to the depth of the routing layer fanned out by each via point in the two adjacent columns. In the case of shielding grooves set along the column direction between adjacent columns in the array, the depth of the shielding grooves set along the column direction between adjacent columns in the array is between the depths of the high-speed routing layers connected by the differential pair vias represented by each via point in the adjacent columns; multiple grounding blind holes are set between adjacent rows in the array, and the grounding blind holes penetrate the first sub-board and are connected to each grounding layer in the first sub-board; wherein, the high-speed routing layers connected by the differential pair vias represented by each via point in the same column are the same, and the high-speed routing layers connected by the differential pair vias represented by each via point in different columns are different.

[0131] exist Figure 6 In the example, assuming that the depth of the routing layer connected by the differential pair vias in column A is less than the depth of the routing layer connected by the differential pair vias in column B, the depth of the shielding slot should exceed the depth of the routing layer connected by the differential pair vias in column A, but not exceed the depth of the routing layer connected by the differential pair vias in column B. Such a setting of the shielding slot depth can ensure that the routing path in the routing layer connected by the differential pair vias in column B will not be blocked, and can also shield the crosstalk between the differential pair vias in columns A and B.

[0132] In this embodiment, the stepped groove can be copper-plated on the inner wall of the groove through an electroplating process to make it conductive and can achieve electrical connection in a multi-layer circuit board like a plated through hole (PTH).

[0133] In this embodiment, the shielding slot actually covers the position of a row of ground pads between two rows of differential pair vias in the PCB. Figure 7 , Figure 7 A schematic diagram of adjacent columns of shielding slots covering the positions of ground pads provided in an embodiment of the present application.

[0134] like Figure 7 As shown, in this embodiment, POFV (Patterned Overlay Film Plating) copper plating is required on the shielding groove, and a solder mask window is opened in the shielding ring area corresponding to the original ground pad position to expose the area connected to the pin of the electronic component. The stepped groove can be connected to the surface grounding copper foil through the shielding ring, and close to the position of the signal pad and the via, a gap with a width of D3 is etched, and D3 can be not less than the minimum gap between the signal pad and the hole plate closest to the signal pad that is not the via corresponding to the signal pad, so as to avoid short circuit.

[0135] Please refer to Figure 8 , Figure 8A schematic diagram of providing shielding slots in adjacent columns provided in an embodiment of the present application.

[0136] like Figure 8 As shown, the shielding grooves between the differential pair vias in the A column and the B column are set in the same manner as described above. For the differential signal vias in other columns, the shielding grooves can also be designed in the same manner.

[0137] In the original pad array, as long as there is a column of ground pads between every two columns of differential pair pads, a shielding groove can be set between the two columns of differential pair pads.

[0138] Among them, the depth of the shielding groove between the nth column of differential pair vias and the n+1th column of differential pair vias should exceed the depth of the routing layer connected to the nth column of differential pair vias, and not exceed the depth of the routing layer connected to the n+1th column of differential pair vias.

[0139] As an embodiment, taking into account the existence of a processing tolerance in the depth of the shielding groove when processing it, in order to avoid affecting the underlying routing channel when processing the shielding groove, assuming that the depth of the shielding groove is h and the depth tolerance is Δh, then its lower limit of the depth h+Δh may not exceed the ground layer depth h(g) between the n and n+1 columns, so as to avoid affecting the routing channel of the routing layer connected to the differential pair vias in the n+1 column.

[0140] After completing all the settings for the shielding slot, Fig. 9 The stepped groove structure formed by each shielding groove as a whole is shown.

[0141] Please refer to Fig. 9 , Fig. 9 The schematic diagram is a PCB structure in which adjacent columns of shielding grooves form a stepped groove as a whole.

[0142] like Fig. 9 As shown, for the convenience of observation, the grounding blind holes between the differential vias in the same column are hidden. A shielding slot is designed between every two columns of differential vias. For n columns of differential vias, the number of shielding slots required is n-1.

[0143] exist Fig. 9 It can be seen that the shielding slots in the PCB are arranged in a stepped manner from the outside to the inside, and each shielding slot actually forms a stepped slot as a whole. Such a structure can ensure that the differential signal passing through each column of differential pair vias can be normally fanned out through the routing layer connected to the differential pair vias. Without affecting the fan-out of the differential signal passing through each column of differential pair vias, the crosstalk of the differential pair vias between each two adjacent columns is shielded.

[0144] Specifically, the first column of differential pair vias and the second column of differential pair vias, and the stepped groove 1 disposed between the two columns are taken as an example.

[0145] The differential signals passing through the first column of differential pair vias can be directly fanned out from the first routing layer, and there is no ground blind via to block the routing fan-out path. (The ground blind vias on both sides are exemplary to indicate that there are ground blind vias in the PCB, and they run through the 1st layer to the nth layer, and do not mean that the ground blind vias are set on the routing paths of each routing layer).

[0146] The depth of the stepped groove 1 is greater than the depth of the first routing layer and less than the depth of the second routing layer, which can isolate the crosstalk between the first column of differential pair vias and the second column of differential pair vias. At the same time, since the differential signals passing through the first column of differential pair vias can be routed through the outside (i.e., the right side of the figure) and directly fanned out to the first routing layer, even if the depth of the stepped groove 1 is greater than the depth of the first routing layer, it will not affect the routing path of the first column of differential pair vias in the first routing layer.

[0147] The differential signals passing through the second column of differential pair vias need to be routed and fanned out from the outside (i.e., the right side in the figure). Since the depth of the stepped groove 1 is less than the depth of the second routing layer, it does not affect the routing and fan-out of the second routing layer.

[0148] The principle of the stepped grooves between other columns is the same as described above and will not be repeated here.

[0149] It can be seen that the stepped groove structure formed by the shielding grooves as a whole can reduce the crosstalk of the differential pair vias between every two adjacent columns without affecting the fan-out of the differential signals passing through the differential pair vias in each column.

[0150] It should be noted that when the depth of the high-speed routing layer of the differential pair via connections between adjacent rows or adjacent columns is small, the crosstalk generated is also small and may not affect the stability of differential signal transmission. In this case, shielding grooves may not be set between adjacent rows or adjacent columns to save processing costs.

[0151] In order to achieve a better shielding effect, in this embodiment, a plurality of grounding blind holes can be further provided inside the stepped groove, and one or more grounding blind holes can be provided inside the shielding groove (including the side wall and the bottom), and the grounding blind holes penetrate the first sub-board from the inside of the shielding groove and are connected to at least one grounding layer in the first sub-board. When setting the grounding blind holes, it is necessary to avoid the wiring channels of each layer to avoid affecting the wiring and signal fan-out.

[0152] Please refer to Fig.10 , Fig.10 A schematic diagram of adding grounding blind holes to adjacent columns of shielding slots provided in an embodiment of the present application.

[0153] like Fig.10As shown, in this embodiment, several grounding blind holes can be added. These grounding blind holes pass through the first sub-board from the inside of the shielding groove and are connected to at least one grounding layer in the first sub-board to achieve a better shielding effect. Note that the blind holes need to avoid the positions where the wiring of each layer passes.

[0154] In this embodiment, the grounding blind hole only needs to avoid the positions where the wiring of each layer passes. It can be at the position of the original grounding pad covered by the shielding groove (that is, the position shown in the figure), or at other positions inside the shielding groove. This application does not impose any restrictions on this.

[0155] So far, the description of the shielding slot setting process of the array arranged in columns has been completed. The following briefly introduces the shielding slot setting process of the array arranged in rows.

[0156] Please refer to Fig.11 , Fig.11 A schematic diagram of a pad array arranged in rows.

[0157] like Fig.11 As shown, each circular area represents a pad, and the pad is connected to its corresponding through hole (not shown in the figure). For the differential pair pads in the same row, their ordinates are the same, for example, A1P and A1N are a pair of differential pair pads, A2P, A2N and A1P, A1N are differential pair pads in the same row (i.e., row A); and the differential pair pads in adjacent rows have the same abscissas, for example, A1P and A1N are a pair of differential pair pads, and B1P, B1N are differential pair pads in adjacent rows (i.e., row B). There can also be several ground pads (i.e., GND pads in the figure) around the differential pair pads.

[0158] Please refer to Fig.12 , Fig.12 A schematic diagram of a grounding blind via between adjacent rows of differential pair vias provided in an embodiment of the present application.

[0159] like Fig.12 As shown, in this signal arrangement, the fan-out direction of the differential signal is vertical, and the differential vias in the same row can be directly shielded from crosstalk by setting ground blind vias. (For example, two ground blind vias are set between A1P, A1N and A2P, A2N)

[0160] There is a row of ground pads between two adjacent rows of differential pairs. However, if crosstalk is shielded by setting ground blind holes, it will affect the routing path of the lower routing layer. In this case, a shielding groove can be set between adjacent rows.

[0161] In this embodiment, in the case of shielding grooves along the row direction arranged between adjacent rows in the array, the depth of the shielding grooves along the row direction arranged between adjacent rows in the array is between the depths of the high-speed routing layers connected by the differential pair vias represented by each via point in the adjacent rows; a plurality of grounding blind holes are arranged between adjacent columns in the array, and the grounding blind holes penetrate the first sub-board and are connected to each grounding layer in the first sub-board; wherein, the high-speed routing layers connected by the differential pair vias represented by each via point in the same row are the same, and the high-speed routing layers connected by the differential pair vias represented by each via point in different rows are different.

[0162] When the shielding grooves along the row direction arranged between adjacent rows in the array pass between the via points of adjacent rows in the array, the direction of the shielding grooves is perpendicular to the connection line of the signal pads of every two matching vias between adjacent rows; wherein, the signal pads of the matching vias between adjacent rows refer to the signal pads of the vias close to the adjacent row side in the differential pair of vias represented by each via point in the array and the signal pads closest to the adjacent row.

[0163] Please refer to Fig.13 , Fig.13 A schematic diagram of the positions of ground pads covered by adjacent rows of shielding slots provided in an embodiment of the present application.

[0164] like Fig.13 As shown, in this arrangement, the connection lines between the differential pair pads between adjacent rows are parallel, and the signal pads of the matching vias between adjacent rows are parallel and closest pads, for example, signal pad A1N and signal pad B1P are matching signal pads, signal pad A2N and signal pad B2P are matching signal pads, and so on.

[0165] Therefore, in the array arranged in rows, the direction of the shielding grooves can be kept horizontal all the time, and according to the shielding groove processing requirements of the aforementioned method, shielding grooves are arranged between every two rows of differential pair vias, which will not be described in detail here.

[0166] Please refer to Fig.14 , Fig.14 A schematic diagram of adding grounding blind holes to adjacent rows of shielding slots provided in an embodiment of the present application.

[0167] like Fig.14 As shown, in the same way as adding grounding blind holes to adjacent columns of shielding slots, several more grounding blind holes can be added. These grounding blind holes pass through the first sub-board from the inside of the shielding slot and are connected to at least one grounding layer in the first sub-board to achieve a better shielding effect. Note that the blind holes need to avoid the positions where the wiring of each layer passes.

[0168] In this embodiment, the grounding blind hole only needs to avoid the positions where the wiring of each layer passes. It can be at the position of the original grounding pad covered by the shielding groove (that is, the position shown in the figure), or at other positions inside the shielding groove. This application does not impose any restrictions on this.

[0169] This concludes the introduction to the PCB structure and the working principle of the shielding slot.

[0170] The following is a description of the PCB processing method.

[0171] Please refer to Fig.15 , Fig.15 A flow chart of a PCB processing method provided in an embodiment of the present application.

[0172] In this embodiment, the PCB includes a first sub-board and a second sub-board, the first sub-board is deployed with a high-speed routing layer and a ground layer, and the second sub-board is deployed with a non-high-speed routing layer.

[0173] As an embodiment, the first sub-board and the second sub-board may be the same sub-board or different sub-boards.

[0174] like Fig.15 As shown, the method may include the following steps:

[0175] Step 1501: Press the first sub-board and the second sub-board together to obtain the PCB.

[0176] Wherein, each via point is arranged in an array manner on the PCB; any via point represents a differential pair of vias; the differential pair of vias represented by each via point in the array are connected to the high-speed routing layer in the PCB in sequence, so as to fan out the differential signal of the differential pair of vias represented by the via point through the connected high-speed routing layer;

[0177] Shielding grooves along the row direction are arranged between adjacent rows of the array; wherein the shielding grooves are connected to the grounding layer in the PCB, and the depths of the shielding grooves arranged between adjacent rows in the array are stepped, so that each shielding groove on the PCB presents a stepped groove; or, shielding grooves along the column direction are arranged between adjacent columns of the array; wherein the shielding grooves are connected to the grounding layer in the PCB, and the depths of the shielding grooves arranged between adjacent columns in the array are stepped, so that each shielding groove on the PCB presents a stepped groove.

[0178] In this embodiment, there are multiple methods for processing a PCB including a stepped groove. For example, the PCB can be obtained by further processing a pressed PCB; or two sub-boards can be processed separately and then pressed together.

[0179] The above two methods are described below respectively.

[0180] (1) A PCB including a stepped groove is obtained by further processing based on a pressed PCB.

[0181] In this embodiment, the method of setting each via point in an array manner on the PCB includes:

[0182] After the first sub-board and the second sub-board are pressed together to obtain the PCB, the PCB is drilled to set various via points on the PCB in an array manner; wherein the drilling direction is the direction from the first sub-board to the second sub-board;

[0183] The method of providing shielding slots along the row direction between adjacent rows of the array includes:

[0184] Controlled depth milling is performed between adjacent rows of the array in the PCB to set shielding grooves along the row direction between adjacent rows of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent rows of the array;

[0185] The method of providing shielding slots along the column direction between adjacent columns of the array includes:

[0186] Controlled depth milling is performed between adjacent columns of the array in the PCB to set shielding grooves along the column direction between adjacent columns of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent columns of the array;

[0187] After performing controlled depth milling between adjacent rows of the array in the PCB, or performing controlled depth milling between adjacent columns of the array in the PCB, the method further comprises:

[0188] The PCB is electroplated and back-drilled so that the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the PCB in sequence, so as to fan out the differential signals of the differential pair vias represented by the via points through the connected high-speed routing layer.

[0189] Specifically, based on the number of high-speed routing layers and ground layers deployed in the first sub-board (for example, a total of n layers) and the number of non-high-speed routing layers deployed in the second sub-board (for example, a total of m layers), the inner layer circuits of each layer can be manufactured and pressed together to obtain a PCB including n+m layers.

[0190] Furthermore, the n+m layer PCB can be drilled according to the positions of the designed differential pair vias and ground vias, and the drilling direction is from the TOP surface of the n layer to the BOTTOM surface of the m layer to obtain the via points arranged in an array manner on the PCB.

[0191] At the same time, according to the pre-designed positions and depths of the shielding slots, the corresponding shielding slots can be processed by controlled depth milling from the top surface downwards between adjacent rows or columns in the array of the PCB. The depth of the shielding slot is controlled between the depths of the routing layers connected by the via points on the left and right sides of the shielding slot.

[0192] After completing the controlled depth milling, the PCB board undergoes processes such as electroplating, back drilling, resin plugging, and surface circuit production. During the resin plugging process, all shielding slots are also completely filled.

[0193] Furthermore, the outer layer of the PCB can be etched. During the outer layer etching process, the connection between the shielding groove and the grounding copper foil on the surface of the PCB is retained, and the gap between the shielding groove and the signal pad and the hole pad is etched out.

[0194] Next, the PCB can be subjected to solder mask processing. During the solder mask processing, a solder mask window is made above the shielding groove to expose the corresponding ground pad.

[0195] The PCB can be processed in other steps subsequently, and this application does not impose any restrictions on this.

[0196] This concludes the description of the steps of further processing a pressed PCB to obtain a PCB including stepped grooves.

[0197] In this embodiment, the method can actually be considered that the first sub-board and the second sub-board are the same sub-board, that is, there is only one PCB with n+m layers, and the PCB is processed to obtain a PCB including a stepped groove.

[0198] (2) The PCB including the stepped groove is obtained by processing two sub-boards separately and then pressing them together.

[0199] In this embodiment, the method of setting various via points in an array manner on the PCB includes:

[0200] Before pressing the first sub-board and the second sub-board together to obtain the PCB, drilling holes in the first sub-board to set various via points in an array manner on the first sub-board;

[0201] The method of providing shielding slots along the row direction between adjacent rows of the array includes:

[0202] Controlled depth milling is performed between adjacent rows in the array in the first sub-board to set shielding grooves along the row direction between adjacent rows of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent rows of the array;

[0203] The method of providing shielding slots along the column direction between adjacent columns of the array includes:

[0204] Performing controlled depth milling between adjacent columns of the array in the first sub-board to set shielding grooves along the column direction between adjacent columns of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent columns of the array;

[0205] Before pressing the first sub-board and the second sub-board together to obtain the PCB, the method further includes:

[0206] The first sub-board is electroplated and back-drilled so that the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the first sub-board in sequence, so as to fan out the differential signals of the differential pair vias represented by the via points through the connected high-speed routing layer.

[0207] Specifically, the inner layer circuits of each layer can be manufactured according to the number of high-speed routing layers and ground layers deployed in the first sub-board (for example, a total of n layers) and the number of non-high-speed routing layers deployed in the second sub-board (for example, a total of m layers), thereby obtaining a first sub-board (including n layers) and a second sub-board (including m layers).

[0208] Furthermore, for the first sub-board, the first sub-board can be drilled according to the positions of the designed differential pair vias and ground vias, and the drilling direction is from the first layer to the nth layer of the first sub-board to obtain the via points arranged in an array manner on the first sub-board.

[0209] At the same time, according to the pre-designed positions and depths of the shielding slots, the corresponding shielding slots can be processed by controlled depth milling from the bottom between adjacent rows or columns in the array of the first sub-board. The depth of the shielding slot is controlled between the depths of the routing layers connected by the via points on the left and right sides of the shielding slot.

[0210] After completing the controlled depth milling, the PCB board undergoes processes such as electroplating, back drilling, resin plugging, and surface circuit production. During the resin plugging process, all shielding slots are also completely filled.

[0211] For the second sub-board, drilling, electroplating, back drilling, resin plugging and other processes can be performed according to the positions of the via holes in the m layers included therein, that is, other processes except controlled depth milling.

[0212] After the first sub-board and the second sub-board are processed separately, the first sub-board and the second sub-board can be pressed together for a second time to obtain a PCB including a stepped groove.

[0213] After the pressing is completed, the PCB can also be subjected to processes such as through-hole drilling and electroplating.

[0214] Furthermore, the outer layer of the PCB can be etched. During the outer layer etching process, the connection between the shielding groove and the grounding copper foil on the surface of the PCB is retained, and the gap between the shielding groove and the signal pad and the hole pad is etched out.

[0215] Next, the PCB can be subjected to solder mask processing. During the solder mask processing, a solder mask window is made above the shielding groove to expose the corresponding ground pad.

[0216] The PCB can be processed in other steps subsequently, and this application does not impose any restrictions on this.

[0217] This concludes the description of the steps of obtaining a PCB including a stepped groove by separately processing two sub-boards and then laminating them.

[0218] In this embodiment, the method can actually be considered that the first sub-board and the second sub-board are different sub-boards, that is, the first sub-board of n layers and the second sub-board of m layers are processed separately, and the processed first sub-board and the second sub-board are pressed together to obtain a PCB including a step groove.

[0219] In this embodiment, after completing the inner layer circuit production of the first sub-board, the first sub-board can be drilled according to the positions of the designed differential pair vias and ground blind holes, and various mechanical holes (including differential pair vias and ground blind holes) in the sub-board are drilled. At this time, the drilled mechanical holes are all vias that pass through the first sub-board.

[0220] As an embodiment, a specific method of setting shielding slots between adjacent rows or adjacent columns of the above array may include:

[0221] If the width of the shielding slot is greater than or equal to the preset processing threshold, the shielding slot is processed by controlled depth milling; the diameter of the milling cutter used in the controlled depth milling is the same as the width of the shielding slot;

[0222] If the width of the shielding groove is smaller than the preset processing threshold, the shielding groove is processed by depth-controlled drilling; the diameter of the drill bit used in the depth-controlled drilling is the same as the width of the shielding groove.

[0223] In this embodiment, for a wider shielding slot, more efficient processing can be achieved by using controlled depth milling. If the shielding slot is narrower, the controlled depth milling may easily cause the milling cutter to break in the direction of travel. A drill with a diameter equal to the slot width can be used to gradually control the depth of the drill to process the shielding slot, and the processing effect of the shielding slot can also be achieved. This application does not impose any restrictions on this.

[0224] As an embodiment, the first sub-board further includes at least one grounding blind via, which penetrates the first sub-board and is connected to each grounding layer in the first sub-board; the surface (i.e., TOP surface) of the first sub-board of the PCB further includes a grounding copper foil, which is connected to the at least one grounding blind via; each via included in any differential pair of vias is connected to the signal pad of the via; the method further includes:

[0225] The outer layer of the PCB is etched to preserve the connection between the shielding slot and the ground copper foil, and to etch out the spacing between the shielding slot and the signal pad of any via in the differential pair via represented by each via point to avoid short circuit.

[0226] As an embodiment, the method may further include:

[0227] The shielding slot is plugged with resin, and holes are drilled inside the shielding slot without affecting the position of the high-speed routing layer in the first sub-board to obtain one or more grounding blind holes. The grounding blind holes pass through the first sub-board from the inside of the shielding slot and are connected to at least one grounding layer in the first sub-board.

[0228] In this embodiment, the above method will be described in detail below and will not be repeated here.

[0229] This concludes Fig.15 Description of PCB processing methods.

[0230] The PCB processing process is described in detail below.

[0231] Before processing the PCB, you first need to complete the design of the PCB. For example, first determine the corresponding pad array based on the pins of the electronic components connected to the PCB, and then further determine the positions of each differential pair of vias and ground vias based on the pad array, and determine the direction, width, depth, etc. of the shielding groove.

[0232] 1. The processing method for a PCB (using N sub-board + M sub-board) without grounding blind holes on the shielding slot can include the following steps:

[0233] a) Make inner layer circuits for each core board of the n-layer daughter board (including the first n layers on the TOP surface), and brown-press them.

[0234] b) Drilling the n-layer daughter board to drill various mechanical holes (including differential pair vias and ground blind vias) in the daughter board n.

[0235] c) According to the pre-designed shielding slot position and depth, controlled depth milling is performed downward from the TOP surface in the area corresponding to the pad array to process several shielding slots. The diameter of the milling cutter used is the shielding slot width D1, and the controlled depth milling depth should be between the routing layers on the left and right sides of the shielding slot.

[0236] In this embodiment, for a shielding groove with a wider width, the controlled depth milling method can be directly used to achieve more efficient processing; if the width of the shielding groove is narrow, when the controlled depth milling method is used for processing, there is a risk of the milling cutter breaking in the direction of travel. At this time, a drill with a diameter equal to the width of the shielding groove can be used to process the shielding groove through step-by-step controlled depth drilling. Although the efficiency is low, the processing effect of the shielding groove can also be achieved. The same applies to the shielding groove in the following processing process.

[0237] d) After the controlled depth milling is completed, the n-layer daughter board is subjected to copper electroplating. During this process, all the vias and shielding slots in the n-layer daughter board will be plated with copper.

[0238] e) Back drilling of the n-layer daughter board (removing unnecessary copper materials in the inner layer through holes, thereby reducing interference and delay during signal propagation, ensuring the signal integrity and reliability of the circuit board), resin plugging, and n-layer line production (which can be used as power, ground, and low-speed routing layers). During the resin plugging process, all shielding slots and vias should be completely filled with resin to improve the overall performance and reliability of the circuit board.

[0239] f) Similarly, the same processing is performed on the m-layer sub-plate, but the m-layer sub-plate does not need to be depth-controlled milling.

[0240] g) Perform secondary lamination on the n-layer sub-board and the m-layer sub-board.

[0241] h) The PCB after lamination is subjected to through-hole drilling, electroplating and other processes. During the electroplating process, a layer of copper will be plated on the surface of the shielding slot.

[0242] i) During the outer layer etching process, the shielding groove is kept connected to the outer layer grounding copper foil, and the gap between the shielding groove and the signal pad and the hole pad is etched out.

[0243] j) During the solder mask processing, a solder mask window is made above the shielding groove to expose the shielding ring area corresponding to the position of the ground pin of the electronic component connected to the PCB, so that the ground pin of the electronic component is connected to the shielding ring of the shielding groove.

[0244] k) Perform the remaining processing steps on the PCB.

[0245] In this embodiment, the processing method for the remaining steps of the PCB is a commonly used method in the related art, and this application does not limit this.

[0246] 2. Processing method for PCB with grounding blind holes on shielding slots (using N sub-board + M sub-board).

[0247] a) Make inner layer circuits for each core board of the n-layer daughter board, and then brown-press them.

[0248] b) According to the pre-designed shielding slot position and depth, controlled depth milling is performed downward from the TOP surface in the BGA area to process several shielding slots. The diameter of the milling cutter used is the shielding slot width D1, and the controlled depth milling depth should be between the routing layers on the left and right sides of the shielding slot.

[0249] c) Perform copper electroplating on the shielding slots and make resin-filled holes to completely fill all the shielding slots with resin.

[0250] d) Drill holes in the daughter board, drill various mechanical holes (including grounding blind holes and differential pair vias) in the n-layer daughter board, and in this process, drill grounding holes located on the shielding slot.

[0251] e) The daughter board is subjected to copper electroplating to plate the signal holes and ground holes with copper.

[0252] f) Perform back drilling, resin plugging, and n-layer circuit production on the n-sub-board. During the resin plugging process, all shielding slots should also be completely filled with resin.

[0253] g) Similarly, the same processing flow is carried out on the m-layer sub-plate, but the m-layer sub-plate does not need to be depth-controlled milling.

[0254] h) Perform secondary lamination on the n-layer and m-layer daughter boards.

[0255] i) The PCB after lamination is subjected to through-hole drilling, electroplating and other processes. During the electroplating process, a layer of copper will be plated on the surface of the shielding slot.

[0256] j) During the outer layer etching process, the shielding groove is kept connected to the outer layer's grounding copper foil, and the gap between the shielding groove and the signal pad and the hole pad is etched out.

[0257] k) During the solder mask processing, a solder mask window is made above the shielding groove to expose the shielding ring area corresponding to the position of the ground pin of the electronic component connected to the PCB, so that the ground pin of the electronic component is connected to the shielding ring of the shielding groove.

[0258] l) Perform the remaining steps on the PCB.

[0259] In this embodiment, unlike the PCB processing method without grounding blind holes on the shielding slot, the PCB processing method with grounding blind holes on the shielding slot can firstly process the shielding slot and then uniformly punch the holes.

[0260] As an embodiment, after completing the PCB processing according to the PCB processing method without grounding blind holes, grounding blind holes can be added to the shielding grooves. It should be noted that the grounding blind holes cannot affect the routing path of the lower routing layer.

[0261] 3. Processing method of n+m layer through-hole board.

[0262] a) Make inner layer patterns for each layer of the n+m-layer through-hole board and press them together.

[0263] b) Drill various through holes on the pressed board.

[0264] c) According to the pre-designed shielding slot position and depth, controlled depth milling is performed downward from the TOP surface in the BGA area to process several shielding slots. The diameter of the milling cutter used is the shielding slot width D1, and the controlled depth milling depth should be between the routing layers on the left and right sides of the shielding slot.

[0265] d) After the controlled depth milling is completed, the PCB board is subjected to copper electroplating. During this process, all holes and shielding slots will be plated with copper.

[0266] e) Perform back drilling, resin plugging, circuit making and other processes on the PCB. During the resin plugging process, all shielding slots should also be completely filled with resin.

[0267] f) During the outer layer etching process, the shielding groove is kept connected to the outer layer's grounding copper foil, and the gap between the shielding groove and the signal pad and the hole pad is etched out.

[0268] g) During the solder mask processing, a solder mask window is made above the shielding groove to expose the shielding ring area corresponding to the position of the ground pin of the electronic component connected to the PCB, so that the ground pin of the electronic component is connected to the shielding ring of the shielding groove.

[0269] h) Perform the remaining processing steps on the PCB.

[0270] This concludes the description of the PCB processing method.

[0271] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A printed circuit board PCB, characterized in that: The PCB includes a first sub-board and a second sub-board, the first sub-board is deployed with a high-speed wiring layer and a ground layer, and the second sub-board is deployed with a non-high-speed wiring layer; The first sub-board also includes via points arranged in an array, and any via point represents a differential pair of vias; shielding grooves along the row direction are arranged between adjacent rows in the array, and the shielding grooves are connected to the ground layer in the first sub-board; wherein the depth of the shielding grooves arranged between adjacent rows in the array is stepped, so that each shielding groove on the first sub-board presents a stepped groove; or, shielding grooves along the column direction are arranged between adjacent columns in the array, and the shielding grooves are connected to the ground layer in the first sub-board; wherein the depth of the shielding grooves arranged between adjacent columns in the array is stepped, so that each shielding groove on the first sub-board presents a stepped groove; The differential pair vias represented by each via point in the array are sequentially connected to the high-speed routing layer in the first sub-board to fan out the differential signals through the differential pair vias represented by the via point through the connected high-speed routing layer.

2. The PCB according to claim 1, characterized in that: In the case of shielding grooves along the row direction arranged between adjacent rows in the array, the depth of the shielding grooves along the row direction arranged between adjacent rows in the array is between the depths of the high-speed routing layers connected by the differential pair vias represented by each via point in the adjacent rows; a plurality of grounding blind holes are arranged between adjacent columns in the array, and the grounding blind holes penetrate the first sub-board and are connected to each grounding layer in the first sub-board; wherein the high-speed routing layers connected by the differential pair vias represented by each via point in the same row are the same, and the high-speed routing layers connected by the differential pair vias represented by each via point in different rows are different; In the case where shielding grooves along the column direction are arranged between adjacent columns in the array, the depth of the shielding grooves along the column direction arranged between adjacent columns in the array is between the depths of the high-speed routing layers connected by the differential pair vias represented by each via point in the adjacent columns; a plurality of grounding blind holes are arranged between adjacent rows in the array, and the grounding blind holes penetrate the first sub-board and are connected to each grounding layer in the first sub-board; wherein the high-speed routing layers connected by the differential pair vias represented by each via point in the same column are the same, and the high-speed routing layers connected by the differential pair vias represented by each via point in different columns are different.

3. The PCB according to claim 1, characterized in that: Each via included in any differential pair of vias is connected to the signal pad of the via; When the shielding grooves arranged along the row direction between adjacent rows in the array pass between the via points of adjacent rows in the array, the direction of the shielding grooves is perpendicular to the connection line of the signal pads of every two matching vias between the adjacent rows; wherein the signal pads of the matching vias between adjacent rows refer to the signal pads of the vias close to one side of the adjacent row in the differential pair of vias represented by each via point in the array and the signal pads closest to the adjacent row; When the shielding grooves along the column direction arranged between adjacent columns in the array pass between the via points of adjacent columns in the array, the direction of the shielding grooves is perpendicular to the connection line of the signal pads of every two matching vias between the adjacent columns; wherein, the signal pads of the matching vias between adjacent columns refer to the signal pads of the vias close to the adjacent column side in the differential pair of vias represented by each via point in the array and the signal pads closest to the adjacent column.

4. The PCB according to claim 3, characterized in that: Both ends of the shielding slot and the turning connections of the shielding slot in different directions are rounded.

5. The PCB according to claim 1, characterized in that: The first sub-board further comprises at least one grounding blind hole, which passes through the first sub-board and is connected to each grounding layer in the first sub-board; the surface of the first sub-board further comprises a grounding copper foil, which is connected to at least one grounding blind hole; The shielding slot also includes a shielding ring, which is located on the surface of the first sub-board and connected to the slot wall of the shielding slot. The shielding ring is also connected to the grounding copper foil.

6. The PCB according to claim 5, characterized in that: There is a spacing between the signal pad of each via in the differential pair vias represented by any via point and the shielding ring to avoid short circuit.

7. The PCB according to claim 1, characterized in that: One or more grounding blind holes are arranged inside the shielding slot, and the grounding blind holes penetrate through the first sub-board from the inside of the shielding slot and are connected to at least one grounding layer in the first sub-board.

8. A PCB processing method, characterized in that: The PCB includes a first sub-board and a second sub-board, the first sub-board is deployed with a high-speed wiring layer and a ground layer, and the second sub-board is deployed with a non-high-speed wiring layer; the method includes: The first sub-board and the second sub-board are pressed together to obtain the PCB; via points are arranged on the PCB in an array manner; any via point represents a differential pair of vias; the differential pair of vias represented by each via point in the array are sequentially connected to the high-speed routing layer in the PCB to fan out the differential signal of the differential pair of vias represented by the via point through the connected high-speed routing layer; Shielding grooves along the row direction are arranged between adjacent rows of the array; wherein the shielding grooves are connected to the grounding layer in the PCB, and the depths of the shielding grooves arranged between adjacent rows in the array are stepped, so that each shielding groove on the PCB presents a stepped groove; or, shielding grooves along the column direction are arranged between adjacent columns of the array; wherein the shielding grooves are connected to the grounding layer in the PCB, and the depths of the shielding grooves arranged between adjacent columns in the array are stepped, so that each shielding groove on the PCB presents a stepped groove.

9. The method according to claim 8, characterized in that The method for setting each via point in an array manner on the PCB includes: After the first sub-board and the second sub-board are pressed together to obtain the PCB, the PCB is drilled to set various via points on the PCB in an array manner; wherein the drilling direction is the direction from the first sub-board to the second sub-board; The method of providing shielding slots along the row direction between adjacent rows of the array includes: Controlled depth milling is performed between adjacent rows of the array in the PCB to set shielding grooves along the row direction between adjacent rows of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent rows of the array; The method of providing shielding slots along the column direction between adjacent columns of the array includes: Controlled depth milling is performed between adjacent columns of the array in the PCB to set shielding grooves along the column direction between adjacent columns of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent columns of the array; After performing controlled depth milling between adjacent rows of the array in the PCB, or performing controlled depth milling between adjacent columns of the array in the PCB, the method further comprises: The PCB is electroplated and back-drilled so that the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the PCB in sequence, so as to fan out the differential signals of the differential pair vias represented by the via points through the connected high-speed routing layer.

10. The method according to claim 8, characterized in that The method for setting each via point in an array manner on the PCB includes: Before pressing the first sub-board and the second sub-board together to obtain the PCB, drilling holes in the first sub-board to set various via points in an array manner on the first sub-board; The method of providing shielding slots along the row direction between adjacent rows of the array includes: Controlled depth milling is performed between adjacent rows in the array in the first sub-board to set shielding grooves along the row direction between adjacent rows of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent rows of the array; The method of providing shielding slots along the column direction between adjacent columns of the array includes: Performing controlled depth milling between adjacent columns of the array in the first sub-board to set shielding grooves along the column direction between adjacent columns of the array; wherein the depth of any shielding groove is between the depths of the high-speed routing layers connected by differential pair vias represented by via points in adjacent columns of the array; Before pressing the first sub-board and the second sub-board together to obtain the PCB, the method further includes: The first sub-board is electroplated and back-drilled so that the differential pair vias represented by each via point in the array are connected to the high-speed routing layer in the first sub-board in sequence, so as to fan out the differential signals of the differential pair vias represented by the via points through the connected high-speed routing layer.

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