Processor performance model considering memory frequency influence

Abstract

The invention discloses a processor performance model considering memory frequency influence. Along with the increase of the performance optimization requirements of the processor, the influence of memory access characteristics on the performance of the processor is increasingly significant, especially the key effect of memory access delay on the instruction cycle number. In a traditional method, adjustment of core frequency and voltage is mainly concerned, and the influence of memory frequency on performance is ignored, so that the optimization effect is limited. The invention provides a performance optimization method based on memory access characteristics. The method focuses on analyzing the influence of memory frequency on storage access delay. By periodically collecting memory access behavior characteristics, a performance model of task and memory interaction is established, and the influence of different memory frequency configurations on task performance is evaluated. The ratio of memory frequency is optimized, and the energy efficiency ratio and performance of the memory are improved. Compared with a traditional method, the method has the advantages that the influence of the memory performance on the core task can be evaluated more accurately, and a new solution thought is provided for performance optimization of the processor.

Description

Technical Field

[0001] The present invention relates to the application of frequency scaling technology in multi-core processors, and belongs to the technical field of processor performance evaluation and optimization. The present invention aims to provide an effective method to predict and optimize the performance impact of memory frequency under various working conditions by modeling and evaluating the performance of memory under different frequency settings. Background Art

[0002] IPS (Instructions Per Second) is a key performance indicator that measures the number of instructions executed by the processor per unit time, and directly reflects the execution efficiency and response speed of the processor. DVFS is an important strategy to improve system energy efficiency and performance. It optimizes the balance between performance and power consumption by dynamically adjusting the frequency and voltage of the processor and memory according to changes in task load. With DVFS, the frequency and voltage can be reduced to save energy when the load is low, and the frequency can be increased to meet performance requirements when the load is high.

[0003] In traditional 2D planar chips, DVFS mainly acts on the frequency adjustment of the core or memory. For CPU-bound computing tasks, if we do not consider the access to storage devices, we can easily get the impact of core frequency on the overall IPS. is the clock frequency in the simulation cycle, is the clock frequency in the simulation cycle, and it is easy to get the following relationship:

[0004]

[0005] However, in the scenario of memory access, the performance of the processor is not only affected by the core frequency, but also closely related to the latency of memory access. At this time, the performance of the core can be expressed by the following formula:

[0006]

[0007] CPI compute It is only related to the currently executed instruction and the clock frequency f core , memory access latency is irrelevant. This means that when evaluating CPI compute When we consider the type and execution logic of the instruction, we only need to consider the type and execution logic of the instruction. mem It is related to multiple factors, including the current execution instruction, clock frequency f core , memory access latency. Therefore, the predicted CPI mem The changes in necessitate considering the interaction of these parameters simultaneously.

[0008] Memory access latency is primarily determined by memory frequency. When memory frequency decreases, the number of cycles required to access data each time increases, significantly extending memory access time. Increased latency not only reduces instruction throughput, but also negatively affects task response time. At high frequencies, although latency is reduced, it may lead to a significant increase in energy consumption. Therefore, a trade-off between performance and energy efficiency needs to be made when adjusting memory frequency.

[0009] Technical problems solved by the invention and purpose of the invention

[0010] The present invention solves the problem of increased modeling complexity and insufficient response speed in the traditional model when predicting the impact of memory frequency changes on performance. The present invention aims to provide a performance optimization method based on memory frequency and delay characteristics: (1) extracting key parameters for modeling memory access delay by periodically monitoring and analyzing the memory access characteristics of tasks; (2) establishing a simplified model of memory frequency and access delay to accurately evaluate the impact of memory delay on performance; (3) based on the model, quickly predicting task performance changes and optimizing memory frequency configuration to achieve adaptive performance optimization for different task types. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following briefly introduces the drawings required to be used in the embodiment of the present invention.

[0012] Figure 1 It is a calculation flow chart provided by the implementation of the present invention;

[0013] Figure 2 It is a block diagram of the monitoring module monitor of the present invention; DETAILED DESCRIPTION

[0014] Step 1: The monitor periodically samples and analyzes the instructions. The input of the monitor includes: unit cycle time parameter (δms), the frequency size f of each core core , the frequency size f of each storage bank mem , sampling instruction Instruction;

[0015] 1.1 The monitor obtains the core frequency (f core ) and memory frequency (f mem ).

[0016] 1.2 The monitor samples the instructions of each working core and records the type of each sampled instruction (instruction type) and the instruction consumption clock cycle (CPI).

[0017] 1.3 The instructions executed in a cycle can be divided into two parts: 1. Core computing part, 2. Storage access part. The former is further subdivided into microinstruction types such as base, dispatch, depend, branch, etc. according to the computing type, and the latter is further subdivided into microinstruction types such as mem-dram, ifetch, etc. according to the storage access purpose;

[0018] Step 2: Sample data through the monitor and calculate the key parameters of the DVFS optimization model.

[0019] 2.1 Read the core calculation counter to obtain the instruction calculation cycle within the unit cycle.

[0020] Because when running the same instruction, it is a fixed value, which is only related to the type of instruction currently executed. It has nothing to do with the core operating frequency and storage access latency. Therefore:

[0021] CPI core =F1(Instruction)

[0022] 2.2 Read the memory access counter to obtain the required cycle for storage access within the unit cycle;

[0023] 2.3 Build a linear dvfs model and calculate the clock frequency (f core ) is the linear impact factor (α) on this type of instruction. In this model, each access to memory takes a fixed time T memory , the access time is related to the type of instruction and has nothing to do with the core operating frequency, and the following relationship can be obtained:

[0024]

[0025] T memory =T1(Intruction)

[0026] CPI mem =F2(f core , T memory )

[0027] 2.4 Build a storage frequency and latency model. Calculate the impact of storage frequency on memory access latency under this type of instruction. When the same is done for storage, the duration of each storage access is no longer fixed, and the duration will change with the change of storage frequency. Therefore, when the core and storage collaborate on dvfs, they will be affected by the instruction type (Instruction), core frequency (f core )、Memory frequency(f mem )The influence of the three.

[0028] T memory=T1(Intruction, f mem )

[0029] CPI mem =F2(f mem , Instruction)

[0030] Step 3: Get the optimization model and optimize IPS performance according to different instruction types. Now the expression of IPS is updated to:

[0031]

[0032] Get the final impact of memory frequency on processor performance.

Claims

1. A processor performance model considering the impact of memory frequency, characterized in that The following two parts: (P1) Periodic instruction monitoring strategy A strategy for periodically monitoring CPI (instructions per cycle) to evaluate processor performance, characterized by: (1.1) Regularly collect the characteristics of instructions executed in each cycle and monitor the execution cycles of different types of instructions; (1.2) The instruction execution cycle is counted by a counter, and divided into a calculation cycle and a memory access cycle; (1.3) By monitoring and collecting CPI at specific time intervals, the load characteristics of the task can be captured in a timely manner; (P2) Modeling Method of Memory Frequency and Access Latency Features: (1.1) In the modeling, only the current instruction type and its execution process are considered, ignoring the impact of core frequency and memory access latency on it; (1.2) In modeling, the impact of factors such as memory frequency and current instruction type on memory access cycle is considered; and the relationship between memory frequency and memory access latency is modeled in the modeling; (1.3) Because this model also takes the instruction type as part of the input parameters, it can monitor the characteristics of the current task in real time (such as compute-intensive tasks, memory-intensive tasks, hybrid tasks, etc.) and adaptively adjust the memory frequency; for compute-intensive tasks, the core frequency is adjusted first to improve computing performance; for memory-intensive tasks, the memory frequency is adjusted first to reduce memory access latency; in hybrid tasks, the combination of core frequency and memory frequency is dynamically adjusted according to the execution stage of the task to optimize the overall performance of the task.

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