Test data processing board card, test data processing method and test machine

Abstract

The invention relates to a test data processing board card, a test data processing method and a test machine, a hard acceleration device confirms configuration parameters according to an instruction issued by a driving engine module, reads corresponding original capture data from a storage device according to the configuration parameters, filters and splices the read original capture data, and sends the filtered and spliced data to a server; the generated and processed capture data are sent to the driving engine module; and the driving engine module performs parallel acceleration processing on the received captured data through an asynchronous thread when the total amount of the data needing to be processed meets a set asynchronous thread starting condition. Data processing is carried out in a mode of combining hard acceleration and soft acceleration, so that the data processing efficiency is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a test data processing board, method and test machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to detect various parameter indicators of the device under test (DUT) and eliminate defective products to control the factory quality of semiconductors. In actual testing, the digital board in the tester obtains the voltage comparison value of the actual channel output of the chip / pin of each chip at each site corresponding to the actual running code data according to the sampling points and comparison voltages set by the timing, and stores it in the storage device. The capture module in the digital board reads the data stored in the storage device and processes the data, and uploads it to the host computer. The traditional capture module data processing method is to use a single thread of software to gradually extract the stored data for processing. With the change in demand from small data volume to large data volume, the processing speed of the traditional processing method can no longer meet the requirements for time efficiency, and there is a disadvantage of low data processing efficiency. Summary of the invention

[0003] Based on this, it is necessary to provide a test data processing board, method and test machine that can improve data processing efficiency in order to address the above problems.

[0004] In a first aspect, the present application provides a test data processing board, comprising a drive engine module and a hard acceleration device, wherein the hard acceleration device is connected to the drive engine module and a storage device;

[0005] The hard acceleration device is used to confirm the configuration parameters according to the instructions issued by the driving engine module, read the corresponding original captured data from the storage device according to the configuration parameters, filter and splice the read original captured data, generate processed captured data and send it to the driving engine module;

[0006] The driving engine module is used to perform parallel accelerated processing on the received captured data through asynchronous threads when the total amount of data to be processed meets the set asynchronous thread start condition.

[0007] In one embodiment, the hard acceleration device includes a communication module, a parameter parsing module, a parameter processing module, a read-write control module, a cache module and a data processing module, the communication module is connected to the drive engine module, the parameter parsing module and the data processing module, the parameter parsing module is connected to the parameter processing module and the data processing module, the read-write control module is connected to the parameter processing module, the cache module and the storage device, and the cache module is connected to the data processing module;

[0008] The parameter parsing module receives the instruction sent by the driving engine module through the communication module, parses the instruction, obtains the configuration parameters and sends them to the parameter processing module and the data processing module;

[0009] The parameter processing module parses the received configuration parameters, obtains data reading information and sends it to the read-write control module; the read-write control module reads the corresponding original captured data from the storage device according to the data reading information, and sends the read original captured data to the cache module for caching;

[0010] The data processing module reads the corresponding original captured data from the cache module according to the received configuration parameters, performs data filtering and splicing, generates processed captured data, and uploads the processed captured data to the driving engine module through the communication module.

[0011] In one of the embodiments, the configuration parameters received by the parameter processing module include read request parameters, and the data reading information includes a read request address and a read request length; the parameter processing module parses the read request parameters, obtains the read request address and the read request length, and sends them to the read-write control module; the read-write control module reads the corresponding original captured data from the storage device according to the read request address and the read request length.

[0012] In one of the embodiments, the configuration parameters received by the data processing module include valid bit positions and frame header information; the data processing module filters and splices the original captured data read from the cache module according to the valid bit positions to obtain uplink data, and reframes the uplink data according to the frame header information to obtain single-bit captured data and uploads it to the drive engine module through the communication module.

[0013] In one embodiment, the data processing module includes a read control unit, a single-bit conversion unit and a single-bit upload unit, the read control unit is connected to the cache module, the single-bit conversion unit is connected to the cache module and the single-bit upload unit, and the single-bit upload unit is connected to the communication module;

[0014] The read control unit is used to output a read enable signal to the cache module so that the cache module outputs the original captured data line by line. The single-bit conversion unit receives a line of original captured data output by the cache module, filters and re-splices according to the valid bit positions, compresses a line of original captured data into uplink data and sends it to the single-bit upload unit; the single-bit upload unit re-frames the received uplink data according to the frame header information, obtains single-bit captured data and outputs it to the communication module.

[0015] In one embodiment, the data processing module also includes a single-bit control unit, which is connected to the parameter parsing module, the read control unit, the single-bit conversion unit and the single-bit upload unit; the single-bit control unit controls the read control unit to output a read enable signal, configures the valid bit position of the single-bit conversion unit, and configures the frame header information of the single-bit upload unit.

[0016] In one of the embodiments, a driver is loaded in the driver engine module. When the total amount of data to be processed meets the set asynchronous thread start condition, the driver sends instructions to the hard acceleration device through the main thread to control the hard acceleration device to read the corresponding original captured data from the storage device for filtering and splicing processing; the driver also stores the captured data uploaded and processed by the hard acceleration device in a message queue, and multiple slave threads of the driver poll the data in the message queue for parallel acceleration processing until the message queue is empty.

[0017] In one of the embodiments, the driving engine module determines the total amount of data to be processed based on the test parameters sent by the host computer. If the total amount of data to be processed is greater than or equal to a preset threshold, the asynchronous thread start condition is met.

[0018] In one of the embodiments, the total amount of data that needs to be processed is the total number of rows of data, and the preset threshold is a preset row number threshold; when the driving engine module determines that the conditions for starting the asynchronous thread are met, it sends an instruction to the hard acceleration device in combination with the preset row number threshold, controls the hard acceleration device to read the original captured data of the number of rows corresponding to the preset row number threshold from the storage device, filters and splices the data, and uploads the processed captured data to the driving engine module.

[0019] A second aspect of the present application provides a test data processing method, comprising:

[0020] The hard acceleration device confirms the configuration parameters according to the instructions issued by the driving engine module;

[0021] The hard acceleration device reads the corresponding raw captured data from the storage device according to the configuration parameters, filters and splices the read raw captured data, generates processed captured data and sends it to the driving engine module;

[0022] When the total amount of data to be processed meets the set asynchronous thread start condition, the driving engine module performs parallel accelerated processing on the received captured data through the asynchronous thread.

[0023] A third aspect of the present application provides a testing machine, comprising a host computer and the above-mentioned test data processing board.

[0024] In the above-mentioned test data processing board, method and test machine, the hard acceleration device confirms the configuration parameters according to the instructions issued by the driving engine module, reads the corresponding original captured data from the storage device according to the configuration parameters, filters and splices the read original captured data, generates processed captured data and sends it to the driving engine module, and completes the hard acceleration processing of the data. When the total amount of data to be processed meets the set asynchronous thread start condition, the driving engine module performs parallel acceleration processing on the received captured data through the asynchronous thread to realize the soft acceleration processing of the data. By combining hard acceleration and soft acceleration to process data, the data processing efficiency is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A structural block diagram of a test data processing board in an embodiment;

[0026] Figure 2 is a structural principle diagram of a hard acceleration device in one embodiment;

[0027] Figure 3 The figure is a flowchart of a test data processing method in one embodiment. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] With the advent of the information age, integrated circuits (ICs) have entered a period of rapid development. The establishment and division of labor of the complete integrated circuit industry has formed an industrial chain, and design, production, processing, testing, and packaging have become key nodes. How to improve test quality, fault coverage, and stability have become the main issues facing the development of testing technology. The basic principle of integrated circuit testing is to apply stimulus to the device under test (DUT) through a tester, compare the output value of the device under test with the expected value, and store the comparison result in a storage device for storing the test results for various functional tests. Usually, the test program of the tester ATE mainly includes three aspects: DC parameter test, AC parameter test, and functional test.

[0030] In the functional test of the device under test (DUT), a major test unit is the capture module (Capture). The device under test is explained by taking a chip as an example. In the actual chip test, the digital board obtains the voltage comparison value of the actual channel output of the chip / pin of each chip at each site corresponding to the actual running code data according to the sampling points and comparison voltages set by the timing, and stores it in the storage device DDR. The capture module in the digital board reads and processes the data in the DDR, processes it into the required data value and returns it to the host computer. With the change in the demand for small data volume to large data volume, the processing speed of the traditional single-threaded data processing method used by the capture module can no longer meet the requirements for time efficiency, and there is a disadvantage of low data processing efficiency.

[0031] The tester supports pin testing. The DDR storage format is to save the test results of the pins in sequence. The DDR is stored separately according to the pin test value. The DDR storage row stores each pin test value, that is, the test data bit. The test data bit specifically includes: test result data bit, pin number flag bit (pin num) and actual valid cycle count bit (cyclecount bit). In order to align the DDR storage row, a fixed bit data structure is designed. When there are insufficient valid data bits in the DDR row, the remaining bits will be automatically supplemented with the default value, such as the default value of 0; therefore, the default value of the supplemented bit is an invalid value, and the capture module (Capture) processing capability is increased for this invalid data volume. In addition, according to different DDR storage methods, shift storage will be involved, thereby increasing the workload of the capture module (Capture) data analysis, and the current capture module (Capture) efficiency cannot meet the standard and cannot cope with the efficient processing of large amounts of data.

[0032] Based on this, the test data processing board provided by the present application, the hard acceleration device confirms the configuration parameters according to the instructions issued by the driving engine module, reads the corresponding original captured data from the storage device according to the configuration parameters, filters and splices the read original captured data, generates processed captured data and sends it to the driving engine module, and completes the hard acceleration processing of the data (all data processing is completed in the hard acceleration device, which is faster than ordinary processing). When the total amount of data to be processed meets the set asynchronous thread start condition, the driving engine module performs parallel acceleration processing on the received captured data through the asynchronous thread to achieve soft acceleration processing of the data. By combining hard acceleration and soft acceleration to process data, the data processing speed is greatly improved compared to the original processing method, effectively saving production time and improving production efficiency.

[0033] In one embodiment, Figure 1 As shown, a test data processing board is provided, including a driving engine module 110 and a hard acceleration device 120, and the hard acceleration device 120 is connected to the driving engine module 110 and the storage device 200. The hard acceleration device 120 is used to confirm the configuration parameters according to the instructions issued by the driving engine module 110, read the corresponding original captured data from the storage device 200 according to the configuration parameters, filter and splice the read original captured data, generate processed captured data and send it to the driving engine module 110; the driving engine module 110 is used to perform parallel acceleration processing on the received captured data through the asynchronous thread when the total amount of data to be processed meets the set asynchronous thread start condition.

[0034] Among them, the hard acceleration device 120 can be a hardware structure such as FPGA, and the storage device 200 can be a DDR storage device, which stores the original captured data corresponding to different pins of the device under test in rows. Each BE board in the digital board of the test machine is connected to multiple FE boards, and each FE board is connected to multiple PE chips. The test signal fed back by each pin of each device under test (DUT) is received through the PE chip, and the original captured data is stored in the DDR. Each row in the DDR stores the original captured data and the corresponding pin number flag (pin num). The test parameters can be sent by the host computer to read the original captured data of the corresponding FE board. Of course, it is known to those skilled in the art that the PE chip can be placed in the FE board. Specifically, the drive engine module 110 communicates with the host computer, and the total amount of data that needs to be processed for the current test item can be determined according to the test parameters sent by the host computer. If the total amount of data that needs to be processed is greater than or equal to the preset threshold, it can be considered that the asynchronous thread start condition is met. The value of the preset threshold is not unique and can be set according to actual conditions. In addition, the driving engine module 110 may also read the number of pins of the device under test returning data from the hardware acceleration device 120 to determine the total amount of data to be processed, and then analyze whether the asynchronous thread start condition is met.

[0035] The driving engine module 110 may send a corresponding instruction to the hard acceleration device 120 when determining that the asynchronous thread start condition is met. The hard acceleration device 120 determines the configuration parameters such as read request parameters, valid bit positions and frame header information according to the received instructions. The hard acceleration device 120 then reads the corresponding original captured data from the storage device 200 based on the configuration parameters, filters and splices the read original captured data, obtains the expected high or low bit data results, completes the hard acceleration of the data, generates the processed captured data and sends it to the driving engine module 110. The driving engine module 110 performs soft acceleration processing on the received captured data in an asynchronous thread manner, completes the secondary packaging of the data and uploads it to the host computer for data analysis by the host computer.

[0036] It can be understood that the driving engine module 110 can send instructions to the hard acceleration device 120 to control the hard acceleration device 120 to read all the original captured data that need to be processed from the storage device 200 at one time, and the hard acceleration device 120 hard-accelerates the read original captured data and sends it to the driving engine module 110; the driving engine module 110 can also send instructions to the hard acceleration device 120 to control the hard acceleration device 120 to read the original captured data from the storage device 200 in batches. After receiving a batch of hard-accelerated data uploaded by the hard acceleration device 120 and completing soft acceleration in an asynchronous thread manner, the driving engine module 110 sends instructions to the hard acceleration device 120 to perform hard acceleration and soft acceleration processing on the next batch of original captured data, until all the original captured data that need to be processed in the storage device 200 have completed hard acceleration and soft acceleration processing.

[0037] Similarly, taking the storage device 200 storing the original captured data in rows according to the pins of the device under test as an example, the total amount of data to be processed is the total number of rows of data, and the preset threshold is the preset row number threshold. When the driving engine module 110 determines that the asynchronous thread start condition is met, it sends an instruction to the hard acceleration device 120 in combination with the preset row number threshold, controls the hard acceleration device 120 to read the original captured data of the number of rows corresponding to the preset row number threshold from the storage device 200 for filtering and splicing, and uploads the processed captured data to the driving engine module 110. For example, the driving engine module 110 determines that there are 100 rows of original captured data to be processed based on the test parameters sent by the host computer, and the preset threshold can be set to 10 rows. The driving engine module 110 sends an instruction to the hard acceleration device 120, controls the hard acceleration device 120 to read 10 rows of original captured data from the storage device 200 each time, and sends it to the driving engine module 110 after hard acceleration processing, and divides the original captured data to be processed into 10 batches for hard acceleration and soft acceleration processing in batches, thereby alleviating data processing pressure.

[0038] The specific structure and data hard acceleration method of the hard acceleration device 120 are not unique. In one embodiment, Figure 2 As shown, the hard acceleration device 120 includes a communication module 121, a parameter parsing module 122, a parameter processing module 123, a read-write control module 124, a cache module 125 and a data processing module 126. The communication module 121 is connected to the drive engine module 110, the parameter parsing module 122 and the data processing module 126. The parameter parsing module 122 is connected to the parameter processing module 123 and the data processing module 126. The read-write control module 124 is connected to the parameter processing module 123, the cache module 125 and the storage device 200, specifically connected to the DDR controller 210 in the storage device 200. The cache module 125 is connected to the data processing module 126.

[0039] Among them, the parameter parsing module 122 receives the instructions issued by the driving engine module 110 through the communication module 121, parses the instructions, obtains the configuration parameters and sends them to the parameter processing module 123 and the data processing module 126. The parameter processing module 123 parses the received configuration parameters, obtains the data reading information and sends it to the read-write control module 124; the read-write control module 124 reads the corresponding original captured data from the storage device 200 according to the data reading information, and sends the read original captured data to the cache module 125 for caching. The data processing module 126 reads the corresponding original captured data from the cache module 125 according to the received configuration parameters, performs data filtering and splicing, generates the processed captured data and uploads it to the driving engine module 110 through the communication module 121.

[0040] Specifically, the configuration parameters received by the parameter processing module 123 include read request parameters, and the data read information includes a read request address and a read request length, and the read request length is used to indicate the number of rows of data to be read from the storage device 200. The parameter processing module 123 parses the read request parameters, obtains the read request address and the read request length, and sends them to the read-write control module 124; the read-write control module 124 reads the corresponding original captured data from the storage device 200 according to the read request address and the read request length. Among them, the parameter processing module 123 can be to send a read request instruction, a read request address and a read request length to the read-write control module 124, and after receiving the read request instruction, the read-write control module 124 communicates with the DDR controller 210 according to the read request address and the read request length to perform a data reading operation, and the DDR controller 210 extracts the original captured data of the corresponding row and returns it to the read-write control module 124, and the read-write control module 124 sends the received original captured data to the cache module 125, and the cache module 125 can specifically use a FIFO (first-in, first-out queue), and also caches the original captured data in rows according to the pins.

[0041] Further, the configuration parameters received by the data processing module 126 include valid bit positions and frame header information; the data processing module 126 filters and splices the original captured data read from the cache module 125 according to the valid bit positions to obtain uplink data, and reframes the uplink data according to the frame header information to obtain single-bit captured data and uploads it to the driving engine module 110 through the communication module 121. Among them, the valid bit position represents whether the high bit is valid or the low bit is valid. The data processing module 126 parses and filters the original captured data cached in the cache module 125 according to the received valid bit positions, filters out invalid data, extracts the desired high or low bit data, and re-splices the filtered data to obtain uplink data. The frame header information may include the frame header type, the frame header length, etc. The data processing module 126 reframes the uplink data and the received frame header information to generate single-bit captured data and send it to the communication module 121.

[0042] Continue to refer to Figure 2 The data processing module 126 may include a read control unit 61, a single-bit conversion unit 62 and a single-bit upload unit 63. The read control unit 61 is connected to the cache module 125. The single-bit conversion unit 62 is connected to the cache module 125 and the single-bit upload unit 63. The single-bit upload unit 63 is connected to the communication module 121. The read control unit 61 is used to output a read enable signal to the cache module 125, so that the cache module 125 outputs the original captured data line by line. The single-bit conversion unit 62 receives a line of original captured data output by the cache module 125, and filters and re-joins according to the valid bit position, compresses a line of original captured data into uplink data and sends it to the single-bit upload unit 63; the single-bit upload unit 63 re-frames the received uplink data according to the frame header information, obtains single-bit captured data and outputs it to the communication module 121. Furthermore, the data processing module 126 also includes a single-bit control unit 64, which connects the parameter parsing module 122, the read control unit 61, the single-bit conversion unit 62 and the single-bit upload unit 63; the single-bit control unit 64 controls the read control unit 61 to output a read enable signal, configures the valid bit position for the single-bit conversion unit 62, and configures the frame header information for the single-bit upload unit 63.

[0043] Specifically, the read / write control module 124 sends each line of raw captured data with a fixed number of bits to the cache module 125 for caching. After receiving the configuration parameters sent by the parameter parsing module 122, the single-bit control unit 64 starts single-bit data processing, controls the read control unit 61 to output a read enable signal to the cache module 125, reads a line of raw captured data with a fixed number of bits to the single-bit conversion unit 62, and the single-bit conversion unit 62 accelerates the processing of the read line of raw captured data with a fixed number of bits, filters out invalid data, compresses a line of raw captured data into N bits, retains the pin num indication of M bits, retains the cycle counter indication of Y bits, and splices the data into uplink data of Z bits. The single-bit upload unit 63 reframes the uplink data according to the communication protocol in combination with the frame header information, generates a packet of single-bit captured data, and sends it to the communication module 121.

[0044] After receiving the processed captured data, the driver engine module 110 performs soft acceleration on the captured data. In one embodiment, the driver engine module 110 is loaded with a driver. When the total amount of data to be processed meets the set asynchronous thread start condition, the driver sends instructions to the hard acceleration device 120 through the main thread to control the hard acceleration device 120 to read the corresponding original captured data from the storage device 200 for filtering and splicing. The driver also stores the captured data uploaded by the hard acceleration device 120 in the message queue, and the multiple slave threads of the driver poll the data in the message queue for parallel acceleration processing until the message queue is empty. The driver can assemble the captured data of the same pin according to the pin number flag, and upload the assembled data to the host computer.

[0045] Specifically, the driving engine module 110 uses the asynchronous thread Future mode to perform parallel accelerated processing of data. The core idea of ​​the asynchronous thread Future mode is asynchronous calling. The driving engine module 110 is designed with multiple slave threads that continuously poll to determine whether there is captured data in the message queue, and transfer the captured data to the slave thread when there is captured data in the message queue. The slave thread calls the data processing function to assemble the captured data according to the storage format of the captured data in the storage device 200, and assembles it into the desired data type. The driving engine module 110 uses the main thread to send a read request to read data and uses the slave thread to process data in parallel. The main thread and each slave thread operate synchronously to complete the secondary packaging of the data, which greatly saves time consumption at the software level. When the slave thread has data to be processed in the message queue, the waiting state of the slave thread is awakened to transfer the captured data from the message queue to the slave thread for data assembly until the reading task is completed, the message queue is empty, the data processing is completed, and the asynchronous task is completed. For example, whenever a line of captured data uploaded by the hard acceleration device 120 is stored in the message queue, a slave thread is activated to transfer the captured data in the message queue; if multiple lines of captured data uploaded by the hard acceleration device 120 are stored in the message queue, multiple slave threads are activated, and each slave thread transfers a corresponding line of captured data in the message queue.

[0046] It is understandable that if the total amount of data to be processed does not meet the set asynchronous thread start condition, that is, when the data amount is small, the driver in the driver engine module 110 can also just call a single sub-thread to read the captured data uploaded to the message queue by the hard acceleration device 120.

[0047] The test data processing board combines the soft acceleration and hard acceleration processing methods. In terms of captured data processing, it can easily handle even large amounts of data, and the speed of capturing data acquisition is improved, which is more significant in terms of large amounts of data. The test data processing board has the following advantages:

[0048] 1. By combining software and hardware acceleration processing methods, the efficiency of data processing is significantly improved, which is suitable for application scenarios with any data volume.

[0049] 2. By changing the previous data processing method through soft acceleration, data reading and processing can be carried out synchronously, saving the time efficiency of the test project.

[0050] 3. The processing speed is further improved by replacing the software data picking process with hardware acceleration.

[0051] In one embodiment, Figure 3 As shown, a test data processing method is also provided, including:

[0052] Step S110: The hardware acceleration device confirms the configuration parameters according to the instructions sent by the driving engine module.

[0053] Step S120: the hard acceleration device reads the corresponding original captured data from the storage device according to the configuration parameters, filters and splices the read original captured data, generates processed captured data and sends it to the driving engine module.

[0054] Step S130: When the total amount of data to be processed meets the set asynchronous thread start condition, the driving engine module performs parallel accelerated processing on the received captured data through the asynchronous thread.

[0055] It can be understood that the specific embodiment of the above test data processing method has been explained in detail in the above test data processing board, and will not be repeated here.

[0056] In one embodiment, a test machine is provided, including a host computer and the above-mentioned test data processing board. The host computer can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices, and the portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0057] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A test data processing board, characterized in that: It includes a driving engine module and a hard acceleration device, wherein the hard acceleration device is connected to the driving engine module and the storage device; The hard acceleration device is used to confirm the configuration parameters according to the instructions issued by the driving engine module, read the corresponding original captured data from the storage device according to the configuration parameters, filter and splice the read original captured data, generate processed captured data and send it to the driving engine module; The driving engine module is used to perform parallel accelerated processing on the received captured data through asynchronous threads when the total amount of data to be processed meets the set asynchronous thread start condition.

2. The test data processing board according to claim 1, characterized in that: The hard acceleration device includes a communication module, a parameter parsing module, a parameter processing module, a read-write control module, a cache module and a data processing module, wherein the communication module is connected to the drive engine module, the parameter parsing module and the data processing module, the parameter parsing module is connected to the parameter processing module and the data processing module, the read-write control module is connected to the parameter processing module, the cache module and the storage device, and the cache module is connected to the data processing module; The parameter parsing module receives the instruction sent by the driving engine module through the communication module, parses the instruction, obtains the configuration parameters and sends them to the parameter processing module and the data processing module; The parameter processing module parses the received configuration parameters, obtains data reading information and sends it to the read-write control module; the read-write control module reads the corresponding original captured data from the storage device according to the data reading information, and sends the read original captured data to the cache module for caching; The data processing module reads the corresponding original captured data from the cache module according to the received configuration parameters, performs data filtering and splicing, generates processed captured data, and uploads the processed captured data to the driving engine module through the communication module.

3. The test data processing board according to claim 2, characterized in that: The configuration parameters received by the parameter processing module include read request parameters, and the data reading information includes a read request address and a read request length; the parameter processing module parses the read request parameters, obtains the read request address and the read request length, and sends them to the read-write control module; the read-write control module reads the corresponding original captured data from the storage device according to the read request address and the read request length.

4. The test data processing board according to claim 2, characterized in that: The configuration parameters received by the data processing module include valid bit positions and frame header information; the data processing module filters and splices the original captured data read from the cache module according to the valid bit positions to obtain uplink data, and reframes the uplink data according to the frame header information to obtain single-bit captured data and uploads it to the drive engine module through the communication module.

5. The test data processing board according to claim 4, characterized in that: The data processing module includes a read control unit, a single-bit conversion unit and a single-bit upload unit, the read control unit is connected to the cache module, the single-bit conversion unit is connected to the cache module and the single-bit upload unit, and the single-bit upload unit is connected to the communication module; The read control unit is used to output a read enable signal to the cache module so that the cache module outputs the original captured data line by line. The single-bit conversion unit receives a line of original captured data output by the cache module, filters and re-splices according to the valid bit positions, compresses a line of original captured data into uplink data and sends it to the single-bit upload unit; the single-bit upload unit re-frames the received uplink data according to the frame header information, obtains single-bit captured data and outputs it to the communication module.

6. The test data processing board according to claim 5, characterized in that: The data processing module also includes a single-bit control unit, which is connected to the parameter parsing module, the read control unit, the single-bit conversion unit and the single-bit upload unit; the single-bit control unit controls the read control unit to output a read enable signal, configures a valid bit position for the single-bit conversion unit, and configures frame header information for the single-bit upload unit.

7. The test data processing board according to any one of claims 1 to 6, characterized in that: The driver engine module is loaded with a driver. When the total amount of data to be processed meets the set asynchronous thread start condition, the driver sends instructions to the hard acceleration device through the main thread to control the hard acceleration device to read the corresponding original captured data from the storage device for filtering and splicing processing; the driver also stores the captured data uploaded by the hard acceleration device into a message queue, and multiple slave threads of the driver poll the data in the message queue for parallel acceleration processing until the message queue is empty.

8. The test data processing board according to any one of claims 1 to 6, characterized in that: The driving engine module determines the total amount of data to be processed based on the test parameters sent by the host computer. If the total amount of data to be processed is greater than or equal to a preset threshold, the asynchronous thread start condition is met.

9. The test data processing board according to claim 8, characterized in that: The total amount of data that needs to be processed is the total number of rows of data, and the preset threshold is the preset row number threshold; when the driving engine module determines that the conditions for starting the asynchronous thread are met, it sends an instruction to the hard acceleration device in combination with the preset row number threshold, controls the hard acceleration device to read the original captured data of the number of rows corresponding to the preset row number threshold from the storage device for filtering and splicing, and uploads the processed captured data to the driving engine module.

10. A test data processing method, characterized in that: include: The hard acceleration device confirms the configuration parameters according to the instructions issued by the driving engine module; The hard acceleration device reads the corresponding raw captured data from the storage device according to the configuration parameters, filters and splices the read raw captured data, generates processed captured data and sends it to the driving engine module; When the total amount of data to be processed meets the set asynchronous thread start condition, the driving engine module performs parallel accelerated processing on the received captured data through the asynchronous thread.

11. A testing machine, characterized in that: It comprises a host computer and a test data processing board as described in any one of claims 1 to 9.

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