A computer channel fault monitoring method and apparatus including an instruction-monitoring branch

Abstract

The application provides a computer channel fault monitoring method and device comprising an instruction-monitoring branch, the method comprising: step 1: obtaining a channel fault reset (RESET) signal by comprehensively obtaining a Power ON Reset Pulse (PORP) signal and a Digital Processor Fault Reset (DPFR) signal; and step 2: judging the channel state by means of instruction branch fault judgment, monitoring branch fault judgment, monitoring branch state judgment, remote channel fault judgment, branch-to-branch fault judgment and channel state judgment according to the RESET signal.

Description

Technical Field

[0001] This invention pertains to system redundancy management and fault tolerance technology, specifically relating to a computer channel fault monitoring method and apparatus that includes an instruction-monitoring branch. Background Technology

[0002] Redundancy management strategy is the core of redundancy technology, and its quality plays a decisive role in the reliability and availability of the redundancy system. For redundant computers, in addition to designing relevant redundancy management software to identify, isolate, and report signal faults within the computer, a monitoring system needs to be introduced at the hardware level to detect the status of each channel, locate and isolate faults, and support the switching of control channels and system reconfiguration.

[0003] Current computer channel fault monitoring systems are designed for architectures with only one or two main instruction branches within a single redundant channel. With technological advancements, computer architectures with self-monitoring capabilities have emerged, where a channel includes both instruction and monitoring branches, improving computer reliability through self-monitoring. However, the increased complexity of these structures necessitates consideration of more factors when designing channel fault monitoring strategies, rendering existing methods inapplicable. Summary of the Invention

[0004] This invention proposes a computer channel fault monitoring method and apparatus that includes an instruction-monitoring branch, which can solve the problem of monitoring computer channel faults with complex architectures that include instruction-monitoring branches.

[0005] In a first aspect, this application provides a computer channel fault monitoring method including an instruction-monitoring branch, the method comprising:

[0006] Step 1: Based on the Power On Reset Pulse (PORP) signal and the Digital Processor Fault Reset (DPFR) signal, the channel fault reset (RESET) signal is obtained.

[0007] Step 2: Based on the RESET signal, the channel status is determined through command branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment, and channel status judgment.

[0008] Furthermore, step 1 includes:

[0009] Step 11: Acquire PORP signal and DPFR signal;

[0010] Step 12: Determine the signal status of the PORP and DPFR signals; the PORP signal is valid upon power-on; the DPFR signal is valid if fault recovery is required.

[0011] Step 13: If the PORP signal is valid, or the DPFR signal is valid, then the output RESET signal is valid.

[0012] Furthermore, step 2 includes:

[0013] Step 21: Determine the status of the Local Channel Valid_Command (LCV_CMD) signal based on the relevant flags representing the health status of the command branch of this channel;

[0014] Step 22: Determine the status of the monitoring branch valid (Local Channel Valid_Monitor, LCV_MON) signal based on the relevant indicators representing the health status of the monitoring branch;

[0015] Step 23: Determine the status of the Digital Processor Valid_Monitor (DPV_MON) signal based on the LCV_MON and RESET signals;

[0016] Step 24: Based on the remote channel's cognitive information regarding whether this channel is operating correctly and the PORP signal, determine the status of the Local Channel Valid Remote (LCHVR) signal;

[0017] Step 25: Determine the status of the command channel self-monitoring (In Line Monitor, ILM) signal based on the command branch self-monitoring (In Line Monitor_Command, ILM_COM) signal, WDV_CMD signal, PSV signal, RESET signal, and DPV_MON signal;

[0018] Step 26: Determine the status of the Channel Valid (CHV) signal based on the LCV_CMD signal, LCHVR signal, RESET signal, ILM signal, and other channel command branch digital processor valid (Digital Processor Valid_Command_From…, DPV_CMD_FX / Y / …) signals.

[0019] Furthermore, step 21 includes:

[0020] Step 211: Collect the health status flags of the command branch, including command branch CPU active (CPUV_CMD), command branch watchdog active (WDV_CMD), and channel power active (PSV).

[0021] Step 212: Determine the status of the CPUV_CMD signal, WDV_CMD signal, and PSV signal; if the instruction branch software is running correctly, the CPUV_CMD signal is valid; if the instruction branch software is running normally, the WDV_CMD signal is valid; if the computer power supply is normal, the PSV signal is valid.

[0022] Step 213: When the CPUV_CMD signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output LCV_CMD signal is valid.

[0023] Furthermore, step 22 includes:

[0024] Step 221: Collect health status flag signals of the monitoring branch, including monitoring branch CPU active (CPUV_MON), monitoring branch watchdog active (WDV_MON), and channel power active (PSV).

[0025] Step 222: Determine the status of the CPUV_MON signal, WDV_MON signal, and PSV signal; if the monitoring branch software is running correctly, the CPUV_MON signal is valid; if the monitoring branch software is running normally, the WDV_MON signal is valid; if the computer power supply is normal, the PSV signal is valid.

[0026] Step 223: When the CPUV_MON signal is valid, the WDV_MON signal is valid, and the PSV signal is valid, the output LCV_MON signal is valid.

[0027] Furthermore, step 23 includes:

[0028] Step 231: If the LCV_MON signal is valid, then the DPV_MON signal is output as valid; if the LCV_MON signal is invalid and the duration exceeds the set fault delay, then the DPV_MON signal is latched as invalid.

[0029] Step 232: If the RESET signal is valid, then release the latch of the DPV_MON signal.

[0030] Furthermore, step 24 includes:

[0031] Step 241: Collect information on whether the remote channel is operating correctly, including digital processor judgments from other channels (Digital Processor From_X / Y…, DP_FX / Y…);

[0032] Step 242: Determine the status of the DP_FX / Y / … signals. If other channels consider this channel to be in good condition, then the DP_FX / Y… signals from this channel are valid.

[0033] Step 243: If any DP_FX / Y / ... signal is valid, then the output LCHVR signal is valid;

[0034] Step 244: If the PORP signal is valid, then the output LCHVR signal is valid.

[0035] Furthermore, step 25 includes:

[0036] Step 251, acquire the ILM_COM signal;

[0037] Step 252: Determine the signal status of the ILM_COM signal by comparing the instruction calculated by the instruction branch CPU with the instruction calculated by the monitoring branch CPU. Use a mature dual-redundancy comparison monitoring algorithm. If there is no fault, the ILM_COM signal is valid.

[0038] Step 253: If the ILM_COM signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output branch integrated valid (In Line Monitor_Monitor, ILM_MON) signal is valid.

[0039] Step 254: If the ILM_MON signal is invalid and the duration exceeds the set delay, then latch the ILM_MON signal as invalid.

[0040] Step 255: If the RESET signal is valid, then release the latch of the ILM_MON signal;

[0041] Step 256: If the DPV_MON signal is valid and the ILM_MON signal is valid, then the output ILM signal is valid.

[0042] Furthermore, step 26 includes:

[0043] Step 261: If the LCV_CMD signal is valid and the LCHVR signal is valid, then the output DPV_CMD signal is valid; otherwise, it is invalid.

[0044] Step 262: If the DPV_CMD signal is invalid and the duration exceeds the set delay, then the DPV_CMD signal is latched as invalid.

[0045] Step 263: If the RESET signal is valid, then release the latch of the DPV_CMD signal;

[0046] Step 264: Acquire DPV_CMD_FX / Y / … signals from other channels.

[0047] Step 265: Determine the status of the DPV_CMD_FX / Y / … signal. If the status of other channels is valid, then the DPV_CMD_FX / Y… signal from this channel is valid.

[0048] Step 266: If at least one of the DPV_CMD signal and the DPV_CMD_FX / Y / … signal is valid, then the DPV_CMD signal of this channel is used to determine the validity. If the DPV_CMD signal is valid, then the output CHV signal is valid. If the DPV_CMD signal is invalid, then the output CHV signal is invalid.

[0049] Step 267: If all signals in DPV_CMD and DPV_CMD_FX / Y / … are invalid or only one signal is valid, then the ILM signal is used to determine the validity. If the ILM signal is valid, the output CHV signal is valid; if the ILM signal is invalid, the output CHV signal is invalid.

[0050] Secondly, this application provides a computer channel fault monitoring device including an instruction-monitoring branch, a channel fault reset unit, and a channel status judgment unit, wherein:

[0051] The channel fault reset unit is used to synthesize the channel fault reset (RESET) signal based on the power-on reset pulse (PORP) signal and the digital processor fault reset (DPFR) signal.

[0052] The channel status judgment unit is used to judge the channel status based on the RESET signal by judging the fault of the command branch, the fault of the monitoring branch, the status of the monitoring branch, the fault of the remote channel, the fault between branches, and the channel status.

[0053] In summary, this invention proposes a computer channel fault monitoring method and device including an instruction-monitoring branch, the beneficial effects of which are:

[0054] 1. When monitoring channel faults, the impact between redundancy channels was comprehensively considered, and a reasonable comprehensive strategy was designed.

[0055] 2. Taking into account the impact between different branches within the redundancy channel, the computer architecture of the self-monitoring system is adapted to support subsequent fault isolation, handling, and reporting, thereby improving system reliability.

[0056] 3. The restoration and establishment of channel monitoring under different scenarios such as reset and startup have been comprehensively considered;

[0057] 4. Through modular and universal strategy design, it supports the configuration of applicable channel fault monitoring methods based on different redundancy level architectures, thereby improving the flexibility and usability of the method. Attached Figure Description

[0058] Figure 1 A schematic diagram illustrating the functional composition of a redundancy computer channel fault monitoring method that includes instruction-monitoring branches;

[0059] Figure 2 This is a schematic diagram of channel fault reset;

[0060] Figure 3 This is a schematic diagram for fault diagnosis of the instruction branch;

[0061] Figure 4 A schematic diagram for fault diagnosis of monitoring branch circuits;

[0062] Figure 5 A schematic diagram for judging the status of monitored branches;

[0063] Figure 6 This is a schematic diagram for remote channel fault diagnosis.

[0064] Figure 7 This is a schematic diagram for fault diagnosis between branches;

[0065] Figure 8 This is a schematic diagram for determining the channel status. Detailed Implementation

[0066] like Figure 1 As shown, this invention proposes a computer channel fault monitoring method including an instruction-monitoring branch, comprising:

[0067] Step 1: Based on the Power On Reset Pulse (PORP) signal and the Digital Processor Fault Reset (DPFR) signal, obtain the channel fault reset (RESET) signal.

[0068] Furthermore, such as Figure 2As shown, step 1 includes:

[0069] Step 11: Acquire PORP signal and DPFR signal;

[0070] Step 12: Determine the signal status of the PORP and DPFR signals; the PORP signal is valid upon power-on; the DPFR signal is valid if fault recovery is required.

[0071] Step 13: If the PORP signal is valid, or the DPFR signal is valid, then the output RESET signal is valid.

[0072] Step 2: Based on the RESET signal, the channel status is determined through command branch fault judgment, monitoring branch fault judgment, monitoring branch status judgment, remote channel fault judgment, inter-branch fault judgment, and channel status judgment.

[0073] Furthermore, step 2 includes:

[0074] Step 21: Determine the status of the Local Channel Valid_Command (LCV_CMD) signal based on the relevant flags representing the health status of the command branch of this channel;

[0075] Specifically, such as Figure 3 As shown, step 21 includes:

[0076] Step 211: Collect the health status flags of the command branch, including command branch CPU active (CPUV_CMD), command branch watchdog active (WDV_CMD), and channel power active (PSV).

[0077] Step 212: Determine the status of the CPUV_CMD signal, WDV_CMD signal, and PSV signal; if the instruction branch software is running correctly, the CPUV_CMD signal is valid; if the instruction branch software is running normally, the WDV_CMD signal is valid; if the computer power supply is normal, the PSV signal is valid.

[0078] Step 213: When the CPUV_CMD signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output LCV_CMD signal is valid.

[0079] Step 22: Determine the status of the monitoring branch valid (Local Channel Valid_Monitor, LCV_MON) signal based on the relevant indicators representing the health status of the monitoring branch;

[0080] Specifically, such as Figure 4 As shown, step 22 includes:

[0081] Step 221: Collect health status flag signals of the monitoring branch, including monitoring branch CPU active (CPUV_MON), monitoring branch watchdog active (WDV_MON), and channel power active (PSV).

[0082] Step 222: Determine the status of the CPUV_MON, WDV_MON, and PSV signals; if the monitoring branch software is running correctly, the CPUV_MON signal is valid; if the monitoring branch software is running normally, the WDV_MON signal is valid; if the computer power supply is normal, the PSV signal is valid.

[0083] Step 223: When the CPUV_MON signal is valid, the WDV_MON signal is valid, and the PSV signal is valid, the output LCV_MON signal is valid.

[0084] Step 23: Determine the status of the Digital Processor Valid_Monitor (DPV_MON) signal based on the LCV_MON and RESET signals.

[0085] Specifically, such as Figure 5 As shown, step 23 includes:

[0086] Step 231: If the LCV_MON signal is valid, then the DPV_MON signal is output as valid; if the LCV_MON signal is invalid and the duration exceeds the set fault delay, then the DPV_MON signal is latched as invalid.

[0087] Step 232: If the RESET signal is valid, then release the latch of the DPV_MON signal.

[0088] Step 24: Based on the remote channel's cognitive information on whether this channel is operating correctly and the PORP signal, determine the status of the Local Channel Valid Remote (LCHVR) signal.

[0089] Specifically, such as Figure 6 As shown, step 24 includes:

[0090] Step 241: Collect information from the remote channel regarding whether this channel is operating correctly, including digital processor judgments from other channels (Digital Processor From X / Y…, DP_FX / Y…);

[0091] If the instruction from another channel is judged as "Digital Processor From X", it indicates that the CPU of channel X is judging the status of this channel.

[0092] It should be noted that the method provided in this application is applied to a redundancy computer. The redundancy computer includes multiple channels, and the number of signals from other channels that instruct the digital machine to determine the redundancy number is related to the redundancy number. Specifically, the number should be the current redundancy number minus 1.

[0093] Step 242: Determine the status of the DP_FX / Y / … signals. If other channels consider this channel to be in good condition, then the DP_FX / Y… signals from this channel are valid.

[0094] Step 243: If any DP_FX / Y / ... signal is valid, then the output LCHVR signal is valid;

[0095] Step 244: If the PORP signal is valid, then the output LCHVR signal is valid.

[0096] Step 25: Determine the status of the command channel self-monitor (In Line Monitor, ILM) signal based on the command branch self-monitor (In Line Monitor_Command, ILM_COM) signal, WDV_CMD signal, PSV signal, RESET signal, and DPV_MON signal.

[0097] It should be noted that the aforementioned inter-branch fault synthesis mainly considers the impact of monitoring on the command branch and the monitoring branch in an architecture with self-monitoring pairs, and leverages the monitoring role of the monitoring branch on the command branch.

[0098] Specifically, such as Figure 7 As shown, step 25 includes:

[0099] Step 251, acquire the ILM_COM signal;

[0100] Step 252: Determine the signal status of the ILM_COM signal by comparing the instruction calculated by the instruction branch CPU with the instruction calculated by the monitoring branch CPU. Use a mature dual-redundancy comparison monitoring algorithm. If there is no fault, the ILM_COM signal is valid.

[0101] Step 253: If the ILM_COM signal is valid, the WDV_CMD signal is valid, and the PSV signal is valid, then the output branch integrated valid (In Line Monitor_Monitor, ILM_MON) signal is valid.

[0102] Step 254: If the ILM_MON signal is invalid and the duration exceeds the set delay, then latch the ILM_MON signal as invalid.

[0103] Step 255: If the RESET signal is valid, then release the latch of the ILM_MON signal;

[0104] Step 256: If the DPV_MON signal is valid and the ILM_MON signal is valid, then the output ILM signal is valid.

[0105] Step 26: Determine the status of the Channel Valid (CHV) signal based on the LCV_CMD signal, LCHVR signal, RESET signal, ILM signal, and other channel command branch digital machine valid (Digital ProcessorValid_Command_FromX / Y…, DPV_CMD_FX / Y / …) signals.

[0106] If other channel command branch digital machine valid is Digital Processor Valid_Command_From X, it means that channel X sent its digital machine status to this channel.

[0107] It should be noted that the method provided in this application is applied to a redundant computer. A redundant computer includes multiple channels, and the number of valid signals of the instruction digital machine in other channels is related to the redundancy number, specifically the current redundancy number minus 1.

[0108] Specifically, such as Figure 8 As shown, step 26 includes:

[0109] Step 261: If the LCV_CMD signal is valid and the LCHVR signal is valid, then the output DPV_CMD signal is valid; otherwise, it is invalid.

[0110] Step 262: If the DPV_CMD signal is invalid and the duration exceeds the set delay, then the DPV_CMD signal is latched as invalid.

[0111] Step 263: If the RESET signal is valid, then release the latch of the DPV_CMD signal;

[0112] Step 264: Acquire DPV_CMD_FX / Y / … signals from other channels.

[0113] Step 265: Determine the status of the DPV_CMD_FX / Y / … signal. If the status of other channels is valid, then the DPV_CMD_FX / Y… signal from this channel is valid.

[0114] Step 266: If at least one of the DPV_CMD signal and the DPV_CMD_FX / Y / … signal is valid, then the DPV_CMD signal of this channel is used to determine the validity. If the DPV_CMD signal is valid, then the output CHV signal is valid. If the DPV_CMD signal is invalid, then the output CHV signal is invalid.

[0115] Step 267: If all signals in DPV_CMD and DPV_CMD_FX / Y / … are invalid or only one signal is valid, then the ILM signal is used to determine the validity. If the ILM signal is valid, the output CHV signal is valid; if the ILM signal is invalid, the output CHV signal is invalid.

[0116] In summary, this invention proposes a computer channel fault monitoring method and apparatus including command-monitoring branches. For redundant computers with command-monitoring branches, it comprehensively considers the mutual influence between redundant channels and between command and monitoring branches based on the status information provided by each redundant channel and branch, thereby identifying computer channel faults and outputting channel status flags to support control channel switching and system reconfiguration. This aims to minimize the impact of channel faults on computer performance and improve system reliability.

[0117] Example 1

[0118] Taking the channel fault monitoring of a certain type of aircraft flight control computer as an example, this flight control computer has a quadruple redundancy architecture, including four redundancy channels: A, B, C, and D. Each redundancy channel is configured with a command branch and a monitoring branch. At this time, the CPU, watchdog, and power supply of the command branch of channel A are all valid. The CPU and watchdog of the monitoring branch are also valid. The power-on reset pulse signal and the digital machine fault reset signal are invalid. The digital machine judgment from channel B, channel C, and channel D are all valid. The self-monitoring of the command branch of channel A is valid. The digital machine judgment of channel B, channel C, and channel D is invalid. The channel fault monitoring method for channel A is as follows:

[0119] 1. If the "Power-on Reset Pulse Signal" is "Invalid" and the "Digital Machine Fault Reset" signal is "Invalid", then the "Channel Fault Reset" signal is invalid.

[0120] 2. If the "Instruction Branch CPU Valid" signal is "Valid", the "Instruction Branch Watchdog Monitoring Valid" signal is "Valid", and the "Channel Power Valid" signal is "Valid", then the "Instruction Branch Valid" signal is "Valid".

[0121] 3. If the "Monitoring Branch CPU Valid" signal is "Valid", the "Monitoring Branch Watchdog Monitoring Valid" signal is "Valid", and the "Channel Power Valid" signal is "Valid", then set the "Monitoring Branch Valid" signal to "Valid".

[0122] 4. If the "Monitoring Branch Valid" signal is "Valid", then the "Monitoring Branch Digital Unit Valid" signal will be "Valid".

[0123] 5. Since the "Digital machine judgment from channels B, C, and D" is "valid", the "Remote channel integrated valid" signal is "valid".

[0124] 6. The “Command Branch Self-Monitoring” signal is “Valid”, the “Command Branch Watchdog Valid” signal is “Valid”, and the “Channel Power Supply Valid” signal is “Valid”. Therefore, the “Branch Integration Valid” signal is “Valid”.

[0125] 7. The "Command Branch Valid" signal is "Valid" and the "Other Channels Integrated Valid" signal is "Valid", therefore the "Command Branch Digital Unit Valid" signal for channel A is "Valid";

[0126] 8. The "Command Branch Digital Machine Valid" signals of the four redundancy channels A, B, C, and D are all "Valid". Based on the "Command Branch Digital Machine Valid" signal of channel A, the current state of channel A is normal, that is, the "Channel Valid" signal is "Valid".

[0127] Example 2

[0128] Taking the channel fault monitoring of a certain type of aircraft servo control computer as an example, this servo control computer has a triple-redundant architecture, including three redundant channels: A, B, and C. Each redundant channel is configured with a command branch and a monitoring branch. At this time, the CPU of the command branch of servo control computer A is valid, the watchdog timer of the command branch is valid, and the power supply is valid; the CPUV of the monitoring branch is valid, the watchdog timer of the monitoring branch is valid, the power-on reset pulse signal is invalid, the digital machine fault reset signal is invalid, the digital machine judgment from the command branch of B is invalid, the digital machine judgment from the command branch of C is invalid, the self-monitoring of the command branch of A is valid, the digital machine judgment of the command branch of B is invalid, and the digital machine judgment of the command branch of C is invalid. The channel fault monitoring method for channel A is as follows:

[0129] 1. If the "Power-on Reset Pulse" signal is "Invalid" and the "Digital Machine Fault Recovery" signal is "Invalid", then the "Channel Fault Reset" signal is invalid.

[0130] 2. If the "Instruction Branch CPU Valid" signal is "Valid", the "Instruction Branch Watchdog Monitoring Valid" signal is "Valid", and the "Channel Power Valid" signal is "Valid", then the "Instruction Branch Valid" signal is "Valid".

[0131] 3. If the "Monitoring Branch CPU Valid" signal is "Valid", the "Monitoring Branch Watchdog Monitoring Valid" signal is "Valid", and the "Channel Power Valid" signal is "Valid", then set the "Monitoring Branch Valid" signal to "Valid".

[0132] 4. If the "Monitoring Branch Valid" signal is "Valid", then the "Monitoring Branch Digital Unit Valid" signal will be "Valid".

[0133] 5. Since the "Instruction from B, C, and D channels is judged by the digital machine" is "invalid", the "Remote channel integrated valid" signal is "invalid".

[0134] 6. The “Command Branch Self-Monitoring” signal is “Valid”, the “Command Branch Watchdog Valid” signal is “Valid”, and the “Channel Power Supply Valid” signal is “Valid”. Therefore, the “Branch Integration Valid” signal is “Valid”.

[0135] 7. The "Command Branch Valid" signal is "Valid", and the "Other Channels Integrated Valid" signal is "Invalid". Therefore, the "Command Branch Digital Unit Valid" signal for channel A is "Invalid".

[0136] 8. The "Command Tributary Digital Machine Valid" signal for channel A is "Invalid". The "Command Tributary Digital Machine Valid" signals for both redundant channels B and C are "Invalid". It is necessary to judge based on the "Tributary Integration Valid" signal. At this time, the "Tributary Integration Valid" signal is "Valid". Therefore, the current status of channel A is normal, that is, the "Channel Valid" signal is "Valid".

Claims

1. A computer channel fault monitoring method comprising an instruction-monitoring leg, characterized by, The method comprises: Step 1: obtaining a channel fault reset (RESET) signal according to a power on reset pulse (PORP) signal and a digital processor fault reset (DPFR) signal; Step 2: judging the channel state according to the RESET signal by means of command branch fault judgment, monitoring branch fault judgment, monitoring branch state judgment, remote channel fault judgment, branch-to-branch fault judgment and channel state judgment; Step 1 comprises: Step 11: collecting the PORP signal and the DPFR signal; Step 12: judging the signal state of the PORP signal and the DPFR signal; the PORP signal is valid at power on; if fault recovery is needed, the DPFR signal is valid; Step 13: if the PORP signal is valid or the DPFR signal is valid, the output RESET signal is valid; Step 2 comprises: Step 21: judging the state of a local channel valid command (LCV_CMD) signal according to related marks representing the health state of a command branch of the channel; Step 22: judging the state of a local channel valid monitor (LCV_MON) signal according to related marks representing the health state of a monitoring branch of the channel; Step 23: judging the state of a digital processor valid monitor (DPV_MON) signal of the monitoring branch according to the LCV_MON signal and the RESET signal; Step 24: judging the state of a local channel valid remote (LCHVR) signal according to the cognition information of the remote channel on whether the channel is running correctly, the PORP signal and the RESET signal; Step 25: judging the state of an in line monitor (ILM) signal of the command channel according to an in line monitor command (ILM_COM) signal, a watchdog valid command (WDV_CMD) signal, a channel power supply valid (PSV) signal, the RESET signal and the DPV_MON signal; Step 26: judging the state of a channel valid (CHV) signal according to the LCV_CMD signal, the LCHVR signal, the RESET signal, the ILM signal and other channel command branch digital processor valid (Digital Processor Valid Command From X / Y / …, DPV_CMD_FX / Y / …) signals.

2. The computer channel failure monitoring method of claim 1, wherein, Step 21 comprises: Step 211, collect instruction branch health status flags, including instruction branch CPU valid (CPUV_CMD), instruction branch watchdog valid (WDV_CMD) and channel power supply valid (PSV); Step 212, judge the states of CPUV_CMD signal, WDV_CMD signal and PSV signal; if the instruction branch software runs correctly, the CPUV_CMD signal is valid; if the instruction branch software runs normally, the WDV_CMD signal is valid; if the computer power supply is normal, the PSV signal is valid; Step 213, when the CPUV_CMD signal is valid, the WDV_CMD signal is valid and the PSV signal is valid, the output LCV_CMD signal is valid.

3. The computer channel failure monitoring method of claim 1, wherein, Step 22 includes: Step 221, collect monitoring branch health status flag signals, including monitoring branch CPU valid (CPUV_MON), monitoring branch watchdog valid (WDV_MON) and channel power supply valid (PSV); Step 222, judge the states of CPUV_MON signal, WDV_MON signal and PSV signal; if the monitoring branch software runs correctly, the CPUV_MON signal is valid; if the monitoring branch software runs normally, the WDV_MON signal is valid; if the computer power supply is normal, the PSV signal is valid; Step 223, when the CPUV_MON signal is valid, the WDV_MON signal is valid and the PSV signal is valid, the output LCV_MON signal is valid.

4. The computer channel failure monitoring method of claim 1, wherein, Step 23 includes: Step 231, if the LCV_MON signal is valid, the output DPV_MON signal is valid; if the LCV_MON signal is invalid and the duration exceeds the set fault delay, the DPV_MON signal is latched as invalid; Step 232, if the RESET signal is valid, the latch of the DPV_MON signal is released.

5. The computer channel failure monitoring method of claim 1, wherein, Step 24 includes: Step 241, collect the cognition information of whether the remote channel correctly runs the current channel, including the judgment of digital processor from other channels (Digital Processor From…, DP_FX / Y…); Step 242, judge the state of DP / FX / Y / … signal, if other channels think that the current channel is in good condition, the DP / F… signal from the channel is valid; Step 243, if any one of DP_FX / Y / … signal is valid, the output LCHVR signal is valid; Step 244, if the PORP signal is valid, the output LCHVR signal is valid.

6. The computer channel failure monitoring method of claim 1, wherein, Step 25 includes: Step 251, collect ILM_COM signal; Step 252, judge the signal state of ILM_COM signal, compare the instructions calculated by the instruction branch CPU with the instructions calculated by the monitoring branch CPU, use mature two-redundancy comparison monitoring algorithm, if there is no fault, the ILM_COM signal is valid; Step 253, if the ILM_COM signal is valid and the WDV_CMD signal is valid and the PSV signal is valid, then the output In Line Monitor_Monitor (ILM_MON) signal is valid; Step 254, if the ILM_MON signal is invalid and the duration exceeds a set delay, then the ILM_MON signal is latched as invalid; Step 255, if the RESET signal is valid, then the latch of the ILM_MON signal is released; Step 256, if the DPV_MON signal is valid and the ILM_MON signal is valid, then the output ILM signal is valid.

7. The computer channel failure monitoring method of claim 1, wherein, Step 26 includes: Step 261, if the LCV_CMD signal is valid and the LCHVR signal is valid, then the output DPV_CMD signal is valid, otherwise it is invalid; Step 262, if the DPV_CMD signal is invalid and the duration exceeds a set delay, then the DPV_CMD signal is latched as invalid; Step 263, if the RESET signal is valid, then the latch of the DPV_CMD signal is released; Step 264, collect the DPV_CMD_FX / Y / … signals from other channels Step 265, determine the state of the DPV_CMD_FX / Y / … signals, if the state of other channels is valid, then the DPV_CMD_FX / Y / … from this channel is valid; Step 266, if there are no less than one DPV_CMD signal and DPV_CMD_FX / Y / … signal valid, then determine according to the DPV_CMD signal of this channel; if the DPV_CMD signal is valid, then the output CHV signal is valid; if the DPV_CMD signal is invalid, then the output CHV signal is invalid; Step 267, if all signals in DPV_CMD and DPV_CMD_FX / Y / … are invalid or only one signal is valid, then determine according to the ILM signal; if the ILM signal is valid, then the output CHV signal is valid; if the ILM signal is invalid, then the output CHV signal is invalid.

8. A computer channel fault monitoring device comprising an instruction-monitoring leg, characterized in that, Channel fault reset unit and channel state determination unit, wherein: The channel fault reset unit is configured to obtain a channel fault reset (RESET) signal by synthesizing a Power ON Reset Pulse (PORP) signal and a Digital Processor Fault Reset (DPFR) signal according to the PORP signal and the DPFR signal; specifically, the channel fault reset unit is configured to collect the PORP signal and the DPFR signal, determine the signal state of the PORP signal and the DPFR signal, and output the RESET signal; when power is turned on, the PORP signal is valid; if fault recovery is needed, the DPFR signal is valid; if the PORP signal is valid or the DPFR signal is valid, the output RESET signal is valid. The channel state judging unit is used for judging the channel state according to the RESET signal through the instruction branch fault judging, the monitoring branch fault judging, the monitoring branch state judging, the remote channel fault judging, the branch-to-branch fault judging and the channel state judging. Specifically, the channel state judging unit is used for judging the state of the instruction branch valid (Local Channel Valid_Command, LCV_CMD) signal according to the related marks representing the health state of the instruction branch of the channel; judging the state of the monitoring branch valid (Local Channel Valid_Monitor, LCV_MON) signal according to the related marks representing the health state of the monitoring branch of the channel; judging the state of the monitoring branch digital processor valid (Digital Processor Valid_Monitor, DPV_MON) signal according to the LCV_MON signal and the RESET signal; judging the state of the remote channel comprehensive valid (Local Channel Valid Remote, LCHVR) signal according to the cognition information of the remote channel to the correct operation of the channel, the PORP signal; judging the state of the instruction channel in line monitor (In Line Monitor, ILM) signal according to the instruction branch in line monitor (In Line Monitor_Command, ILM_COM) signal, the instruction branch watchdog valid (WDV_CMD), the channel power supply valid (PSV), the RESET signal and the DPV_MON signal; and judging the state of the channel valid (Channel Valid, CHV) signal according to the LCV_CMD signal, the LCHVR signal, the RESET signal, the ILM signal and the digital processor valid command from X / Y / … (Digital Processor Valid_Command_From X / Y / …, DPV_CMD_FX / Y / …) signal.

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