An emulation testing method, system, device and storage medium

Abstract

Embodiments of the present application provide a simulation test method, system, device and storage medium, wherein the simulation test method comprises: obtaining a simulation test tool on a bus simulation development software; the simulation test tool contains a test message to be sent, the bus simulation development software is in communication connection with a measured controller through a board, and the board contains a first processor core and a second processor core; the simulation test tool is sent to the first processor core; the first processor core is used for calling the second processor core according to the simulation test tool, and the second processor core is used for sending the test message in the simulation test tool to the measured controller; a response message returned by the measured controller in response to the test message is received; and the test message and the response message are taken as simulation test data and displayed. The method can ensure the real-time performance of simulation test, improve the simulation test efficiency and effectiveness.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicle testing, in particular to a simulation test method and system, an electronic device and a storage medium. BACKGROUND

[0002] A vehicle bus simulation test system is a tool specially used for the development, testing and verification of automotive electronic systems. It can simulate the communication and behavior between electronic control units (ECU) inside the vehicle, monitor CAN, LIN, FlexRay and other bus data in real time, and ensure the stability and reliability of vehicle communication. Through virtual simulation technology, various driving scenarios and fault conditions are simulated to verify the performance of the vehicle control system.

[0003] However, in the related art, the vehicle bus simulation test system is usually developed using C language or C++ language, which requires too high a coding ability for the test personnel. At the same time, the system software or test script does not fully consider the real-time requirements of the test, and cannot ensure the real-time performance of the test when controlling the hardware, which may lead to inaccurate or delayed simulation results, affecting the efficiency and effectiveness of the test.

[0004] Therefore, how to complete the vehicle bus simulation test in real time and efficiently has become a problem to be solved. SUMMARY

[0005] The embodiments of the present application provide a simulation test method to solve the problem of reduced test efficiency and effectiveness caused by the inability to ensure test real-time performance in the vehicle bus simulation test in the prior art.

[0006] Correspondingly, the embodiments of the present application also provide a simulation test system, an electronic device and a storage medium to ensure the implementation and application of the above method.

[0007] To solve the above problem, the embodiments of the present application disclose a simulation test method, the method comprising:

[0008] Obtaining a simulation test tool on a bus simulation development software; the simulation test tool contains a test message to be sent, and the bus simulation development software is connected to a controller under test through a board card, which contains a first processor core and a second processor core;

[0009] Sending the simulation test tool to the first processor core; the first processor core is used to call the second processor core according to the simulation test tool, and the second processor core is used to send the test message in the simulation test tool to the controller under test;

[0010] Receiving a response message returned by the controller under test in response to the test message.

[0011] The test packet and the response packet are taken as simulation test data and displayed.

[0012] Optionally, after the simulation test tool is sent to the first processor core, the method further comprises:

[0013] The first processor core is configured to obtain the test packet by running the simulation test tool.

[0014] Optionally, after the simulation test tool is sent to the first processor core, the method further comprises:

[0015] A first signal database on the bus simulation development software is obtained, and first data in the first signal database comprises a packet structure and a signal name of the test packet;

[0016] The first data is synchronized to a second signal database of the first processor core to obtain corresponding second data;

[0017] The first processor core is controlled to run the simulation test tool, and the test packet is parsed according to the second data.

[0018] Optionally, after the simulation test tool is sent to the first processor core, the method further comprises:

[0019] A first signal database on the bus simulation development software is obtained, and first data in the first signal database comprises a packet structure and a signal name of the test packet;

[0020] A sending period of the test packet is defined in the first signal database; the sending period is configured to control a frequency of calling the second processor core by the first processor core;

[0021] The first data and the sending period are synchronized to a third signal database of the first processor core to obtain third data;

[0022] The first processor core is controlled to run the simulation test tool, and the test packet is parsed according to the third data.

[0023] Optionally, the simulation test method further comprises:

[0024] The first processor core is controlled to generate a control command for calling the second processor core according to the simulation test tool;

[0025] After the second processor core receives the control command and the test packet sent by the first processor core, the test packet is sent to the controller under test through a programmable logic device on a board card in response to the control command; the programmable logic device is configured to add a time stamp to the test packet when the test packet is sent.

[0026] Optionally, the test packet and the response packet are displayed as simulation test data.

[0027] The test packet and the response packet are directly displayed.

[0028] Or, according to the packet structure and the signal name saved in the first signal database, the test packet and the response packet are parsed to generate parsed data.

[0029] The parsed data is displayed.

[0030] Optionally, the simulation test method further comprises:

[0031] The time service request of the first processor core is received.

[0032] In the case of a single board card, the clock is sent to the board card in response to the time service request.

[0033] In the case of multiple board cards, one of the board cards is selected as a master node board card, and the board cards other than the master node board card are selected as slave node board cards, and the clock is sent to the master node board card in response to the time service request; the master node board card is used to synchronize the clock to the slave node board cards.

[0034] The embodiment of the application further discloses a simulation test system, and the system comprises:

[0035] The simulation test tool acquisition module is configured to acquire a simulation test tool on a bus simulation development software; the simulation test tool contains a test packet to be sent; the bus simulation development software is in communication connection with a controller under test through a board card; the board card contains a first processor core and a second processor core.

[0036] The sending module is configured to send the simulation test tool to the first processor core; the first processor core is configured to call the second processor core according to the simulation test tool; and the second processor core is configured to send the test packet in the simulation test tool to the controller under test.

[0037] The receiving module is configured to receive a response packet returned by the controller under test in response to the test packet.

[0038] The display module is configured to display the test packet and the response packet as simulation test data.

[0039] The embodiment of the application further discloses an electronic device, which comprises a processor and a memory having executable codes stored thereon, wherein the executable codes, when executed, cause the processor to perform the simulation test method according to one or more of the embodiments of the application.

[0040] The embodiment of the application further discloses a computer readable storage medium, characterized in that a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to realize one or more simulation test methods in the embodiment of the application.

[0041] Compared with the prior art, the embodiment of the application has the following advantages:

[0042] In the embodiment of the application, a simulation test tool on bus simulation development software is acquired, the simulation test tool contains a test message to be sent, the bus simulation development software is in communication connection with a measured controller through a board, and the board contains a first processor core and a second processor core. The simulation test tool is sent to the first processor core, the first processor core is used to call the second processor core to send the test message in the simulation test tool to the measured controller according to the simulation test tool, the hardware control command can be directly called, the real-time performance of the simulation test process is ensured, and the test efficiency is improved. The response message returned by the measured controller in response to the test message is received, the test message and the response message are taken as simulation test data and are displayed, and the simulation test data of the controller can be accurately and efficiently obtained. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0044] Figure 1 is a logical architecture schematic diagram of a simulation test system embodiment of the application;

[0045] Figure 2 is a technical architecture schematic diagram of a simulation test system embodiment of the application;

[0046] Figure 3 is a step flowchart of a simulation test method embodiment of the application;

[0047] Figure 4 is a structural block diagram of a simulation test system embodiment of the application. DETAILED DESCRIPTION

[0048] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below in combination with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0049] In order to reduce the difficulty of the test personnel writing code, and fully consider the real-time requirements of simulation testing, ensure the effectiveness and efficiency of the test. A bus simulation development platform can be developed, which includes the development of bus simulation development software, the design and development of the board card. The bus simulation development software mainly involves C#, Python, unstructured database, structured database, file storage, signal definition and analysis (signal database), Ethernet (TCP) transmission, USB3.1Gen2 and above, PCIe3.0 and above. The design and development of the board card includes chip selection, communication interface selection (Ethernet / USB / PCIe), Linux system, real-time operating system, C++, Python, shared memory scheme (inter-core communication), driver development, FPGA (Field-Programmable Gate Array, programmable logic device) programming, TSN (Time-Sensitive Networking, time-sensitive network) time synchronization, etc.

[0050] Reference Figure 1 is a logical architecture schematic diagram of an embodiment of a simulation test system of the present application.

[0051] The application provides a logic architecture of a simulation test system, which can include bus simulation development software, a HIL (Hardware-in-the-Loop Simulation) platform and a controller. The bus simulation development software can include a configuration and editing module and an execution and display module. The configuration and editing module can include a device configuration submodule and an auxiliary tool submodule, and the execution and display module can include a simulation model submodule, a test platform submodule, a data sending submodule, a diagnosis submodule, a system interface submodule and a data analysis submodule. The configuration and editing module can be used to configure and edit various function submodules on the execution and display module. The HIL platform can include a board card integration module and a power supply and control module. The board card integration module can include a digital IO acquisition feedback fault injection submodule, an analog IO acquisition feedback fault injection submodule, a CAN (FD) acquisition feedback fault injection submodule, a LIN acquisition feedback fault injection submodule, an Ethernet acquisition feedback fault injection submodule and a repeater. The power supply and control module can include an external power supply and a programmed power supply, which provide power supply for the board card integration. The execution and display module in the bus simulation development software and the board card integration in the HIL platform can transmit data to each other. The controller can include various communication network interfaces, including CAN, LIN, Ethernet, DIDO and AIAO. The controller can transmit data to the board card integration in the HIL platform.

[0052] Reference Figure 2 FIG. 1 is a technical architecture schematic diagram of an embodiment of a simulation test system of the application.

[0053] This application provides a simulation testing system architecture that may include bus simulation development software and a HIL (High-Intensity Link) bench. The bus simulation development software may include a simulation and functional logic control module, a data processing module, a device configuration module, a signal database, a Python library, and a data storage module. The simulation and functional logic control module may include a simulation model submodule, a test platform submodule, a diagnostic submodule, and a data transmission submodule. The data processing module may include a data analysis submodule and a data export submodule. The device configuration module may include a device configuration submodule and a system interface. The system interface may be an editable interface, allowing external programs or systems to access or control simulation nodes or controllers in the bus simulation development platform. The signal database may contain signal data corresponding to various communication protocols, such as CAN, LIN, Ethernet, DIDO proprietary protocol, and AIAO proprietary protocol. The Python library may be categorized according to the corresponding communication protocol, such as CAN, LIN, Ethernet, DIDO, and AIAO libraries. The data storage module may include a structured database, an unstructured database, and a file storage system. The HIL bench may contain multiple boards. The board can include an A-core, an R-core, shared memory, an FPGA, and a PIN interface. The A-core can include a data acquisition and injection fault injection configuration module, a data acquisition and injection fault injection script module, a time synchronization module, a Python library, an inter-core communication module, a data storage module, a signal database, and a driver module. The R-core can include a CAN transceiver module, a LIN transceiver module, an Ethernet transceiver module, a DIDO transceiver module, an AIAO transceiver module, and a driver module. The FPGA can include a timestamp module, a clock synchronization module, a message transceiver module, and an inter-core communication module. The PIN interface can include CAN, LIN, and Ethernet PIN interfaces. Furthermore, the simulation and functional logic control modules and data storage modules in the bus simulation development software communicate with the board in the HIL test bench via Ethernet / USB / PCIe.

[0054] Reference Figure 3 This is a flowchart illustrating the steps of an embodiment of a simulation testing method according to this application, including the following steps:

[0055] Step 301: Obtain the simulation testing tools from the bus simulation development software;

[0056] The simulation test tool contains test messages to be sent, and the bus simulation development software communicates with the controller under test through the board. The board contains a first processor core and a second processor core.

[0057] The bus simulation development software is based on a Windows system and developed using C#. The software tool can be used to provide configuration and programming of simulation and functional logic control processes, data processing, and testing of automotive general-purpose protocols. The simulation test tool includes a simulation node and a test script. The simulation node is a virtual entity that can simulate the behavior of actual devices by receiving inputs, processing data, and generating outputs. In vehicle bus simulation testing, the simulation node can be a virtual node that simulates the behavior of a real ECU and can simulate the communication process in an actual vehicle. The test script is an automated test software script that can be written and executed to test cases. In vehicle bus simulation testing, the test script can simulate and verify communication and data exchange between various components of a vehicle. The test message is included in the test script of the simulation test tool and can simulate the message data received and sent in actual vehicle communication, helping to detect and diagnose potential problems in the vehicle system. The board card can be a hardware device used for acquisition, back-annotation, fault injection, and power supply support for the controller. It can also provide a certain number of circuit channels for communication with the controller. If the circuit channels provided by a board card do not meet the needs of the controller under test, multiple board cards can be used in cooperation. The first processor core can be an A core located on the board card. The A core uses an ARM architecture SoC chip, and the system is Linux. The software in the A core is developed based on C++, and is mainly used for communication and functional interaction with the bus simulation development software on the Windows side. The second processor core can be an R core located on the board card. The R core uses an ARM architecture SoC chip, and the system is FreeRTOS. The software in the R core is developed based on C, and is mainly used for communication and functional interaction with the A core and the FPGA. The communication and functional interaction between the first processor core and the second processor core are realized through an inter-core communication module. For example, Figure 2 The inter-core communication between the first processor core and the second processor core can be realized using the openamp framework in a shared memory manner.

[0058] Step 302, sending the simulation test tool to the first processor core;

[0059] The first processor core is configured to call the second processor core according to the simulation test tool. The second processor core is configured to send the test message in the simulation test tool to the controller under test. The controller under test can be each electronic control unit used to manage and regulate the functions of various parts of the vehicle.

[0060] Step 303, receiving a response message returned by the controller under test in response to the test message;

[0061] The response message is a message returned by the controller under test after receiving the test message and performing corresponding processing according to the test message. The response message can include information confirming successful reception of the test message, test result information, or other related information.

[0062] Step 304, the test packet and the response packet are taken as simulation test data and displayed.

[0063] In order to realize real-time and efficient vehicle bus simulation testing, a simulation test tool on a bus simulation development software can be acquired, including a simulation node and a test script. Exemplarily, the simulation node and the test script can be written in Python language. Using Python language as the simulation test code editing language can reduce the requirement for the ability of the tester to write simulation node, test scene and test script code, and improve the writing efficiency of the simulation test tool. The test script contains a test packet to be sent. The bus simulation development software is in communication connection with a board, and the board is in communication connection with a measured controller. The board contains a first processor core and a second processor core, i.e. A core and R core. Therefore, the bus simulation development software can send the simulation test tool to the A core on the board through a high-bandwidth interface. After receiving the simulation test tool, the A core directly calls the R core to send the test packet in the test script to the measured controller according to the simulation node and the test script in the simulation test tool, so as to ensure the real-time performance of the simulation test. The high-bandwidth interface can be a high-bandwidth Ethernet, USB or PCIe interface, such as a 1 Gb / s Ethernet interface and above, a USB3.1 Gen2 and above USB interface, or a PCIe3.0 and above PCIe interface. After receiving the test packet, the measured controller responds to the test packet and returns a corresponding response packet. The response packet returned by the measured controller in response to the test packet is received, and then the test packet and the response packet are taken as simulation test data and displayed. Through the above steps, the tester can be provided with a convenient editing tool to facilitate the user to edit the simulation node and the test scene, to ensure the real-time performance of the simulation test process, to improve the test efficiency, and to accurately and efficiently obtain the simulation test data of the controller.

[0064] Exemplarily, as shown in Figure 2 The simulation test method provided by the application can be used for HiL hardware-in-the-loop testing of the controller. The bus simulation development software provides the ability to create simulation nodes and test steps, calls various types of boards in the HIL rack to simulate one or more simulation nodes, or even a simulation controller, then communicates with the measured controller in real time, and finally judges whether the communication data is correct through the verification conditions established in the bus simulation development software.

[0065] Optionally, in an embodiment of the application, after the simulation test tool is sent to the first processor core, the method further includes:

[0066] The first processor core is controlled to obtain the test packet by running the simulation test tool.

[0067] Exemplarily, the simulation test tool written in Python language can be sent to the first processor core, i.e., the A core on the board, and the A core software directly runs the simulation nodes and test scripts in the simulation test tool to obtain the test packet in the test script according to the Python function therein. To support Python as the language for writing the simulation nodes and test scripts, the relevant Python library can be provided in the bus simulation development software and the A core software on the board. For reference Figure 2 In the bus simulation development software, the code in the Python library can be set by the simulation machine function logic control module, and the function, interface, and the like of the Python library can be provided with the name, and the actual content of the function is empty, which is used for searching and static code checking when the user writes the simulation nodes and test scripts. In the Python library of the A core on the board, the content of all function interfaces corresponding to the Python library in the bus simulation development software can be provided, and when the A core on the board receives the Python simulation nodes and test scripts written by the bus simulation development software, the Python scripts can be normally run. Among them, the Python library can provide the underlying function for simulation and function logic control, and the hardware control function in the A core is called by the Python code to realize the collection and transmission of CAN, LIN, Ethernet, DIDO, AIAO, and the like.

[0068] Optionally, in an embodiment of the present application, after the simulation test tool is sent to the first processor core, the method further comprises:

[0069] obtaining a first signal database on the bus simulation development software, wherein the first data in the first signal database contains the message structure and signal name of the test packet;

[0070] Among them, the first signal database can contain a file defining the message structure and signal name, etc. The CAN (Controller Area Network) network can correspond to the DBC (Database for CAN) file, the LIN bus can correspond to the LDF (LIN Description File) file, the Ethernet can correspond to the ARXML file, and the DIDO or AIAO can correspond to the JSON file.

[0071] synchronizing the first data to a second signal database of the first processor core to obtain corresponding second data;

[0072] controlling the first processor core to run the simulation test tool, and obtaining the test packet according to the second data.

[0073] In some embodiments of the present application, for referenceFigure 2 The bus simulation development software can define a plurality of message structures and signal names in the first signal database through the simulation machine function logic control module on the simulation development software, and the pre-defined messages and signals in the first signal database can be used when writing the simulation nodes or test scripts in the simulation test tool. The bus simulation development software can synchronize the content of the first signal database to the second signal database in the first processor core through the Ethernet, USB or PCIe protocol. The content of the first signal database, i.e., the pre-defined message structures and signal names, is stored as second data in the second signal database. The first processor core runs the simulation test tool, and the Python function in the simulation nodes and test scripts is used to parse the signals according to the message structures in the second data to obtain the test messages to be sent.

[0074] Optionally, in an embodiment of the present application, after the simulation test tool is sent to the first processor core, the method further comprises:

[0075] obtaining a first signal database on the bus simulation development software, wherein first data in the first signal database includes message structures and signal names of the test messages;

[0076] defining a sending period of the test messages in the first signal database, wherein the sending period is used to control the frequency of calling the second processor core by the first processor core;

[0077] synchronizing the first data and the sending period to a third signal database of the first processor core to obtain third data;

[0078] controlling the first processor core to run the simulation test tool and parse the test messages according to the third data.

[0079] In some embodiments of the present application, a plurality of message structures and signal names can be defined in a first signal database on the bus simulation development software, and the predefined messages and signals in the first signal database can be used when writing the simulation nodes or test scripts in the simulation test tool. The sending period of the test messages can also be defined in the first signal database. The bus simulation development software can synchronize the content of the first signal database to a second signal database in the first processor core through Ethernet, USB or PCIe protocol. The content of the first signal database, i.e. the predefined message structures and signal names and the sending period of the test signals, is stored as third data in the third signal database. The first processor core is controlled to run the simulation test tool, and the Python functions in the simulation nodes and test scripts are used to parse the signals according to the message structures in the second data to obtain the test messages to be sent. In addition, when sending the test messages, the second processor core can be called according to the test signal sending period in the third data to send the test messages.

[0080] Optionally, in an embodiment of the present application, the method further comprises:

[0081] controlling the first processor core to generate a control command for calling the second processor core according to the simulation test tool;

[0082] controlling the second processor core to send the test messages to the controller under test through the programmable logic device on the board card in response to the control command after receiving the control command and the test messages sent by the first processor core; the programmable logic device is used to add a time stamp to the test messages when sending the test messages.

[0083] wherein the programmable logic device (Field-Programmable Gate Array, FPGA) is communicatively connected with the second processor core and the controller under test respectively, and is used to complete the final sending of the test messages and the receiving of the response messages returned by the controller under test. For details, please refer to Figure 2The acquisition back-annotation fault injection configuration module and the acquisition back-annotation fault injection script module exist in the first processor core. After the acquisition back-annotation fault injection script receives the simulation test tool sent by the bus simulation development software, the Python code in the simulation node and the test script is directly executed, the function in the Python code directly generates a call to the second processor core control command, and the second processor core sends the test message parsed by the first processor core in response to receiving the control command and the test message sent by the first processor core. The FPGA sends the test message to the controller under test. When the FPGA sends the test message, a timestamp is added to the sent message, and correspondingly, when the response message returned by the controller under test is received, a timestamp is also added to the received message. By generating a control command that can directly call hardware, the real-time performance of the simulation test process can be guaranteed, and the test efficiency can be improved.

[0084] Since the implementation systems corresponding to the first processor core, the second processor core and the FPGA are different, the acquisition back-annotation fault injection configuration module on the first processor core can first convert the message sending configuration information of the test message into configuration information after receiving the message sending configuration information, that is, the test message with the code script format, and then send the test message converted into the configuration information to the second processor core. The configuration information that can be recognized by the second processor core is a driver configuration. There are multiple transceiver modules on the second processor, including CAN, LIN, Ethernet, DIDO and AIAO transceivers. Correspondingly, the controller under test can also be a controller using CAN, LIN, Ethernet, DIDO and AIAO as a communication protocol. After the second processor core receives the test message and the control command from the transceiver module, it can convert the configuration information corresponding to the test message and the control command into configuration and then send it to the FPGA. The configuration refers to the message code that can be recognized by the FPGA. The communication and functional interaction between the second processor core and the FPGA is realized through inter-core communication. For example, refer to Figure 2 The inter-core communication between the second processor core and the FPGA can be realized by using DMA (Direct Memory Access) and FIFO (First In, First Out data structure). Similarly, after the signal database on the first processor core receives the synchronization information of the first signal database from the bus simulation development software, the corresponding message sending configuration information can be converted into configuration information and sent to the second processor core.

[0085] Optionally, in an embodiment of the present application, the method further comprises:

[0086] acquire a first signal database on the bus simulation development software, wherein first data in the first signal database comprises message structure and signal name of the test message;

[0087] generate message sending configuration information by configuring the test message to be sent;

[0088] send the message sending configuration information to the first processor core;

[0089] synchronize the first data and the sending period to a fourth signal database of the first processor core to obtain fourth data;

[0090] control the first processor core to parse the test message according to the message sending configuration information and the fourth data;

[0091] control the first processor core to generate a control command for calling a second processor core;

[0092] control the second processor core to send the test message to the controller under test through a programmable logic device on the board card in response to the control command after receiving the control command and the test message sent by the first processor core, wherein the programmable logic device is configured to add a time stamp to the test message when sending the test message.

[0093] In some embodiments of the present application, the message structure and signal name of the test message can be defined in a first signal database on the bus simulation development software, and then the message sending configuration information can be configured by sending the message in the first signal database. For example, the first signal database in the bus simulation development software can be selected by a user, and the user can select a message in the library as the test message to be sent by clicking a corresponding button. The bus simulation development software sends the message sending configuration information to the first processor core through Ethernet, USB or PCIe protocol, and synchronizes the content of the first signal database to the fourth signal database in the first processor core through Ethernet, USB or PCIe protocol to obtain corresponding fourth data. The first processor core parses the test message according to the message sending configuration information and the fourth signal database, and then generates a control command for calling the second processor core to control the second processor core to send the test message to the controller under test through the programmable logic device on the board card. The programmable logic device adds a time stamp to the sent message when sending the test message, and correspondingly, adds a time stamp to the received message when receiving the response message returned by the controller under test.

[0094] Optionally, in an embodiment of the present application, the method further comprises:

[0095] The test message sending configuration information is generated by configuring the test message to be sent.

[0096] The diagnosis message sending configuration information is generated by configuring the diagnosis message to be sent.

[0097] The test message sending configuration information and the diagnosis message sending configuration information are sent to the first processor core.

[0098] The first processor core is controlled to parse the test message or the diagnosis message according to the test message sending configuration information or the diagnosis message sending configuration information.

[0099] The first processor core is controlled to generate a control command for calling the second processor core.

[0100] The second processor core is controlled to send the test message or the diagnosis message to the controller under test through the programmable logic device on the board card in response to the control command after receiving the test message or the diagnosis message sent by the first processor core, and the programmable logic device is used to add a time stamp to the test message or the diagnosis message when sending the test message.

[0101] In some embodiments of the present application, the test message sending configuration information or the diagnosis message sending configuration information can be configured in the bus simulation development software. For example, referring to Figure 2 , a local information database can be set in the bus simulation development software for users to select messages according to test requirements, and users can select messages in the library as test messages to be sent by clicking corresponding buttons. The local information database can be generated by parsing message data according to various protocols corresponding to files in the first signal database, and then storing the parsed message data in a structured database in the local data storage module. The local information database can be used by users when writing simulation nodes, writing test scripts, and data analysis. The device configuration module on the bus simulation development software can ensure correct data transmission. The bus simulation development software can send the test message sending configuration information or the diagnosis message sending configuration information to the first processor core through Ethernet, USB, or PCIe protocol. The first processor core parses the test message or the diagnosis message according to the test message sending configuration information or the diagnosis message sending configuration information, and then generates a control command for calling the second processor core to control the second processor core to send the test message or the diagnosis message to the controller under test through the programmable logic device on the board card. The programmable logic device adds a time stamp to the sent message when sending the test message or the diagnosis message, and correspondingly, adds a time stamp to the received message when receiving the response message returned by the controller under test.

[0102] Optionally, in an embodiment of the present application, the method further comprises:

[0103] directly displaying the test message and the response message;

[0104] or, according to the message structure and signal name saved in the first signal database, parsing the test message and the response message to generate parsed data;

[0105] displaying the parsed data.

[0106] In some embodiments of the present application, referring to Figure 2 , after triggering the communication between the board card and the controller under test, the messages sent and received by the board card during the communication are added with corresponding line-of-sight stamps when the FPGA sends and receives the messages, and then the messages are transmitted to the first processor core through the second processor core and stored in the data storage of the first processor core. The data storage of the first processor core can be a time sequence database in which a file is mapped into memory through mmap (memory map). Using mmap can improve the data access speed and processing efficiency. The first processor core can send the message content in the data storage to the bus simulation development software in real time, and the bus simulation development software stores these sent and received messages in a local unstructured database. The local unstructured database can use Mangodb, which is a document-oriented, distributed database that can be used to store and manage a large amount of structured and unstructured data. When a simulation test data reading instruction is obtained, the data processing module in the bus simulation development software can read the messages stored in the local unstructured database in real time, and then display these messages to the user. When a simulation test data export instruction is obtained, the data processing module in the bus simulation development software can export the messages that the user wants according to the data type and time length contained in the instruction from the unstructured database. When a simulation test data analysis instruction is obtained, the data processing module in the bus simulation development software parses the messages stored in the local unstructured database according to the structure definition and signal name definition of the messages in the first information database, and displays the parsed data information to the user. In addition, the test personnel can also perform various operations such as viewing, filtering, and statistics on all messages stored in the local unstructured database according to actual needs through data analysis. The simulation test data of the controller is accurately and efficiently obtained.

[0107] Optionally, in an embodiment of the present application, the method further comprises:

[0108] receiving a time service request of the first processor core;

[0109] The time-providing request is a message for requesting other devices or systems to provide time information, and can be used to ensure time synchronization of various devices or systems, thereby meeting the requirements for time accuracy in various application scenarios.

[0110] In the case of a single board card, a clock is sent to the board card in response to the time-providing request.

[0111] In the case of multiple board cards, one of the board cards is selected as a master node board card, and the board cards other than the master node board card are selected as slave node board cards, and a clock is sent to the master node board card in response to the time-providing request; the master node board card is configured to synchronize the clock to the slave node board cards.

[0112] In some embodiments of the present application, the first processor core can request the bus simulation development software for its system time, and after receiving the time-providing request of the first processor core, the bus simulation development software can send a clock to the first processor core that sent the request. In the case of a single board card being used independently, the bus simulation development software responds to the time-providing request and directly sends a clock to the first processor core on the board card. In the case of multiple board cards being used jointly in the system, the bus simulation development software responds to the time-providing request and first selects one of the multiple board cards as a master node board card, and selects the remaining board cards other than the master node board card as slave node board cards, and then sends a clock to the first processor core on the master node board card. The first processor core on the master node board card receives the clock and synchronizes the system time, and then synchronizes the clock to each slave node board card through Ethernet. For example, refer to Figure 2 The TSN architecture can be used to implement clock synchronization. The FPGA on the board card can obtain time-providing through the first processor core on the board card, or through an external GPS. Through the above steps, the PXI or PCI architecture can be abandoned, so that the board cards can be used independently through Ethernet TSN to implement clock synchronization. In the case of multiple board cards being used, all communication data in the system can also be kept in clock synchronization. The cost problem of the PXI / PCI rack in the traditional test system is overcome, and the real-time performance of simulation testing is also guaranteed.

[0113] It should be noted that, for the method embodiments, in order to simply describe, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present application are not limited to the action order described, because according to the embodiments of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0114] On the basis of the above-mentioned embodiments, the present embodiment further provides a simulation test system applied to electronic devices such as terminal devices and servers.

[0115] Referring to Figure 4 , a structural block diagram of an embodiment of the simulation test system of the present application is shown, which can specifically include the following modules:

[0116] The simulation test tool acquisition module 401 is configured to acquire a simulation test tool on a bus simulation development software; the simulation test tool contains a test message to be sent, and the bus simulation development software is in communication connection with a measured controller through a board card containing a first processor core and a second processor core;

[0117] The sending module 402 is configured to send the simulation test tool to the first processor core; the first processor core is configured to call the second processor core according to the simulation test tool, and the second processor core is configured to send the test message in the simulation test tool to the measured controller;

[0118] The receiving module 403 is configured to receive a response message returned by the measured controller in response to the test message;

[0119] The display module 404 is configured to display the test message and the response message as simulation test data.

[0120] Optionally, the simulation test system further includes:

[0121] The first test message acquisition module is configured to control the first processor core to acquire the test message by running the simulation test tool.

[0122] Optionally, the simulation test system further includes:

[0123] The first database acquisition module is configured to acquire a first signal database on the bus simulation development software, and first data in the first signal database contains a message structure and a signal name of the test message;

[0124] The first synchronization module is configured to synchronize the first data to a second signal database of the first processor core to obtain corresponding second data.

[0125] The second test message acquisition module is configured to control the first processor core to run the simulation test tool and parse the test message according to the second data.

[0126] Optionally, the simulation test system further includes:

[0127] a second database acquisition module configured to acquire a first signal database on the bus simulation development software, wherein first data in the first signal database comprises a message structure and a signal name of the test message;

[0128] a sending cycle definition module configured to define a sending cycle of the test message in the first signal database, wherein the sending cycle is used to control a frequency of calling the second processor core by the first processor core;

[0129] a second synchronization module configured to synchronize the first data and the sending cycle to a third signal database of the first processor core to obtain third data;

[0130] a third test message acquisition module configured to control the first processor core to run the simulation test tool and parse the test message according to the third data.

[0131] Optionally, the simulation test system further comprises:

[0132] a control command generation module configured to control the first processor core to generate a control command for calling the second processor core according to the simulation test tool;

[0133] a control command response module configured to control the second processor core to send the test message to the controller under test through a programmable logic device on the board card in response to the control command after receiving the control command and the test message sent by the first processor core, wherein the programmable logic device is used to add a time stamp to the test message when sending the test message.

[0134] Optionally, the display module further comprises:

[0135] a message display sub-module configured to directly display the test message and the response message;

[0136] a parsing sub-module configured to parse the test message and the response message to generate parsed data according to the message structure and the signal name saved in the first signal database;

[0137] a parsed data display sub-module configured to display the parsed data.

[0138] Optionally, the simulation test system further comprises:

[0139] a time service request receiving module configured to receive a time service request of the first processor core;

[0140] The time-providing module is configured to send a clock to the board card in response to the time-providing request when there is only one board card; and when there are multiple board cards, select one of the board cards as a master node board card, and send a clock to the master node board card in response to the time-providing request; and the master node board card is configured to synchronize the clock to the slave node board cards.

[0141] The simulation test system provided by the embodiment of the application can obtain a simulation test tool on a bus simulation development software, the simulation test tool containing a test message to be sent, the bus simulation development software being in communication connection with a controller under test through a board card, the board card containing a first processor core and a second processor core. The simulation test tool is sent to the first processor core, and the first processor core is configured to send the test message in the simulation test tool to the controller under test according to the simulation test tool calling the second processor core, so that a hardware control command can be directly called, the real-time performance of the simulation test process is ensured, and the test efficiency is improved. The response message returned by the controller under test in response to the test message is received, the test message and the response message are taken as simulation test data and displayed, and the simulation test data of the controller can be accurately and efficiently obtained.

[0142] For the above system embodiment, the description is relatively simple because it is basically similar to the method embodiment, and the relevant parts can be referred to the part of the method embodiment.

[0143] The embodiment of the application further provides a nonvolatile readable storage medium, the storage medium storing one or more programs, and when the one or more programs are applied to a device, the device can execute instructions of the method steps in the embodiment of the application.

[0144] The embodiment of the application provides a computer readable storage medium, the computer readable storage medium storing a computer program, and when the computer program is executed by a processor, the computer program implements one or more simulation test methods in the above embodiments. In the embodiment of the application, the electronic device includes terminal devices, servers (clusters), and various types of devices.

[0145] Each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0146] The computer program instructions can also be loaded onto a computer or other programmable processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0147] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0148] These computer program instructions can also be loaded onto a computer or other programmable processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks Figure 1 one or more flowcharts and / or blocks

[0149] While preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description. Therefore, the appended claims are intended to encompass within their scope all possible variations and modifications of the preferred embodiments.

[0150] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0151] The simulation test method and device, the electronic device and the storage medium provided in the present application are described in detail above, the principles and implementation manners of the present application are described by applying specific examples in the present article, the above example description is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will have changes, and the above description should not be understood as a limitation on the present application.

Claims

1. A method of emulation testing, characterized by, The method comprises: acquiring a simulation test tool on a bus simulation development software; the simulation test tool contains a test message to be sent, and the bus simulation development software is in communication connection with a controller under test through a board; the board contains a first processor core and a second processor core; sending the simulation test tool to the first processor core; the first processor core is configured to call the second processor core according to the simulation test tool, and the second processor core is configured to send the test message in the simulation test tool to the controller under test; controlling the first processor core to generate a control command for calling the second processor core according to the simulation test tool; controlling the second processor core to send the test message to the controller under test through a programmable logic device on the board in response to the control command after receiving the control command and the test message sent by the first processor core; the programmable logic device is configured to add a time stamp to the test message when sending the test message; receiving a response message returned by the controller under test in response to the test message; displaying the test message and the response message as simulation test data.

2. The method of claim 1, wherein, After sending the simulation test tool to the first processor core, the method further comprises: controlling the first processor core to acquire the test message by running the simulation test tool.

3. The method of claim 1, wherein, After sending the simulation test tool to the first processor core, the method further comprises: acquiring a first signal database on the bus simulation development software; first data in the first signal database contains a message structure and a signal name of the test message; synchronizing the first data to a second signal database of the first processor core to obtain corresponding second data; the first processor core is configured to run the simulation test tool and parse the test message according to the second data.

4. The method of claim 1, wherein, After sending the simulation test tool to the first processor core, the method further comprises: acquiring a first signal database on the bus simulation development software; first data in the first signal database contains a message structure and a signal name of the test message; defining a sending period of the test message in the first signal database; the sending period is configured to control the frequency of calling the second processor core by the first processor core; synchronizing the first data and the sending period to a third signal database of the first processor core to obtain third data; controlling the first processor core to run the simulation test tool and parse the test message according to the third data.

5. The method of claim 3, wherein, The method further comprises: directly displaying the test message and the response message; or, parsing the test message and the response message according to the message structure and the signal name saved in the first signal database to generate parsed data; displaying the parsed data.

6. The method of claim 1, wherein, The method further comprises: receiving a time service request of the first processor core; In the presence of a single board card, a clock is sent to the board card in response to the time service request; In the presence of multiple board cards, one of the board cards is selected as a master node board card, and the board cards other than the master node board card are selected as slave node board cards, and a clock is sent to the master node board card in response to the time service request; the master node board card is configured to synchronize the clock to the slave node board cards.

7. An emulation test system, comprising: The system comprises: An emulation test tool acquisition module configured to acquire an emulation test tool on a bus emulation development software; the emulation test tool contains a test message to be sent, and the bus emulation development software is in communication connection with a controller under test through a board card containing a first processor core and a second processor core; A sending module configured to send the emulation test tool to the first processor core; the first processor core is configured to call the second processor core according to the emulation test tool, and the second processor core is configured to send the test message in the emulation test tool to the controller under test; A control command generation module configured to control the first processor core to generate a control command for calling the second processor core according to the emulation test tool; A control command response module configured to control the second processor core to send the test message to the controller under test through a programmable logic device on the board card in response to the control command after receiving the control command and the test message sent by the first processor core; the programmable logic device is configured to add a time stamp to the test message when sending the test message; A receiving module configured to receive a response message returned by the controller under test in response to the test message; A display module configured to display the test message and the response message as emulation test data.

8. An electronic device, comprising: comprise: a processor; and a memory having stored thereon executable code that, when executed, cause the processor to perform the emulation test method of one or more of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the emulation test method of one or more of claims 1-6. The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the emulation test method of one or more of claims 1-6.

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