Page configuration method, DDR controller and system on chip

Abstract

The invention relates to the technical field of memory management, and discloses a page configuration method, a DDR controller and a system on chip, and the method comprises the steps that a command queue sends address information of a to-be-processed read-write request to a monitoring module; the monitoring module determines the line conflict rate of the read-write request in the command queue based on the received address information, and sends the line conflict rate to the arbitration module; the arbitration module matches the received line conflict rate with a preset condition threshold value, generates a page configuration strategy according to a line conflict rate interval represented by a matching result, and issues the page configuration strategy to a register; and the register executes the page configuration strategy, and transmits configuration parameters represented by the page configuration strategy to the command queue, so that the read-write request in the command queue is processed according to the configuration parameters. According to the technical scheme provided by the invention, the system power consumption is reduced by optimizing the Bank management strategy, and the system performance is improved, so that a more efficient page configuration strategy is provided.

Description

Technical Field

[0001] The present application relates to the field of memory management technology, and in particular to a page configuration method, a DDR controller and a system on chip. Background Art

[0002] In modern computer systems, the memory controller is responsible for the management and allocation of memory resources. It is the bridge between the CPU and DDR SDRAM (Double Data Rate SDRAM). One of its main tasks is to manage the pages of the DDR memory subsystem.

[0003] In actual applications, when reading and writing data, the common memory controller's switch page strategy is fixed. If the access behavior changes during the application operation, the strategy cannot be adjusted in time, which may easily lead to long loading time or page conflicts, thus affecting the overall performance. In addition, when the number of banks in the memory system is large, page management is more complicated, which may easily lead to low memory access efficiency and increase system power consumption.

[0004] In view of this, how to implement a more efficient page configuration strategy in terms of memory access is the focus of current research. Summary of the invention

[0005] The present application provides a page configuration method, a DDR controller and a system on chip, which can provide a more efficient page configuration strategy.

[0006] In a first aspect, the present application provides a page configuration method, which is applied to a DDR controller, wherein the DDR controller includes a command queue, a monitoring module, an arbitration module, and a register, wherein the command queue is used to store pending read and write requests, and the method includes: the command queue sends address information of the pending read and write requests to the monitoring module; the monitoring module determines a row conflict rate of the read and write requests in the command queue based on the received address information, and sends the row conflict rate to the arbitration module; the arbitration module matches the received row conflict rate with a preset condition threshold, and dynamically generates a page configuration strategy according to a row conflict rate interval represented by the matching result, and sends the page configuration strategy to the register; wherein the generated page configuration strategy is at least used to represent an open page strategy or a closed page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the closed page strategy; the register executes the page configuration strategy, and passes the configuration parameters represented by the page configuration strategy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters.

[0007] The technical solution provided in this embodiment of the present application can generate a page configuration strategy based on the address information of the read and write requests, and dynamically perform page configuration. First, obtain the address information of the read and write requests in the command queue containing the read and write requests, calculate the row conflict rate of the read and write requests based on the above address information, and then dynamically generate an adaptive page configuration strategy based on the interval of the above row conflict rate, and finally dynamically configure the pages of the memory according to the above page configuration strategy. It can be seen that through the technical solution provided in this embodiment of the present application, page configuration can be performed dynamically, so that when the row conflict rate is high, a closed page strategy is adopted to reduce the power consumption of the memory system, and when the row conflict rate is low, an open page strategy is adopted to reduce request latency and improve system performance, while dynamically adjusting the page opening time, thereby providing a more efficient page configuration strategy.

[0008] In a possible implementation, the preset conditional threshold includes a first threshold and a second threshold; dynamically generating a page configuration strategy based on the row conflict rate interval represented by the matching result includes: if the row conflict rate interval represented by the matching result is greater than the first threshold and less than the second threshold, generating a retention strategy representing maintaining the original page configuration strategy; if the row conflict rate interval represented by the matching result is less than or equal to the first threshold, generating an open page strategy representing disabling the automatic pre-charging function; if the row conflict rate interval represented by the matching result is greater than or equal to the second threshold, generating a closed page strategy representing enabling the automatic pre-charging function.

[0009] The technical solution provided in this embodiment of the present application refines the generation process of the page configuration strategy, specifically involving the comparison between the row conflict rate and multiple threshold intervals. By using the preset conditional thresholds, the intervals where the row conflict rate is located can be accurately divided, and then a matching page configuration strategy can be generated.

[0010] In a possible implementation, the DDR controller also includes a Bank resource management module; the method also includes: the command queue sends the target address information of the target read and write request currently to be processed to the Bank resource management module; the Bank resource management module allocates Bank resources to the target read and write request according to the target address information, and activates the target page represented by the Bank resources.

[0011] The technical solution provided by this embodiment of the present application allocates bank resources to the target read and write requests to be processed through the bank resource management module and activates the corresponding target page. The bank resource management module is introduced to optimize the allocation management and page management of bank resources.

[0012] In one possible implementation, the Bank resource management module pre-configures a threshold counter for the target page, and a specified value is pre-loaded in the threshold counter; after the target page is activated and opened, the method further includes: the specified value gradually decreases, and when the specified value decreases to a fixed value, the Bank resource management module closes the target page and loads a new value in the threshold counter; wherein, after the new page is activated and opened, the new value gradually decreases, and when the new value decreases to a fixed value, the Bank resource management module closes the new page.

[0013] The technical solution provided by this embodiment of the present application uses a threshold counter to manage the duration of the target page after the target page is activated and opened. The threshold counter can ensure that the page remains open during the processing of read and write requests, and can also ensure that the page can be closed in time after opening, thereby optimizing the duration management of the target page and avoiding unnecessary opening time of the page, so as to reduce system power consumption and resource usage.

[0014] In one possible implementation, the specified value loaded in the threshold counter is determined in the following manner: if the row conflict rate is greater than a first threshold and less than a second threshold, the specified value is set to the first value; if the row conflict rate is less than or equal to the first threshold, the specified value is set to the second value; if the row conflict rate is greater than or equal to the second threshold, the specified value is set to a third value; wherein the third value is less than the first value, and the first value is less than the second value.

[0015] The technical solution provided in this embodiment of the present application further describes the setting method of the specified value in the threshold counter. The specified value is dynamically adjusted according to the row conflict rate; when the row conflict rate of read and write requests occurs more frequently, reducing the page opening time can speed up access to new rows and reduce access delays caused by the row conflict rate; in the case of frequent row conflicts, the system may switch rows frequently, so shortening the opening time can improve memory access efficiency, reduce performance losses caused by waiting, and may also help reduce energy consumption. In the case of a low row conflict rate, the system can usually access the data of the same row smoothly, and extending the page opening time can allow more accesses to hit the same row, thereby reducing repeated row switching and improving the efficiency of memory access.

[0016] In one possible implementation, after allocating Bank resources for the target read and write request, the method further includes: for other read and write requests in the command queue except the target read and write request, if the address information of the other read and write requests indicates that the other read and write requests and the target read and write request are located in the same row of the same Bank, the Bank resource management module marks the other read and write requests as ready to issue; wherein the read and write requests marked as ready to issue in the command queue are continuously issued while meeting preset timing requirements.

[0017] The technical solution provided by this embodiment of the present application describes that requests located in the same bank and the same row can be marked as ready so that they can be issued continuously in the future. Read and write requests located in the same bank and in the same row can be issued continuously while meeting the DDR timing requirements, thereby reducing the delay of the switch page, reducing the system consumption caused by the switch page, and improving the efficiency of processing the read and write requests.

[0018] In one possible implementation, after allocating Bank resources for the target read / write request, the method further includes: if the target read / write request and the previous read / write request are located in different rows of the same Bank, the Bank resource management module issues a precharge command and an activation command to reopen the target page corresponding to the target read / write request.

[0019] The technical solution provided in this embodiment of the present application describes that if the read and write requests are located in different rows of the same Bank, it is necessary to reopen the page after closing it through precharge commands and activation commands, thereby ensuring that the read and write requests of different rows can be processed normally.

[0020] In a possible implementation, the monitoring module determines the row conflict rate of the read and write requests in the command queue based on the received address information, including: the monitoring module counting the total number of the pending read and write requests in the command queue; the monitoring module traverses the adjacent first read and write requests and the second read and write requests in the pending read and write requests, and compares the first address information of the first read and write request with the second address information of the second read and write request to obtain an address comparison result; when the address comparison result indicates that the first read and write request and the second read and write request are located in the same BankGroup, the same Bank, and in different rows, the number of row conflicts is accumulated; and the ratio of the accumulated number of row conflicts to the total number of requests is determined as the row conflict rate of the read and write requests in the command queue.

[0021] The technical solution provided by this embodiment of the present application can calculate the row conflict rate according to the address information of the read / write request. By comparing the addresses of any adjacent read / write requests, the read / write requests in the same bank but different rows can be determined, and the row conflict rate can be accurately calculated.

[0022] According to a second aspect of the present application, a DDR controller is provided, which includes a command queue, a monitoring module, an arbitration module and a register, wherein: the command queue is used to store pending read and write requests, and send the address information of the pending read and write requests to the monitoring module; the monitoring module is used to determine the row conflict rate of the read and write requests in the command queue based on the received address information, and send the row conflict rate to the arbitration module; the arbitration module is used to match the received row conflict rate with a preset condition threshold, and dynamically generate a page configuration policy according to the row conflict rate interval represented by the matching result, and send the page configuration policy to the register; wherein the generated page configuration policy is at least used to represent an open page policy or a closed page policy, and the row conflict rate under the open page policy is lower than the row conflict rate under the closed page policy; the register is used to execute the page configuration policy, and pass the configuration parameters represented by the page configuration policy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters.

[0023] The third aspect of the present application provides a system on chip, which includes a DDR controller, a processor core and a memory, wherein: the processor core is used to process instructions obtained by the DDR controller from the memory, and write the processing results into the memory through the DDR controller; the DDR controller is used to execute the above-mentioned page configuration method on the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of the steps of a page configuration method provided in one embodiment of the present application; Figure 2 A schematic diagram of the steps of a method for determining a row conflict rate provided in one embodiment of the present application; Figure 3 A flowchart of a page configuration method provided in one embodiment of the present application; Figure 4 A strategy structure diagram for adaptively adjusting the page opening time provided in one embodiment of the present application; Figure 5 A schematic diagram of the steps of a page configuration method provided in another embodiment of the present application; 6(a) to (d) are timing waveform diagrams of various access commands provided by an embodiment of the present application; Figure 7 A schematic diagram of the structure of a DDR controller provided in one embodiment of the present application; Figure 8 A schematic diagram of the structure of a system on a chip provided for one embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​can be based on additional conditions or beyond the described values ​​in practice.

[0028] The DDR memory module is composed of multiple memory chips, each of which has an independent storage unit. The storage units are arranged in a certain hierarchy, namely channel (memory channel), DIMM (dual in-line memory module), rank (memory bar), chip (chip), Bank (memory bank), row (row), and column (column). Generally speaking, one channel can correspond to one DDR controller. Each storage unit is equipped with a unique address for addressing in data read and write operations. Taking DDR5 as an example, a DDR5 chip contains multiple independent Bank areas, each of which has an independent row address decoder and column address selector. By selecting different banks, multiple storage areas can be accessed in parallel, thereby improving the efficiency of data access. In addition, in DDR4 and DDR5, the concept of BankGroup (memory bank group) is introduced to facilitate Bank management. Among them, there can be multiple BankGroups in a DDR chip, and a BankGroup contains multiple Banks.

[0029] It should be noted that the addressing of SDRAM is exclusive, so if you want to address another row in the same bank after a read or write operation, you must first close the original valid row and reactivate the required row. If two read or write operations are in different rows of the same bank group and the same bank, this situation can be called a row conflict.

[0030] Generally speaking, different page strategies are used in memory management to optimize the efficiency and latency of data access. Among them, the closed page strategy can be understood as once the data access to a row is completed, the memory controller will immediately close the row, so each time the data is accessed, the required row needs to be reactivated. This strategy can avoid row conflicts and make data access more stable and predictable, but it will cause access delays for a certain period of time. The open page strategy can be understood as the memory controller keeping a row of data in the Bank open for a period of time. If consecutive memory access requests are all in the same row, then compared to the closed page mode, these accesses will not need to reactivate the row, thereby avoiding access delays. However, if the access requests are not in the same row, a row conflict will occur. At this time, the data of the previous valid row needs to be written back and the previous valid row needs to be closed, and then the next required row needs to be opened. In this case, the delay of reading and writing data is the largest, which increases the memory access time and system power consumption.

[0031] In current related technologies, page policies can be statically allocated by monitoring the density of memory access behavior information. However, this method has poor adaptability. If the memory access behavior changes during the application operation, the policy cannot be adjusted in time, which easily increases system power consumption. In addition, in some memory systems, if there are many banks, improper management of activated banks can easily lead to reduced access efficiency, and monitoring and analyzing memory access behavior information requires additional hardware resources and time, which increases the system burden.

[0032] In view of this, one or more embodiments of the present application provide a page configuration method, a DDR controller and a system on chip, which can solve the above problems and reduce the power consumption of the memory system and improve the performance of the memory system by optimizing the Bank management strategy.

[0033] See also Figure 1 In one embodiment of the present application, a page configuration method is provided. The method is applied to a DDR controller. The DDR controller includes a command queue, a monitoring module, an arbitration module, and a register. The command queue is used to store pending read and write requests. The method may include the following steps: S1: The command queue sends the address information of the read and write requests to be processed to the monitoring module.

[0034] Specifically, the command queue is an important component of memory management, responsible for storing and scheduling read and write requests. The command queue stores multiple entries, each of which can store a pending read and write request waiting for access operations. The number of entries in the command queue represents the maximum number of requests that can be stored in the command queue.

[0035] In this embodiment, the DDR controller is responsible for connecting the CPU and the DDR storage unit and generating control signals to manage read and write operations. The DDR controller receives one or more read and write requests from the CPU and generates corresponding command sequences.

[0036] The address information of the above read / write request can be understood as the location information of the storage area that the read / write request needs to access. In the DDR memory module, each storage unit is equipped with a unique address for addressing in data read / write operations. Therefore, before addressing, it is necessary to determine the BankGroup, Bank, row, and column of the storage area to be accessed corresponding to the request.

[0037] S3: The monitoring module determines the row conflict rate of the read and write requests in the command queue based on the received address information, and sends the row conflict rate to the arbitration module.

[0038] The above row conflict rate can be understood as the probability of a row conflict occurring in a command queue. In a command queue, if the address information of two adjacent read and write requests is in different rows of the same BankGroup and the same Bank, it is considered that a row conflict occurs.

[0039] After determining the row conflict rate of the read and write requests in the command queue, the row conflict rate may be sent to the arbitration module so that a matching page configuration strategy may be dynamically generated through the arbitration module.

[0040] S5: The arbitration module matches the received row conflict rate with a preset conditional threshold, and dynamically generates a page configuration strategy according to the row conflict rate interval represented by the matching result, and sends the page configuration strategy to the register; wherein the generated page configuration strategy is at least used to represent an open page strategy or a closed page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the closed page strategy.

[0041] In this embodiment, the page configuration strategy includes an open page strategy and a closed page strategy, and the value of the row conflict rate is compared with the preset condition threshold to determine the page configuration strategy matched by the current memory system. Among them, when the row conflict rate is low, the probability that the row address information of consecutive read and write requests is in the same row is high, and the open page strategy can keep the row data in the open state in the Bank for a period of time without reactivating the row, thereby reducing the request delay; on the contrary, when the row conflict rate is high, the probability that the row address information of consecutive read and write requests is in the same row is low, and the closed page strategy can avoid causing additional memory access time and reduce system power consumption.

[0042] In one possible implementation, the preset conditional threshold includes a first threshold and a second threshold, and the row conflict rate is matched with the first threshold and the second threshold, and a corresponding page configuration strategy is generated according to the row conflict rate interval represented by the matching result. Specifically, if the row conflict rate interval is greater than the first threshold and less than the second threshold, the page configuration strategy adopts the original page configuration strategy; if the row conflict rate interval is less than or equal to the first threshold, an open page strategy representing the disabling of the automatic precharge function is generated; if the row conflict rate interval is greater than or equal to the second threshold, a closed page strategy representing the enabling of the automatic precharge function is generated.

[0043] Precharging can be understood as the operation of closing an existing working row of a Bank. In fact, precharging is to rewrite the data of all storage bodies in the working row and reset the row address. Therefore, precharging is often used between two consecutive read and write request operations of the closed page strategy to write back the data of the last valid row and close the last valid row. Precharging can be controlled by commands, or the chip can be automatically precharged after each read and write operation through auxiliary settings.

[0044] It should be noted that when the open page strategy is adopted, the conflict rate of the requested rows in the command queue is low, and it is not necessary to perform precharge operations every time the memory is accessed. Therefore, disabling the automatic precharge function can avoid excessive energy consumption of the system. When the closed page strategy is adopted, the conflict rate of the requested rows in the command queue is high, and it is necessary to perform precharge operations frequently and reopen the next row. Enabling the automatic precharge function can avoid causing additional memory access time.

[0045] S7: The register executes the page configuration policy, and transmits the configuration parameters represented by the page configuration policy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters.

[0046] In this embodiment, after the register is configured according to a specific page configuration policy, the register will pass the configuration parameters to the command queue. After the command queue receives the read and write requests from the processor, it will process these requests according to the configuration parameters passed in the register. Exemplarily, the above configuration parameters may include automatic precharge parameters, and the read and write requests in the command queue are automatically precharged according to the above configuration parameters before accessing the memory. In the command queue, ensuring that its configuration operation is consistent with the system's memory management policy can optimize the overall memory access performance.

[0047] Exemplarily, when the open page strategy is adopted, the register module configures the corresponding parameter for disabling automatic precharging, and passes the parameter to the command queue, thereby disabling automatic precharging of each read and write request. When the closed page strategy is adopted, the register module configures the corresponding parameter for enabling automatic precharging, and passes the parameter to the command queue, thereby enabling automatic precharging of each read and write request.

[0048] See also Figure 2 In one embodiment, based on the above step S3, the monitoring module determines the row conflict rate of the read and write requests in the command queue based on the received address information, wherein the row conflict rate is determined according to the following steps: S31: the monitoring module counts the total number of the pending read and write requests in the command queue; S33: the monitoring module traverses the adjacent first read / write request and the second read / write request in the read / write request to be processed, and compares the first address information of the first read / write request with the second address information of the second read / write request to obtain an address comparison result; S35: accumulating the number of row conflicts when the address comparison result indicates that the first read / write request and the second read / write request are located in the same BankGroup, the same Bank, and different rows; S37: Determine the ratio of the accumulated number of row conflicts to the total number of requests as the row conflict rate of the read and write requests in the command queue.

[0049] In this embodiment, the row conflict rate is the ratio of the cumulative number of row conflicts in the command queue to the total number of all pending read and write requests. The total number of read and write requests can be counted by the monitoring module. Specifically, the monitoring module reads the entry information contained in the command queue, and identifies the placeholder identifier representing the read and write request in the entry information. One read and write request corresponds to one placeholder identifier. By counting the number of placeholder identifiers, the total number of pending read and write requests contained in the command queue can be determined. The technical solution provided in this embodiment uses the entry information to characterize whether there is a read and write request in the entry of the command queue, so as to quickly and accurately count the total number of requests.

[0050] Exemplarily, the valid value of the full_list signal is used as a placeholder. Each entry in the command queue has a built-in full_list signal. If a request is stored in the current entry, the full_list signal value of the entry becomes a valid value. Therefore, whenever a valid value of the full_list signal is detected, it means that a read or write request is detected. On the contrary, if the full_list signal in the current entry is an invalid value, it means that there is no read or write request in the current entry. In a specific application example, the full_list signal value can be set by pulling the level high or low, wherein the high level can correspond to a valid value, and the low level can correspond to an invalid value.

[0051] In this embodiment, by comparing the address information of adjacent read and write requests, it is determined whether a row conflict occurs, and the cumulative number of row conflicts in the command queue is counted. Among them, whether a row conflict occurs can be determined by the monitoring module. Specifically, the monitoring module obtains the address information of the first read and write request and the second read and write request adjacent to each other in the command queue, and the address information includes the Bank group identifier, the Bank identifier and the row identifier, wherein the Bank group identifier represents the BankGroup address information of the read and write request, the Bank identifier represents the Bank address information of the read and write request, and the row identifier represents the row address information of the read and write request. Comparing the first address information of the first read and write request with the second address information of the second read and write request, if the first read and write request and the second read and write request are located in the same BankGroup, the same Bank, and different rows, that is, the Bank group identifier and the Bank identifier of the first address information and the second address information correspond to each other, but the row identifier is inconsistent, indicating that a row conflict occurs. By successively judging whether a row conflict occurs in the adjacent read and write requests in the command queue, the number of row conflicts can be accumulated. The technical solution provided in this embodiment can accurately determine the requests located in the same bank but in different rows by comparing the three elements in the address information one by one, thereby counting the number of row conflicts.

[0052] Optionally, a counter may be used to count the number of row conflicts and the total number of requests. The monitoring module is configured with a first counter and a second counter. The first counter is used to count the total number of requests. If a placeholder mark is detected, the first counter automatically increases by one. The second counter is used to accumulate the number of row conflicts. If it is determined that adjacent read and write requests have a row conflict, the second counter automatically increases by one. Therefore, it is more convenient and accurate to use a counter to count the total number of requests and the number of row conflicts.

[0053] In view of this, the technical solution provided in this embodiment of the present application performs address comparison for any adjacent read and write requests, thereby determining requests located in the same BankGroup and the same Bank but in different rows, and can accurately calculate the row conflict rate. Using the preset conditional threshold, the row conflict rate interval can be accurately divided, thereby generating a matching page configuration strategy.

[0054] In one embodiment, the DDR controller further includes a bank resource management module. After the above step S7, bank resource management needs to be performed. In practical applications, the number of banks may be large, and it is difficult for the DDR controller to control all banks. Therefore, bank resource management is required. The DDR controller manages the activated banks to improve the processing efficiency of commands.

[0055] In this embodiment, the command queue sends the target address information of the target read and write request currently to be processed to the Bank resource management module; the Bank resource management module allocates Bank resources to the target read and write request according to the target address information, and activates the target page represented by the Bank resources.

[0056] Specifically, the Bank resource management module allocates Bank resources to the target read / write request according to the target address information of the target read / write request. When the target Bank resource of the target read / write request is in an inactive state, the Bank resource management module allocates the corresponding Bank resource to the target read / write request and activates the target page. When the target Bank resource is already in an activated state, it is necessary to wait for the previous read / write request to complete the read / write operation, and then the Bank resource management module allocates the target read / write request to the Bank. If the previous read / write request and the target read / write request access the same BankGroup and the same row of the same Bank, the access operation is performed directly. If the previous read / write request and the target read / write request access different rows of the same BankGroup and the same Bank, the Bank resource management module needs to pre-charge and activate the target page represented by the Bank resource.

[0057] Furthermore, after allocating Bank resources for the target read / write request, the requests in the same Bank and the same row in the command queue are marked. Specifically, for other read / write requests in the command queue except the target read / write request, if the address information of other read / write requests and the address information of the target read / write request are located in the same BankGroup and the same row of the same Bank, the Bank resource management module marks the other read / write requests as ready to issue, and the read / write requests marked as ready to issue in the command queue can be issued continuously if the preset timing requirements are met.

[0058] Furthermore, after allocating Bank resources for the target read / write request, if the target read / write request is located in a different row of the same BankGroup and the same Bank as the previous read / write request, the Bank resource management module issues a precharge command and an activation command to reopen the target page corresponding to the target read / write request.

[0059] In this embodiment, the Bank resource management module pre-configures a threshold counter for the target page. After the target page is activated and turned on, the threshold counter is also needed to manage the opening duration. The threshold counter can ensure that the page remains open during the processing of read and write requests, and can also ensure that the page can be closed in time after opening, thereby reducing system power consumption and resource usage.

[0060] Specifically, a specified value is preloaded in the threshold counter. When the target page is activated and opened, the specified value gradually decreases. When the specified value decreases to a fixed value, the Bank resource management module closes the target page and preloads a new specified value in the threshold counter. After the new page is activated and opened, the new specified value gradually decreases. When the new value decreases to a fixed value, the Bank resource management module closes the new page. Furthermore, the specified value loaded in the threshold counter is determined in the following manner: Type 1: if the row conflict rate is greater than the first threshold and less than the second threshold, the specified value is set to the first value; Type 2: if the row conflict rate is less than or equal to the first threshold, the specified value is set to the second value; Type three: If the row conflict rate is greater than or equal to the second threshold, the specified value is set to a third value; wherein the third value is smaller than the first value, and the first value is smaller than the second value.

[0061] Based on the above ideas, the size of the specified value loaded in the threshold counter is dynamically adjusted according to the size of the row conflict rate, which is the third value, the first value, and the second value in sequence. The page opening time is dynamically adjusted by adjusting the size of the specified value. When there are many row conflicts in read and write requests, reducing the page opening time can speed up access to new rows and reduce access delays caused by row conflicts. At the same time, it will also reduce energy consumption and prevent the controller from being in a high power consumption state during the waiting period for a long time.

[0062] For example, when the row conflict rate is high, the system needs to switch rows frequently, so shortening the open time can improve the memory access efficiency and reduce the performance loss caused by waiting. When the row conflict rate is low, the system often needs to access the data of the same row, so extending the page open time can allow more accesses to hit the same row, thereby reducing repeated row switching and improving the efficiency of memory access.

[0063] The technical solution provided by this embodiment of the present application introduces a Bank resource management module, which is responsible for allocating, activating and managing Bank resources for target read and write requests, thereby optimizing the allocation management and page management of bank resources and improving the processing efficiency of commands. At the same time, read and write requests for the same row in the same BankGroup and the same Bank can be issued continuously while meeting the DDR timing requirements, thereby reducing the delay of the switch page, reducing the system consumption caused by the switch page, and improving the efficiency of the read and write request processing.

[0064] Based on the above ideas, the technical solution provided by one or more embodiments of the present application can generate a page configuration strategy according to the address information of the read and write requests, and dynamically perform page configuration. First, obtain the address information of the read and write requests in the command queue containing the read and write requests, calculate the row conflict rate of the read and write requests according to the above address information, and then generate an adaptive page configuration strategy according to the numerical value of the above row conflict rate, and finally dynamically configure the pages of the memory according to the above page configuration strategy. It can be seen that through the technical solution provided by one or more embodiments of the present application, page configuration can be performed dynamically, so that when the row conflict rate is high, a closed page strategy is adopted to reduce the power consumption of the memory system, and when the row conflict rate is low, an open page strategy is adopted to reduce request latency and improve system performance, thereby providing a more efficient page configuration strategy.

[0065] See also Figure 3 The present application provides an embodiment of applying the above-mentioned page configuration method, and the embodiment is performed according to the following steps: Step S101: The command queue in the DDR controller sends the address information of the read and write requests therein to the monitoring module; Step S103: The monitoring module receives the address information of the read and write request sent by the command queue, and identifies the Bank Group, Bank and row address information therein. At the same time, the monitoring module is equipped with two counters, the first counter is used to count the total number of requests in the command queue, and the second counter is used to count the number of row conflicts in the command queue. The monitoring module calculates the row conflict rate based on the number of row conflicts and the total number of requests and sends it to the arbitration module.

[0066] In this embodiment, the monitoring module counts the total number of requests in the command queue, and when a full_list signal is identified, the total number of requests in the first counter is increased by 1. Specifically, the command queue contains multiple entry information, each entry information contains a full_list signal, and when there is a request in the corresponding entry information, the corresponding bit of the full_list signal in the entry is pulled high, and each time there is a full_list signal that is pulled high, the first counter is increased by 1, thereby determining the total number of requests in the counted command queue.

[0067] In this embodiment, the monitoring module counts the number of row conflicts in the command queue, and when the BankGroup address and the Bank address of the address information of two adjacent requests in the command queue are the same but the row addresses are different, the number of the second counter is increased by 1. Each two adjacent requests in the command queue are traversed in turn to determine the number of row conflicts in the command queue.

[0068] Further, the row conflict rate is determined according to the total number of requests and the number of row conflicts in the command queue. Specifically, the row conflict rate is the ratio of the number of row conflicts to the total number of requests.

[0069] Step S105: the arbitration module determines whether the row conflict rate sent by the monitoring module meets a predetermined condition, thereby determining the configured page strategy.

[0070] In one implementation of this embodiment, if the row conflict rate meets preset condition 1, that is, the row conflict rate calculated by the monitoring module is greater than the first threshold and less than the second threshold, the register module maintains the original configuration unchanged, that is, maintains the original page strategy.

[0071] In one implementation of the present embodiment, if the row conflict rate satisfies the preset condition 2, that is, the row conflict rate calculated by the monitoring module is less than the first threshold value, the automatic precharge function of each command is disabled and the page strategy of opening the page is adopted. Specifically, the register module configures the corresponding parameters for automatic precharge, disables the automatic precharge function, and sends the parameters to the command queue module. When the row conflict rate is low, disabling the automatic precharge function can save the time of reopening pages without row conflicts. Therefore, configuring the parameters of automatic precharge for the requests in the command queue can improve the memory access efficiency.

[0072] In one implementation of this embodiment, if the row conflict rate satisfies the preset condition 3, that is, the row conflict rate calculated by the monitoring module is greater than the second threshold, the automatic precharge function of each command is enabled and the closed page strategy is adopted. Specifically, the register module configures corresponding parameters for automatic precharge, enables the automatic precharge function and sends the parameters to the command queue.

[0073] Also, see Figure 4 In the page opening strategy, each page is provided with a threshold counter and a judgment logic, which are used to adaptively adjust the page opening time to meet different memory access requirements. Specifically, the counter for opening the page is loaded with a threshold value, and the setting of the threshold value is determined by the row conflict rate in the command queue of the DDR controller. When the row conflict rate is too high, the threshold value will be appropriately reduced, and when the row conflict rate is too low, the threshold value will be appropriately increased. When the page enters the open state, the threshold value will gradually decrease. When it decreases to a fixed value, the open page will be closed, and a new initial threshold value will be loaded into the counter for recounting. According to the row conflict rate, the size of the threshold value is dynamically adjusted, thereby adaptively adjusting the page opening time and improving the efficiency of memory access. Among them, the row buffer sensitive amplifier can be understood as a page for reading and writing corresponding data.

[0074] In this embodiment, when the DDR controller issues a refresh request, it also sends an enable signal to the judgment logic, closes the corresponding open page, and reloads the initial threshold in the counter to re-count when the page is opened next time. It should be noted that the DDR controller needs to periodically refresh all working rows in the Bank to retain the data in the storage unit. In practical applications, the currently recognized refresh speed is equal to the number of rows / 64ms, and the refresh command is valid for one row at a time, so the time interval for sending the refresh signal varies with the total number of rows.

[0075] Please refer to Figure 5 The present application provides another embodiment, which configures a Bank resource management module and applies it to the above-mentioned dynamic page management strategy method. The embodiment is performed according to the following steps: Step S301: When the command queue receives a new read / write request, the command queue sends the address information of the read / write request to the Bank resource management module.

[0076] Step S303: The Bank resource management module allocates resources to the corresponding Bank according to the address information of the read / write request.

[0077] In one implementation of this embodiment, when the bank resources corresponding to the new request command are not allocated, the bank resource management module allocates bank resources for the command and issues an activation command to open the row corresponding to the new command. In addition, the commands in the command queue with the same address information as the new command will be marked as ready to ensure that the commands of the same page can be issued continuously.

[0078] In one implementation of this embodiment, when the Bank resources corresponding to the new request command have been allocated and are in the same row as the previous command, the access is continued directly after the previous command access is completed.

[0079] In one implementation of this embodiment, when the bank resources corresponding to the new request command have been allocated and the command is in a different row from the previous command, the DDR controller will allocate the same bank resources to the new command, and issue a precharge command and an activation command to reopen the row corresponding to the new command. In addition, the command in the command queue with the same address information as the new command will be marked as ready, and the commands of the same page can be issued continuously after the timing requirements are met.

[0080] Step S305: After the Bank resources are allocated, the resources are recycled.

[0081] Specifically, after the Bank resources are allocated, the resources are selectively recycled, including recycling the Bank resources of commands that have been opened and have no corresponding pages in the command queue, recycling the Bank resources that are being refreshed, and recycling the Bank resources of the Bank where row conflicts occur.

[0082] In one implementation of the present embodiment, the Bank resource management module can recycle the allocated Bank resources. To recycle the allocated Bank resources, the open page is precharged and closed. For an already opened page, if there is no read or write instruction matching the page in the command queue, the Bank resources of the already opened page are reclaimed; for a page with a row conflict, the corresponding Bank resources are reclaimed. Timely recycling of Bank resources can speed up the Bank resource allocation process for subsequent requests and improve the processing efficiency of read and write requests.

[0083] In view of this, in the embodiment of the present application, the row conflict rate in the command queue is counted and calculated in the monitoring module of the DDR controller, the preset condition corresponding to the row conflict rate is judged in the arbitration module, and the corresponding page strategy is determined and switched according to the judgment result. Among them, under the page opening strategy, the opening time of the corresponding page is adaptively adjusted according to the row conflict rate, so as to switch the page in real time, thereby improving the system's ability to cope with dynamic changes in memory access requests and reducing the power consumption of the memory system.

[0084] In a possible implementation, the DDR controller sends different commands to implement the above-mentioned page configuration method, including a refresh command, an activation command, a precharge command, and a read / write command, wherein the command truth table of the DDR controller is shown in Table 1, and the timing waveforms of the commands corresponding to the page management strategy are shown in Figures 6(a) to (d), specifically: Table 1 DDR memory command truth table As shown in Table 1, CKE is the clock enable signal; CS_n is the rank chip select enable signal; ACT_n is the activation signal; RAS_n, CAS_n, and WE_n are command input signals used to determine the input code of the current command; BG0-BG1 are address selection signals used to determine the BankGroup address; BA0-BA1 are address selection signals used to determine the Bank address. Among them, 'H' represents a high level, and 'L' represents a low level. When the activation command is issued, ACT_n is a low level, and RAS_n, CAS_n, and WE_n are used as address lines, that is, RA in the table. When ACT_n is a high level, RAS_n, CAS_n, and WE_n are used as command codes.

[0085] Please refer to Figures 6(a) to (d), Figure 6(a) is a timing waveform diagram of the access command, and Figures 6(b), 6(c) and 6(d) are timing waveform diagrams of phase I, phase II and phase III in Figure 6(a), respectively. The clock enable signal of the current page is always at a high level. For example, when CS_n, ACT_n, RAS_n, CAS_n, and WE_n all become low levels, it indicates that an activation command is issued. When CS_n, RAS_n, and WE_n become low levels and ACT_n and CAS_n become high levels, it indicates that a precharge command is issued. When CS_n and CAS_n become low levels and ACT_n, RAS_n, and WE_n become high levels, it indicates that a write command is issued.

[0086] In this embodiment, FIG6(b) represents the stage I in FIG6(a), at which the page adopts the open page strategy and sends a precharge command between two read and write requests. FIG6(c) represents the stage II in FIG6(a), at which the row conflict rate is high, the page adopts the closed page strategy, and does not need to send a precharge command, but configures an automatic precharge command. FIG6(d) represents the stage III in FIG6(a), at which the row conflict rate is low, the page adopts the open page strategy, and the read and write requests can be sent continuously.

[0087] In view of this, in an embodiment of the present application, the page strategy is dynamically adjusted and switched according to the size of the row conflict rate, which improves the system's ability to cope with dynamic changes in access requests and reduces system power consumption, thereby providing a more efficient page management strategy.

[0088] See also Figure 7 The present application also provides a DDR controller, the controller comprising a command queue, a monitoring module, an arbitration module and a register, wherein: The command queue is used to store pending read and write requests and send address information of the pending read and write requests to the monitoring module; The monitoring module is used to determine the row conflict rate of the read and write requests in the command queue based on the received address information, and send the row conflict rate to the arbitration module; The arbitration module is used to match the received row conflict rate with a preset condition threshold, and dynamically generate a page configuration strategy according to the row conflict rate interval represented by the matching result, and send the page configuration strategy to the register; wherein the generated page configuration strategy is at least used to represent an open page strategy or a closed page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the closed page strategy; The register is used to execute the page configuration policy and transfer the configuration parameters represented by the page configuration policy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters.

[0089] In this embodiment, the command queue is specifically used to process read and write requests from the processor according to the configuration parameters passed in the register after receiving the read and write requests. The command queue stores multiple entry information that can store pending read and write requests to wait for access operations, and sends the address information of the pending read and write requests to the monitoring module.

[0090] In this embodiment, the monitoring module is specifically used to receive address information of read and write requests from the command queue, count the total number of read and write requests to be processed in the command queue, and accumulate the number of row conflicts to calculate the row conflict rate of the read and write requests in the command queue, and send the row conflict rate to the arbitration module.

[0091] In this embodiment, the arbitration module is specifically used to receive the row conflict rate calculated by the monitoring module, compare the row conflict rate with a preset condition threshold, determine the range of the row conflict rate, and then determine a matching page configuration strategy.

[0092] In this embodiment, the register module is specifically used to perform page configuration according to a specified page configuration strategy and pass configuration parameters to the command queue, wherein the configuration parameters may include automatic precharge parameters. The register is a storage device in a computer processor for storing instructions, data and addresses.

[0093] In one embodiment, the DDR controller further includes a Bank resource management module, which is used to allocate Bank resources to the target read / write request according to the target address information sent by the command queue, and activate the target page represented by the Bank resources.

[0094] In this embodiment, the command queue is also used to send the target address information of the target read / write request to be processed to the Bank resource management module.

[0095] The further functional description of each of the above modules is the same as that of the corresponding method embodiments above, and will not be repeated here.

[0096] See also Figure 8 The present application also provides a system on chip, the system on chip comprising a DDR controller, a processor core and a memory, wherein: The processor core is used for processing the instruction obtained by the DDR controller from the memory, and writing the processing result into the memory through the DDR controller; The DDR controller is used to execute the above-mentioned page configuration method on the memory.

[0097] In this embodiment, when the processor core needs to read or write data to the memory, an access request is generated, which includes the memory address, the operation type (read request or write request), and the data to be transmitted. The DDR controller receives and parses the access request from the processor core, and prepares the corresponding memory command according to the memory address and the operation type. The DDR controller puts the memory command into a command queue and sends the command in the command queue to the memory. For a read request, the data read from the memory by the DDR controller is transmitted back to the processor core via the internal bus. For a write request, the data provided by the processor core is transmitted to the DDR controller via the internal bus and then written to the memory.

[0098] The processor core may be selected as: CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), TPU (Tensor Processing Unit), DPU (Deep Learning Processing Unit), microprocessor, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or a combination of at least two of these processor forms. The memory stores instructions that can be executed by at least one processor, and the at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0099] The above memory can be implemented by DDR memory particles, and the DDR memory particles are DDR SDRAM (Double Data Rate SDRAM, double rate synchronous dynamic random access memory). The storage unit storage order is organized into a multi-level structure, namely channel, DIMM, rank, chip, Bank, row, column, and one channel corresponds to a DDR controller. Among them, each group of ranks can be regarded as an independent memory module, with an independent address space and control logic, and can perform read and write operations independently. In the memory controller, different memory modules can be accessed by selecting different ranks, thereby realizing parallel access to multiple ranks and improving memory bandwidth and performance.

[0100] The systems described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0101] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods and systems. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0102] The present application is described with reference to the flowcharts and / or block diagrams of the methods and systems according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0103] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0104] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0105] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0106] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0107] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0108] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A page configuration method, characterized in that: Applied to a DDR controller, the DDR controller comprises a command queue, a monitoring module, an arbitration module and a register, the command queue is used to store pending read and write requests, the method comprises: the command queue sends address information of the pending read and write requests to the monitoring module; The monitoring module determines the row conflict rate of the read and write requests in the command queue based on the received address information, and sends the row conflict rate to the arbitration module; The arbitration module matches the received row conflict rate with a preset condition threshold, and dynamically generates a page configuration strategy according to the row conflict rate interval represented by the matching result, and sends the page configuration strategy to the register; wherein the generated page configuration strategy is at least used to represent an open page strategy or a closed page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the closed page strategy; The register executes the page configuration policy and transfers the configuration parameters represented by the page configuration policy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters.

2. The method according to claim 1, characterized in that The preset condition threshold includes a first threshold and a second threshold; The page configuration strategy dynamically generated according to the row conflict rate interval represented by the matching result includes: If the row conflict rate interval represented by the matching result is greater than the first threshold and less than the second threshold, generating a retention strategy representing the retention of the original page configuration strategy; If the row conflict rate interval represented by the matching result is less than or equal to the first threshold, generating a page opening policy representing disabling the automatic precharge function; If the row conflict rate interval represented by the matching result is greater than or equal to the second threshold, a closed page policy representing enabling of the automatic precharge function is generated.

3. The method according to claim 1, characterized in that The DDR controller also includes a Bank resource management module; the method also includes: The command queue sends the target address information of the target read / write request to be processed to the Bank resource management module; the Bank resource management module allocates Bank resources to the target read / write request according to the target address information, and activates the target page represented by the Bank resources.

4. The method according to claim 3, characterized in that The Bank resource management module pre-configures a threshold counter for the target page, and a specified value is pre-loaded in the threshold counter; after the target page is activated and opened, the method further includes: The specified value gradually decreases, and when the specified value decreases to a fixed value, the Bank resource management module closes the target page and loads a new value in the threshold counter; wherein, after the new page is activated and opened, the new value gradually decreases, and when the new value decreases to a fixed value, the Bank resource management module closes the new page.

5. The method according to claim 4, characterized in that The specified value loaded in the threshold counter is determined as follows: If the row conflict rate is greater than a first threshold and less than a second threshold, setting the specified value to the first value; If the row conflict rate is less than or equal to the first threshold, setting the specified value to a second value; If the row conflict rate is greater than or equal to the second threshold, setting the specified value to a third value; The third value is smaller than the first value, and the first value is smaller than the second value.

6. The method according to claim 3, characterized in that After allocating Bank resources for the target read / write request, the method further includes: For other read / write requests in the command queue except the target read / write request, if the address information of the other read / write requests indicates that the other read / write requests and the target read / write request are located in the same row of the same bank, the bank resource management module marks the other read / write requests as ready to be issued; Wherein, the read and write requests marked as being in a ready-to-issue state in the command queue are continuously issued when a preset timing requirement is met.

7. The method according to claim 3, characterized in that After allocating Bank resources for the target read / write request, the method further includes: If the target read / write request and the previous read / write request are located in different rows of the same Bank, the Bank resource management module issues a precharge command and an activate command to reopen the target page corresponding to the target read / write request.

8. The method according to claim 1, characterized in that The monitoring module determines the row conflict rate of the read and write requests in the command queue based on the received address information, including: The monitoring module counts the total number of the pending read and write requests in the command queue; The monitoring module traverses the adjacent first read / write request and the second read / write request in the read / write request to be processed, and compares the first address information of the first read / write request with the second address information of the second read / write request to obtain an address comparison result; when the address comparison result indicates that the first read / write request and the second read / write request are located in the same BankGroup, the same Bank, and in different rows, the number of row conflicts is accumulated; The ratio of the accumulated number of row conflicts to the total number of requests is determined as the row conflict rate of the read and write requests in the command queue.

9. A DDR controller, characterized in that: The DDR controller includes a command queue, a monitoring module, an arbitration module and a register, wherein: The command queue is used to store pending read and write requests and send address information of the pending read and write requests to the monitoring module; The monitoring module is used to determine the row conflict rate of the read and write requests in the command queue based on the received address information, and send the row conflict rate to the arbitration module; The arbitration module is used to match the received row conflict rate with a preset condition threshold, and dynamically generate a page configuration strategy according to the row conflict rate interval represented by the matching result, and send the page configuration strategy to the register; wherein the generated page configuration strategy is at least used to represent an open page strategy or a closed page strategy, and the row conflict rate under the open page strategy is lower than the row conflict rate under the closed page strategy; The register is used to execute the page configuration policy and transfer the configuration parameters represented by the page configuration policy to the command queue, so that the read and write requests in the command queue are processed according to the configuration parameters.

10. A system on chip, characterized in that: The system on chip includes a DDR controller, a processor core and a memory, wherein: the processor core is used to process instructions obtained by the DDR controller from the memory, and write the processing results into the memory through the DDR controller; The DDR controller is used to execute the page configuration method as claimed in any one of claims 1 to 8 on the memory.

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