Cache device and operation method thereof, processor, device and medium

Abstract

A cache device, an operation method of the cache device, a processor, a device and a medium. The cache device comprises a plurality of cache spaces, and the plurality of cache spaces comprise a first cache space for caching a page table entry according to a page table entry caching rule. The operation method for the cache device comprises: receiving a first cache request; and in response to an operation object of the first cache request comprising a first page table entry, writing the first page table entry into the first cache space according to the page table entry caching rule. The operation method of the cache device can prevent a processor page table access miss caused by cache flushing, and improve the memory access performance of the processor.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a caching device, a method of operating the caching device, a processor, an apparatus, and a medium. Background Technology

[0002] With the development of technologies such as cloud computing and big data, and the continuous growth in the demand for memory capacity, various high-capacity memory technologies are also constantly developing. Since the processor needs to translate the virtual address into the physical address through the corresponding page table entry before accessing memory resources, it is very important to quickly access the target page table entry for fast access to memory resources. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an operation method for a caching device, the caching device including a plurality of cache spaces, the plurality of cache spaces including a first cache space allocated for caching page table entries according to page table entry caching rules, the operation method of the caching device including receiving a first cache request; and responding to the first cache request by an operation object including a first page table entry, writing the first page table entry into the first cache space according to the page table entry caching rules.

[0004] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, the plurality of cache spaces further include a second cache space for caching data items; the operation method of the caching device further includes: receiving a second cache request; and writing the first processed data into the second cache space in response to the operation object of the second cache request being first processed data.

[0005] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, the method further includes: receiving a second caching request; and writing the first processing data into the first cache space in response to the operation object of the second caching request being first processing data and the first cache space including free cache lines.

[0006] For example, in the operation method of the cache device provided in at least some embodiments of this disclosure, the cache device is configured as a first-level cache, a second-level cache, or a third-level cache for the processor.

[0007] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, the caching device is a group-associative mapping, and the multiple cache spaces are multiple cache groups or multiple cache paths of the caching device, and the first cache space includes some cache groups or some cache paths of the caching device.

[0008] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, page table entry caching rules are read from the configuration register.

[0009] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, page table entries are written to the configuration register to cache rules.

[0010] For example, in the operation method of the cache device provided in at least some embodiments of this disclosure, writing page table entry cache rules into the configuration register includes: writing page table entry cache rules in response to monitoring information of the processor including the cache device or monitoring information of the cache device itself; or, the page table entry cache rules are written by a user of the processor including the cache device.

[0011] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, the page table entry caching rules are written by a user for a processor including the caching device, including: the user analyzes the microarchitecture state information of the processor through a hardware counter and provides the analysis results for adjusting the page table entry caching rules.

[0012] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, the page table entry caching rules are determined by the page table mask in the configuration register.

[0013] For example, in the operation method of the caching device provided in at least some embodiments of this disclosure, the page table mask includes multiple bits, each bit corresponding to a multiple cache space. When each bit is a first value, it indicates that the corresponding cache space is allocated for caching page table entries. When each bit is a second value, it indicates that the corresponding cache space is not allocated for caching page table entries.

[0014] At least one embodiment of this disclosure also provides a caching device, which includes a plurality of cache spaces and a cache controller. The cache controller is configured to determine a first cache space among the plurality of cache spaces for caching page table entries according to page table entry caching rules, and to write the first page table entry into the first cache space in response to a received first cache request, the operation object of which includes the first page table entry.

[0015] At least one embodiment of this disclosure also provides a processor, which includes a caching device and a configuration register provided in any embodiment of this disclosure, the configuration register being configured to store page table entry caching rules.

[0016] For example, in the processor provided in at least some embodiments of this disclosure, the processor includes multiple hardware threads or multiple processor cores, and the page table entry caching rules include setting multiple page table entry caching sub-rules for each of the multiple hardware threads or multiple processor cores.

[0017] For example, in the processor provided in at least some embodiments of this disclosure, the page table entry caching rule sets the object page table entry caching sub-rules of the object hardware thread in multiple hardware threads by using multiple service type markers corresponding to multiple hardware threads respectively.

[0018] For example, the processor provided in at least some embodiments of this disclosure also includes a monitoring module configured to dynamically monitor the page table cache miss rate or data cache miss rate of the caching device and provide monitoring results for adjusting page table entry caching rules.

[0019] At least some embodiments of this disclosure also provide an electronic device, including a cache device or a processor provided in any embodiment of this disclosure.

[0020] At least some embodiments of this disclosure also provide a non-transitory storage medium that non-transitoryly stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, they implement the operation method of the cache device provided in any embodiment of this disclosure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1 A flowchart illustrating a processor reading data is shown;

[0023] Figure 2 A schematic diagram of an address translation process using page tables is shown.

[0024] Figure 3 A flowchart illustrating an operation method of a caching device provided in at least one embodiment of this disclosure is shown;

[0025] Figure 4 A schematic diagram illustrating the group-associative organization and addressing mode of a cache device provided in at least one embodiment of the present disclosure is shown;

[0026] Figure 5 This illustration shows an operational diagram of a multi-level cache based on a cache path, provided by at least one embodiment of the present disclosure.

[0027] Figure 6 This illustration shows an operation diagram of multi-level caching by cache group according to at least one embodiment of the present disclosure;

[0028] Figure 7 This illustration shows an operational diagram based on a service type identifier provided in at least one embodiment of the present disclosure;

[0029] Figure 8 This diagram illustrates an operation flowchart of a caching device provided in at least one embodiment of the present disclosure;

[0030] Figure 9 This diagram illustrates a page table entry caching rule writing method provided in at least one embodiment of the present disclosure.

[0031] Figure 10 This diagram illustrates a page table entry caching rule writing method provided in at least one embodiment of the present disclosure.

[0032] Figure 11 A block diagram of a caching device provided in at least one embodiment of the present disclosure is shown;

[0033] Figure 12 A block diagram of a processor provided in at least one embodiment of the present disclosure is shown;

[0034] Figure 13 A schematic diagram of the structure of an electronic device provided in at least one embodiment of this disclosure is shown; and

[0035] Figure 14 A schematic diagram of a non-transitory storage medium provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0038] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components are omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is indicated by the same or similar reference numerals in each drawing.

[0039] The terminology used in this disclosure is that which is currently widely used in the art in consideration of the functionality of this disclosure; however, these terms may vary depending on the intent, precedent, or new technology of those skilled in the art. Furthermore, specific terms may be chosen by the applicant, and in such cases, their detailed meanings will be described in the detailed description of this disclosure. Therefore, the terminology used in this specification should not be construed as simple names, but rather based on the meaning of the terms and the overall description of this disclosure.

[0040] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0041] With the development of emerging industry technologies, the demand for memory capacity from various applications is constantly increasing. For accessing large amounts of memory, modern computer systems (such as LINUX) use page tables for memory management. For example, whenever an application accesses a page, the processor, upon receiving the access request, first looks up the page table (PTE) to translate the virtual address of the access request into the actual physical address in memory.

[0042] Figure 1 A flowchart illustrating a processor reading data is shown. For example... Figure 1 As shown, the data reading process of the processor includes the following steps S01-S07. It should be noted that the processor here can also be replaced by other processing devices or units with information processing capabilities. For example, for a multi-core processor, the processor here can also be replaced by one of the processor cores.

[0043] Step S01: The processor (or processor core) outputs the virtual address of the target data or instruction of the access request to the address translator 101 (e.g., an address translation pipeline), which translates the virtual address into a physical address. The processor then determines whether the target data or instruction of the access request is in the first-level cache (e.g., L1 cache). The access request can be a data or instruction read request; for example, the address translator 101 stores page tables for address translation.

[0044] Step S02: If the target data or instruction of the access request exists in the first-level cache, retrieve the target data or instruction of the access request from the first-level cache, and send the target data or instruction of the access request to the processor through the following step S07.

[0045] Step S03: If the target data or instruction of the access request does not exist in the first-level cache, then request a storage item from the miss address cache (MAB) 102 and allocate the storage item to the above access request.

[0046] Step S04: Cache miss 102 requests the target data or instruction of the access request from the next level cache (e.g., the second-level cache, L2 Cache) based on the storage item.

[0047] Step S05: The next level cache retrieves the target data or instruction of the access request and returns the target data or instruction of the access request to the cache of the missed address.

[0048] like Figure 1 As shown, if the target data or instruction of the access request is stored in the L2 cache, the L2 cache retrieves the target data or instruction from the L2 cache. If the target data or instruction of the access request is not stored in the L2 cache, the L2 cache can retrieve the target data or instruction from the memory located at the next level below the L2 cache. For example, the memory located at the next level below the L2 cache can be a L3 cache, a L4 cache (e.g., the Last Level Cache), or memory (e.g., DRAM).

[0049] Step S06: Address cache miss 102 Write the target data or instruction of the access request to the first-level cache.

[0050] Step S07: The first-level cache provides the target data or instruction of the access request to the processor for further processing.

[0051] Because access requests involve a wide variety of data that the processor needs to process, caches (such as the first or second level cache mentioned above) may only store data that the processor has recently accessed. Therefore, when there is a large volume of data access in a short period, previously cached data, limited by cache size, may be evicted (flushed) from the cache. This forces some cached data to be retrieved from memory (e.g., DRAM), degrading processor access performance. Therefore, a cache allocation technique is proposed.

[0052] For example, the first-level cache or the second-level cache can be partitioned. For instance, multiple data types that an access request might access can be allocated corresponding cache spaces in the first-level cache or the second-level cache. For example, the first cache space in the first-level cache stores data, and the second cache space in the first-level cache stores instructions. Thus, after the physical address of the access request is determined by the address translator 101 (e.g., after step S01 above), the system can determine whether the access request is for reading data or reading instructions, and then access the corresponding first or second cache space in the first-level cache (e.g., the target data or instruction of the access request in step S02 above exists in the first-level cache).

[0053] For example, when a processor includes multiple processing cores or multiple processing threads, the aforementioned Level 1 cache or Level 2 cache can also be divided into different cache spaces according to different processing cores or different processing threads.

[0054] The aforementioned cache allocation techniques, while offering some improvement for data that doesn't need to be evicted from the cache processor and preventing some data from being replaced by a large number of short-term accesses, still have limitations. Figure 1 In the processor data reading process of steps S01-S07 above, the processor first needs to use the address translator 101 to translate the virtual address into a physical address through the page table, and then use the physical address to search for the target data or instruction in the first or second level cache in order to achieve the purpose of accessing the target data.

[0055] Therefore, if the address translator 101 misses an address during the address translation process, even if some data is prevented from being replaced, the processor's overall processing efficiency for access requests cannot be improved. Especially when dealing with an application that requires a large amount of memory, the address translator 101 will be limited by storage space and unable to effectively manage the large amount of memory required by the application.

[0056] To address the aforementioned address translation problem in page tables, a multi-level page table index translation method is proposed, which supports a larger address space within a limited storage space by using multi-level page tables.

[0057] For example, a page table (PTE) is multi-level. Each level of the page table can be regarded as a translation from a "virtual address" to a "physical address". However, the "virtual address" here is a subset of the bit fields of the virtual address to be translated. Except for the last level page table PTE, which directly points to the physical page, the "physical address" in other levels of page tables points to the starting address of the corresponding next level page table.

[0058] Figure 2 This is a schematic diagram of an address translation process using page tables, illustrating the address translation process of a four-level page table.

[0059] like Figure 2As shown, a virtual address is divided into several segments, for example, represented as EXT, OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, OFFSET_lvl1, and OFFSET_pg. In this example, the higher-order virtual address segment EXT is not used. The virtual address segments OFFSET_lvl4, OFFSET_lvl3, OFFSET_lvl2, and OFFSET_lvl1 represent the offset values ​​of the four-level page tables, respectively. That is, OFFSET_lvl4 represents the offset value of the fourth-level page table, OFFSET_lvl3 represents the offset value of the third-level page table, OFFSET_lvl2 represents the offset value of the second-level page table, and OFFSET_lvl1 represents the offset value of the first-level page table. The initial address of the highest-level page table (i.e., the fourth-level page table) is stored in the architecture register REG_pt, the contents of which are set by the operating system and cannot be changed by the application program. In the second-level, third-level, and fourth-level page tables, each page table entry stores the starting address of the next-level page table. The first-level page table entry (PTE) stores the high-order bits of the physical address of the corresponding memory page. Combining this with the virtual address offset (OFFSET_pg) yields the physical address corresponding to that virtual address. Thus, by obtaining the starting address of the next-level page table level by level in this manner, the first-level page table entry (PTE) can be obtained, and subsequently, the corresponding physical address can be derived, achieving the translation from virtual address to physical address.

[0060] While using more page table levels in a limited space can support a larger memory address space, it slows down the translation process from virtual address to physical address, thus reducing processor performance.

[0061] For example, a typical Page Table Entries (PTE) is 8 bytes in size, and a typical page size is 4KB (also known as a memory page). The ratio of PTE size to page size is 1:512. For a 32MB cache, it can store 4MB of PTE entries, corresponding to a maximum of 16GB of data. Assuming that the application's hotspot memory accesses 20% of the total memory, once the application's memory requirements exceed 80GB (80GB * 20% = 16GB), the 4MB page table entries will be insufficient to manage all the memory.

[0062] Furthermore, excessively large amounts of data accessed during hotspots will cause at least two misses during each application memory access: one for page table access and one for data cache miss, resulting in two misses for access requests and severely degrading processor memory access performance.

[0063] To address the aforementioned problems, at least one embodiment of this disclosure provides an operation method for a caching device. The caching device includes multiple cache spaces, including a first cache space allocated for caching page table entries according to page table entry caching rules. The operation method includes: receiving a first cache request; responding to the first cache request by an operation object including a first page table entry, and writing the first page table entry into the first cache space according to the page table entry caching rules.

[0064] In the operation method of the caching device of the above embodiments of this disclosure, since page table entries are written into the first cache space according to the page table entry caching rules, and page table entries are cached in isolation from other data types, page table entries can have independent cache space; and since independent cache space is set up, protection is formed for the page table entries stored in the caching device, so that even under the condition of a large amount of data access, page table entries will not be flushed out of the cache by data, so that when the processor processes access requests, page table cache misses will not occur, improving the efficiency of virtual address to physical address translation, thereby improving the processor's memory access performance.

[0065] The various embodiments of this disclosure will now be described with reference to specific examples.

[0066] Figure 3 A flowchart illustrating an operation method of a caching device provided in at least one embodiment of the present disclosure is shown.

[0067] like Figure 3 As shown, in some embodiments of this disclosure, the operation method of the cache device includes steps S30 and S31.

[0068] Step S30: Receive the first cache request.

[0069] Step S31: The operation object in response to the first cache request includes the first page table entry. The first page table entry is written into the first cache space according to the page table entry caching rules.

[0070] The aforementioned caching device includes multiple cache spaces, including a first cache space allocated for caching page table entries according to page table entry caching rules. The first cache space can be any one of the multiple cache spaces, which may be equal or unequal cache spaces divided within the caching device. In the above description, "first cache request" refers to the cache request as the object of description, such as a read request or a write request; "first page table entry" refers to the page table entry as the object of description, and the operation object of its cache request corresponds to either a read request or a write request, which can be the object being read or the object being written.

[0071] A caching device consists of multiple cache sets, each containing multiple cache lines, which are the basic units of a cache. For example, in a set-associative cache, a cache set can be divided into multiple cache paths, each capable of independently storing different data blocks. Multiple cache paths allow for greater flexibility in data storage within the same cache set, thereby reducing cache conflicts and improving cache efficiency.

[0072] For example, the cache device can be a storage array composed of random-access memory (RAM). For instance, the RAM array includes a tag array and a data array, used to store tag information and data information in the access address of the stored object (e.g., data or instructions), respectively. For example, the tag array and data array can also be referred to as a data RAM array and a tag RAM array, respectively. For example, the RAM can be static random-access memory (SRAM), and the data array can also be a data SRAM array.

[0073] In embodiments of this disclosure, the page table entry caching rule is a rule for selecting a first cache space from multiple cache spaces for caching page table entries.

[0074] For example, page table entry caching rules can be set separately for different processor cores or for different threads. For instance, different page table entry caching rules can be set for applications running on different processor cores or in different threads, depending on their characteristics. Alternatively, a separate page table entry caching rule can be set for each processor core or each thread, increasing the flexibility of cache partitioning. For example, the first cache request can be determined based on the access requests issued by the processor.

[0075] For example, the cache operation requested by the first cache request is a page table entry, and the first page table entry can be any page table entry among all page table entries.

[0076] In some embodiments of this disclosure, the cache device in the operation method of the cache device is configured as a first-level cache, a second-level cache, or a third-level cache for the processor.

[0077] A processor may include multiple processor cores, which share a cache and each has its own dedicated cache. For example, each processor core's dedicated cache may include a Level 1 cache (L1 cache) or a Level 2 cache (L2 cache), or each processor core may have different Level 1 and Level 2 caches. For example, the shared cache shared by multiple processor cores may include a Level 3 cache.

[0078] The Level 1 cache (hereinafter referred to as L1) is used to store the most frequently used data and instructions. L1 capacity is usually small, for example, tens of KB, but access speed is very fast. For example, L1 uses static RAM (SRAM).

[0079] The second-level cache (hereinafter referred to as L2) is used to store more data and instructions to provide more backups when the L1 cache is missed. The L2 capacity is usually larger than the L1, for example, the L2 capacity is between 256KB and several MB. L2 access is faster but slower than the L1 cache.

[0080] The Level 3 cache (hereinafter referred to as L3) is used to enable multiple processor cores to share the same cache, which helps reduce data transfer latency between processor cores. The L3 cache is usually much larger than the L1 and L2 caches, and L3 access speed is slower than L1 and L2.

[0081] For example, the first cache space can be divided into one or more of the first-level cache, second-level cache, or third-level cache.

[0082] For example, a portion of the capacity on the first, second, or third level cache can be used as the first cache space for caching page table entries.

[0083] For example, the size of a page table entry is 8 bytes, and the size of a page (also known as a memory page) is 4KB.

[0084] For example, if the capacity of the first cache space on L1 is 64KB, then L1 can store 64KB / 8Bytes = 8K (thousands) page table entries, and can cover a maximum memory size of 8K*4KB = 32MB.

[0085] For example, if the capacity of the first cache space on L2 is 1MB, then L2 can store 1MB / 8B = 128K (thousands) page table entries, and can cover a maximum memory size of 128K * 4KB = 512MB.

[0086] For example, if the capacity of the first cache space on L3 is 32MB, then L3 can store 32MB / 8B = 4M (megabytes) page table entries, which can cover a maximum memory size of 4M * 4KB = 16GB.

[0087] For example, by dividing the first cache space on the first cache, second cache, or third cache, page table coverage can be achieved for different memory sizes, allowing the page table to translate the physical addresses of different memory sizes.

[0088] It should be noted that although the above embodiments are described using three levels of cache, namely the first level cache, the second level cache and the third level cache, in some necessary cases, the cache device may further include a fourth level cache or a fifth level cache, etc. The fourth level cache or the fifth level cache may be located inside the processor or outside the processor. This disclosure does not limit the number and location of the cache.

[0089] In some embodiments of this disclosure, the caching device is a multi-level cache. For example, the caching device may include a first-level cache and a second-level cache, or a first-level cache, a second-level cache, and a third-level cache.

[0090] In some embodiments of this disclosure, the cache device in the operation method of the cache device is a group-associative mapping. For example, multiple cache spaces are multiple cache groups or multiple cache paths of the cache device, and the first cache space includes some cache groups or some cache paths of the cache device.

[0091] For example, at least one or more of the first-level cache, second-level cache, and third-level cache are set-associative mappings.

[0092] Figure 4 A schematic diagram is shown illustrating the group-associative organization and addressing mode of a cache device provided in at least one embodiment of the present disclosure.

[0093] like Figure 4 As shown, a cache device can be organized as a cache set. A column of cache rows forms a way, and multiple cache rows at the same position in multiple columns form a group. A cache device includes multiple cache sets. The location (Set, Way, Byte) of the accessed data or instruction in the cache device is obtained by reading the access address of the access request. Each access address can include:

[0094] (a) The index section is used to select a cache set in the cache device. All cache lines in the same set are selected by the index.

[0095] (b) The tag part is used to select a specific cache line in a cache set. The tag of the physical address is compared with the tag of each cache line. If they match, the cache is hit and the cache line is selected; otherwise, the cache is missed.

[0096] (c) The offset portion is used to select the corresponding address in the cache line. It represents the first byte (Byte) of the access address in the cache line, and the corresponding data or instruction is read from the position of this byte.

[0097] For example, when accessing a target page table entry cached in a cache device, the cache group containing the target page table entry can be determined by the index portion of the access address, and the cache line containing the target page table entry can be determined by the tag portion within the cache group. For example, if a cache miss occurs in the first-level cache, the second-level cache is searched; if a cache miss occurs in the second-level cache, the third-level cache is searched, and so on.

[0098] Figure 5 This illustration shows an operational diagram of a multi-level cache based on a cache path, according to at least one embodiment of the present disclosure. Figure 6 The illustration shows an operation diagram of multi-level caching by cache group provided in at least one embodiment of the present disclosure.

[0099] For example, a page table entry caching rule may include multiple page table entry caching sub-rules set separately for multiple hardware threads or multiple processor cores. For example, if a processor includes multiple hardware threads, the page table entry caching rule may include multiple page table entry caching sub-rules corresponding to each of the multiple hardware threads. Similarly, if a processor includes multiple processor cores, the page table entry caching rule may include multiple page table entry caching sub-rules corresponding to each of the multiple processor cores.

[0100] For example, page table entry caching rules can be configured for the first-level cache, second-level cache, and third-level cache, respectively. The first-level cache is configured with first-level page table entry caching rules, the second-level cache with second-level page table entry caching rules, and the third-level cache with third-level page table entry caching rules. For instance, the first-level, second-level, and third-level page table entry caching rules can each include multiple page table entry caching sub-rules set based on multiple hardware threads or multiple processor cores.

[0101] like Figure 5 As shown, processor core 10 and processor core 11 are included. For example, corresponding page table entry cache sub-rules can be set for processor core 10 and processor core 11 in the first-level page table entry cache rule, the second-level page table entry cache rule, and the third-level page table entry cache rule, respectively.

[0102] For example, processor core 10 is a multi-threaded processor core, including multiple hardware threads such as thread 0 and thread 1; processor core 11 is a multi-threaded processor core, including thread 2 and thread 3. Threads 0, 1, 2, and 3 can be threads provided by Simultaneous Multi-Threading (SMT) technology, i.e., hardware threads (different from software threads in the operating system running on the processor). For example, in SMT mode, multiple similar threads among threads 0, 1, 2, and 3 are allowed to share resources (such as cache, execution units, etc.) within the corresponding processor core, enabling multiple similar threads to execute in parallel, thereby improving the processor's efficiency and performance.

[0103] For example, a first-level page table entry caching rule may include multiple first-level page table entry caching sub-rules, a second-level page table entry caching rule may include multiple second-level page table entry caching sub-rules, and a third-level page table entry caching rule may include multiple third-level page table entry caching sub-rules. For example, for different hardware threads of the processor, each hardware thread may have its own page table entry caching rule at the corresponding cache level. For example, in the first-level, second-level, and third-level page table entry caching rules, threads 1, 2, 3, and 4 each have their own page table entry caching sub-rules in the page table entry caching rules at their respective cache levels.

[0104] like Figure 5 As shown, taking thread 0 as an example, the first-level page table entry cache sub-rule 4001 is configured in the first-level cache L1; the second-level page table entry cache sub-rule 4002 is configured in the second-level cache L2; and the third-level page table entry cache sub-rule 4003 is configured in the third-level cache L3.

[0105] For each level of a multi-level cache, the page table entry caching rules can be determined by the cache path to determine the available cache path in each level of the multi-level cache. For example, the page table entry caching rules for each level can be set according to the cache path division of each level.

[0106] For example, the first-level cache 3001 is divided into 8 cache paths, way0 to way7. The first-level page table entry cache sub-rule 4001 includes 8 cache path selection rules corresponding to each cache path of the first-level cache 3001, used to determine the availability status of way0 to way7 respectively. The second-level cache 3002 is divided into 16 cache paths, way0 to way15. The second-level page table entry cache sub-rule 4002 is set to 16 cache paths, way0 to way15. The second-level page table entry cache sub-rule 4002 includes 8 cache path selection rules corresponding to each cache path of the first-level cache 3001, used to determine the availability status of way0 to way7 respectively. Each cache path in cache 3002 has 16 cache path selection rules corresponding to it, which are used to determine the availability status of way0 to way15 respectively. The third-level cache 3003 is divided into 16 cache paths, way0 to way15. The third-level page table entry cache sub-rule 4003 is set to 16 cache paths, way0 to way15. The third-level page table entry cache sub-rule 4003 includes 16 cache path selection rules corresponding to each cache path in the third-level cache 3003, which are used to determine the availability status of way0 to way15 respectively.

[0107] For example, for thread 0, the first-level page table entry cache sub-rule 4001 determines that way0 to way2 of the first-level cache 3001 are available cache paths; the second-level page table entry cache sub-rule 4002 determines that way0 to way4 of the second-level cache 3002 are available cache paths; and the third-level page table entry cache sub-rule 4003 determines that way0 to way7 of the third-level cache 3003 are available cache paths.

[0108] like Figure 6 As shown, for different threads of the processor, page table entry caching rules can determine the available cache groups in each cache level of a multi-level cache based on cache groups. For example, page table entry caching rules for each level can be set according to the cache group division of each cache level. Alternatively, page table entry caching rules can be customized to correspond to the availability status of different cache groups. For example, if the first-level cache 3001 is divided into four cache groups set0 to set3, the first four bits of the first-level page table entry caching sub-rule 4001 are used to determine the availability status of set0 to set3 respectively; if the second-level cache 3002 is divided into four cache groups set0 to set3, the first four bits of the second-level page table entry caching sub-rule 4002 are used to determine the availability status of set0 to set3 respectively; if the third-level cache 3003 is divided into n+1 cache groups set0 to setn, where n is a positive integer, the first n+1 bits of the third-level page table entry caching sub-rule 4003 are used to determine the availability status of set0 to set3 respectively.

[0109] It should be noted that each cache set can include multiple cache paths. When a cache set is determined to be an available cache set, it means that all cache paths included in that cache set are available cache paths.

[0110] For example, for thread 0, the first-level page table entry cache sub-rule 4001 determines that set0 to set1 of the first-level cache 3001 are available cache groups; the second-level page table entry cache sub-rule 4002 determines that set0 of the second-level cache 3002 is available cache group; and the third-level page table entry cache sub-rule 4003 determines that set0 of the third-level cache 3003 is available cache group.

[0111] It should be noted that, despite the above Figure 5 and Figure 6 The example uses a specific number of cache paths and cache groups, but this does not imply a limitation on the number of cache paths and cache groups at each level of the cache device. Furthermore, although the above explanation uses thread 0 as an example, threads 1, 2, and 3 also have corresponding page table entry cache sub-rules in the first-level, second-level, and third-level page table entry cache sub-rules, respectively. The method for determining the availability of cache paths or cache groups can be the same as that for thread 0.

[0112] For example, the operation object responding to the first cache request includes the first page table entry. For instance, taking a cache line containing a page table entry as an example, when the cache device needs to write a new cache line containing a page table entry, it can determine the cache path or cache group that can write the page table entry by checking the page table entry cache rules corresponding to the current cache device. Then, it can determine the cache path or cache group in an available state from these cache paths or cache groups. Then, it can further determine the old cache line that can be replaced from the available cache paths or cache groups. Then, it can replace the old cache line with the new cache line containing the page table entry to insert the new cache line containing the page table entry into the cache path or cache group in an available state that was finally selected above.

[0113] In some embodiments of this disclosure, the page table entry caching rules in the operation of the caching device are determined by the page table mask in the configuration register.

[0114] In some embodiments of this disclosure, the page table mask in the operation method of the caching device includes multiple bits, each bit corresponding to a multiple cache space. When each bit is a first value, it indicates that the corresponding cache space is allocated for caching page table entries. When each bit is a second value, it indicates that the corresponding cache space is not allocated for caching page table entries.

[0115] For example, in Figure 5 and Figure 6 In this example, the gray portion can represent the corresponding bits of the page table mask as the first value, and the white portion can represent the corresponding bits of the page table mask as the second value. For example, the first value can be set to 1, and the second value can be set to 0.

[0116] It should be noted that the specific settings of the first value and the second value can be numbers, symbols or letters. The embodiments of this disclosure do not limit the specific settings of the first value and the second value, as long as it is possible to distinguish and determine the available state cache path or cache group that can be used to cache page table entries.

[0117] Figure 7 This illustration shows an operational diagram of a page table entry cache line based on a service type identifier, provided in at least one embodiment of this disclosure.

[0118] like Figure 7 As shown, different hardware threads can determine the corresponding page table entry caching rules based on the corresponding service type identifier. For example, multiple service type identifiers (Classes of Service) include CLOS 0, CLOS1 to CLOS n, where n is a positive integer. For example, the page table entry caching rules corresponding to each service type identifier are different. For example, when the caching device is a multi-level cache, a service type identifier can include the page table entry caching rules for each level of the cache. For example, for thread 0, the page table entry caching sub-rules for thread 0 in the corresponding level of cache can be determined based on the configured service type identifier CLOS 0. For example, the service type identifier CLOS 0 corresponds to the first-level page table entry caching sub-rule 4001 for the first-level cache L1, the second-level page table entry caching sub-rule 4002 for the second-level cache L2, and the third-level page table entry caching sub-rule 4003 for the third-level cache L3.

[0119] For example, each CLOS may contain at least one mask register (or simply MASK register) that controls the cache allocation according to a policy.

[0120] It should be noted that although the above explanation only uses thread 0 as an example, threads 1, 2, and 3 can also determine their respective page table entry caching sub-rules based on the configured service type identifier. For example, threads 0, 1, 2, and 3 can be configured with different service type identifiers, and at least two threads among threads 0, 1, 2, and 3 can have the same service type identifier.

[0121] For example, if threads 1, 2, and 3 are not configured with a service type identifier, the first cache space for the cached page table entry is selected according to the default configuration. For instance, under the default configuration, any one of multiple cache spaces can be selected as the first cache space.

[0122] In some embodiments of this disclosure, the operation method of the caching device further includes a second cache space for caching data items among the multiple cache spaces, and the operation method of the caching device further includes steps S40 and S41.

[0123] Step S40: Receive the second cache request.

[0124] Step S41: In response to the second cache request, the operation object is the first processed data, and the first processed data is written into the second cache space.

[0125] For example, the second cache request can be determined based on the access request issued by the processor. For example, the operation object of the second cache request is data, and the first processed data can be any of the processed data. In the above description, "second cache request" refers to a cache request other than "first cache request" as the object of description, for example, it can be a read request or a write request, and "first processed data" refers to the processed data as the object of description, whose operation object corresponds to a read request or a write request, which can be the object being read or the object being written.

[0126] For example, upon receiving an access request, responding to the request can involve accessing both page table entries and processed data. Therefore, caching operations can be performed on the page table entries and the processed data separately. For instance, a first cache request can be sent to the cache device for the page table entries, and a second cache request can be sent to the cache device for the processed data. Alternatively, the first and second cache requests can be responded to by the cache device simultaneously or separately.

[0127] It should be noted that the second cache space can be determined in any way. For example, the second cache space can be configured as any cache space in the caching device, or it can overlap with part of the first cache space. For example, different processor cores or different threads can be configured with corresponding cache paths or cache groups for caching processed data as the second cache space. For example, different processor cores or different threads have corresponding data processing caching rules, and the second cache space for the corresponding processor core or thread can be determined by the data processing caching rules. For example, the data processing caching rules can be configured in the same way as the page table entry caching rules described above, which will not be repeated here.

[0128] By writing the processed data into the second cache space according to the second cache request when the operation object is data to be processed, the caching of processed data and the caching of page table entries are processed separately in the cache device, thus isolating the cache operations.

[0129] For example, the second cache space can be any cache space other than the first cache space.

[0130] By storing the processed data in a different cache space than the page table entries, cache isolation is achieved between the page table entries and the processed data. This prevents cache conflicts between page table entries and processed data from flushing page table entries in the cache during large-scale data access by memory-intensive applications. As a result, more page table entries are stored in the cache, which speeds up the processor's virtual address translation process, reduces the occurrence of secondary cache misses (one page table entry miss and one processed data miss) during processing, and improves the processor's memory access performance.

[0131] In some embodiments of this disclosure, the operation method of the cache device further includes steps S50 and S51.

[0132] Step S50: Receive the second cache request.

[0133] Step S51: In response to the second cache request, the operation object is the first processed data and the first cache space includes free cache lines, the first processed data is written into the first cache space.

[0134] For example, when the first cache space of a cache page table entry includes a free cache line, the first processing data can be written to the free cache line in the first cache space so that the cache space of the cache device can be fully utilized.

[0135] In some embodiments of this disclosure, the operation method of the caching device further includes step S32.

[0136] Step S32: Read the page table entry caching rules from the configuration register.

[0137] Page table entry caching rules can be stored in a configuration register and can be read from the configuration register. For example, the configuration register stores a page table mask representing the page table entry caching rules. The number of bits in the configuration register can be selected based on the number of cache paths or cache groups the cache device is divided into; for example, an 8-bit register is selected for a cache device with 8 cache paths, and a 16-bit register is selected for a cache device with 16 cache paths.

[0138] Figure 8 A flowchart illustrating the operation of a caching device provided in at least one embodiment of the present disclosure is shown.

[0139] like Figure 8As shown, an example of cache device operation by cache path is given. It can be determined whether the operation object of the new cache line written by the cache request includes page table entries. If so, the available cache path can be selected according to the page table mask, and the old cache line that can be replaced can be found from the cache path. If not, it means that page table entries are not included, which may be for processing data. In this case, the cache line that can be replaced can be selected from all cache paths.

[0140] Then, the new cache line replaces the old cache line, thus completing the operation on the cache device based on the cache request.

[0141] In some embodiments of this disclosure, the operation method of the cache device further includes step S33.

[0142] Step S33: Write page table entry caching rules to the configuration register.

[0143] For example, fixed page table entry caching rules can be pre-written when configuring the configuration register, or the page table entry caching rules can be dynamically updated according to the caching device.

[0144] In some embodiments of this disclosure, step S33 in the operation method of the cache device further includes step S330 or step S331.

[0145] Step S330: In response to monitoring information about the processor, including the cache device, or monitoring information about the cache device itself, write the page table entry cache rule.

[0146] For example, a monitoring module can be set up inside the processor. The monitoring module can monitor at least one processor core or at least one thread in the processor to obtain monitoring information related to cache hits and misses in the cache device, thereby determining or adjusting the page table entry caching rules and writing them into the page table entry caching rules.

[0147] Alternatively, the monitoring module can monitor the caching device itself. For example, the monitoring module can dynamically monitor indicators such as page table cache miss rate and / or data cache miss rate in the caching device, analyze the monitoring information, and then write the determined or adjusted page table entry caching rules.

[0148] Page table cache miss rate reflects the cache miss rate of page table entries in the cache device, while data cache miss rate reflects the cache miss rate of processed data in the cache device.

[0149] For example, page table entry caching rules can be written into the configuration register in the form of a page table mask. Alternatively, page table entry caching rules can be written by adjusting the numerical bits in the configuration register based on monitoring information.

[0150] Figure 9A schematic diagram illustrating the writing of a page table entry caching rule according to at least one embodiment of the present disclosure is shown.

[0151] For example, processor core 10 is equipped with a monitoring module 5001. The monitoring module 5001 obtains monitoring information by monitoring processor core 10 or cache devices (such as L1 cache 3001, L2 cache 3002 and L3 cache 3003), and writes page table entry caching rules, such as page table masks, according to the monitoring information.

[0152] For example, if the page table entry cache miss rate is high for accesses from thread 0, the size of the first cache space for thread 0 in the cache device can be adjusted.

[0153] For example, if the application has a large amount of hot data and the page table cache miss rate and data cache miss rate from each thread are both high (i.e., secondary cache misses occur frequently in the cache device), the first cache space used by each thread to cache page table entries can be adjusted to all cache spaces to ensure that the cache is hit at least once (i.e., the page table entry is hit) when the processor processes the access request.

[0154] It should be noted that the above method of adjusting page table entry caching rules through hardware monitoring modules is only an example, and this disclosure does not limit the method of adjusting page table entry caching rules.

[0155] Step S331: The user writes page table entries to the cache rules for the processor, which includes the cache device.

[0156] For example, users can adjust page table entry caching rules via software. For example, this "user" could be a thread or process running on the processor.

[0157] In some embodiments of this disclosure, step S331 of the operation method of the cache device further includes step S3310.

[0158] Step S3310: The user analyzes the processor's microarchitecture status information through a hardware counter and provides the analysis results for adjusting page table entry caching rules.

[0159] Figure 10 A schematic diagram illustrating the writing of a page table entry caching rule according to at least one embodiment of the present disclosure is shown.

[0160] like Figure 10 As shown, the microarchitecture status information of the processor can be analyzed through hardware counters, allowing users to determine or adjust page table entry caching rules through software, thereby writing page table entry caching rules.

[0161] For example, hardware counters (Performance Monitoring Counters, PMCs) are programmable registers on the processor used to monitor and count specific hardware events (such as microarchitecture status information). Hardware counters can pass the monitored and counted specific hardware events to software (such as monitoring clients) so that users can determine or adjust page table entry caching rules and write page table entry caching rules through software.

[0162] For example, processor microarchitectural state information can include instruction pipeline paths, instruction cycle counts, instruction scheduling status, number of executed instructions, or cache misses. For instance, users can configure software to specify which microarchitectural state information should be analyzed using hardware counters.

[0163] It should be noted that the specific microarchitecture state information monitored and analyzed by the hardware counter is not limited in the embodiments of this disclosure. The analysis of microarchitecture state information by the hardware counter may include counting the total number, counting the state over a period of time, or calculating the proportion of a certain situation. This disclosure does not limit the analysis method of the hardware counter.

[0164] At least one embodiment of this disclosure also provides a caching device, which includes a plurality of cache spaces and a cache controller. The cache controller is configured to determine a first cache space among the plurality of cache spaces for caching page table entries according to page table entry caching rules, and to write the first page table entry into the first cache space in response to a received first cache request, the operation object of which includes the first page table entry.

[0165] Figure 11 A block diagram of a caching device provided in at least one embodiment of the present disclosure is shown.

[0166] The cache device 300 includes multiple cache spaces and a cache controller 310. For example, the multiple cache spaces may include cache spaces 1 to n, where n is a positive integer.

[0167] For example, cache controller 310 is configured to determine a first cache space among multiple cache spaces for caching page table entries based on page table entry caching rules, and in response to a received first cache request whose operation object includes the first page table entry, write the first page table entry into the first cache space according to the page table entry caching rules.

[0168] For example, the cache controller 310 is also configured to determine a second cache space among a plurality of cache spaces for caching processed data, and in response to the operation object of the second cache request being the first processed data, write the first processed data into the second cache space.

[0169] For example, cache controller 310 is also configured to receive a second cache request; in response to the operation object of the second cache request being first processed data and the first cache space including free cache lines, the first processed data is written into the first cache space.

[0170] In some embodiments of this disclosure, the caching device is configured as a first-level cache, a second-level cache, or a third-level cache for the processor.

[0171] In some embodiments of this disclosure, the caching device is a group-associative mapping, and the multiple cache spaces are multiple cache groups or multiple cache paths of the caching device, with the first cache space including some cache groups or some cache paths of the caching device.

[0172] For example, cache controller 310 is also configured to read page table entry cache rules from the configuration register. For example, cache controller 310 is also configured to write page table entry cache rules to the configuration register.

[0173] The cache controller 310 is also configured to write page table entry cache rules in response to monitoring information for a processor including the cache device or for the cache device itself; or, to have page table entry cache rules written by a user for a processor including the cache device.

[0174] The cache controller 310 is also configured to allow users to analyze the processor’s microarchitectural state information via hardware counters and provide the analysis results for adjusting page table entry caching rules.

[0175] In some embodiments of this disclosure, the page table entry caching rules are determined by the page table mask in the configuration register.

[0176] In some embodiments of this disclosure, the page table mask includes multiple bits, each bit corresponding to a multiple cache space. When each bit is a first value, it indicates that the corresponding cache space is allocated for caching page table entries. When each bit is a second value, it indicates that the corresponding cache space is not allocated for caching page table entries.

[0177] The technical effects of the caching device in the above embodiments of this disclosure are the same as the technical effects of the operation method of the above caching device, and therefore will not be described again.

[0178] At least one embodiment of this disclosure also provides a processor, which includes a caching device and a configuration register provided in any embodiment of this disclosure, the configuration register being configured to store page table entry caching rules.

[0179] Figure 12 A block diagram of a processor provided in at least one embodiment of the present disclosure is shown.

[0180] The processor 100 includes a cache device 300 and a configuration register 400.

[0181] Configure register 400 to store page table entry caching rules.

[0182] In some embodiments of this disclosure, the processor includes multiple hardware threads or multiple processor cores, and the page table entry caching rules include setting multiple page table entry caching sub-rules for each of the multiple hardware threads or multiple processor cores.

[0183] In some embodiments of this disclosure, page table entry caching rules set object page table entry caching sub-rules for object hardware threads in multiple hardware threads by using multiple service type markers corresponding to multiple hardware threads respectively.

[0184] In some embodiments of this disclosure, the processor 100 further includes a monitoring module 5001, which is configured to dynamically monitor the page table cache miss rate or data cache miss rate of the cache device 300 and provide monitoring results for adjusting page table entry caching rules.

[0185] The technical effects of the processor in the above embodiments of this disclosure are the same as those of the cache device described above, and therefore will not be repeated here.

[0186] At least one embodiment of this disclosure also provides an electronic device, wherein the electronic device includes the cache device described in the at least one embodiment above or the processor described in the at least one embodiment above.

[0187] Figure 13 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0188] The electronic devices in this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 13 The illustrated electronic device 1000 is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0189] For example, refer to Figure 13In some examples, electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1008 into random access memory (RAM) 1003. For example, processing device 1001 can serve as a processor in embodiments of this disclosure. Various programs and data required for the operation of the computer system are also stored in RAM 1003. Processing device 1001, ROM 1002, and RAM 1003 are connected via interconnection network 1004. Input / output (I / O) interface 1005 is also connected to interconnection network 1004.

[0190] For example, the following components can be connected to I / O interface 1005: input devices 1006 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1007 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1008 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009, such as network interface cards like LAN cards and modems, etc. Communication device 1009 allows electronic device 1000 to communicate wirelessly or wiredly with other devices to exchange data and perform communication processing via networks such as the Internet. Drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage device 1008 as needed. Although Figure 13 An electronic device 1000 including various devices is shown; however, it should be understood that implementation or inclusion of all shown devices is not required. More or fewer devices may be implemented or included alternatively.

[0191] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure). This peripheral interface can be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 1009 can communicate wirelessly with a network and other devices, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication can use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0192] For example, the electronic device 1000 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be a combination of any cache device operating device and hardware. The embodiments disclosed herein do not limit this.

[0193] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions. For example, when the computer-executable instructions are executed by a processor, they implement the operation method of the cache device provided in at least one embodiment of this disclosure.

[0194] Figure 14 This is a schematic diagram of a non-transitory storage medium provided in some embodiments of this disclosure. For example... Figure 14 As shown, the non-temporary storage medium 900 can non-temporarily store computer-executable instructions 910, which, when executed by a computer, implement the operation method of the cache device provided in any embodiment of this disclosure.

[0195] The following points need to be clarified regarding this disclosure:

[0196] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0197] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0198] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of operating a caching device, the caching device comprising a plurality of cache spaces and a cache controller, the caching device being configured with page table entry caching rules, the plurality of cache spaces including a first cache space allocated by the cache controller for caching page table entries according to the page table entry caching rules, the method comprising: After the address translator in the processor determines the physical address of the access request, it receives the first cache request; The operation object in response to the first cache request includes a first page table entry. The cache controller checks the page table entry caching rules and writes the first page table entry into the first cache space according to the page table entry caching rules. The page table entry caching rules are the rules for selecting the first cache space from the plurality of cache spaces.

2. The operating method as described in claim 1, wherein, The plurality of cache spaces also includes a second cache space for caching data items; The operation method further includes: Receive the second cache request; In response to the second cache request, the operation object is the first processed data, and the first processed data is written into the second cache space.

3. The operating method as described in claim 1, further comprising: Receive the second cache request; In response to the second cache request, where the operation object is the first processed data and the first cache space includes free cache lines, the first processed data is written into the first cache space.

4. The operating method as described in claim 1, wherein, The cache device is configured as a first-level cache, a second-level cache, or a third-level cache for the processor.

5. The operating method as described in claim 1, wherein, The cache device is a set-associative mapping. The plurality of cache spaces are respectively a plurality of cache groups or a plurality of cache paths of the cache device, and the first cache space includes a portion of the cache groups or a portion of the cache paths of the cache device.

6. The operating method as described in any one of claims 1-5, further comprising: Read the page table entry caching rules from the configuration register.

7. The operating method as described in claim 6, further comprising: Write the page table entry caching rule into the configuration register.

8. The operating method as described in claim 7, wherein, The step of writing the page table entry caching rule to the configuration register includes: In response to monitoring information about the processor including the cache device or monitoring information about the cache device itself, the page table entry caching rule is written; or, The page table entry caching rules are written by the user for the processor that includes the caching device.

9. The operating method as described in claim 8, wherein, The cache rules for page table entries written by users to processors including the cache device include: The user analyzes the processor's microarchitecture state information using a hardware counter and provides the analysis results to adjust the page table entry caching rules.

10. The operating method as described in claim 7, wherein, The page table entry caching rules are determined by the page table mask in the configuration register.

11. The operating method as described in claim 10, wherein, The page table mask includes multiple bits, each of which corresponds to a multiple cache space. When each bit is a first value, it indicates that the corresponding cache space is allocated for caching page table entries. When each bit is a second value, it indicates that the corresponding cache space is allocated for not caching page table entries.

12. A buffer device, wherein, The caching device is configured with page table entry caching rules, and the caching device includes: Multiple cache spaces; A cache controller is configured to determine a first cache space among the plurality of cache spaces for caching page table entries based on page table entry caching rules, and, after the address translator in the processor determines the physical address of the access request, in response to the operation object of the received first cache request including the first page table entry, to check the page table entry caching rules and write the first page table entry into the first cache space according to the page table entry caching rules; wherein, the page table entry caching rules are the rules for selecting the first cache space from the plurality of cache spaces.

13. A processor, comprising: The caching device according to claim 12; Configure the register to store the page table entry caching rules.

14. The processor of claim 13, wherein, The processor includes multiple hardware threads or multiple processor cores, and the page table entry caching rules include setting multiple page table entry caching sub-rules for each of the multiple hardware threads or the multiple processor cores.

15. The processor of claim 14, wherein, The page table entry caching rule sets the object page table entry caching sub-rules for the object hardware thread in the multiple hardware threads by using multiple service type markers corresponding to multiple hardware threads respectively.

16. The processor of claim 15, further comprising: The monitoring module is configured to dynamically monitor the page table cache miss rate or data cache miss rate of the caching device, and provide monitoring results for adjusting the page table entry caching rules.

17. An electronic device comprising the cache device of claim 12 or the processor of any one of claims 13-16.

18. A non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, When the computer-executable instructions are executed by at least one processor, the method of operating the cache device according to any one of claims 1-11 is implemented.

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