Method and device for replacing data in cache

Abstract

The invention relates to the field of storage strategies, in particular to a method and a device for replacing data in a cache. The method mainly comprises the following steps of: when new data enters cache groups, generating a pseudo-random binary sequence with corresponding digits according to the number of cache paths in each cache group; and obtaining a cache path accessed last time in the current cache group as an access history, and determining a cache path for data replacement according to the access history and the pseudo-random binary sequence. According to the method, fairness can be ensured based on randomness, so that resource consumption can be reduced, and the problem that a traditional PLRU strategy is too large in resource consumption or insufficient in fairness is solved.

Description

Technical Field

[0001] The present invention relates to the field of storage strategies, and in particular to a method and device for replacing data in a high-speed cache. Background Art

[0002] The increase in the CPU's main frequency will improve system performance, but the access speed of the main memory is usually much lower than the CPU's data processing speed, so the CPU needs to wait for a long time to read and write data, which reduces the processing speed and wastes CPU capacity. In current computer architectures, one or more levels of faster, smaller random access memories are usually inserted between the slow main memory and the fast CPU as caches to make up for the speed difference between the CPU and the main memory, so that the CPU can quickly access data in the main memory, thereby improving the overall performance of the system without increasing the system cost too much.

[0003] Since the cache capacity is small, only part of the data in the main memory can be saved. In order to improve the utilization of data in the cache, the least recently used (LRU) can be used as the data replacement strategy in the cache. Currently, most caches use the pseudo LRU (PLRU) strategy. In this strategy, the old data in the cache line with the least number of uses in the recent period is replaced, and the new data is written to the cache line. However, when using the LRU strategy for data replacement, it is necessary to record the access status of each cache line, so the resources occupied are very large. For example, tree-LRU, as the most commonly used PLRU strategy, needs to record the status of all cache lines in each cache set, and it consumes more logic when selecting the replacement line, which is not friendly to timing. In another simpler PLRU, some bits of the address are used as the basis for replacement, but this PLRU strategy is highly related to the address, which will lead to obvious unfair selection.

[0004] In view of this, how to overcome the defects of the existing technology and solve the problem of excessive resource consumption or insufficient fairness of the traditional PLRU strategy is a problem to be solved in this technical field. Summary of the invention

[0005] In view of the above defects or improvement requirements of the prior art, the present invention solves the problem of excessive resource consumption or insufficient fairness of the traditional PLRU strategy.

[0006] The embodiment of the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for replacing data in a cache, specifically: when new data enters a cache group, a pseudo-random binary sequence of corresponding bits is generated according to the number of cache ways in each cache group; the cache way that was previously accessed in the current cache group is obtained as an access history, and the cache way for data replacement is determined according to the access history and the pseudo-random binary sequence.

[0008] Preferably, the method of generating a pseudo-random binary sequence of corresponding bits according to the number of cache ways in each cache group specifically includes: calculating the number of bits of the pseudo-random binary sequence according to the number of cache ways, and constructing a generating polynomial of the pseudo-random binary sequence according to the number of bits; and generating the pseudo-random binary sequence through an XOR operation according to the calculation rules of the generating polynomial.

[0009] Preferably, a status value of a corresponding number of bits is set for each cache group according to the number of cache ways in each cache group, and obtaining the cache way that was last accessed in the current cache group as the access history specifically includes obtaining the sequence number of the cache way last accessed, and setting the corresponding bit in the status value of the corresponding cache group to a specified value according to the cache way sequence number; obtaining the status value of the cache group that needs to perform data replacement, and obtaining the access history according to the value of the corresponding bit in the status value.

[0010] Preferably, the method of determining the cache way for data replacement based on the access history and the pseudo-random binary sequence specifically includes: obtaining the cache way sequence number of the previous access based on the access history, and obtaining the cache way sequence number to be replaced based on the pseudo-random binary sequence; when the cache way sequence number of the previous access and the cache way sequence number to be replaced are different, using the cache way sequence number to be replaced as the cache way for data replacement; when the cache way sequence number of the previous access and the cache way sequence number to be replaced are the same, obtaining an adjustment strategy based on the parity check value of the pseudo-random binary sequence at the time of the previous data replacement, and calculating the cache way for data replacement based on the adjustment strategy.

[0011] Preferably, the method of obtaining an adjustment strategy based on the parity check value of the pseudo-random binary sequence during the previous data replacement and calculating the cache way for data replacement based on the adjustment strategy specifically includes: calculating the parity check value of the pseudo-random binary sequence used during the previous data replacement in a bitwise XOR manner, wherein the parity check value is 1 bit; when the parity check value is a first specified value, using the previous cache way of the cache way sequence number to be replaced as the cache way for data replacement; when the parity check value is a second specified value, using the next cache way of the cache way sequence number to be replaced as the cache way for data replacement.

[0012] Preferably, before new data enters the cache group, the method also includes: determining whether the data to be accessed this time already exists in the cache; when the data already exists in the cache, no data replacement is performed, and only the access history is modified according to the cache path where the data is located; when the data does not exist in the cache, the data to be accessed this time is obtained from the memory as new data, and the new data is replaced in the cache.

[0013] In a second aspect, the present invention provides a device for replacing data in a cache, specifically: at least one pseudo-random binary sequence generator, a comparator, a check module, a first selector and an access history register, for implementing the method for replacing data in a cache provided in the first aspect, specifically including: the output end of the pseudo-random binary sequence generator is respectively connected to the check module, the first input end of the first selector and the first input end of the comparator, for generating a pseudo-random binary sequence; wherein the number of pseudo-random binary sequence generators is determined according to the number of cache ways; the two input ends of the comparator are respectively connected to the pseudo-random binary sequence generator and the access history register, for comparing whether the cache way number accessed last time is the same as the cache way number to be replaced; the input end of the check module is connected to the pseudo-random binary sequence generator, and the output end is connected to the second input end of the first selector, for generating a parity check value according to the pseudo-random binary sequence, and determining an adjustment strategy for the cache way number according to the parity check value; the first selector is used to select a cache way for data replacement according to the pseudo-random binary sequence, the comparison result of the comparator and the adjustment strategy; the access history register is used to store the access history of each cache way.

[0014] Preferably, the pseudo-random binary sequence generator includes: a shift register and an XOR circuit, specifically including: the number of shift registers is consistent with the number of bits of the pseudo-random binary sequence to be generated, all the shift registers are linearly connected in sequence, and are used to perform linear shifts on the binary sequence, with the value of the last bit of the shift register being used as the output of the pseudo-random binary sequence; the XOR circuit is used to perform an XOR operation on the values ​​of the last two bits of the last two shift registers, and input the value of the XOR operation into the first bit of the shift register.

[0015] Preferably, the check module includes: a parity check generator, a check value register, a second selector and an accumulation circuit, specifically including: the parity check generator generates a parity check value according to a pseudo-random binary sequence, and outputs the parity check value to the check value register; the second selector selects an accumulation value corresponding to an adjustment strategy according to the value of the check value register, so as to adjust the pseudo-random binary sequence; the accumulation circuit adds the pseudo-random binary sequence and the accumulation value, so as to obtain an adjusted cache path.

[0016] Preferably, the parity generator includes: a parity register and an XOR circuit, specifically including: the number of parity registers is consistent with the number of bits of the pseudo-random binary sequence, each parity register is connected through a multi-stage XOR circuit, and the output of all parity registers after bitwise XOR is used as the parity check value.

[0017] Compared with the prior art, the beneficial effect of the present invention is that data replacement is not completely based on the data usage and access status of the cache, but a pseudo-random binary sequence is used to solve the fairness problem. Since the pseudo-random binary sequence is simple to implement and requires fewer states, it can also ensure fairness based on randomness, thereby reducing resource consumption and alleviating the problem of excessive resource consumption or insufficient fairness of the traditional PLRU strategy. At the same time, by recording the previous data access history, the most recently used data of the previous access caused by the random replacement method is avoided from being replaced, thereby ensuring the data hit rate in the cache. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A flow chart of a method for replacing data in a cache provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a cache architecture used in a method provided in an embodiment of the present invention;

[0021] Figure 3 A flow chart of another method for replacing data in a cache provided by an embodiment of the present invention;

[0022] Figure 4 A flow chart of another method for replacing data in a cache provided by an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the structure of a device for replacing data in a cache provided by an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of a group of pseudo-random binary sequence generators used in the device provided by an embodiment of the present invention;

[0025] Figure 7 A schematic diagram of the structure of each pseudo-random binary sequence generator in the device provided in an embodiment of the present invention;

[0026] Figure 8 A schematic diagram of the structure of a verification module used in the device provided in an embodiment of the present invention;

[0027] Fig. 9 A schematic diagram of the structure of a parity check generator used in the device provided in an embodiment of the present invention;

[0028] Fig.10 A schematic diagram of the structure of the device provided by an embodiment of the present invention in a specific scenario. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] The present invention is an architecture of a specific functional system, so the specific embodiments mainly illustrate the functional logical relationship between the various structural modules, and do not limit the specific software and hardware implementation methods.

[0031] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0032] Pseudorandom (PN) code sequence, also known as pseudo noise, is a commonly used address code. Pseudorandom code sequence has basic characteristics similar to random sequence. It is a periodic binary sequence that looks random but is actually regular. In actual use, pseudorandom sequence can provide a sufficiently random but regular sequence to meet the fairness requirements of data replacement without increasing additional consumption.

[0033] In this embodiment, in order to facilitate the generation and identification of the PN code by a logic circuit, a pseudo-random binary sequence (Pseudo-Random Binary Sequence, abbreviated as PRBS) containing only 0 and 1 is used.

[0034] like Figure 1 As shown, the specific steps of the method for replacing data in a cache provided by an embodiment of the present invention are as follows.

[0035] Step 101: When new data enters a cache group, a pseudo-random binary sequence of corresponding bits is generated according to the number of cache ways in each cache group.

[0036] In this embodiment, Figure 2The model shown in the figure is used as an example to represent the data storage structure in the cache. The model contains N cache sets and 4 cache ways. Figure 2 In the example, each row is a set and each column is a way. In some implementations, the number of sets and ways is set according to actual needs. Each set contains 4 cache lines. Figure 2 In the figure, it is represented as a white box. The cache line stores the valid data currently used by the CPU. Whenever new data needs to enter a set, one of the four cache lines needs to be selected to store the new data.

[0037] In some implementations, each bit of the PRBS may represent a way, and only one bit in the sequence has a value of 1. When data replacement is performed, the cache line corresponding to the bit with a value of 1 is replaced. Figure 2 In the model, 4-bit PRBS is used to represent 4 ways. When new data enters set0, the generated PRBS value is Ob0010, and the corresponding way value of sequence number 2 is 1, indicating that the way number 2 needs to be replaced with data. In this case, the cache line corresponding to way2 in set0 is replaced with data.

[0038] The PRBS value can also be used to directly represent the sequence number of the way. When there are M ways, only log2M bits are needed to correspond to the sequence numbers of the M ways, further reducing resource consumption and hardware complexity and improving randomness. Figure 2 In the model, 2-bit PRBS is used to represent 4 ways. When new data enters set0, the generated PRBS value is Ob10, indicating that the way number 2 needs to be replaced. Then the data of the cache line corresponding to way2 in set0 is replaced.

[0039] Step 102: Obtain the cache way that was accessed last time in the current cache group as the access history, and determine the cache way for data replacement according to the access history and the pseudo-random binary sequence.

[0040] When the CPU processes data, it usually processes data related to the same task in a short period of time, and these data are usually used repeatedly. If such data is replaced, it must be obtained from the main memory again, which affects the processing efficiency of the CPU. Therefore, in the method provided in this embodiment, it is also necessary to record the access history of the previous data access to avoid the data to be used in this time period from being replaced, so as to meet the replacement principle of the LRU strategy and obtain a higher data hit rate.

[0041] In specific implementation, Figure 2 As shown, each set also contains a status. When a cache line of a way in a set is accessed, the status of the set will record the way number of the cache line being accessed. Since only the access history of one access needs to be recorded, when there are M ways, the status only needs log2M bits, which consumes less resources. For example, in set1, when the data last accessed by the CPU is in the cache line corresponding to way1, the status value of set1 is 0b01.

[0042] When performing data replacement, it is necessary to compare the way number represented by the access history with the way number corresponding to the PRBS. When the way numbers of the two are different, directly replace the data of the way number corresponding to the PRBS; otherwise, replace the data of other ways. For example, when the way number corresponding to the access history is 2, if the way number corresponding to the PRBS is 1, replace the data of the cache line corresponding to way1; if the way number corresponding to the PRBS is 2, select a way from way0, way1 and way3, and replace the data of the corresponding cache line.

[0043] After step 101 to step 102 provided in this embodiment, the PLRU strategy can be improved through PRBS, and data replacement can be completed efficiently using fewer resources while ensuring fairness and hit rate.

[0044] like Figure 3 As shown, the following method can be used to generate a pseudo-random binary sequence of corresponding bit numbers according to the number of cache ways in each cache group.

[0045] Step 201: Calculate the number of bits of the pseudo-random binary sequence according to the number of cache ways, and construct a generator polynomial of the pseudo-random binary sequence according to the number of bits.

[0046] In some embodiments, an n-bit PRBS can be expressed as (2 n -1), or (x n-1 +x n +1), in this embodiment, this form of polynomial is used as the generator polynomial of PRBS. In this embodiment, the number of bits of the PRBS used is related to the number of ways. In a certain scenario, the cache has 8 ways and a 3-bit PRBS needs to be generated. Then n is 3, and its generator polynomial is x 2 +x 3 +1.

[0047] Step 202: Generate a pseudo-random binary sequence through an XOR operation according to the calculation rules of the generator polynomial.

[0048] After obtaining the generating polynomial, the PRBS can be directly calculated based on the generating polynomial, or the corresponding logic circuit can be used to calculate the PRBS. For example, when the PRBS is 7 bits, the initial value of the generating polynomial can be set to 0000001. Each time the calculation is performed, the 6th and 7th bits are XORed as the first bit of the next PRBS, and the generated PRBS is output.

[0049] After step 201 to step 202 provided in this embodiment, the required PRBS can be generated.

[0050] In order to avoid replacing the data accessed last time, in this embodiment, a status value of a corresponding number of bits can be set for each cache group according to the number of cache ways in each cache group, and the status value can be used to record and obtain the previous data access history. Figure 4 As shown, the following method can be used to obtain the cache way that was previously accessed in the current cache group as the access history.

[0051] Step 301: Obtain the cache way number of the previous access, and set the corresponding bit in the state value of the corresponding state group to a specified value according to the cache way number.

[0052] When there are N ways in the cache, log2N bits of status value need to be added to each set, and the status value is used to indicate which way in the set was last accessed. For example, when there are 4 ways in the cache, 2 bits of status are needed. If the third way of a set was last accessed, the status value is 3 (Ob11).

[0053] Step 302: Obtain the state value of the cache group that needs to perform data replacement, and obtain the access history of each cache way according to the value of the corresponding bit in the state value.

[0054] When you need to access a set, get the state value of the set, and then you can know the sequence number of the way that was last accessed in the set based on the state value. For example, if the state value of the set to be replaced is (Ob11), it means that way3 in the set is the way that was last accessed, so the data corresponding to the way will not be replaced this time.

[0055] After step 301 to step 302 provided in this embodiment, the access history of each set can be recorded through the state value. Since only one access history needs to be recorded, there is no need to record the access order of all cache lines in the recent time period, so very few resources are occupied.

[0056] In some implementations, after data replacement, the replaced new data will also be accessed. Therefore, after data replacement, the state value of this set also needs to be set to the sequence number of the replaced way.

[0057] On the other hand, in some embodiments, data replacement is only required when the data to be accessed does not exist in the cache, that is, in the case of a miss; if the data already exists in the cache, that is, when the data hits, no replacement is required. However, regardless of whether data replacement is performed, the status bit needs to be set to the sequence number of the corresponding way. Specifically, when data access is required, it is determined whether the data to be accessed this time already exists in the cache; when the data already exists in the cache, the data is not replaced, and the access history is only modified according to the cache way where the data is located; when the data does not exist in the cache, the data to be accessed this time is obtained from the memory as new data, and the new data is replaced in the cache.

[0058] In this embodiment, in order to avoid replacing the data accessed last time, it is also necessary to compare the way number calculated by the PRBS with the way number in the status, and determine the way number that actually needs to be replaced based on the comparison result. Specifically: the cache way number of the last access is obtained based on the access history, and the cache way number to be replaced is obtained based on the pseudo-random binary sequence; when the cache way number of the last access is different from the cache way number to be replaced, the cache way number to be replaced is used as the cache way for data replacement; when the cache way number of the last access is the same as the cache way number to be replaced, the adjustment strategy is obtained based on the parity check value of the pseudo-random binary sequence during the last data replacement, and the cache way for data replacement is calculated based on the adjustment strategy.

[0059] In this embodiment, when the way number calculated by PRBS is the same as the way number in status, an offset is added to the PRBS calculation result, and the cache line corresponding to the previous or next way is used for data replacement. In the specific implementation, the result of the previous calculation of PRBS can be parity checked. Since the implementation process of the parity check is simple and consumes less resources, and the check result has only two types: pass / fail, the previous or next cache line can be selected according to the result of the parity check. Specifically: the parity check value of the pseudo-random binary sequence used in the previous data replacement is calculated in a bitwise XOR manner, wherein the parity check value is 1 bit; when the parity check value is the first specified value, the previous cache way of the cache way number to be replaced is used as the cache way for data replacement; when the parity check value is the second specified value, the next cache way of the cache way number to be replaced is used as the cache way for data replacement. In this way, only 1 bit of parity check value needs to be recorded to confirm the way number to be replaced without causing additional performance and resource loss.

[0060] The method for replacing data in the cache provided in this embodiment does not completely replace data based on the data usage and access status of the cache, but uses a pseudo-random binary sequence to solve the problem of fairness. Since the pseudo-random binary sequence is simple to implement and requires fewer states, it can also ensure fairness based on randomness, thereby reducing resource consumption and alleviating the problem of excessive resource consumption or insufficient fairness of the traditional PLRU strategy. At the same time, by recording the previous data access history, the most recently used data of the previous access caused by the random replacement method is avoided from being replaced, thereby ensuring the data hit rate in the cache.

[0061] Based on the method for replacing data in a cache provided in the above embodiment, the present invention also provides a device for replacing data in a cache that can be used to implement the above method.

[0062] like Figure 5 FIG. 1 is a schematic diagram of the data replacement device used in an embodiment of the present invention, comprising: at least one pseudo-random binary sequence generator, a comparator, a check module, a first selector and an access history register, for implementing the method for replacing data in a cache in an embodiment of the present invention.

[0063] The output end of the pseudo-random binary sequence generator is connected to the check module, the first input end of the first selector and the first input end of the comparator respectively, so as to generate a pseudo-random binary sequence; wherein the number of pseudo-random binary sequence generators is determined according to the number of cache ways. In a specific implementation, according to step 101, a pseudo-random binary sequence generator can be used to generate the required PRBS, and the number of pseudo-random binary sequence generators is consistent with the number of bits of the PRBS. Figure 6 In the example, three pseudo-random binary sequence generators PRBS0, PRBS1 and PRBS2 are used to generate a 3-bit PRBS.

[0064] The two input ends of the comparator are connected to the pseudo-random binary sequence generator and the access history register respectively, and are used to compare whether the cache way number of the previous access is the same as the cache way number to be replaced. In a specific implementation, the access history register can be used to store the status value, and the comparator can be used to compare the way number corresponding to the calculated PRBS value and the way number corresponding to the status value in accordance with the steps to determine whether to directly use the way number corresponding to the PRBS value for data replacement.

[0065] The input end of the check module is connected to the pseudo-random binary sequence generator, and the output end is connected to the first selector, for generating a parity check value according to the pseudo-random binary sequence, and determining an adjustment strategy for the cache way number according to the parity check value.

[0066] The input end of the first selector is used to select a cache way for data replacement according to the pseudo-random binary sequence, the comparison result of the comparator and the adjustment strategy. In a specific implementation, the first selector can be connected to each way of the cache, and the way for data replacement is selected according to the comparison result.

[0067] The access history register is used to store the access history of each cache way. In specific implementation, each set can use an access history register to store the status value of the set, and the number of bits of the access history register is consistent with the value of the status.

[0068] In some implementations, PRBS can be viewed as a coding sequence consisting of a series of 0s and 1s, and a maximum length shift register sequence is often used in logic circuits for hardware implementation. The register sequence consists of a set of linear feedback shift registers (LFSR) and XOR circuits. Specifically: The pseudo-random binary sequence generator includes shift registers and XOR circuits, specifically including: the number of shift registers is consistent with the number of bits of the pseudo-random binary sequence to be generated, and all shift registers are linearly connected in sequence to perform linear shifts on the binary sequence, with the value of the last bit of the shift register being used as the output of the pseudo-random binary sequence; the XOR circuit is used to perform an XOR operation on the values ​​of the last two bits of the last two shift registers, and input the XOR value into the first bit of the shift register. Figure 7 As shown in the figure, the hardware circuit for generating PRBS of 7-bit PRBS (PRBS7) is shown, and its generating polynomial is x 6 +x 7 +1, initial value is 0000001. Figure 7 In the example, each box with a number is a shift register. Each shift register stores one bit of data to be checked. The number in the box indicates the bit of the register. An XOR circuit is connected between the 6th and 7th bits of the shift register ( Figure 7 China-Israel When calculating, the 6th and 7th bits of the shift register are XORed and input to the 1st bit of the shift register, and the 7th bit of the shift register is used as the output of PRBS7.

[0069] When performing hardware calculations, since the number of bits in the shift register is fixed and cannot be carried, for an n-bit binary number, add (2 n-1 -1) is equivalent to (-1). Therefore, when the way number calculated by PRBS is the same as the way number of status, no matter whether the previous way number or the next way number is needed, it can be calculated through the accumulator. Specifically, Figure 8 As shown, the check module includes: a parity check generator, a check value register, a second selector and an accumulation circuit. The parity check generator generates a parity check value according to a pseudo-random binary sequence and outputs the parity check value to the check value register. The second selector selects an accumulation value corresponding to an adjustment strategy according to the value of the check value register so as to adjust the pseudo-random binary sequence. The accumulation circuit adds the pseudo-random binary sequence and the accumulation value to obtain an adjusted cache path. In a specific implementation, the accumulation (2 n-1 -1) to get the previous way number, or add 1 to get the next way number. For example, when the PRBS is 3 bits, you can choose to add the PRBS value (22 -1), that is, 0b111, to get the previous way number; you can also choose to add 1 (that is, 0b001) to get the next way number.

[0070] In some implementations, the calculation of the parity check bit can be implemented by a simple bitwise XOR method. For example, the data X to be checked is 4 bits, each bit is stored in a parity register, and the value of each bit is x0, x1, x2, and x3, then the parity check value xn = (x0) xor (x1) xor (x2) xor (x3), where xor is an XOR operator, and the calculated xn is output to the check value register. This operation method can be simply used as follows Fig. 9 The logic circuit shown in the figure is implemented, and "=1" in the figure represents an XOR operation. A multi-stage XOR circuit is used to perform a bitwise XOR operation on x0, x1, x2 and x3, and finally obtains a parity check value xn. Specifically: the parity check generator includes: a parity register and an XOR circuit, specifically including: the number of parity registers is consistent with the number of bits of the pseudo-random binary sequence, each parity register is connected through a multi-stage XOR circuit, and the output after the bitwise XOR of all parity registers is used as the parity check value.

[0071] In a specific scenario, for an 8-way, 128-set cache, the data replacement circuit can be used as follows: Fig.10 The hardware structure shown is implemented. Because there are 8 ways, three PRBS generators are needed to produce a 3-bit result, that is, Fig.10 PRBS0, PRBS1 and PRBS2 in .

[0072] When a set needs to replace data, first compare the way number corresponding to the PRBS result with the way number corresponding to the status in the access history register. If the way numbers are not equal, the way number corresponding to the PRBS is directly used as the way to be replaced. If the way numbers are equal, the parity check value generated according to the last PRBS result needs to be stored in the check value register, and the PRBS result is added or subtracted by 1 according to the result of the check value register as the way to be replaced.

[0073] After the replacement is completed, the status in the access history register of the set needs to be set to the sequence number of the replaced way. For example, if the data of way3 is replaced, the status needs to be set to 3.

[0074] It is worth noting that the information interaction, execution process, etc. between the modules and units in the above-mentioned device are based on the same concept as the processing method in the above-mentioned embodiment. The specific contents can be found in the description of the embodiments of the present invention and will not be repeated here.

[0075] A person skilled in the art may understand that all or part of the steps in the various methods of the embodiments may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the storage medium may include: a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for replacing data in a cache, characterized in that: include: When new data enters the cache group, a pseudo-random binary sequence of corresponding bits is generated according to the number of cache ways in each cache group; The cache way that was accessed last time in the current cache group is obtained as the access history, and the cache way for data replacement is determined according to the access history and the pseudo-random binary sequence.

2. The method for replacing data in a cache according to claim 1, characterized in that: Generating a pseudo-random binary sequence of corresponding bits according to the number of cache ways in each cache group includes: Calculate the number of bits of the pseudo-random binary sequence according to the number of cache ways, and construct a generating polynomial of the pseudo-random binary sequence according to the number of bits; According to the calculation rules of the generating polynomial, a pseudo-random binary sequence is generated through an XOR operation.

3. The method for replacing data in a cache according to claim 1, characterized in that: According to the number of cache ways in each cache group, a state value of a corresponding number of bits is set for each cache group, and obtaining the cache way that was previously accessed in the current cache group as the access history includes: Obtain the cache way number of the previous access, and set the corresponding bit in the state value of the corresponding cache group to a specified value according to the cache way number; The state value of the cache group that needs to replace data is obtained, and the access history is obtained according to the value of the corresponding bit in the state value.

4. The method for replacing data in a cache according to claim 1, characterized in that: Determining the cache way for data replacement according to the access history and the pseudo-random binary sequence includes: Obtain the cache way number of the previous access according to the access history, and obtain the cache way number to be replaced according to the pseudo-random binary sequence; When the sequence number of the cache way accessed last time is different from the sequence number of the cache way to be replaced, the sequence number of the cache way to be replaced is used as the cache way for data replacement; When the sequence number of the cache way accessed last time is the same as the sequence number of the cache way to be replaced, an adjustment strategy is obtained according to the parity check value of the pseudo-random binary sequence during the previous data replacement, and the cache way for data replacement is calculated according to the adjustment strategy.

5. The method for replacing data in a cache according to claim 4, characterized in that: The step of obtaining an adjustment strategy according to the parity check value of the pseudo-random binary sequence during the previous data replacement, and calculating the cache path for data replacement according to the adjustment strategy comprises: Calculate the parity check value of the pseudo-random binary sequence used in the previous data replacement in a bitwise XOR manner, where the parity check value is 1 bit; When the parity check value is the first specified value, using a cache way before the cache way sequence number to be replaced as a cache way for data replacement; When the parity check value is the second specified value, a cache way following the sequence number of the cache way to be replaced is used as the cache way for data replacement.

6. The method for replacing data in a cache according to claim 1, characterized in that: Before new data enters the cache group, the method further includes: Determine whether the data to be accessed this time already exists in the cache; When the data already exists in the cache, no data replacement is performed, and only the access history is modified according to the cache way where the data is located; When the data does not exist in the cache, the data to be accessed this time is obtained from the memory as new data, and the new data is replaced in the cache.

7. A device for replacing data in a cache, characterized in that: include: At least one pseudo-random binary sequence generator, a comparator, a check module, a first selector and an access history register, for implementing the method for replacing data in a cache as claimed in any one of claims 1 to 6, wherein: The output end of the pseudo-random binary sequence generator is respectively connected to the check module, the first input end of the first selector and the first input end of the comparator, so as to generate a pseudo-random binary sequence; wherein the number of the pseudo-random binary sequence generators is determined according to the number of cache ways; Two input ends of the comparator are connected to the pseudo-random binary sequence generator and the access history register respectively, and are used to compare whether the cache way number accessed last time is the same as the cache way number to be replaced; The input end of the check module is connected to the pseudo-random binary sequence generator, and the output end is connected to the second input end of the first selector, and is used to generate a parity check value according to the pseudo-random binary sequence, and determine the adjustment strategy of the cache way number according to the parity check value; The first selector is used to select a cache way for data replacement according to the pseudo-random binary sequence, the comparison result of the comparator and the adjustment strategy; The access history register is used to store the access history of each cache way.

8. The device for replacing data in a cache according to claim 7, characterized in that: The pseudo-random binary sequence generator comprises: a shift register and an XOR circuit, wherein: The number of shift registers is consistent with the number of bits of the pseudo-random binary sequence to be generated, and all the shift registers are linearly connected in sequence to perform linear shift on the binary sequence, and the value of the last bit of the shift register is used as the output of the pseudo-random binary sequence; The XOR circuit is used for performing an XOR operation on the values ​​of the last two bits of the last two shift registers, and inputting the XOR-operated value into the first bit of the shift register.

9. The device for replacing data in a cache according to claim 7, characterized in that: The check module comprises: a parity check generator, a check value register, a second selector and an accumulation circuit, wherein: The parity check generator generates a parity check value according to a pseudo-random binary sequence, and outputs the parity check value to a check value register; The second selector selects the accumulated value corresponding to the adjustment strategy according to the value of the check value register, so as to adjust the pseudo-random binary sequence; The accumulation circuit adds the pseudo-random binary sequence and the accumulation value to obtain the adjusted cache way.

10. The device for replacing data in a cache according to claim 8, characterized in that: The parity generator comprises: a parity register and an XOR circuit, wherein: The number of parity registers is consistent with the number of bits of the pseudo-random binary sequence, and each parity register is connected through a multi-stage XOR circuit, and the output of all parity registers after bitwise XOR is used as a parity check value.

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