Data transmission system of SRB development board

By designing the data transmission system of the SRB development board, using connectors, PHY chips and network connection interfaces, the RGMII signal is converted into a Gigabit Ethernet signal, and efficient two-way data transmission between the SRB development board and the upper computer is achieved, solving the problem of being unable to transmit signals with the upper computer.

CN119829489APending Publication Date: 2025-04-15北京傲星科技有限公司
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Patent Information

Application Number
CN202411880186.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-19
Publication Date
2025-04-15

AI Technical Summary

Technical Problem

The SRB development board cannot transmit signals with the upper computer, which limits its application and data transmission capabilities.

Method used

A data transmission system for the SRB development board is designed, including connectors, physical layer PHY chips and network connection interfaces. The connector acquires the RGMII signal through the EMIF interface of the SRB development board, and the PHY chip converts the RGMII signal into a Gigabit Ethernet signal, and transmits it to the upper computer through the network connection interface.

Benefits of technology

It realizes efficient two-way data transmission between the SRB development board and the upper computer, breaks the limitations of the original vehicle network, and improves the accuracy, timeliness and reliability of data transmission.

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Abstract

The invention discloses a data transmission system of an SRB development board. The data transmission system of the SRB development board combines a connector, a PHY chip and a network connection interface. Wherein the connector is connected with an EMIF interface of the SRB development board, the connector is further connected with the PHY chip, the PHY chip is connected with the network connection interface, and the network connection interface is connected with the upper computer. The connector firstly obtains an RGMII signal through an EMIF interface of the SRB development board. And then the PHY chip converts the RGMII signal into a gigabit Ethernet signal, so that the network connection interface transmits the gigabit Ethernet signal to an upper computer. According to the invention, the EMIF interface of the SRB development board is connected with the RGMII signal through the connector, and the RGMII signal is converted into the gigabit Ethernet signal through the PHY chip, so that standard gigabit Ethernet communication between the SRB development board and the upper computer is realized.
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Description

Technical Field

[0001] The present application relates to the field of network communication technology, and in particular to a data transmission system of an SRB development board. Background Art

[0002] In the related technical solutions, the Secure Real-Time Bus (SRB) development board can only transmit data with other devices through its interface. However, since the SRB development board can only be used as a downlink device for testing and debugging, it can only be connected using the in-vehicle Ethernet, which makes it impossible for the SRB development board to transmit signals with the host computer.

[0003] Therefore, how to prevent the SRB development board from transmitting signals to the host computer is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] Based on the above problems, the present application provides a data transmission system for an SRB development board, which can test the connectivity and transmission rate of the vehicle network before the vehicle leaves the factory to ensure the accuracy, timeliness and reliability of data transmission, thereby improving the stability and safety of the entire vehicle system.

[0005] The embodiments of the present application disclose the following technical solutions:

[0006] A data transmission system for an SRB development board, the system comprising: a connector, a physical layer PHY chip and a network connection interface;

[0007] The connector is connected to the external memory interface EMIF interface of the secure real-time bus SRB development board; the connector is also connected to the PHY chip; the PHY chip is connected to the network connection interface; the network connection interface is connected to the host computer;

[0008] The connector is used to obtain a simplified Gigabit Media Independent Interface RGMII signal through the EMIF interface of the SRB development board;

[0009] The PHY chip is used to convert the RGMII signal into a Gigabit Ethernet signal;

[0010] The network connection interface is used to transmit the Gigabit Ethernet signal to the host computer.

[0011] In a possible implementation, the connector is selected as ZX-PM2.54-2-25PY.

[0012] In a possible implementation, the PHY chip is YT8521-SH.

[0013] In a possible implementation, the network connection interface includes an RJ45 network port.

[0014] In a possible implementation, the system further includes: a verification module; the verification module is connected to the PHY chip and the network connection interface respectively;

[0015] The verification module is used to perform a cyclic redundancy check (CRC) on the obtained RGMII signal;

[0016] The verification module is further used to perform CRC verification on the Gigabit Ethernet signal to be transmitted.

[0017] In a possible implementation, the system further includes: an indication module; the indication module is connected to the connector;

[0018] The indication module is used to indicate whether the connector is correctly connected to the EMIF interface of the SRB development board.

[0019] In a possible implementation, the system further includes: a data cache module; the data cache module is connected to the connector;

[0020] The data cache module is used to temporarily store the RGMII signal obtained from the EMIF interface of the SRB development board in a cache to ensure smooth transmission of the data stream.

[0021] In a possible implementation, the system further includes: a power supply module; the power supply module is connected to the PHY chip;

[0022] The power supply module is used to supply power to the PHY chip.

[0023] Compared with the prior art, this application has the following beneficial effects:

[0024] The present application provides a data transmission system for an SRB development board, which includes a connector, a physical layer PHY chip, and a network connection interface. Specifically, the connector is connected to the external memory interface (Enhanced Memory Interface, EMIF) of the secure real-time bus SRB development board, and is also connected to the physical layer (PHY) chip. The PHY chip is connected to the network connection interface, and the network connection interface is connected to the host computer. The function of the connector is to obtain the Reduced Gigabit Media Independent Interface (RGMII) signal through the EMIF interface of the SRB development board. The PHY chip converts the obtained RGMII signal into a standard Gigabit Ethernet signal. The network connection interface is responsible for transmitting the converted Gigabit Ethernet signal to the host computer, thereby realizing efficient data transmission between the SRB development board and the host computer. The present application is connected to the EMIF interface of the SRB development board through a connector, and uses the RGMII signal to obtain the signal required for data transmission. This design makes the SRB development board no longer limited to passive downlink transmission in the vehicle network, and can be connected to the host computer through the RGMII signal, breaking the original limitation. At the same time, the PHY chip in this application converts the RGMII signal into a standard Gigabit Ethernet signal. Through this conversion, the SRB development board can support the Gigabit Ethernet protocol, rather than being limited to the vehicle network protocol. In this way, the SRB development board can communicate with the host computer through standard Gigabit Ethernet and realize two-way data transmission, thereby solving the problem in the prior art that the SRB development board cannot transmit signals with the host computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A structural schematic diagram of a data transmission system of an SRB development board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the background technology involved in the embodiments of the present application will be described below.

[0028] In the relevant technical solution, the SRB development board can only transmit data with other devices through its interface, and due to its limited functions, it can only be used as a downlink device for testing and debugging. Therefore, it can only be connected using the on-board Ethernet, which makes the SRB development board unable to transmit signals with the host computer.

[0029] In order to solve this problem, a data transmission system of an SRB development board is provided in an embodiment of the present application, and its structure includes a connector, a physical layer PHY chip and a network connection interface, which is intended to achieve efficient data transmission between the SRB development board and the host computer. Specifically, the connector obtains the RGMII signal through the EMIF interface of the SRB development board, and the RGMII signal is then transmitted to the PHY chip through the connector. The function of the PHY chip is to convert the RGMII signal into a standard Gigabit Ethernet signal so that the converted signal can be transmitted to the host computer through the network connection interface. The present application connects the EMIF interface of the SRB development board with the RGMII signal through a connector, and uses the PHY chip to convert the RGMII signal into a Gigabit Ethernet signal, thereby achieving standard Gigabit Ethernet communication between the SRB development board and the host computer. This design breaks the original vehicle network limitations, enables the SRB development board to support two-way data transmission, and solves the problem that the prior art cannot transmit signals with the host computer.

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] See also Figure 1 , Figure 1 A structural diagram of a data transmission system of an SRB development board provided in an embodiment of the present application, such as Figure 1 As shown, the data transmission system of the SRB development board includes: a connector, a physical layer PHY chip and a network connection interface. The connector is connected to the external memory interface EMIF interface of the secure real-time bus SRB development board; the connector is also connected to the PHY chip; the PHY chip is connected to the network connection interface; the network connection interface is connected to the host computer.

[0032] In a possible implementation, the connector is selected as ZX-PM2.54-2-25PY.

[0033] ZX-PM2.54-2-25PY is a connector series produced by Panasonic. Specifically, this connector model can be disassembled into the following parts:

[0034] ZX: Usually indicates that the connector belongs to the ZX series.

[0035] PM2.54: Indicates the pin pitch of the connector, that is, the distance between each pin is 2.54 mm.

[0036] 2: This number indicates the number of pins on the connector, i.e., the connector has two pins.

[0037] 25: This number usually refers to the arrangement number or size specification of the connector, which may indicate the length of the connector or the number of pin arrangements.

[0038] PY: Usually the material or type code of the connector.

[0039] In a possible implementation, the PHY chip is YT8521-SH. YT8521-SH is a PHY chip, which is usually used in high-speed network connection devices, especially in applications such as automotive Ethernet. It is mainly responsible for converting the signal of the upper data link layer into the Ethernet signal of the physical layer, thereby realizing data transmission.

[0040] In a possible implementation, the network connection interface includes an RJ45 network port. The RJ45 (Registered Jack 45) network port is a common standardized connection interface in network devices, and is mainly used for connection between Ethernet devices.

[0041] The connector is used to obtain a simplified Gigabit Media Independent Interface RGMII signal through the EMIF interface of the SRB development board.

[0042] The main function of the connector is to extract the RGMII signal from the EMIF interface of the SRB development board. Specifically, the EMIF interface on the SRB development board provides the ability to communicate with external memory or other peripherals, and the role of the connector is to capture the RGMII signal from this interface. The RGMII signal is a simplified Gigabit Ethernet medium independent interface signal that contains various control and data information required for high-speed data transmission. By obtaining these signals from the EMIF interface through the connector, the system can further process these signals to realize the data transmission function with the host computer.

[0043] The PHY chip is used to convert the RGMII signal into a Gigabit Ethernet signal.

[0044] The main function of the PHY chip is to convert the RGMII signal obtained from the EMIF interface of the SRB development board through the connector into a standard Gigabit Ethernet signal. Specifically, the RGMII signal is a simplified Gigabit Ethernet Media Independent Interface signal, which contains the control and data information required for data transmission, but the format does not fully comply with the standard Gigabit Ethernet protocol. As a physical layer chip, the PHY chip is specifically responsible for processing the data transmission task of the physical layer. It can parse various data and control information in the RGMII signal and convert it into a signal format that complies with the standard Gigabit Ethernet protocol. This conversion not only ensures the compatibility of the signal, but also enables these signals to be transmitted through a standard network connection interface (such as an RJ45 network port), thereby communicating efficiently with the host computer or other network devices. Through this conversion process, the SRB development board can use the standard Gigabit Ethernet protocol to perform bidirectional data transmission with external devices, greatly improving its data transmission capability and application flexibility.

[0045] The network connection interface is used to transmit the Gigabit Ethernet signal to the host computer.

[0046] The main function of the network connection interface is to transmit the standard Gigabit Ethernet signal converted by the PHY chip to the host computer. Specifically, the network connection interface usually refers to a physical interface, such as an RJ45 Ethernet interface, which can receive the standard Gigabit Ethernet signal from the PHY chip and send it to the host computer through a wired connection.

[0047] In this process, the role of the network connection interface is crucial, because it not only ensures the physical transmission of the signal, but also ensures the stability and reliability of the signal during the transmission process. Through this interface, the SRB development board can establish a direct network connection with the host computer for efficient data exchange and communication. This design makes the SRB development board no longer limited to data transmission in the vehicle network, but can perform two-way data transmission with the host computer through the standard Gigabit Ethernet protocol, thereby greatly enhancing its application scope and flexibility.

[0048] In a possible implementation, the system further includes: a verification module; the verification module is connected to the PHY chip and the network connection interface respectively.

[0049] In the data transmission system of the entire SRB development board, in addition to the connector, PHY chip and network connection interface, it also contains a module dedicated to data verification. The main function of this verification module is to perform verification operations during data transmission.

[0050] Specifically, the verification module is used to perform a cyclic redundancy check (CRC) on the obtained RGMII signal. This means that when the connector obtains the RGMII signal from the EMIF interface of the SRB development board, the verification module will verify these signals to ensure their integrity. Through the CRC check, it is possible to detect whether the signal has errors or damage during the transmission process, thereby ensuring that the data processed subsequently is accurate.

[0051] In addition, the verification module is also used to perform CRC verification on the Gigabit Ethernet signals to be transmitted. This means that before the verification module transmits the converted standard Gigabit Ethernet signals to the host computer through the network connection interface, the signals will be CRC verified again. This process is also to ensure the integrity and correctness of the signal and further improve the reliability of data transmission.

[0052] Through these two verification steps, the system can perform strict data verification when data enters and leaves the system, effectively ensuring the accuracy and reliability of data transmission and avoiding data anomalies or losses due to transmission errors.

[0053] In a possible implementation manner, the system further includes: an indication module; the indication module is connected to the connector.

[0054] The indication module is used to indicate whether the connector is correctly connected to the EMIF interface of the SRB development board.

[0055] The main function of the indicator module is to detect and display the status of the connection between the connector and the SRB development board. When the connector is successfully and correctly inserted or connected to the EMIF interface of the SRB development board, the indicator module will notify the user that the connection is successful in some way (such as lighting up an LED light or displaying specific status information). On the contrary, if the connection is wrong or not fully connected, the indicator module will display the corresponding error or disconnected status.

[0056] This design increases the reliability and user-friendliness of the system, allowing users to intuitively understand whether the connector is installed correctly, thereby avoiding data transmission failure or other failures caused by connection problems. In this way, the system is able to provide real-time connection status feedback, which helps to quickly diagnose and solve potential problems.

[0057] In a possible implementation, the system further includes: a data cache module; the data cache module is connected to the connector.

[0058] The data cache module is used to temporarily store the RGMII signal obtained from the EMIF interface of the SRB development board in a cache to ensure smooth transmission of the data stream.

[0059] The main function of the data cache module is to temporarily store the RGMII signals obtained from the EMIF interface of the SRB development board through the connector in the cache to ensure smooth transmission of the data stream. This means that when the connector captures the RGMII signals from the EMIF interface of the SRB development board, these signals will be stored in the data cache module first, instead of being immediately passed to the subsequent processing unit (such as the PHY chip).

[0060] This design has several important uses:

[0061] Smooth data flow: By temporarily storing data in the cache, it can effectively solve the problem of sudden traffic that may occur during data transmission and ensure that the data flow is smoothly transmitted to the next processing stage.

[0062] Reduce packet loss rate: During the data transmission process, you may encounter instantaneous data transmission bottlenecks or delays. The cache mechanism can avoid packet loss caused by mismatched data transmission rates.

[0063] Improved reliability: The cache mechanism can also serve as a temporary storage point for data, improving the reliability and stability of the overall system and ensuring data integrity and continuity even when data transmission is unstable for a short period of time.

[0064] Through such a design, the data cache module not only enhances the data transmission capability of the system, but also improves the stability and reliability of the system, ensuring the efficient operation of the entire data transmission process.

[0065] In a possible implementation, the system further includes: a power supply module; the power supply module is connected to the PHY chip;

[0066] The power supply module is used to supply power to the PHY chip.

[0067] The main function of the power supply module is to supply power to the PHY chip. This means that the power supply module is connected to the PHY chip through a physical connection and provides the necessary power support to ensure that the PHY chip can operate normally. As a physical layer chip, the PHY chip is responsible for processing the conversion and transmission of data signals, so a stable power supply is required to ensure its normal operation.

[0068] The above is a detailed introduction to the data transmission system of an SRB development board provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can refer to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0069] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

Claims

1. A data transmission system for an SRB development board, characterized in that: The system comprises: a connector, a physical layer PHY chip and a network connection interface; The connector is connected to the external memory interface EMIF interface of the secure real-time bus SRB development board; the connector is also connected to the PHY chip; the PHY chip is connected to the network connection interface; the network connection interface is connected to the host computer; The connector is used to obtain a simplified Gigabit Media Independent Interface RGMII signal through the EMIF interface of the SRB development board; The PHY chip is used to convert the RGMII signal into a Gigabit Ethernet signal; The network connection interface is used to transmit the Gigabit Ethernet signal to the host computer.

2. The method according to claim 1, characterized in that The selected connector is ZX-PM2.54-2-25PY.

3. The method according to claim 1, characterized in that The PHY chip selected is YT8521-SH.

4. The method according to claim 1, characterized in that The network connection interface includes an RJ45 network port.

5. The method according to claim 1, characterized in that The system further comprises: a verification module; the verification module is connected to the PHY chip and the network connection interface respectively; The verification module is used to perform a cyclic redundancy check (CRC) on the obtained RGMII signal; The verification module is further used to perform CRC verification on the Gigabit Ethernet signal to be transmitted.

6. The method according to claim 1, characterized in that The system further comprises: an indication module; the indication module is connected to the connector; The indication module is used to indicate whether the connector is correctly connected to the EMIF interface of the SRB development board.

7. The method according to claim 1, characterized in that The system further comprises: a data cache module; the data cache module is connected to the connector; The data cache module is used to temporarily store the RGMII signal obtained from the EMIF interface of the SRB development board in a cache to ensure smooth transmission of the data stream.

8. The method according to claim 1, characterized in that: The system further includes: a power supply module; the power supply module is connected to the PHY chip; The power supply module is used to supply power to the PHY chip.