Clock extension implementation method and device based on integrated circuit bus IIC

Abstract

The invention provides a clock extension implementation method and device based on an integrated circuit bus (IIC). According to the invention, the clock extension indication signal line is added between the IIC master device and the control device in the communication control system, and the IIC master device sends the first notification to the control device through the clock extension indication signal line to start clock extension, so that the control device maintains the SCL pin of the slave device to be in a low-level state to pause data transmission, and the communication control efficiency is improved. Under the condition that a second notice sent by the IIC master device to the control device through the clock extension indication signal line to cancel the clock extension is not received, even if the specified time period of the SCL clock period is ended, the SCL pin is maintained at a low level instead of being controlled to be in a high-resistance state in a conventional IIC data transmission mechanism, so that the SCL pin is prevented from being in a high-resistance state, and the SCL pin is prevented from being in a high-resistance state. According to the invention, the limitation of the current data transmission mechanism is broken, and the clock extension mechanism is triggered by the IIC master device.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method and device for implementing clock extension based on an integrated circuit bus IIC. Background Art

[0002] Clock stretching is an important mechanism in the IIC (Inter-Integrated Circuit) communication protocol, which means that the IIC master or slave device suspends data transmission by keeping the SCL signal line at a low level until the serial clock line (SCL: Serial Clock Line) changes from a low level to a high level to resume data transmission. For example, when the IIC master device is transmitting data with the IIC slave device, it receives a higher priority task. At this time, the IIC master device can control the SCL pin connected to the IIC slave device to a low level, so that the SCL signal line maintains a low level to give priority to the higher priority task. After completing the higher priority task, the IIC master device can control the SCL pin connected to the IIC slave device to a high impedance state to resume data transmission with the IIC slave device.

[0003] In practical applications, in order to apply the IIC bus more flexibly, the IIC master device usually communicates with the IIC slave device through a control device. When the SCL between the IIC master device and the IIC slave device is not directly connected, the clock stretching mechanism in the IIC communication protocol cannot be implemented. Summary of the invention

[0004] In view of this, the present application provides a communication control system, method and apparatus based on an integrated circuit bus IIC, so as to implement a clock stretching mechanism in the IIC communication protocol by controlling the device when there is no direct connection between the SCL of the IIC master device and the IIC slave device.

[0005] The technical solutions provided by this application are as follows:

[0006] According to an embodiment of the first aspect of the present application, a clock stretching implementation method based on an integrated circuit bus IIC is provided, and the method is applied to an IIC master device in a communication control system; the communication control system also includes an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock stretching indication signal line is also connected between the IIC master device and the control device; the method includes:

[0007] If it is determined to start the clock stretching, a first notification is sent to the control device through the clock stretching indication signal line, so that the control device maintains the pin connected to the slave device SCL on the control device in a low level state based on the first notification; wherein, when the control device receives the falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state;

[0008] If it is determined to cancel the clock stretch, a second notification is sent to the control device through the clock stretch indication signal line, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0009] Optionally, the control device includes a slave device SCL control component; the slave device SCL control component is used to control the state of a pin on the control device connected to the slave device SCL;

[0010] The IIC master device is connected to the slave device SCL control component via the clock stretch indication signal line.

[0011] Optionally, a pin on the IIC master device connected to the SCL of the master device is in a high-impedance state after the IIC master device determines to cancel clock stretching.

[0012] Optionally, the first notification is sent within a specified time period of an SCL clock cycle after sending a falling edge of the SCL clock signal, and the SCL clock cycle is a set duration starting from a falling edge of the SCL clock signal.

[0013] Optionally, the SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period includes:

[0014] The SCL low level period, and the SCL high level period except the data transmission period.

[0015] According to an embodiment of the second aspect of the present application, a clock stretching implementation method based on an integrated circuit bus IIC is provided, and the method is applied to a control device in a communication control system; the communication control system further includes an IIC master device and an IIC slave device connected to the IIC master device, the control device is connected between the IIC master device and the IIC slave device, and a clock stretching indication signal line is also connected between the control device and the IIC master device; the method includes:

[0016] If a first notification sent by the IIC master device is received through the clock stretch indication signal line between the IIC master device and the IIC master device, then based on the first notification, the pin connected to the slave device SCL on the control device is maintained in a low level state; wherein, when the control device receives the falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state;

[0017] If a second notification sent by the IIC master device is received through the clock stretch indication signal line between the IIC master device and the control device, the pin connected to the slave device SCL on the control device is controlled to be in a high impedance state based on the second notification;

[0018] If it is detected that the level of the slave device SCL is converted from a low level to a high level, the pin of the control device connected to the master device SCL is controlled to be in a high impedance state.

[0019] Optionally, the control device includes a slave device SCL control component; the slave device SCL control component is used to control the state of a pin on the control device connected to the slave device SCL;

[0020] The slave device SCL control component is connected to the IIC master device via the clock stretch indication signal line.

[0021] Optionally, the first notification is sent within a specified time period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal; the SCL clock cycle is an SCL clock cycle starting from the falling edge of the SCL clock signal most recently received from the master device SCL.

[0022] Optionally, the SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period includes:

[0023] The SCL low level period, and the SCL high level period except the data transmission period.

[0024] Optionally, the first notification is sent during an SCL low level period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises:

[0025] If a second notification is received from the IIC master device through the clock stretch indication signal line, check whether the current moment is before the end of the SCL low level period in the SCL clock cycle; if so, end the SCL clock cycle; if not, continue to execute the operation of controlling the pin of the control device connected to the slave device SCL to be in a high-impedance state based on the second notification.

[0026] Optionally, the first notification is sent during an SCL low level period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises:

[0027] If the second notification sent by the IIC master device through the clock stretch indication signal line is not received at the end of the SCL low level period in the SCL clock cycle, the pin on the control device connected to the slave device SCL continues to be maintained at a low level state.

[0028] Optionally, the first notification is sent in an SCL high level period other than a data transmission period in an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises:

[0029] End the SCL clock cycle and start a new SCL clock cycle. If a second notification sent by the IIC master device through the clock stretch indication signal line is received, check whether the current moment is before the end of the SCL low level period in the new SCL clock cycle; if so, end the new SCL clock cycle; if not, continue to execute the operation of controlling the pin of the control device connected to the slave device SCL to be in a high-impedance state based on the second notification; the pin of the IIC master device connected to the master device SCL is in a low level state after the IIC master device determines to start clock stretching.

[0030] Optionally, the first notification is sent in an SCL high level period other than a data transmission period in an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises:

[0031] The SCL clock cycle ends and a new SCL clock cycle starts. If the second notification sent by the IIC master device through the clock stretch indication signal line has not been received at the end of the SCL low level period in the new SCL clock cycle, the pin on the control device connected to the SCL of the slave device continues to be maintained in a low level state; the pin on the IIC master device connected to the SCL of the master device is in a low level state after the IIC master device determines to start clock stretching.

[0032] According to an embodiment of the third aspect of the present application, a clock stretching implementation device based on an integrated circuit bus IIC is provided, and the device is applied to an IIC master device in a communication control system; the communication control system also includes an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock stretching indication signal line is also connected between the IIC master device and the control device; the device includes:

[0033] An enabling unit, configured to send a first notification to the control device through the clock extension indication signal line if it is determined to enable the clock extension, so that the control device maintains the pin connected to the slave device SCL on the control device in a low level state based on the first notification; wherein, when the control device receives a falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state;

[0034] The canceling unit is used to send a second notification to the control device through the clock stretch indication signal line if it is determined to cancel the clock stretch, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0035] According to an embodiment of a fourth aspect of the present application, a clock stretching implementation device based on an integrated circuit bus IIC is provided, and the device is applied to a control device in a communication control system; the communication control system also includes an IIC master device and an IIC slave device connected to the IIC master device, the control device is connected between the IIC master device and the IIC slave device, and a clock stretching indication signal line is also connected between the control device and the IIC master device; the device includes:

[0036] A maintaining unit, configured to maintain the pin connected to the slave device SCL on the control device in a low level state based on the first notification if the first notification sent by the IIC master device is received through the clock stretch indication signal line between the control device and the IIC master device; wherein, when the control device receives a falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state;

[0037] A control unit, for controlling the pin on the control device connected to the slave device SCL to be in a high-impedance state based on the second notification if a second notification sent by the IIC master device is received through the clock stretch indication signal line between the control device and the IIC master device; and for controlling the pin on the control device connected to the master device SCL to be in a high-impedance state if it is detected that the level of the slave device SCL is converted from a low level to a high level.

[0038] According to an embodiment of the fifth aspect of the present application, an IIC master device is provided, wherein the IIC master device is an IIC master device in a communication control system; the communication control system further comprises an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock stretch indication signal line is further connected between the IIC master device and the control device; the IIC master device is used to execute the method described in the first aspect.

[0039] According to an embodiment of a sixth aspect of the present application, a control device is provided, the control device being a control device in a communication control system, the communication control system further comprising an IIC master device and an IIC slave device connected to the IIC master device, the control device being connected between the IIC master device and the IIC slave device, and a clock stretch indication signal line being further connected between the IIC master device and the control device; the control device comprising:

[0040] A frequency counter, which is in communication with the slave device SCL control module, and is used to count according to a preset frequency, and trigger the slave device SCL control module to control the pin on the control device connected to the slave device SCL to be in a high impedance state when counting reaches the end of a specified period;

[0041] A slave device SCL control module is connected to the frequency counter and the master-slave SCL control module in communication, connected to the IIC slave device through the slave device SCL, and connected to the IIC master device through the clock extension indication signal line, and the slave device SCL control module is used to control the state of the pin connected to the slave device SCL on the control device according to the signal sent by the master-slave SCL control module, the frequency counter and the clock extension indication signal line;

[0042] A first edge detection module is connected to the IIC master device through the master device SCL and is in communication connection with the master-slave SCL control module, and the first edge detection module is used to detect the level change of the master device SCL;

[0043] a master-slave SCL control module, which is communicatively connected with the first edge detection module, the slave device SCL control module and the second edge detection module, and is connected with the IIC master device through the master device SCL, and the master-slave SCL control module is used to control the state of the pin connected to the master device SCL on the control device according to the detection results of the first edge detection module and the second edge detection module, and control the slave device SCL control module, so that the slave device SCL control module controls the state of the pin connected to the slave device SCL on the control device;

[0044] The second edge detection module is connected to the IIC slave device through the slave device SCL and is in communication connection with the master-slave SCL control module. The second edge detection module is used to detect the level change of the slave device SCL.

[0045] It can be seen from the above technical scheme that the present application adds a clock extension indication signal line between the IIC master device and the control device in the communication control system. When the IIC master device determines to start the clock extension, it sends a first notification to the control device through the clock extension indication signal line, so that the control device maintains the slave device SCL pin connected to the slave device SCL on the control device in a low level state based on the first notification. When the clock extension invalid indication signal is not received, even if the specified time period of the SCL clock cycle ends, the slave device SCL pin connected to the slave device SCL will not be controlled to be in a high impedance state like a conventional data transmission mechanism, but the slave device SCL pin connected to the slave device SCL on the control device is always maintained in a low level state to suspend data transmission, breaking the limitation of the current IIC data transmission mechanism. Until the master device sends a second notification to the control device through the clock extension indication signal line to cancel the clock extension, the slave device SCL pin connected to the slave device SCL is controlled to be in a high impedance state to resume data transmission, so as to implement the clock extension mechanism in the IIC communication protocol when the SCL between the IIC master device and the IIC slave device is not directly connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0047] Figure 1 A schematic diagram of the communication control system structure provided in an embodiment of the present application;

[0048] Figure 2 A flowchart of a clock extension implementation method based on an integrated circuit bus IIC provided in an embodiment of the present application;

[0049] Figure 3A flowchart of another clock extension implementation method based on an integrated circuit bus IIC provided in an embodiment of the present application;

[0050] Figure 4 A schematic diagram of specific modules of a communication control system provided in an embodiment of the present application;

[0051] Figure 5 A schematic diagram of the specific structure of a communication control system of multiple IIC hosts provided in an embodiment of the present application;

[0052] Figure 6 A schematic diagram of specific modules of another communication control system provided in an embodiment of the present application;

[0053] Figure 7 A schematic diagram of the structure of a clock extension implementation device based on an integrated circuit bus IIC provided in an embodiment of the present application;

[0054] Figure 8 A schematic diagram of the structure of another clock stretching implementation device based on an integrated circuit bus IIC provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application and to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0056] First combine Figure 1 A brief description is given of the communication control system used in this application.

[0057] Please refer to Figure 1 , Figure 1 A schematic diagram of the communication control system structure provided in an embodiment of the present application.

[0058] like Figure 1 As shown, the communication control system includes an integrated circuit bus (IIC: Inter-Integrated Circuit) master device, an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device. A clock extension indication signal line is also connected between the IIC master device and the control device.

[0059] In this embodiment, the IIC master device and the control device communicate via the master device serial clock line (SCL ：Serial ClockLine) and clock extension indication signal line; the IIC slave device and the control device are connected through the slave device SCL; the IIC master device and the IIC slave device are connected through the serial data line (SDA: Serial Data Line).

[0060] In this embodiment, the control device may be a complex programmable logic device (CPLD: Complex Programmable Logic Device) or a field programmable gate array (FPGA: Field-Programmable Gate Array), and this application does not impose any limitation on this.

[0061] As an embodiment, the control device includes a control component for controlling the SCL of the slave device; the control component is used to control the state of the SCL pin of the slave device;

[0062] The IIC master device is connected to the control component via a clock extension indication signal line.

[0063] Based on the above control communication control system, the present application proposes a clock extension implementation method based on the integrated circuit bus IIC to realize the host start-up clock extension.

[0064] Please refer to Figure 2 , Figure 2 A flowchart of a method for implementing clock extension based on an integrated circuit bus IIC provided in an embodiment of the present application.

[0065] like Figure 2 As shown, the method is applied to an IIC master device in a communication control system, and the method may include the following steps:

[0066] Step 201: If it is determined to start clock stretching, a first notification is sent to the control device through the clock stretch indication signal line, so that the control device maintains the pin connected to the slave device SCL on the control device at a low level state based on the first notification.

[0067] In this embodiment, when the control device receives the falling edge of the SCL clock signal, the pin on the control device connected to the slave device SCL is controlled to be in a low level state and the pin on the control device connected to the master device SCL is controlled to be in a low level state.

[0068] In this embodiment, the SCL clock signal includes a low-level signal and a high-level signal. The conversion from a high level to a low level is called the falling edge of the clock signal, and the conversion from a low level to a high level is called the rising edge of the clock signal. The SCL clock cycle is a set duration based on the falling edge of the SCL clock signal, and one SCL clock cycle transmits 1 bit of data.

[0069] In this embodiment, an SCL clock cycle includes an SCL low-level period and an SCL high-level period. The data on the serial data line SDA changes during the SCL low-level period and starts to be read at the rising edge of the clock signal, that is, the rising edge generated when the SCL low-level period is converted to the SCL high-level period. The period in which the data reading process is completed can be recorded as a data transmission period, and the data transmission period is part of the SCL high-level period.

[0070] As an embodiment, an SCL clock cycle may include a low level in the first 1 / 2 cycle and a high level in the last 1 / 2 cycle, and the present application does not limit this.

[0071] Among them, the falling edge of the SCL clock signal can be the falling edge caused by the SCL low level period in the normal SCL clock cycle, or it can be the falling edge caused by the control device controlling the pin connected to the slave device SCL on the control device to be in a low level state based on the first notification. The above two situations will be described in detail through specific embodiments below, and will not be repeated here.

[0072] As an embodiment, the first notification is sent within a specified period of the SCL clock cycle after sending the falling edge of the SCL clock signal, and the specified period may include an SCL low level period and an SCL high level period except a data transmission period.

[0073] Regarding the two different time periods for sending the first notification, the above two situations will be described in detail through specific embodiments below, and will not be described again here.

[0074] Step 202: If it is determined to cancel the clock stretching, a second notification is sent to the control device through the clock stretching indication signal line, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0075] In this embodiment, before receiving the second notification, the control device will always maintain the pin on the control device connected to the slave device SCL in a low level state. Since no rising edge and falling edge are generated, the communication between the IIC master device and the IIC slave device is suspended.

[0076] When the IIC master device determines to cancel the clock stretch, it can send a second notification for indicating the cancellation of the clock stretch through the clock stretch indication signal line. After receiving the second notification, the control device can control the pin connected to the slave device SCL on the control device to be in a high-impedance state. At this time, the slave device SCL is converted from a low level to a high level, generating a rising edge, and the data on the SDA line is read, and the communication between the IIC master device and the IIC slave device is restored.

[0077] As an embodiment, the pin on the IIC master device connected to the SCL of the master device is in a high impedance state after the IIC master device determines to cancel the clock stretching.

[0078] When the IIC master device determines to cancel the clock stretching, the pin on the IIC master device connected to the master device SCL can be controlled to be in a high impedance state to wait for the start of the next SCL clock cycle.

[0079] The specific process of enabling clock stretching of the master device will be described in detail in the specific embodiments below and will not be repeated here.

[0080] This concludes Figure 2 Description of the process in .

[0081] Please refer to Figure 3 , Figure 3 A flowchart of another clock stretching implementation method based on an integrated circuit bus IIC provided in an embodiment of the present application.

[0082] like Figure 3 As shown, the method is applied to a control device in a communication control system, and the method may include the following steps:

[0083] Step 301: If a first notification sent by the IIC master device is received through the clock stretch indication signal line between the IIC master device and the IIC master device, then based on the first notification, the pin of the control device connected to the slave device SCL is maintained in a low level state.

[0084] When the control device receives the falling edge of the SCL clock signal, the pin on the control device connected to the slave device SCL is controlled to be in a low level state and the pin on the control device connected to the master device SCL is controlled to be in a low level state.

[0085] Step 302: If a second notification sent by the IIC master device is received through the clock stretch indication signal line between the IIC master device and the IIC master device, the pin of the control device connected to the slave device SCL is controlled to be in a high impedance state based on the second notification.

[0086] Step 303: If it is detected that the level of the slave device SCL is converted from a low level to a high level, the pin of the control device connected to the master device SCL is controlled to be in a high impedance state.

[0087] It is easy to understand that Figure 3 The method described in this paper is based on the control device as the execution subject, and its overall process is similar to Figure 2 The method in is similar.

[0088] In this embodiment, the first notification is sent within a specified period of an SCL clock cycle after the IIC master sends a falling edge of an SCL clock signal; an SCL clock cycle is an SCL clock cycle starting from the falling edge of an SCL clock signal sent by the most recently received master SCL.

[0089] The SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period may include:

[0090] The SCL low level period, and the SCL high level period except the data transmission period.

[0091] In this embodiment, the sending timing of the first notification may include an SCL low level period and an SCL high level period except a data transmission period.

[0092] As an embodiment, the first notification is sent during the SCL low level period of the SCL clock cycle after the IIC master device sends the falling edge of the SCL clock signal, and the method proposed in this embodiment may further include:

[0093] If a second notification is received from the IIC master device through the clock stretch indication signal line, check whether the current moment is before the end of the SCL low level period in the SCL clock cycle; if so, end the SCL clock cycle; if not, continue to execute the operation of controlling the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0094] If the second notification sent by the IIC master device through the clock stretch indication signal line is not received at the end of the SCL low level period in the SCL clock cycle, the pin on the control device connected to the slave device SCL continues to be maintained at a low level state.

[0095] In this embodiment, during the SCL low level period, the SDA line has completed the level conversion, converting the level of the SDA line to the level signal that needs to be transmitted in the current SCL clock cycle, and when the next rising edge appears, the level signal on the SDA line can be transmitted.

[0096] If the second notification is received before the end of the SCL low level period in the SCL clock cycle, it means that the clock stretching has been canceled before the end of the SCL low level period. Since the master device SCL and the slave device SCL are also in a low level state in the conventional signal transmission mechanism during the SCL low level period, this is equivalent to not performing clock stretching. At this time, data transmission can be carried out normally according to the process of the conventional mechanism, and the recording of the length of this clock cycle is ended.

[0097] If the second notification is not received before the end of the SCL low level period in the SCL clock cycle, it indicates that the clock stretching is still continuing at the end of the SCL low level period. At this time, if the conventional mechanism is followed, the pin on the control device connected to the slave device SCL needs to be adjusted to a high impedance state, and data transmission is performed according to the generated rising edge. However, since the clock stretching is still continuing, the scheme proposed in this embodiment will continue to maintain the pin on the control device connected to the slave device SCL in a low level state to suspend the communication between the IIC master device and the IIC slave device, that is, suspend the level signal transmission in the current SCL clock cycle until the second notification sent by the IIC master device through the clock stretch indication signal line is received. Only then will the SCL pin of the slave device connected to the slave device SCL be controlled to a high impedance state to restore the communication between the IIC master device and the IIC slave device and complete the level signal transmission in the current SCL clock cycle.

[0098] It can be seen that the method proposed in this embodiment breaks the limitations of the conventional IIC transmission mechanism. At the end of the SCL low-level period, the pin on the control device connected to the slave device SCL will not be directly adjusted to a high-impedance state according to the conventional transmission mechanism, and data transmission will not be performed according to the generated rising edge. Instead, the SCL pin of the slave device connected to the slave device SCL is controlled to a high-impedance state only when the second notification is received to restore the communication between the IIC master device and the IIC slave device, so that the IIC master device can also initiate clock stretching.

[0099] In this embodiment, the first notification is sent during the SCL low level period of the SCL clock cycle after the IIC master device sends the falling edge of the SCL clock signal. The IIC master device turns on the clock stretch and can suspend the level signal transmission in the current SCL clock cycle. After canceling the clock stretch, the level signal transmission in the current SCL clock cycle is restored and completed.

[0100] As an embodiment, the first notification is sent during an SCL high level period of an SCL clock cycle other than a data transmission period after the IIC master device sends a falling edge of an SCL clock signal. The method proposed in this embodiment may further include:

[0101] End the SCL clock cycle and start a new SCL clock cycle. If a second notification sent by the IIC master device through the clock stretch indication signal line is received, check whether the current moment is before the end of the SCL low level period in the new SCL clock cycle; if so, end the new SCL clock cycle; if not, continue to execute the operation of controlling the pin of the control device connected to the slave device SCL to be in a high-impedance state based on the second notification; the pin of the IIC master device connected to the master device SCL is in a low level state after the IIC master device determines to start clock stretching.

[0102] If the second notification sent by the IIC master device through the clock stretch indication signal line is not received at the end of the SCL low level period in the new SCL clock cycle, the pin on the control device connected to the slave device SCL continues to be maintained at a low level state.

[0103] In this embodiment, the first notification is sent during the SCL high level period of the SCL clock cycle except the data transmission period after the IIC master device sends the falling edge of the SCL clock signal, that is, clock stretching is started when the data transmission of the current SCL clock cycle has been completed.

[0104] Since the clock stretching is turned on during the SCL high level period, after the clock stretching is turned on, the IIC master device controls the pin on the IIC master device connected to the master device SCL to be at a low level, and the control device controls the pin on the control device connected to the slave device SCL to be at a low level. At this time, the master device SCL and the slave device SCL are both converted from high level to low level, and a falling edge occurs on the master device SCL, entering the next SCL clock cycle (recorded as a new SCL clock cycle). When the control device detects the falling edge of the SCL clock signal, the pin on the control device connected to the slave device SCL is in a low level state, and the pin on the control device connected to the master device SCL is in a low level state.

[0105] If the second notification is received before the end of the SCL low level period in the new SCL clock cycle, it indicates that the clock stretching has been canceled before the end of the SCL low level period. Since the master device SCL and the slave device SCL are also in a low level state in the conventional signal transmission mechanism during the SCL low level period, this is equivalent to not performing clock stretching. At this time, the transmission of the level signal in the new SCL clock cycle can be carried out normally according to the process of the conventional mechanism, and the recording of the length of this clock cycle is ended.

[0106] If the second notification is not received before the end of the SCL low level period in the new SCL clock cycle, it indicates that the clock stretching is still continuing at the end of the SCL low level period. At this time, if the conventional mechanism is followed, the pin on the control device connected to the slave device SCL needs to be adjusted to a high impedance state, and data transmission is performed according to the generated rising edge. However, since the clock stretching is still continuing, the scheme proposed in this embodiment will continue to maintain the pin on the control device connected to the slave device SCL in a low level state to suspend the communication between the IIC master device and the IIC slave device, that is, suspend the level signal transmission in the new SCL clock cycle until the second notification sent by the IIC master device through the clock stretch indication signal line is received. Only then will the SCL pin of the slave device connected to the slave device SCL be controlled to a high impedance state to restore the communication between the IIC master device and the IIC slave device and complete the level signal transmission in the new SCL clock cycle.

[0107] Similarly, the method proposed in this embodiment breaks the limitations of the conventional IIC transmission mechanism. At the end of the SCL low-level period, the pin on the control device connected to the slave device SCL will not be directly adjusted to a high-impedance state according to the conventional transmission mechanism, and the level signal will not be transmitted according to the generated rising edge. Instead, the SCL pin of the slave device connected to the slave device SCL is controlled to a high-impedance state only when the second notification is received to restore the communication between the IIC master device and the IIC slave device, so that the IIC master device can also initiate clock stretching.

[0108] In this embodiment, the first notification is sent during the SCL high level period other than the data transmission period of the SCL clock cycle after the IIC master device sends the falling edge of the SCL clock signal. The IIC master device turns on the clock stretch and can suspend data transmission in the new SCL clock cycle (i.e., the next SCL clock cycle of the SCL clock cycle after the IIC master device sends the falling edge of the SCL clock signal). After canceling the clock stretch, the data transmission of the new SCL clock cycle is resumed and completed.

[0109] The specific process of enabling clock stretching of the master device will be described in detail in the specific embodiments below and will not be repeated here.

[0110] This concludes Figure 3 Description of the process in .

[0111] The present application adds a clock extension indication signal line between the IIC master device and the control device in the communication control system. When the IIC master device determines to start the clock extension, it sends a first notification to the control device through the clock extension indication signal line, so that the control device maintains the slave device SCL pin connected to the slave device SCL on the control device in a low-level state based on the first notification. When the clock extension invalid indication signal is not received, even if the specified time period of the SCL clock cycle ends, the slave device SCL pin connected to the slave device SCL on the control device is not controlled to be in a high-impedance state like a conventional data transmission mechanism, but the slave device SCL pin connected to the slave device SCL on the control device is always maintained in a low-level state to suspend data transmission, breaking the limitation of the current IIC data transmission mechanism. Until the master device sends a second notification to the control device through the clock extension indication signal line to cancel the clock extension, the slave device SCL pin connected to the slave device SCL is controlled to be in a high-impedance state to resume data transmission, so as to implement the clock extension mechanism in the IIC communication protocol when the SCL between the IIC master device and the IIC slave device is not directly connected.

[0112] The present application also provides an IIC master device, which is an IIC master device in a communication control system; the communication control system also includes an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is also connected between the IIC master device and the control device. The IIC master device is used to execute the above Figure 2 The method in .

[0113] The present application also provides a control device, which is a control device in a communication control system. The communication control system also includes an IIC master device and an IIC slave device connected to the IIC master device. The control device is connected between the IIC master device and the IIC slave device. A clock extension indication signal line is also connected between the IIC master device and the control device.

[0114] Specifically, the control device may include:

[0115] A frequency counter is connected to the slave device SCL control module for communication. The frequency counter is used to count according to a preset frequency and trigger the slave device SCL control module to control the pin of the control device connected to the slave device SCL to be in a high impedance state when the count reaches the end of a specified period.

[0116] The slave device SCL control module is connected to the frequency counter and the master-slave SCL control module in communication, connected to the IIC slave device through the slave device SCL, and connected to the IIC master device through the clock extension indication signal line. The slave device SCL control module is used to control the state of the pin connected to the slave device SCL on the control device according to the signal sent by the master-slave SCL control module, the frequency counter and the clock extension indication signal line;

[0117] A first edge detection module is connected to the IIC master device through the master device SCL and is in communication connection with the master-slave SCL control module. The first edge detection module is used to detect the level change of the master device SCL;

[0118] A master-slave SCL control module is communicatively connected with the first edge detection module, the slave device SCL control module and the second edge detection module, and is connected with the IIC master device through the master device SCL. The master-slave SCL control module is used to control the state of the pin connected to the master device SCL on the control device according to the detection results of the first edge detection module and the second edge detection module, and control the slave device SCL control module, so that the slave device SCL control module controls the state of the pin connected to the slave device SCL on the control device;

[0119] The second edge detection module is connected to the IIC slave device through the slave device SCL and is in communication connection with the master-slave SCL control module. The second edge detection module is used to detect the level change of the slave device SCL.

[0120] The coordination between the modules in the control device will be described in detail in the specific embodiments below and will not be repeated here.

[0121] The communication control system and method based on the integrated circuit bus IIC proposed in this application are introduced through several specific embodiments below.

[0122] Example 1

[0123] Please refer to Figure 4 , Figure 4 A schematic diagram of the specific structure of an IIC communication control system provided in an embodiment of the present application.

[0124] like Figure 4 As shown, the system includes an IIC master device, a control device and two IIC slave devices.

[0125] Specifically, the control device may include:

[0126] The frequency counter is connected to the slave device SCL control module for communication. The frequency counter is used to count according to a preset frequency and trigger the slave device SCL control module to control the pin connected to the slave device SCL on the control device to be in a high impedance state when the counting reaches the end of a specified period.

[0127] The slave device SCL control module is communicatively connected with the frequency counter and the master-slave SCL control module, connected with the IIC slave device through the slave device SCL, and connected with the IIC master device through the clock extension indication signal line. The slave device SCL control module is used to control the state of the pin connected to the slave device SCL on the control device according to the signal sent by the master-slave SCL control module, the frequency counter and the clock extension indication signal line.

[0128] The first edge detection module is connected to the IIC master device through the master device SCL and is in communication connection with the master-slave SCL control module. The first edge detection module is used to detect the level change of the master device SCL.

[0129] The master-slave SCL control module is communicatively connected with the first edge detection module, the slave device SCL control module and the second edge detection module, and is connected with the IIC master device through the master device SCL. The master-slave SCL control module is used to control the state of the pin connected to the master device SCL on the control device according to the detection results of the first edge detection module and the second edge detection module, and control the slave device SCL control module, so that the slave device SCL control module controls the state of the pin connected to the slave device SCL on the control device.

[0130] The second edge detection module is connected to the IIC slave device through the slave device SCL and is in communication connection with the master-slave SCL control module. The second edge detection module is used to detect the level change of the slave device SCL.

[0131] The SCL selector is connected to each IIC slave device through the slave device SCL, and is in communication connection with the slave device SCL control module and the second edge detection module, and is used to determine the IIC slave device that needs to communicate according to the instruction of the IIC master device.

[0132] Based on the above-mentioned IIC communication control system, the IIC communication control method proposed in this application is described below.

[0133] Before describing the process of enabling the clock stretching function of the IIC host, a brief introduction to the level conversion mechanism in the IIC communication control system is first given.

[0134] In this embodiment, the master device SCL refers to the serial clock line between the IIC host and the control device, and its level is controlled by the master device and the control device. When the master device or the control device controls the pin of the master device SCL to be in a low level state (recorded as pulling down the master device SCL), the level of the master device SCL is low; when the master device or the control device controls the pin of the master device SCL to be in a high impedance state (recorded as releasing the master device SCL), the level of the master device SCL is high.

[0135] Similarly, the slave device SCL refers to the serial clock line between the IIC slave and the control device, and its level is controlled by the slave device and the control device. When the slave device or the control device controls the pin of the slave device SCL to a low level state (recorded as pulling down the slave device SCL), the level of the slave device SCL is low; when the slave device or the control device controls the pin of the slave device SCL to a high impedance state (recorded as releasing the slave device SCL), the level of the slave device SCL is high.

[0136] It should be noted that the IIC system performs a level signal transmission in one cycle of the SCL signal. Taking the example of a cycle of the SCL signal including a low level in the first 1 / 2 cycle and a high level in the second 1 / 2 cycle, the data on SDA changes during the low level period in the first 1 / 2 cycle of SCL, and starts to be read at the rising edge generated by the conversion from low level to high level, that is, it is read during the high level period in the second 1 / 2 cycle.

[0137] The following describes the method of enabling the clock stretching function on the ICC host side by taking the scenario in which the IIC communication control system performs an IIC task of multi-byte reading and writing as an example.

[0138] In this embodiment, the clock stretching function is turned on on the host side during the SCL low level period in any SCL clock cycle included in the SCL clock signal. In the current scenario, it means turning on the clock stretching function in the first 1 / 2 cycle of any SCL clock cycle in the process of reading and writing a byte.

[0139] Taking the IIC task of multi-byte reading and writing that needs to read and write 8 bytes of data as an example, in the process of reading any byte, such as the second byte, 1 bit of data is read in each SCL clock cycle.

[0140] Taking the data of the third bit of the second byte in the current SCL clock cycle as an example, at the beginning of the SCL clock cycle corresponding to the third bit, the master device controls the pin connected to the master device SCL on the master device to be at a low level according to the SCL clock signal, and a falling edge occurs on the master device SCL.

[0141] When the control device detects a falling edge on the master device SCL through the first edge detection module, it instructs the master-slave SCL control module to control the pin connected to the master device SCL on the control device to be at a low level, and at the same time, the master-slave SCL control module controls the pin connected to the slave device SCL on the control device to be at a low level. (At this time, the master device SCL is in a low level state pulled down by the master device and the control device at the same time, and the slave device SCL is in a low level state pulled down by the control device)

[0142] In the first 1 / 2 cycle of the SCL clock cycle for transmitting the third bit (SCL low level period), the master device SCL is in a low level state pulled down by both the master device and the control device, and the slave device SCL is in a low level state pulled down by the control device.

[0143] If the IIC master device has a higher priority task to process within the first 1 / 2 cycle of the SCL clock cycle that transmits the third bit, it can actively start clock stretching and send the first notification to the control device through the clock stretch indication signal line to maintain the pin connected to the slave device SCL on the control device at a low level. At this time, it is necessary to wait for the IIC master device to cancel the clock stretching, and the communication between the master and slave devices is suspended. (At this time, the master device SCL is in a low level state pulled down by the master device and the control device at the same time, and the slave device SCL is in a low level state pulled down by the control device)

[0144] The IIC frequency counter starts counting at the beginning of the SCL clock cycle corresponding to the third bit. When the host completes processing of higher priority tasks, the clock extension can be canceled, and a second notification is sent to the control device through the clock extension indication signal line. When the slave device SCL control module receives the second notification sent by the IIC master device through the clock extension indication signal line, it detects whether the IIC frequency counter counts to 1 / 2 SCL clock cycle. If not, it indicates that the clock extension has ended within the SCL low level period (the first 1 / 2 cycle) of the SCL clock cycle. At this time, it is only necessary to transmit the third bit of data according to the normal IIC transmission mechanism, and the counting of the IIC frequency counter can be stopped at the same time.

[0145] If the IIC frequency counter has counted more than 1 / 2 of the SCL clock cycle, it indicates that the master device is still currently opening the clock stretch, that is, maintaining the pin on the control device connected to the master device SCL at a low level. At this time, the master device cancels the clock stretch, controls the pin on the master device connected to the master device SCL to be in a high-impedance state, and controls the pin on the control device connected to the slave device SCL to be in a high-impedance state through the slave device SCL control module. At this time, the slave device SCL is converted from a low level to a high level, generating a rising edge of the clock signal. The slave device receives or sends the third bit of data through SDA according to the rising edge, and the communication between the master and slave devices is restored. (At this time, the master device SCL is in a low-level state pulled down by the controlled device, and the slave device SCL is in a high-level state released by both the controlled device and the slave)

[0146] When the control device detects a rising edge on the slave device SCL through the second edge detection module, it instructs the master-slave SCL control module to control the pin on the control device connected to the master device SCL to be in a high impedance state. (At this time, the master device SCL is released by the control device and the host, and is converted from a low level state to a high level state, and the slave device SCL remains in a high level state)

[0147] At this point, the clock stretching initiated by the host is completed, the slave completes reading the current third bit of data, the master device SCL and the slave device SCL return to a high level state, and the reading of the fourth bit of data is continued.

[0148] This concludes the description of Embodiment 1.

[0149] Example 2

[0150] In this embodiment, still based on Figure 4 The IIC communication control system shown in the figure describes the IIC communication control method proposed in this application.

[0151] In this embodiment, the clock stretching function is turned on at the host side during the SCL high level period of the SCL clock cycle except the data transmission period. In the current scenario, it means turning on the clock stretching function in the second half of any SCL clock cycle in the process of reading and writing a byte except the period for data transmission.

[0152] Still taking the IIC task of multi-byte reading and writing that needs to read and write 8 bytes of data as an example, in the process of reading any byte, such as the second byte, 1 bit of data is read in each SCL clock cycle.

[0153] Taking the reading of the third bit of data of the second byte in the current SCL clock cycle as an example, in the SCL clock cycle corresponding to the third bit, after the transmission of the third bit of data is completed in the second half cycle, the master device SCL and the slave device SCL are both in a high level state.

[0154] If the IIC master device has a higher priority task to process after completing the transmission of the third bit of data in the last 1 / 2 cycle, it can actively start clock stretching, control the pin connected to the master device SCL on the IIC master device to be at a low level, end the current SCL clock cycle, and start a new SCL clock cycle (the SCL clock cycle corresponding to the transmission of the fourth bit of data). The IIC frequency counter starts timing and sends the first notification to the control device through the clock stretch indication signal line, controlling the pin connected to the slave device SCL on the control device to be at a low level. At this time, it is necessary to wait for the IIC master device to cancel the clock stretch, and the communication between the master and slave devices is suspended. (At this time, the master device SCL is pulled down by the master device, converted from a high level state to a low level state, and a falling edge is generated. The slave device SCL is pulled down by the control device, and converted from a high level state to a low level state)

[0155] When the control device detects a falling edge of the host SCL through the first edge detection module, the pin connected to the slave device SCL on the control device is in a low level state and the pin connected to the master device SCL on the control device is in a low level state. (At this time, the master device SCL is pulled down by the master device and the control device and is in a low level state; the slave device SCL is pulled down by the control device and is in a low level state)

[0156] The IIC frequency counter starts counting at the beginning of the new SCL clock cycle corresponding to the 4th bit. When the host completes processing of higher priority tasks, the clock extension can be canceled, and a second notification is sent to the control device through the clock extension indication signal line. When the slave device SCL control module receives the second notification sent by the IIC master device through the clock extension indication signal line, it detects whether the IIC frequency counter counts to 1 / 2 of the new SCL clock cycle. If not, it indicates that the clock extension has ended within the SCL low level period (the first 1 / 2 cycle) of the new SCL clock cycle. At this time, it is only necessary to transmit the 3rd bit of data according to the normal IIC transmission mechanism, and the counting of the IIC frequency counter can be stopped at the same time.

[0157] If the IIC frequency counter has counted more than 1 / 2 of the new SCL clock cycle, it indicates that the master device is still currently opening the clock stretch, that is, maintaining the pin connected to the master device SCL on the control device at a low level. At this time, the master device cancels the clock stretch, controls the pin connected to the master device SCL on the master device to be in a high-impedance state, and controls the pin connected to the slave device SCL on the control device to be in a high-impedance state through the slave device SCL control module. At this time, the slave device SCL is converted from a low level to a high level, generating a rising edge of the clock signal. The slave device receives or sends the fourth bit of data through SDA according to the rising edge, and the communication between the master and slave devices is restored. (At this time, the master device SCL is in a low-level state pulled down by the controlled device, and the slave device SCL is in a high-level state released by both the controlled device and the slave)

[0158] When the control device detects a rising edge on the slave device SCL through the second edge detection module, it instructs the master-slave SCL control module to control the pin on the control device connected to the master device SCL to be in a high impedance state. (At this time, the master device SCL is released by the control device and the host, and is converted from a low level state to a high level state, and the slave device SCL remains in a high level state)

[0159] At this point, the clock stretching initiated by the host is completed, the slave completes reading the current 4th bit of data, the master device SCL and the slave device SCL return to the high level state, and then continue to read the 5th bit of data.

[0160] This concludes the description of Embodiment 2.

[0161] Example 3

[0162] Please refer to Figure 5 , Figure 5 A schematic diagram of the specific structure of an IIC communication control system provided in an embodiment of the present application.

[0163] like Figure 5As shown, the system includes two IIC master devices, a control device and two IIC slave devices.

[0164] In this embodiment, if the IIC master device 1 turns on clock stretching, data transmission with the IIC slave device 1 is suspended. During this process, since the slave device SCL of the IIC slave device 1 is already occupied by the IIC master device 1, the IIC master device 2 cannot transmit data with the IIC slave device 1.

[0165] If the IIC master device 2 needs to perform data transmission with the IIC slave device 1, the IIC master device 2 can perform data transmission with the IIC slave device 1 only after the IIC master device 1 finishes clock stretching and releases the occupation of the IIC slave device 1.

[0166] This concludes the description of Embodiment 3.

[0167] Example 4

[0168] Please refer to Figure 6 , Figure 6 A schematic diagram of the specific structure of another communication control system provided in an embodiment of the present application.

[0169] In the above embodiment 1, since the SDA signal line is level sampled instead of edge sampled, the SDA signal line does not need to pass through the control device, but can be directly connected to each host, which can save the resources of the control device.

[0170] In this embodiment, if Figure 6 As shown, a structure is provided in which an SDA signal line also passes through a control device, and an SDA direction indication signal line needs to be added to the control device to open a corresponding transmission path according to the direction indication of data transmission.

[0171] Meanwhile, in the case where there are multiple IIC slave devices, an SDA selector may be added to the control device to determine the IIC slave device that needs to communicate according to the instruction of the IIC master device.

[0172] This concludes the description of Embodiment 4.

[0173] Please refer to Figure 7 , Figure 7 The present invention proposes a clock extension device based on an integrated circuit bus IIC structure diagram, the device is applied to an IIC master device in a communication control system; the communication control system also includes an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is also connected between the IIC master device and the control device. Figure 7As shown, the device may include an opening unit 701 and a canceling unit 702. Specifically, the device includes:

[0174] The start unit 701 is used for sending a first notification to the control device through the clock stretch indication signal line if it is determined to start the clock stretch, so that the control device maintains the pin connected to the slave device SCL on the control device in a low level state based on the first notification; wherein, when the control device receives the falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state;

[0175] The canceling unit 702 is configured to send a second notification to the control device through the clock stretch indication signal line if it is determined to cancel the clock stretch, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0176] Optionally, the control device includes a slave device SCL control component; the slave device SCL control component is used to control the state of a pin on the control device connected to the slave device SCL;

[0177] The IIC master device is connected to the slave device SCL control component via a clock extension indication signal line.

[0178] Optionally, a pin on the IIC master device connected to the master device SCL is in a high impedance state after the IIC master device determines to cancel clock stretching.

[0179] Optionally, the first notification is sent within a specified time period of an SCL clock cycle after sending a falling edge of the SCL clock signal, where the SCL clock cycle is a set duration starting from a falling edge of the SCL clock signal.

[0180] Optionally, the SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period includes:

[0181] The SCL low level period, and the SCL high level period except the data transmission period.

[0182] This concludes Figure 7 Description of the structure diagram of the clock extension implementation device based on the integrated circuit bus IIC.

[0183] Please refer to Figure 8 , Figure 8This is a structural diagram of a target detection model training device proposed in an embodiment of the present application, which is applied to a control device in a communication control system; the communication control system also includes an IIC master device and an IIC slave device connected to the IIC master device, the control device is connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is also connected between the control device and the IIC master device. Figure 8 As shown, the device may include a maintaining unit 801 and a control unit 802. Specifically, the device includes:

[0184] The maintaining unit 801 is used for maintaining the pin connected to the slave device SCL on the control device in a low level state based on the first notification if the first notification sent by the IIC master device is received through the clock stretch indication signal line between the control device and the IIC master device; wherein, when the control device receives the falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state;

[0185] The control unit 802 is used to control the pin on the control device connected to the slave device SCL to be in a high-impedance state based on the second notification if a second notification sent by the IIC master device is received through the clock stretch indication signal line between the control device and the IIC master device; if it is detected that the level of the slave device SCL is converted from a low level to a high level, the pin on the control device connected to the master device SCL is controlled to be in a high-impedance state.

[0186] Optionally, the control device includes a slave device SCL control component; the slave device SCL control component is used to control the state of a pin on the control device connected to the slave device SCL;

[0187] The slave device SCL control component is connected to the IIC master device through a clock stretch indication signal line.

[0188] Optionally, the first notification is sent within a specified period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal; the SCL clock cycle is an SCL clock cycle starting from a falling edge of an SCL clock signal sent by the most recently received master device SCL.

[0189] Optionally, the SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period includes:

[0190] The SCL low level period, and the SCL high level period except the data transmission period.

[0191] Optionally, the first notification is sent during an SCL low level period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the control unit 802 is further configured to:

[0192] If a second notification is received from the IIC master device through the clock stretch indication signal line, check whether the current moment is before the end of the SCL low level period in the SCL clock cycle; if so, end the SCL clock cycle; if not, continue to execute the operation of controlling the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

[0193] Optionally, the first notification is sent during an SCL low level period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the control unit 802 is further configured to:

[0194] If the second notification sent by the IIC master device through the clock stretch indication signal line is not received at the end of the SCL low level period in the SCL clock cycle, the pin on the control device connected to the slave device SCL continues to be maintained at a low level state.

[0195] Optionally, the first notification is sent during an SCL high level period other than a data transmission period in an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the control unit 802 is further configured to:

[0196] End the SCL clock cycle and start a new SCL clock cycle. If a second notification sent by the IIC master device through the clock stretch indication signal line is received, check whether the current moment is before the end of the SCL low level period in the new SCL clock cycle; if so, end the new SCL clock cycle; if not, continue to execute the operation of controlling the pin of the control device connected to the slave device SCL to be in a high-impedance state based on the second notification; the pin of the IIC master device connected to the master device SCL is in a low level state after the IIC master device determines to start clock stretching.

[0197] Optionally, the first notification is sent during an SCL high level period other than a data transmission period in an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the control unit 802 is further configured to:

[0198] End the SCL clock cycle and start a new SCL clock cycle. If the second notification sent by the IIC master device through the clock stretch indication signal line has not been received at the end of the SCL low level period in the new SCL clock cycle, continue to maintain the pin on the control device connected to the slave device SCL in a low level state; the pin on the IIC master device connected to the master device SCL is in a low level state after the IIC master device determines to start clock stretching.

[0199] This concludes Figure 8 Description of the structure diagram of another target detection model training device in .

[0200] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A clock extension implementation method based on an integrated circuit bus IIC, characterized in that: The method is applied to an IIC master device in a communication control system; the communication control system further comprises an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is further connected between the IIC master device and the control device; the method comprises: If it is determined to start the clock stretching, a first notification is sent to the control device through the clock stretching indication signal line, so that the control device maintains the pin connected to the slave device SCL on the control device in a low level state based on the first notification; wherein, when the control device receives the falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state; If it is determined to cancel the clock stretch, a second notification is sent to the control device through the clock stretch indication signal line, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

2. The method according to claim 1, characterized in that The control device comprises a slave device SCL control component; the slave device SCL control component is used to control the state of the pin connected to the slave device SCL on the control device; The IIC master device is connected to the slave device SCL control component via the clock stretch indication signal line.

3. The method according to claim 1, characterized in that The pin on the IIC master device connected to the SCL of the master device is in a high impedance state after the IIC master device determines to cancel the clock stretching.

4. The method according to claim 1, characterized in that: The first notification is sent within a specified period of an SCL clock cycle after sending a falling edge of the SCL clock signal, where the SCL clock cycle is a set time length starting from the falling edge of the SCL clock signal.

5. The method according to claim 4, characterized in that The SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period includes: The SCL low level period, and the SCL high level period except the data transmission period.

6. A clock extension implementation method based on an integrated circuit bus IIC, characterized in that: The method is applied to a control device in a communication control system; the communication control system further comprises an IIC master device and an IIC slave device connected to the IIC master device, the control device is connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is also connected between the control device and the IIC master device; the method comprises: If a first notification sent by the IIC master device is received through the clock stretch indication signal line between the IIC master device and the IIC master device, then based on the first notification, the pin connected to the slave device SCL on the control device is maintained in a low level state; wherein, when the control device receives the falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state; If a second notification sent by the IIC master device is received through the clock stretch indication signal line between the IIC master device and the control device, the pin connected to the slave device SCL on the control device is controlled to be in a high impedance state based on the second notification; If it is detected that the level of the slave device SCL is converted from a low level to a high level, the pin of the control device connected to the master device SCL is controlled to be in a high impedance state.

7. The method according to claim 6, characterized in that The control device comprises a slave device SCL control component; the slave device SCL control component is used to control the state of the pin connected to the slave device SCL on the control device; The slave device SCL control component is connected to the IIC master device via the clock stretch indication signal line.

8. The method according to claim 6, characterized in that The first notification is sent within a specified period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal; the SCL clock cycle is an SCL clock cycle starting from the falling edge of an SCL clock signal sent by the master device SCL that is most recently received.

9. The method according to claim 8, characterized in that The SCL clock cycle includes an SCL low level period and an SCL high level period, the SCL high level period includes a data transmission period, and the specified period includes: The SCL low level period, and the SCL high level period except the data transmission period.

10. The method according to claim 9, characterized in that The first notification is sent during an SCL low level period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises: If a second notification is received from the IIC master device through the clock stretch indication signal line, check whether the current moment is before the end of the SCL low level period in the SCL clock cycle; if so, end the SCL clock cycle; if not, continue to execute the operation of controlling the pin of the control device connected to the slave device SCL to be in a high-impedance state based on the second notification.

11. The method according to claim 9, characterized in that The first notification is sent during an SCL low level period of an SCL clock cycle after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises: If the second notification sent by the IIC master device through the clock stretch indication signal line is not received at the end of the SCL low level period in the SCL clock cycle, the pin on the control device connected to the slave device SCL continues to be maintained at a low level state.

12. The method according to claim 9, characterized in that The first notification is sent in an SCL high level period of an SCL clock cycle excluding a data transmission period after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises: End the SCL clock cycle and start a new SCL clock cycle. If a second notification sent by the IIC master device through the clock stretch indication signal line is received, check whether the current moment is before the end of the SCL low level period in the new SCL clock cycle; if so, end the new SCL clock cycle; if not, continue to execute the operation of controlling the pin of the control device connected to the slave device SCL to be in a high-impedance state based on the second notification; the pin of the IIC master device connected to the master device SCL is in a low level state after the IIC master device determines to start clock stretching.

13. The method according to claim 9, characterized in that The first notification is sent in an SCL high level period of an SCL clock cycle excluding a data transmission period after the IIC master device sends a falling edge of an SCL clock signal, and the method further comprises: The SCL clock cycle ends and a new SCL clock cycle starts. If the second notification sent by the IIC master device through the clock stretch indication signal line has not been received at the end of the SCL low level period in the new SCL clock cycle, the pin on the control device connected to the SCL of the slave device continues to be maintained in a low level state; the pin on the IIC master device connected to the SCL of the master device is in a low level state after the IIC master device determines to start clock stretching.

14. A clock extension implementation device based on an integrated circuit bus IIC, characterized in that: The device is applied to an IIC master device in a communication control system; the communication control system also includes an IIC slave device connected to the IIC master device, and a control device connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is also connected between the IIC master device and the control device; the device includes: An enabling unit, configured to send a first notification to the control device through the clock extension indication signal line if it is determined to enable the clock extension, so that the control device maintains the pin connected to the slave device SCL on the control device in a low level state based on the first notification; wherein, when the control device receives a falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state; The canceling unit is used to send a second notification to the control device through the clock stretch indication signal line if it is determined to cancel the clock stretch, so that the control device controls the pin connected to the slave device SCL on the control device to be in a high impedance state based on the second notification.

15. A clock extension implementation device based on an integrated circuit bus IIC, characterized in that: The device is applied to a control device in a communication control system; the communication control system also includes an IIC master device and an IIC slave device connected to the IIC master device, the control device is connected between the IIC master device and the IIC slave device, and a clock extension indication signal line is also connected between the control device and the IIC master device; the device includes: A maintaining unit, configured to maintain the pin connected to the slave device SCL on the control device in a low level state based on the first notification if the first notification sent by the IIC master device is received through the clock stretch indication signal line between the control device and the IIC master device; wherein, when the control device receives a falling edge of the SCL clock signal, the pin connected to the slave device SCL on the control device is controlled to be in a low level state and the pin connected to the master device SCL on the control device is controlled to be in a low level state; Upon receiving a second notification sent by the IIC master device, the pin on the control device connected to the slave device SCL is controlled to be in a high-impedance state based on the second notification; if it is detected that the level of the slave device SCL is converted from a low level to a high level, the pin on the control device connected to the master device SCL is controlled to be in a high-impedance state.

Images