Data processing method, circuit, equipment and storage medium

Abstract

The invention provides a data processing method, circuit and equipment and a storage medium, and the method comprises the steps: receiving first differential data, and carrying out the oversampling processing of the first differential data, and obtaining a plurality of pieces of sampling data; identifying hopping edges in the plurality of pieces of sampling data, and determining effective data from the plurality of pieces of sampling data according to the hopping edges; and outputting the effective data. Through the technical scheme of the invention, unstable data at the jump edge can be prevented from being sampled to the greatest extent, so that the robustness of differential data is improved to obtain stable and effective data to be output.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data processing method, circuit, device and storage medium. Background Art

[0002] With the development of high-speed interface circuits, the data transmission rate on differential lines is getting faster and faster, and data recovery at the receiving end is becoming more and more important. Since the reference clocks of the transmitter and receiver are not homologous, and due to the deviation of the manufacturing process, there is a certain frequency deviation between the reference clocks of the transmitter and receiver. These factors will cause the receiver to be unable to stably recover the correct data. Summary of the invention

[0003] The present invention provides a data processing method, circuit, device and storage medium, which are used to solve the problem that a receiving end cannot stably recover and obtain correct data.

[0004] In a first aspect, the present invention provides a data processing method, comprising: receiving first differential data, and performing oversampling processing on the first differential data to obtain a plurality of sampling data; Identify a jump edge in a plurality of sampled data, and determine valid data from the plurality of sampled data according to the jump edge; Output valid data.

[0005] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, comprises: Identifying first sampling data without a transition edge among the plurality of sampling data; Valid data of the first differential data is determined from the first sampled data.

[0006] In some embodiments, determining valid data of the first differential data from the first sampled data includes: Identifying second sampled data having a transition edge among the plurality of sampled data; Determine, from the first sampled data, third sampled data having a phase opposite to that of the second sampled data; The third sample data is determined as valid data of the first differential data.

[0007] In some embodiments, the method further comprises: If there is no third sampling data having a phase opposite to that of the second sampling data in the first sampling data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data is received.

[0008] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, further comprises: If there are transition edges in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

[0009] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, further comprises: If there is no transition edge in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

[0010] In some embodiments, outputting valid data includes: When the valid data reaches a preset data volume threshold, the read pointer for reading the data is determined according to the difference between the front and rear jump edges; Read valid data according to the read pointer and output the read valid data.

[0011] In a second aspect, the present invention further provides a data processing circuit, comprising: a front-end sampling module, a phase detection module and a buffer module; One end of the front-end sampling module receives the first differential data, and the other end is connected to one end of the phase detection module; the other end of the phase detection module is connected to one end of the buffer module; Among them, the front-end sampling module is used to oversample the first differential data to obtain multiple sampling data; the phase detection module is used to identify the jump edges in the multiple sampling data, and determine the valid data from the multiple sampling data according to the jump edges; the cache module is used to temporarily store the valid data.

[0012] In a third aspect, the present invention further provides a data processing device, comprising: a processor, a memory and a communication bus; A communication bus, used to realize the connection and communication between the processor and the memory; The processor is used to execute the data processing program stored in the memory to implement the data processing method as described in the first aspect.

[0013] In a fourth aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data processing method as described in the first aspect.

[0014] The data processing method, circuit, device and storage medium provided by the present invention obtain multiple sampling data by oversampling the received first differential data, thereby increasing the sample size, and determine valid data from the multiple sampling data according to the jump edges by identifying the jump edges, thereby avoiding the sampling of unstable data at the jump edges to the greatest extent, thereby improving the robustness of the differential data to obtain stable valid data for output. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a flow chart of the data processing method provided by the present invention.

[0017] Figure 2 This is an example diagram of the multi-phase oversampling provided by the present invention.

[0018] Figure 3 This is an example diagram of identifying a transition edge provided by the present invention.

[0019] Figure 4 This is an example diagram of a data processing circuit provided by the present invention.

[0020] Figure 5 It is a structural schematic diagram of the data processing device provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0023] In the present invention, the term "plurality" refers to two or more than two, and other quantifiers are similar to them.

[0024] In the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0025] Combine the following Figure 1-Figure 5 Embodiments of the present invention are described.

[0026] Figure 1 It is a flow chart of the data processing method provided by the present invention, such as Figure 1 As shown, the method includes the following steps 101, 102 and 103.

[0027] Step 101: Receive first differential data, and perform oversampling processing on the first differential data to obtain a plurality of sampling data.

[0028] Specifically, the data processing method provided by the present invention can be used to stabilize data at the receiving end, that is, to improve the robustness of differential data at the receiving end.

[0029] The first differential data may be any differential data arriving at the receiving end, and the receiving end may obtain valid data corresponding to the first differential data through the data processing method provided by the present invention, thereby realizing correct recovery of the first differential data at the receiving end; it should be noted that the differential data may be image data or video data, and the data processing method provided by the present invention may be applied to image data processing, for example, to stably and efficiently recover data transmitted by the sending end.

[0030] In some embodiments, oversampling may be performed at different phases. For example, a phase locked loop (PLL) may generate multiple clock signals of different phases consistent with the differential line rate, which are respectively applied to multiple samplers to sample the same differential data, and the number of clock signals of different phases is the same as the number of samplers.

[0031] In some embodiments, M first differential data may be oversampled by N samplers to obtain M groups of sampled data; wherein each group of sampled data is obtained by N samplers oversampling the same differential data, and the multiple sampled data in step 101 may be the M groups of sampled data. The number of data in the second differential data described later is also M, and the first differential data and the second differential data both belong to the same differential signal. The present invention sequentially processes many data in the same differential signal in parallel, and each time processes a preset number (here M) of differential data in parallel. N is an integer greater than or equal to 2, and M is an integer greater than or equal to 1. M data may also be referred to as M bit data.

[0032] In some embodiments, the phases of the multiple clock signals with different phases may be 0°, 1×360° / A, 2×360° / A, ..., (A-1)×360° / A, where A represents the number of clock signals with different phases. For example, four clock signals with different phases may be generated, and their phases are 0°, 90°, 180°, and 270°, respectively.

[0033] Figure 2 is an example diagram of multi-phase oversampling provided by the present invention, such as Figure 2 As shown in the figure, the PLL can generate 4 clock signals with different phases consistent with the differential line rate, which act on 4 groups of samplers to perform oversampling processing on the same differential data. As shown in the figure, the original input 1-bit differential data can obtain 4-bit sampled data after 4-phase oversampling processing.

[0034] For example, assuming that the 4-bit differential data is oversampled, the 4-bit differential data is 0101. After 4-phase oversampling, 16-bit sampled data 0000111100001111 can be obtained, that is, each data will obtain 4 identical data, but the phase will change. For example, the first 4 data "0000" in the 16-bit sampled data are data of different phases obtained by oversampling the first data "0" in the 4-bit differential data by 4-phase oversampling. The first "0" in "0000" corresponds to a phase of 0°, the second "0" corresponds to a phase of 90°, the third "0" corresponds to a phase of 180°, and the fourth "0" corresponds to a phase of 270°.

[0035] Step 102: Identify a transition edge in a plurality of sampled data, and determine valid data from the plurality of sampled data according to the transition edge.

[0036] Specifically, a transition edge refers to a change in the bit value of the data. For example, a level change from 0 to 1 or from 1 to 0 represents a transition edge. The transition edge can be obtained by performing an exclusive OR (XOR) process on two adjacent sampled data. When the transition edge is identified, the XOR result is 1.

[0037] Take the 16-bit sampled data 0000111100001111 as an example, assuming that each data in the 16-bit sampled data is represented by K[i], i=0, 1, ..., 15, the first data is represented by k[0], and the last data is represented by K

[15] . If the identified 16-bit sampled data is 0000111100001111, by performing XOR processing on the two adjacent sampled data, the jump edges will be identified at K[4], K[8] and K

[12] . Whether there is a jump edge at K[0] needs to be determined based on the XOR result of the last bit of the previous round of 16-bit sampled data and K[0].

[0038] Figure 3 is an example diagram of identifying a transition edge provided by the present invention, Figure 3 Taking 16-bit sampled data as an example, K[15:0] represents the 16-bit sampled data of the current round, and K-1

[15] represents the last bit of the 16-bit sampled data of the previous round. By performing XOR on each adjacent two sampled data, 16 XOR results can be obtained, represented by d[i], i=0, 1, ..., 15. These 16 XOR results are 16-bit d[15:0]. The valid data can be determined by this 16-bit d[15:0] later.

[0039] It can be understood that M valid data are determined corresponding to the M first differential data, and for any first differential data, the corresponding valid data is one of the multiple sampling data obtained by oversampling the first differential data.

[0040] There are many ways to determine valid data, which are not specifically limited here. The following text will illustrate them with multiple embodiments.

[0041] Step 103: Output the valid data.

[0042] In some embodiments, a cache module (e.g., a cache module with elastic cache characteristics) may be set to temporarily store valid data. When the data cached in the cache module reaches a preset data volume threshold, the valid data is output, thereby ensuring that a certain amount of data is already in the cache module before reading, thereby avoiding the situation of reading empty data. Considering that the depth of a general cache is 32, half of the depth, i.e., 16, may be selected as the preset data volume threshold.

[0043] The data processing method provided by the present invention obtains multiple sampling data by oversampling the received first differential data, increases the sample size of the differential data, and identifies the jump edges in the multiple sampling data. Valid data is determined from the multiple sampling data according to the jump edges, which can avoid sampling unstable data at the jump edges to the greatest extent, thereby obtaining stable output data and being able to more stably restore correct data.

[0044] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, comprises: Identifying first sampling data without a transition edge among the plurality of sampling data; Valid data of the first differential data is determined from the first sampled data.

[0045] Taking the 16-bit sampled data 0000111100001111 as an example, in the 16-bit sampled data, there are transition edges at K[4], K[8] and K

[12] . It is assumed that according to the XOR result of the last bit of the previous round of 16-bit sampled data and K[0], it is determined that there is no transition edge at K[0]. Then, the first sampling data without a transition edge in the 16-bit sampling data includes: K[0], K[1], K[2], K[3], K[5], K[6], K[7], K[9], K

[10] , K

[11] , K

[13] , K

[14] , K

[15] . Valid data can be determined from these sampling data. For example, one valid data can be determined from K[0], K[1], K[2], K[3], one valid data can be determined from K[5], K[6], K[7], one valid data can be determined from K[9], K

[10] , K

[11] , and one valid data can be determined from K

[13] , K

[14] , K

[15] , and finally 4 valid data can be obtained.

[0046] It should be noted that the multiple valid data determined may be multiple data corresponding to the same phase, or multiple data corresponding to different phases. For example, the above four valid data may be K[2], K[6], K

[10] , K

[14] , or K[0], K[6], K

[10] , K

[14] , or K[0], K[5], K

[10] , K

[15] , and the present invention does not limit this.

[0047] Since the sampling data at the position where the jump edge exists is unstable, by identifying the first sampling data without the jump edge among the multiple sampling data and determining the valid data of the first differential data from the first sampling data, it is beneficial to recover the correct data more stably.

[0048] In some embodiments, determining valid data of the first differential data from the first sampled data includes: Identifying second sampled data having a transition edge among the plurality of sampled data; Determine, from the first sampled data, third sampled data having a phase opposite to that of the second sampled data; The third sample data is determined as valid data of the first differential data.

[0049] As mentioned above, the multiple valid data determined may be multiple data corresponding to the same phase or multiple data corresponding to different phases. Therefore, the third sampling data may be multiple data corresponding to the same phase or multiple data corresponding to different phases.

[0050] In some embodiments, the third sampled data is a plurality of data corresponding to the same phase, which is different from the phase corresponding to all the data in the second sampled data and opposite to the phase corresponding to any one of the data in the second sampled data.

[0051] For example, Figure 3 Take the 16 XOR results, i.e., 16-bit d[15:0], as an example. K[15:0] in the figure is the 16-bit sampled data obtained by performing 4-phase oversampling on the 4-bit differential data. Assume that edge_dt0 represents the jump result of 4-bit data under 0° phase sampling, edge_dt1 represents the jump result of 4-bit data under 90° phase sampling, edge_dt2 represents the jump result of 4-bit data under 180° phase sampling, and edge_dt3 represents the jump result of 4-bit data under 270° phase sampling, that is: edge_dt0 = d[0] | d[4]| d[8] | d

[12] ; edge_dt1 = d[1] | d[5]| d[9] | d

[13] ; edge_dt2 = d[2] | d[6]| d

[10] | d

[14] ; edge_dt3 = d[3] | d[7]| d

[11] | d

[15] .

[0052] Taking edge_dt1 as an example, if d[1], d[5], d[9], and d

[13] are all 0, that is, there is no transition between K[0] and K[1], there is no transition between K[4] and K[5], there is no transition between K[8] and K[9], and there is no transition between K

[12] and K

[13] , then edge_dt1 is 0; if at least one of d[1], d[5], d[9], and d

[13] is 1, that is, there is at least one transition between K[0] and K[1], between K[4] and K[5], between K[8] and K[9], and between K

[12] and K

[13] , then edge_dt1 is 1.

[0053] Let acc_st[3:0] = {edge_dt3, edge_dt2, edge_dt1, edge_dt0}, that is, acc_st[3:0] is the phase information of the data that has jumped in the sampled data obtained by oversampling the 4-bit differential data. The position of 4 valid data in the 16 sampled data can be obtained through the value of acc_st[3:0]. For example, acc_st[3:0] = 4'b0000 means edge_dt3, edge_dt2, edge_dt1, and edge_dt0 are all 0; acc_st[3:0] = 4'b0001 means edge_dt3, edge_dt2, and edge_dt1 are 0, and edge_dt0 is 1; acc_st[3:0] = 4'b0010 means edge_dt3, edge_dt2, and edge_dt0 are 0, and edge_dt1 is 1; acc_st[3:0] = 4'b0100 means edge_dt3, edge_dt1, and edge_dt0 are 0, and edge_dt2 is 1, 4'b0010 means edge_dt3, edge_dt2, and edge_dt0 are 0, and edge_dt1 is 1, and acc_st[3:0] = 4'b1000 means that edge_dt2, edge_dt1, edge_dt0 are 0, and edge_dt3 is 1; the meaning of other values ​​of acc_st[3:0] can be deduced similarly and will not be described in detail.

[0054] Taking acc_st[3:0] = 4'b0001 as an example, it means that at least one of the 4-bit data under 0° phase sampling has a transition edge, and the third sampling data (that is, valid data) can be 4-bit data under phase sampling opposite to 0° phase, that is, 4-bit data K[2], K[6], K

[10] , K

[14] under 180° phase sampling.

[0055] For another example, acc_st[3:0] = 4'b0011, which means that at least one of the 4-bit data under 0° phase sampling has a transition edge, and at least one of the 4-bit data under 90° phase sampling has a transition edge. The third sampling data (that is, valid data) can be 4-bit data under phase sampling opposite to 0° phase, that is, 4-bit data K[2], K[6], K

[10] , K

[14] under 180° phase sampling, or can be 4-bit data under phase sampling opposite to 90° phase, that is, 4-bit data K[3], K[7], K

[11] , K

[15] under 270° phase sampling.

[0056] In some embodiments, the third sampling data may be a plurality of data corresponding to different phases, and each data (i.e., valid data) may be determined based on the plurality of sampling data of different phases corresponding to the respective first differential data. Specifically, data having a phase opposite to that of the sampling data having a jump edge may be selected from the plurality of sampling data of different phases during the determination.

[0057] For example, take the 4-bit first differential data "0110" as an example, after 4-phase oversampling, the 16-bit sampled data 0000111111110000 is obtained. In the 16-bit sampled data, there are jump edges at K[4] and K

[12] , and assuming that there is a jump edge at K[0]. Then, for the first valid data, since there is a jump edge at K[0], K[2] with a phase opposite to K[0] can be selected as the valid data; for the second valid data, since there is a jump edge at K[4], K[6] with a phase opposite to K[4] can be selected as the valid data; for the third valid data, since there is no jump edge between K[8]~K

[11] , any one of K[8]~K

[11] can be selected as the valid data; for the fourth valid data, since there is a jump edge at K

[12] , K

[14] with a phase opposite to K

[12] can be selected as the valid data.

[0058] Since the data sampled at a 180° angle from the transition edge is relatively the most stable, the stability of the valid data can be better guaranteed by the above method.

[0059] In some embodiments, the method further comprises: If there is no third sampling data having a phase opposite to that of the second sampling data in the first sampling data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data is received.

[0060] It can be understood that if there is no third sampling data with a phase opposite to that of the second sampling data in the first sampling data, it means that it is difficult to obtain the most stable sampling data. In this case, the phase of the valid data of the previous round of differential data can be referred to to obtain relatively stable sampling data.

[0061] For example, acc_st[3:0] = 4'b0101 or 4'b1010. Since the two phases with bit values ​​of 1 are exactly 180° apart, the other two phases with bit values ​​of 0 do not meet the above-mentioned opposite phase condition. In this case, the valid data of the first differential data can be determined according to the phase of the valid data of the second differential data. For example, if the phase of the valid data of the second differential data is 90°, then the data corresponding to the 90° phase among the multiple sampling data of the first differential data, that is, K[1], K[5], K[9], and K

[13] are selected as the valid data; or, if the valid data of the second differential data corresponds to multiple different phases, then the valid data of the first differential data can be determined according to the phases corresponding to the valid data of the second differential data. For example, the four valid data of the second differential data correspond to 0°, 0°, 90°, and 180° phases respectively, then the four valid data of the first differential data can be K[0], K[4], K[9], and K

[14] respectively.

[0062] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, further comprises: If there are transition edges in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

[0063] For example, acc_st[3:0] = 4'b1111. Since the values ​​of the four bits are all 1, in this case, the valid data of the first differential data can be determined according to the phase of the valid data of the second differential data. For example, if the phase of the valid data of the second differential data is 0°, then the data corresponding to the 0° phase among the multiple sampled data of the first differential data, that is, K[0], K[4], K[8], and K

[12] are selected as the valid data; or, if the valid data of the second differential data corresponds to multiple different phases, then the valid data of the first differential data can be determined according to the phases corresponding to the valid data of the second differential data. For example, if the four valid data of the second differential data correspond to the phases of 0°, 0°, 90°, and 180°, respectively, then the four valid data of the first differential data can be K[0], K[4], K[9], and K

[14] .

[0064] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, further comprises: If there is no transition edge in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

[0065] For example, acc_st[3:0] = 4'b0000. Since there is no transition edge in all sampled data, in this case, valid data can be selected arbitrarily, or the valid data of the first differential data can be determined according to the phase of the valid data of the second differential data. For example, if the phase of the valid data of the second differential data is 180°, then the data corresponding to the 180° phase in the multiple sampled data of the first differential data, that is, K[2], K[6], K

[10] , and K

[14] are selected as valid data; or, if the valid data of the second differential data corresponds to multiple different phases, then the valid data of the first differential data can be determined according to the phases corresponding to the valid data of the second differential data. For example, the four valid data of the second differential data correspond to phases of 0°, 0°, 90°, and 180°, respectively, then the four valid data of the first differential data can be K[0], K[4], K[9], and K

[14] , respectively.

[0066] In some embodiments, outputting valid data includes: When the valid data reaches a preset data volume threshold, the read pointer for reading the data is determined according to the difference between the front and rear jump edges; Read valid data according to the read pointer and output the read valid data.

[0067] The read pointer can be understood as a flag or an identifier of the corresponding position of valid data. When the valid data reaches the preset data volume threshold, the valid data is output, ensuring that the cache module is read after a certain amount of data has been stored, thus avoiding the situation of reading empty data.

[0068] The difference between the front and back transition edges refers to the difference in bits between two adjacent transition edges in multiple sampling data. Taking the 16-bit sampling data 0000111100001111 as an example, in this 16-bit sampling data, there are transition edges at K[4], K[8] and K

[12] . The difference between the front and back transition edges corresponding to K[4] and K[8] is 4, and the difference between the front and back transition edges corresponding to K[8] and K

[12] is also 4.

[0069] In some implementations, for 4-phase oversampling (other multi-phase oversampling can be deduced accordingly and will not be described in detail), since the phases of the valid data are not necessarily the same, in the process of determining the valid data based on the jump edge, if it is found that the difference between the front and rear jump edges is 3, the read pointer of the elastic cache can be given +3; if it is found that the difference between the front and rear jump edges is 4, the read pointer of the elastic cache can be given +4; if it is found that the difference between the front and rear jump edges is 5, the read pointer of the elastic cache can be given +5; in other cases, the read pointer is kept at +4, and the data position output to the elastic cache remains unchanged.

[0070] In some embodiments, the read pointer of the elastic cache is +4 by default, and the write pointer value is greater than 16 (the depth of the elastic cache is 32) to prevent empty reads. When a data transfer is completed, the read and write pointers and the elastic cache are cleared.

[0071] The data processing circuit provided by the present invention is described below. The data processing circuit described below and the data processing method described above can be referred to each other.

[0072] Figure 4 is an example diagram of a data processing circuit provided by the present invention, such as Figure 4 As shown, the data processing circuit includes: a front-end sampling module 410, a phase detection module 420 and a cache module 430; one end of the front-end sampling module 410 receives the first differential data, and the other end is connected to one end of the phase detection module 420; the other end of the phase detection module 420 is connected to one end of the cache module 430; wherein, the front-end sampling module 410 is used to perform oversampling processing on the first differential data to obtain a plurality of sampling data; the phase detection module 420 is used to identify the jump edge in the plurality of sampling data, and determine the valid data from the plurality of sampling data according to the jump edge; the cache module 430 is used to temporarily store the valid data.

[0073] In some embodiments, the front-end sampling module 410 generates 0°, 90°, 180° and 270° clocks consistent with the differential line rate by PLL, and acts on 4 groups of samplers to perform oversampling processing on the same first differential data, that is, the originally input 1-bit differential data can obtain 4-bit sampling data after 4-phase oversampling processing. In order to reduce the clock frequency of parallel data transmission, the sampling data output by the front-end sampling module can be 16 bits (that is, the input 4-bit differential data can obtain 16-bit sampling data after 4-phase oversampling processing), which is provided to the phase detection module 420. The phase detection module 420 obtains the 16-bit sampling data from the front-end sampling module 410, identifies the jump edge in the 16-bit sampling data, and determines the valid data from the 16-bit sampling data according to the jump edge, and outputs it to the cache module 430. The cache module 430 temporarily stores the valid data, and outputs the valid data when the data cached in the cache module 430 reaches the preset data amount threshold.

[0074] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, comprises: Identifying first sampling data without a transition edge among the plurality of sampling data; Valid data of the first differential data is determined from the first sampled data.

[0075] In some embodiments, determining valid data of the first differential data from the first sampled data includes: Identifying second sampled data having a transition edge among the plurality of sampled data; Determine, from the first sampled data, third sampled data having a phase opposite to that of the second sampled data; The third sample data is determined as valid data of the first differential data.

[0076] In some embodiments, the phase detection module 420 determines the valid data, further comprising: If there is no third sampling data having a phase opposite to that of the second sampling data in the first sampling data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data is received.

[0077] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, further comprises: If there are transition edges in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

[0078] In some embodiments, identifying a transition edge in a plurality of sampled data, and determining valid data from the plurality of sampled data according to the transition edge, further comprises: If there is no transition edge in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

[0079] In some embodiments, the cache module 430 is further configured to output valid data, including: When the valid data reaches a preset data volume threshold, the read pointer for reading the data is determined according to the difference between the front and rear jump edges; Read valid data according to the read pointer and output the read valid data.

[0080] It should be noted here that the above-mentioned data processing circuit provided by the present invention can implement all the method steps implemented by the above-mentioned method embodiment, and can achieve the same technical effect. Compared with the existing clock data recovery circuit (Clock and Data Recovery, CDR), the data processing circuit has the characteristics of smaller area, lower complexity and higher stability. The parts and beneficial effects that are the same as those in the method embodiment in this embodiment will not be described in detail here.

[0081] Figure 5 is a schematic diagram of the structure of the data processing device provided by the present invention, such as Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other via the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the above data processing method.

[0082] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0083] It should be noted here that the above-mentioned data processing device provided by the present invention can implement all the method steps implemented by the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be specifically repeated here.

[0084] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, which is implemented to execute the above-mentioned data processing method when the computer program is executed by a processor.

[0085] It should be noted here that the above-mentioned computer-readable storage medium provided by the present invention can implement all the method steps implemented by the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects that are the same as the method embodiment in this embodiment will not be described in detail here.

[0086] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0087] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method, characterized in that: include: receiving first differential data, and performing oversampling processing on the first differential data to obtain a plurality of sampling data; Identifying a transition edge in a plurality of the sampled data, and determining valid data from the plurality of the sampled data according to the transition edge; The valid data is outputted.

2. The data processing method according to claim 1, characterized in that: The step of identifying the transition edges in the plurality of sampled data and determining valid data from the plurality of sampled data according to the transition edges comprises: Identifying first sampling data without a transition edge among the plurality of sampling data; Valid data of the first differential data is determined from the first sampled data.

3. The data processing method according to claim 2, characterized in that: Determining valid data of the first differential data from the first sampled data includes: Identifying second sampled data having a transition edge among the plurality of sampled data; Determine, from the first sampled data, third sampled data having a phase opposite to that of the second sampled data; The third sample data is determined as valid data of the first differential data.

4. The data processing method according to claim 3, characterized in that: Also includes: If there is no third sampling data having a phase opposite to that of the second sampling data in the first sampling data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before receiving the first differential data.

5. The data processing method according to claim 1, characterized in that: The step of identifying the transition edges in the plurality of sampled data and determining valid data from the plurality of sampled data according to the transition edges further includes: If there are transition edges in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

6. The data processing method according to claim 1, characterized in that: The step of identifying the transition edges in the plurality of sampled data and determining valid data from the plurality of sampled data according to the transition edges further includes: If there is no transition edge in the plurality of sampled data, the valid data of the first differential data is determined according to the phase of the valid data of the second differential data; wherein the second differential data is data received before the first differential data.

7. The data processing method according to claim 1, characterized in that: The outputting of the valid data comprises: When the valid data reaches a preset data amount threshold, a read pointer for reading the data is determined according to the difference between the front and rear jump edges; The valid data is read according to the read pointer, and the read valid data is output.

8. A data processing circuit, characterized in that: include: Front-end sampling module, phase detection module and cache module; One end of the front-end sampling module receives the first differential data, and the other end is connected to one end of the phase detection module; The other end of the phase detection module is connected to one end of the cache module; The front-end sampling module is used to perform oversampling processing on the first differential data to obtain a plurality of sampling data; the phase detection module is used to identify the jump edges in the plurality of sampling data, and determine the valid data from the plurality of sampling data according to the jump edges; The cache module is used to temporarily store the valid data.

9. A data processing device, characterized in that: include: processor, memory, and communications bus; The communication bus is used to realize the connection and communication between the processor and the memory; The processor is used to execute the data processing program stored in the memory to implement the data processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data processing method according to any one of claims 1 to 7 is implemented.

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