Adaptive SpMV method based on new-generation domestic many-core processor

Abstract

The invention discloses an adaptive SpMV method based on a new-generation domestic many-core processor. The adaptive SpMV method comprises the following steps: setting starting parameters; an SpMV parameter is obtained; setting and loading an input vector x in the main memory to a vector sx in the shared LDM; setting a private LDM local storage space; dividing a SpMV row block load; if the remaining row blocks are to be processed, taking the row blocks from the core, otherwise, exiting; loading a row block row offset vector dptr and initializing a row block output vector dy; spMV adaptive decision making is carried out; the rest part in the row block is calculated in batches, if a shared LDM flag bit started by the row block is true, a shared LDM-based batch SpMV method is adopted for processing, and otherwise, a hardware DCache-based batch SpMV method is adopted for processing; and returning to continue the row block taking processing until no residual row block is to be processed. The invention provides a self-adaptive SpMV method based on a new-generation domestic many-core processor, fine-grained self-adaption is realized, and SW26010P architecture characteristics are fully played to optimize memory access, so that the SpMV computing performance is finally improved.

Description

Technical Field

[0001] The present invention relates to the field of high performance computing, and in particular to an adaptive SpMV method based on a new generation of domestic many-core processors. Background Art

[0002] Sparse Matrix Vector Multiplication (SpMV) is a classic operator in the field of high-performance computing. It not only plays an important role in scientific and engineering applications, but also has wide applications in many fields such as graphics processing, network analysis, and machine learning. At present, with the growing demand for higher precision and larger-scale problem-solving capabilities in scientific research and technological development, it is particularly important to develop faster and more efficient SpMV methods. Especially for processors with unique architectural characteristics, how to make full use of specific hardware characteristics to further improve computing efficiency is an important topic in current SpMV research.

[0003] The matrix processed by sparse matrix-vector multiplication (SpMV) contains a large number of zero elements, which means that if the dense matrix processing method is directly used in the actual calculation process, a large number of unnecessary zero-element multiplication operations will be performed, which greatly wastes computing resources and time.

[0004] To solve this problem, SpMV is often designed to compress and store sparse matrices in a special storage format. Compressed Sparse Row (CSR) is a widely used basic sparse matrix compression format, which is particularly suitable for sparse matrix operations processed by rows. This format reduces memory usage by compactly storing the non-zero elements in the matrix and their related information. CSR mainly consists of three vectors: 1.val[nnz_len]: non-zero element vector; 2.ind[nnz_len]: non-zero element column index vector; 3.ptr[rows+1]: row offset vector. Through the above three vectors, the CSR format can effectively encode the complete information of a sparse matrix. When performing operations such as SpMV that require frequent access to non-zero elements of sparse matrices, the CSR format can significantly reduce memory usage and speed up the calculation process, which also facilitates efficient cache utilization and further improves algorithm performance.

[0005] However, although CSR-based SpMV avoids redundant multiplication operations on zero elements, it also introduces new challenges. While compressing non-zero elements, CSR discretizes the memory access of the input vector x, which will greatly affect the overall performance of SpMV. In CSR, unlike the continuous memory access mode of non-zero elements, the access to the input vector x depends on the column index vector ind corresponding to the non-zero elements.

[0006] As Moore's Law gradually fails, modern high-performance processor architecture design is gradually developing towards heterogeneous multi-core to cope with the physical limits of single core performance improvement. This shift not only greatly improves the floating-point computing capability of a single chip, but also makes the storage access bottleneck problem more prominent. The new generation of Shenwei supercomputer uses the heterogeneous multi-core processor SW26010P independently developed by my country. This processor has a floating-point computing capability of 14TFLOPS on a single chip and provides a memory access bandwidth of up to 300GB / s. Compared with the previous generation processor SW26010, SW26010P has been improved in many aspects. Although SW26010P has made significant progress in computing power, its memory access speed still has certain limitations compared to the growing data processing needs. Especially when executing memory-intensive operators such as SpMV, its memory access latency and bandwidth limitations have become key factors restricting the overall performance. In order to address this problem, the architectural optimization of SW26010P on the slave core LDM provides new possibilities for SpMV algorithm innovation and creates favorable conditions for improving SpMV performance.

[0007] At present, most of the research on sparse matrix-vector multiplication (SpMV) is focused on traditional CPUs and GPUs. These studies have explored a variety of optimization strategies, including efficient sparse matrix storage formats, data prefetching techniques, and parallel computing methods. In recent years, with the development of domestic supercomputers, some studies have also begun to focus on the design of SpMV algorithms based on the Shenwei SW26010 processor. However, since the new generation of SW26010P architecture has been upgraded in many aspects, such as increasing the number of core groups, expanding the local data storage (LDM) capacity, and supporting more flexible data storage configurations, it is necessary to develop SpMV algorithms that can fully utilize these new features.

[0008] Currently, existing SpMV research on the SW26010P platform focuses on two directions: one is the optimization of the compression format, which reduces memory usage and accelerates data access by improving sparse matrix representation methods such as CSR; the other is the application of automatic tuning mechanisms, which aims to dynamically adjust algorithm parameters or execution paths according to the specific conditions of actual runtime to achieve optimal performance. Although these efforts have improved the performance of SpMV on SW26010P to a certain extent, considering the uniqueness of this architecture, there is still room for further optimization. In particular, how to effectively use shared LDM to improve the problem of irregular memory access to vector x, and how to better combine the advantages of private LDM and hardware cache to achieve higher data locality and computing efficiency are key issues that need to be solved.

[0009] SpMV is a typical memory-intensive application, and its key performance bottleneck lies in the discrete access pattern of vector x. Unlike dense matrix operations, access to the input vector x in SpMV is usually based on the non-zero element column index ind in the sparse matrix, which leads to irregular and random data access patterns. Traditionally, one of the ways to solve this memory access problem is to use hardware cache to improve data access efficiency, that is, by saving the most recently or frequently accessed data in the cache to reduce the number of direct accesses to the external memory. However, the effectiveness of this method is highly dependent on the distribution characteristics of non-zero elements in the sparse matrix. If the distribution of non-zero elements in the matrix has good locality, that is, they are relatively concentrated in adjacent positions, the hardware cache can work effectively; on the contrary, if the distribution of non-zero elements is very scattered, it will lead to a high miss rate and frequent cache line elimination.

[0010] Taking the SW26010P processor as an example, it supports hardware cache settings of various sizes, including three configuration options of 0KB, 32KB and 128KB. The size of each cache line is 256 bytes, which can accommodate 32 double-precision floating-point numbers. When the non-zero elements in each row of the sparse matrix have good locality in the column distribution, it means that the positions of the input vector x elements corresponding to these non-zero elements are relatively close, and the hardware cache can work effectively at this time. Because a cache line load can meet the access requirements of multiple consecutive x elements at the same time, a higher cache hit rate can be achieved. Such a layout is conducive to reducing the additional overhead caused by cache misses and improving the overall computing efficiency. For example, if a cache line contains all the vector x elements that need to be accessed in a sparse matrix row, then all multiplication and addition operations of this row can be completed efficiently without accessing the main memory again.

[0011] However, if the distribution of non-zero elements of the sparse matrix exhibits poor locality, efficient data access cannot be guaranteed even with a larger cache. In this case, the hardware cache may experience a high frequency of miss events, which means that new data needs to be frequently reloaded from the main memory into the cache. In addition, due to the limited cache capacity, the newly loaded data is likely to replace the previously useful but unused data. Frequent cache line elimination not only adds additional data transmission latency, but may also cause the cache to not function fully, seriously affecting the overall performance of SpMV. Therefore, when designing the SpMV algorithm for the SW26010P architecture, it is necessary to consider how to improve the access pattern of the input vector x to make it more suitable for a specific LDM configuration, and how to evaluate the locality of the sparse matrix row blocks, so as to adopt an adaptive SpMV strategy based on its memory access locality characteristics. Summary of the invention

[0012] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is that the existing adaptive SpMV method for the Shenwei series processors has coarse granularity, does not fully exploit the architectural characteristics, and handles poor memory access locality. The present invention provides an adaptive SpMV method based on a new generation of domestic multi-core processors, which evaluates the locality of the sparse matrix row blocks of SpMV through PMU collection data, and uses the SpMV method of the shared LDM cache input vector x to handle row blocks with poor memory access locality, thereby achieving fine-grained adaptation and giving full play to the SW26010P architectural characteristics to optimize memory access, so as to ultimately improve the SpMV computing performance.

[0013] To achieve the above object, the present invention provides an adaptive SpMV method based on a new generation of domestic many-core processors, comprising the following steps:

[0014] Step S101, setting startup parameters;

[0015] Step S102, obtaining SpMV parameters;

[0016] Step S103, setting and loading the input vector x in the main memory into the vector sx in the shared LDM;

[0017] Step S104, setting private LDM local storage space;

[0018] Step S105, dividing the SpMV row block load;

[0019] Step S106, if there are remaining rows to be processed, then fetch the rows from the core, otherwise exit;

[0020] Step S107, loading the row block offset vector dptr and initializing the row block output vector dy;

[0021] Step S108, SpMV adaptive decision;

[0022] Step S109, batch calculating the remaining part in the row block, if the shared LDM flag of the row block is true, then using the batch SpMV method based on shared LDM for processing, otherwise using the batch SpMV method based on hardware DCache for processing;

[0023] Step S110, return to step S106 to continue processing until there are no remaining row blocks to be processed.

[0024] Further, step S101, setting startup parameters, specifically includes:

[0025] Set load partitioning parameters, including the number of row blocks for load rows;

[0026] Set adaptive SpMV decision parameters, including row block load sampling rate, single batch DCache miss rate tolerance threshold, and row block shared LDM enablement threshold;

[0027] Set shared LDM configuration parameters, including the shared LDM default startup size.

[0028] Further, step S102, obtaining SpMV parameters, specifically includes:

[0029] Get matrix parameters, CSRMatrx type, including: row offset vector ptr main memory address, non-zero element vector val main memory address, non-zero element column index vector ind main memory address, matrix row number n, matrix non-zero element number nnz;

[0030] Input vector x main memory address;

[0031] Output vector y main memory address.

[0032] Further, step S103, setting and loading the input vector x in the main memory to the vector sx in the shared LDM, includes two steps of space size mode setting and input vector x loading, specifically including:

[0033] Set the sharing mode and size of the shared LDM according to the size of the input vector x, that is, the number of matrix columns;

[0034] Loads input vector x into shared LDM vector sx.

[0035] Furthermore, the input vector x is loaded into the shared LDM vector sx using a cluster-based high-affinity shared LDM loading method, specifically including:

[0036] Step S501: Calculate the slave core cluster number;

[0037] Step S502: Calculate the local number of the slave core in the slave core cluster;

[0038] Step S503: Calculate the slave core global number related to the slave core cluster according to the slave core cluster number and the slave core local number inside the slave core cluster;

[0039] Step S504: evenly divide the x loading load by blocks according to the slave core global number associated with the slave core cluster;

[0040] Step S505: Align the input vector x to load the payload size according to 8*loop unrolling times;

[0041] Step S506: Use DMA to load the input vector x in the main memory into the LDM private space LMEM;

[0042] Step S507: load the input vector x in the LDM private space LMEM into the vector sx in the shared LDM, and accelerate it by using SIMD and loop unrolling;

[0043] Step S508: Synchronize the slave core array.

[0044] Furthermore, in step S104, a private LDM local memory space is set up to be used as a data cache space for row blocks and batches of SpMV.

[0045] Furthermore, a private LDM local storage space is set, specifically including:

[0046] The row block load related variables are set according to the row block load parameter configuration, including the row block result vector dy corresponding to the row block size, and the row block row offset vector dptr corresponding to the row block size + 1;

[0047] Batch load related variables are set to determine the maximum single batch non-zero element vector dval and its column index vector dind length available to the batch SpMV based on the size of the available space of the private LDM.

[0048] Furthermore, in step S105, the SpMV row block load is divided, specifically, the row is divided into a plurality of row blocks according to a preset BLOCK_SIZE row.

[0049] Further, step S106, if there are remaining row blocks to be processed, then take the row blocks from the core, otherwise exit, specifically including: if there are remaining row blocks to be processed, then the core takes the row block load from the matrix according to the core number _PEN for calculation; if the remaining number of rows is less than the preset BLOCK_SIZE, then the remaining number of rows is used as a row block for calculation; if the actual number of row blocks block_size is calculated and there is no remaining row block, then exit from the core.

[0050] Further, step S107, loading the row block row offset vector dptr and initializing the row block output vector dy, specifically including loading the row block row offset vector dptr, taking _PEN*BLOCK_SIZE as the offset row_gbgn, taking a fragment vector of type int with a length of block_size+1 from the main memory row offset vector ptr to the LDM local memory row block row offset vector dptr.

[0051] Technical Effects

[0052] The present invention provides an adaptive SpMV method based on a new generation of domestic many-core processors, which selects the SpMV strategy by collecting DCache PMU data, optimizes the memory access of the input vector x by using the on-chip shared LDM, and optimizes the process of loading the input vector x by the shared LDM based on the characteristics of the core cluster. The present invention provides an adaptive SpMV method based on a new generation of domestic many-core processors, which realizes a fine-grained, low-overhead adaptive SpMV method.

[0053] The concept, specific structure and technical effects of the present invention will be further described below in conjunction with the accompanying drawings to fully understand the purpose, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 It is a flowchart of an adaptive SpMV method based on a new generation of domestic many-core processors according to a preferred embodiment of the present invention;

[0055] Figure 2 It is a flow chart of a cluster-based high-affinity shared LDM loading method based on an adaptive SpMV method of a new generation of domestic multi-core processors according to a preferred embodiment of the present invention;

[0056] Figure 3 It is a flowchart of a SpMV strategy selection method based on hardware DCache PMU of an adaptive SpMV method based on a new generation of domestic multi-core processors according to a preferred embodiment of the present invention;

[0057] Figure 4 It is a flow chart of a batch SpMV method based on shared LDM of a preferred embodiment of the present invention, which is an adaptive SpMV method based on a new generation of domestic multi-core processors;

[0058] Figure 5 It is a flowchart of a batch SpMV method based on hardware DCache, which is an adaptive SpMV method based on a new generation of domestic multi-core processors according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0060] In the following description, specific details such as specific internal procedures and techniques are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0061] The embodiment of the present invention first uses the main core version SpMV as a comparative example of the embodiment of the present invention, and its implementation process includes the following steps:

[0062] Step 1: Obtain SpMV parameters;

[0063] Step 2: Calculate the multiplication and addition reduction of non-zero elements row by row;

[0064] Step 3: The calculation result is stored in the output vector y in the main memory.

[0065] like Figure 1 As shown, another preferred embodiment of the present invention provides an adaptive SpMV method based on a new generation of domestic multi-core processors, which calculates y=Ax, including the following steps:

[0066] Step S101: Setting startup parameters, including:

[0067] 1) Load partitioning parameters: number of rows in the row block load.

[0068] 2) Adaptive SpMV decision parameters: row block load sampling rate, single batch DCache miss rate tolerance threshold, row block shared LDM enabling threshold.

[0069] 3) Shared LDM configuration parameters: Shared LDM default startup size.

[0070] Step S102: Obtaining SpMV parameters, including:

[0071] 1) Matrix parameters, CSRMatrx type, including: row offset vector ptr main memory address, non-zero element vector val main memory address, non-zero element column index vector ind main memory address, matrix row number n, matrix non-zero element number nnz;

[0072] 2) Input vector x main memory address;

[0073] 3) Output the main memory address of vector y.

[0074] Step S103: Setting and loading the input vector x into the shared LDM vector sx, including two steps: spatial size mode setting and input vector x loading:

[0075] 1) Set the sharing mode and size of the shared LDM according to the size of the input vector x, that is, the number of matrix columns;

[0076] 2) Load the input vector x into the shared LDM vector sx.

[0077] Among them, Figure 2 As shown, step 2) uses a cluster-based high-affinity shared LDM loading method, which includes:

[0078] Step S501: Calculate the slave core cluster number;

[0079] Step S502: Calculate the local number of the slave core in the slave core cluster;

[0080] Step S503: Calculate the slave core global number related to the slave core cluster according to the slave core cluster number and the slave core local number inside the slave core cluster;

[0081] Step S504: evenly divide the x loading load by blocks according to the slave core global number associated with the slave core cluster;

[0082] Step S505: Align the input vector x to load the payload size according to 8*loop unrolling times;

[0083] Step S506: Use DMA to load the input vector x in the main memory into the LDM private space LMEM;

[0084] Step S507: load the input vector x in the LDM private space LMEM into the vector sx in the shared LDM, and accelerate it by using SIMD and loop unrolling;

[0085] Step S508: Synchronize the slave core array.

[0086] Step S104: Setting a private LDM local storage space, setting a data cache space for row blocks and batch SpMV, including:

[0087] 1) Row block load related variables are set according to the row block load parameter configuration, including the row block result vector dy corresponding to the row block size, and the row block row offset vector dptr corresponding to the row block size + 1.

[0088] 2) Batch load related variables are set to determine the maximum single batch non-zero element vector dval and its column index vector dind length available to the batch SpMV according to the size of the available space of the private LDM.

[0089] Step S105: Divide the SpMV row block load into a number of row blocks according to a preset BLOCK_SIZE row;

[0090] Step S106: If there are remaining row blocks to be processed, the slave core takes the row block load from the matrix according to the slave core number _PEN for calculation. If the number of remaining rows is less than the preset BLOCK_SIZE, the remaining number of rows is used as a row block for calculation. If there are no remaining row blocks after calculating the actual number of row blocks block_size, the slave core exits.

[0091] Step S107: The row block row offset vector dptr is loaded, with _PEN*BLOCK_SIZE as the offset row_gbgn, and a fragment vector of type int with a length of block_size+1 is taken from the main memory row offset vector ptr to the LDM local memory row block row offset vector dptr.

[0092] Step S108: SpMV adaptive decision, a SpMV strategy selection method based on hardware DCache PMU, selects the SpMV strategy to be executed in step S109 according to the sampling result and the threshold setting.

[0093] Among them, a SpMV strategy selection method based on hardware DCache PMU is used, and its steps include:

[0094] Step S601: confirm the sampling parameter settings, including: row block load row sampling rate, single batch DCache miss rate tolerance threshold, batch voting counter, row block shared LDM enable threshold;

[0095] Step S602: Divide sampling batches;

[0096] Step S603: Start the PMU counter;

[0097] Step S604: Calculate a single batch of SpMVs;

[0098] Step S605: record the PMU counter value;

[0099] Step S606: if the DCache memory miss rate for the input vector x during the single batch SpMV calculation process exceeds the single batch DCache miss rate tolerance threshold in step S601, the batch voting counter is incremented by one;

[0100] Step S607: If all sampling batches have been processed, execute step S608, otherwise return to step S603;

[0101] Step S608: Divide the batch voting counter by the total number of sampled batches. If the value exceeds the row block shared LDM enable threshold in step S601, the enable shared LDM flag is set to true.

[0102] Step S109: According to the decision result of step S108, if the flag bit of enabling shared LDM for the row block is true, the batch SpMV method based on shared LDM is used for processing; otherwise, the batch SpMV method based on hardware DCache is used for processing.

[0103] Among them, for the batch SpMV method based on shared LDM, it includes the steps of:

[0104] Step S701: Searching for SpMV batch size;

[0105] Step S702: if the number of non-zero elements in a single row exceeds the size of the private LDM local memory space, use the hardware DCache to access the non-zero element vector val and the non-zero element column index vector ind in the main memory to perform SpMV, i.e. skip step S703 and execute step S704;

[0106] Step S703: According to the number of non-zero elements in a single batch, the corresponding fragments of the non-zero metadata vector val and the corresponding fragments of the non-zero element column index vector ind are loaded from the main memory by DMA into the single batch non-zero element vector dval and the single batch non-element column index vector dind in the LDM local memory;

[0107] Step S704: for a single batch of row loads, SpMV calculation is performed row by row, the process of accessing the main memory input vector x is replaced by accessing the vector sx in the shared LDM, and the result of multiplication and addition of the single row vector of the matrix and the vector x is written into the local position corresponding to the row block output vector dy in the LDM;

[0108] Step S705: if the row block has not been processed, the starting row number of the next batch of loads is refreshed and the process returns to step S701; otherwise, the process executes step S706;

[0109] Step S706: write the row block output vector dy in the LDM into the corresponding fragment position of the main memory output vector y in DMA mode according to the row block load size and the offset.

[0110] Among them, for the batch SpMV method based on DCache, compared with the batch SpMV method based on shared LDM, the memory access to the main memory input vector x is to enable the slave core hardware Dcache mode, where the DCache size is 32KB.

[0111] Step S110: Return to step S106.

[0112] The following will use a specific embodiment to illustrate an adaptive SpMV method based on a new generation of domestic many-core processors of the present invention. Specifically, the nd24k matrix in SuiteSparse will be taken as an example to illustrate an adaptive SpMV method based on a new generation of domestic many-core processors of the present invention. The specific steps are as follows:

[0113] Step S101: Setting startup parameters, including:

[0114] 1) Load partitioning parameters: Based on the DMA continuous memory access characteristics of SW26010P, the row block load size is set to 256 rows, that is, each row block SpMV is calculated to obtain a row block output vector dy of length 256 double type, with a size of 2048B (256*8B).

[0115] 2) Adaptive SpMV decision parameters: Set the row block load sampling rate to 0.1, which means that the first 0.1 (i.e. 25 rows) elements in a row block of 256 rows are sampled. The single batch DCache miss rate tolerance threshold is 0.01, which means that if the memory access miss of x calculated by each batch of SpMV during the sampling process reaches 0.01, the batch voting counter is incremented by one. The row block shared LDM enable threshold is 0.5, which means that the batch counters of sample_batch_n batches during the sampling process are accumulated. If the counter exceeds 0.5*sample_batch_n, the row block shared LDM enable flag is set to true, enabling shared LDM memory access x, otherwise hardware DCache is used to access memory x.

[0116] 3) Shared LDM configuration parameters: Set the shared LDM default mode to full slave core array sharing, and continuously address the 64KB LDM space in each slave core to form a continuous shared space on the chip.

[0117] Step S102: Obtaining SpMV parameters, including:

[0118] 1) Matrix parameters, CSRMatrx type, including: row offset vector ptr main memory address, non-zero element vector val main memory address, non-zero element column index vector ind main memory address, matrix row number n=72000, matrix non-zero element number nnz=28715634;

[0119] 2) Input vector x main memory address;

[0120] 3) Output the main memory address of vector y.

[0121] Step S103: Setting and loading the shared LDM, including the shared LDM size and mode setting, and the input vector x loading two steps:

[0122] 1) Set the sharing mode and size of the shared LDM. The length of the input vector x is the number of columns of the F1 matrix, which is 72000. The element type stored in the x vector is double, and each element occupies 8B. Therefore, the overall space occupied by x is 72000 * 8 = 576000B, approximately 563KB. Averaged across 64 slave cores, each slave core needs to bear a loading space of 563 / 64 = 9KB.

[0123] 2) Load the vector x into the shared LDM using a cluster - based high - affinity shared LDM loading method, and its steps include:

[0124] Step S501: Calculate the slave core cluster number. The slave core array is arranged in an 8 * 8 layout, and every 2 * 2 slave cores form a slave core cluster. Calculate the slave core cluster number cid = _ROW / 2 * 4 + _COL / 2;

[0125] Step S502: Calculate the local number of the slave core within the cluster, that is, the intra - cluster number ccid of each slave core = _ROW % 2 * 2 + _COL % 2;

[0126] Step S503: According to the slave core cluster number and the local number of the slave core within the cluster, calculate the global number gid of the slave core related to the cluster = cid * 4 + ccid;

[0127] Step S504: According to the global number of the slave core related to the cluster, evenly divide the x loading load by blocks. This process is divided into two stages. In the first stage, calculate the size of the loading load initially allocated to each slave core according to base_n = num_x / 64 = 1125, and at the same time get the remaining unallocated x elements according to rest_n = num_x % 64 = 0. In the second stage, for the slave cores with _PEN < rest_n, each slave core is responsible for one of the remaining loads, that is, base_n of each slave core is incremented by 1 (in this example, there is no slave core that needs to be incremented), and its starting position x_idx_bgn = _PEN * base_n. For the slave cores with _PEN >= rest_n, their loads remain unchanged, but the starting position is x_idx_bgn = _PEN * base_n + rest_n.

[0128] Step S505: Align the x loading load according to the element size of 8 * 2 = 16 for subsequent optimization. The starting position x_idx_bgn = x_idx_bgn / 16 * 16, and the number of loaded elements base_n = (base_n + 31) / 16 * 16;

[0129] Step S506: Use DMA to load the input vector x in the main memory into the private space LMEM of the LDM;

[0130] Step S507: load the input vector x in the LDM private space LMEM into the vector sx in the shared LDM, and accelerate it by using SIMD and loop unrolling;

[0131] Step S508: Synchronize the slave core array.

[0132] Step S104: Setting a private LDM local storage space, setting a data cache space for row blocks and batch SpMV, including:

[0133] 1) Set row block load related variables and configure them according to the row block size configuration of 256 rows. The result vector dy will store 256 double type elements, so the LDM configuration size is 256*8B=2024B. The row offset vector dptr will store (256+1) int type elements, so the LDM configuration size is (256+1)*4B=1028B.

[0134] 2) Set batch load related variables. The maximum private space of the slave core is 128KB, of which 1KB is allocated to store scalar local variables. The remaining 127KB space can be allocated to the largest single batch of non-zero elements dval and its column index vector dind available for batch SpMV. Each non-zero element needs to occupy 8B to store the value and 4B to store the column index. Therefore, a single batch can allocate a maximum of 127*1024 / (4*3)=10922 non-zero elements.

[0135] Step S105: Divide the SpMV row block load, and divide the entire matrix into several row blocks by row with row_block_size=256 rows as the granularity.

[0136] Step S106: If there are remaining row blocks to be processed, the slave core will take the row block with the starting row number of _PEN*row_block_size=_PEN*256 for calculation, and in the next iteration, it will cross 63 row blocks (i.e. 64*row_block_size=64*256=16384 rows) to take the next row block. The slave core will take the row block load from the matrix according to the slave core number _PEN for calculation. If there are no remaining row blocks, the slave core will exit.

[0137] Step S107: load the row block row offset vector dptr, take _PEN*row_block_size=_PEN*256 as the offset row_gbgn, and fetch a fragment vector of type int with a length of block_size+1 from the main memory row offset vector ptr to the row block row offset vector dptr in the LDM local memory.

[0138] Step S108: SpMV adaptive decision, a SpMV strategy selection method based on hardware DCache PMU, selects the SpMV strategy to be executed in step S109 according to the shared LDM flag bit enabled in the row block, and selects the batch SpMV method based on shared LDM if it is true, otherwise the batch SpMV method based on hardware DCache is executed.

[0139] Among them, Figure 3 As shown, for the SpMV strategy selection method based on hardware DCache PMU, the steps include:

[0140] Step S601: confirm the sampling parameter settings, including: row block load row sampling rate, single batch DCache miss rate tolerance threshold, batch voting counter, row block shared LDM enable threshold;

[0141] Step S602: Divide the sampling batches. Calculate the number of sampling rows in the row block: sample_row_n = sample_ratio*row_block_size = 0.1*256 = 25 rows. Define the sampling row range as [_PEN*row_block_id:_PEN*row_block_id+25], and the local row number marking range is [0:25];

[0142] Step S603: Start the PMU counter, and start the DCache memory access count and DCache miss rate counters;

[0143] Step S604: Calculate the single batch SpMV, using the SpMV method based on hardware DCache to process the steps, such as Figure 5 As shown, first search for the maximum number of rows that can be processed in a single batch, and at the same time increment the batch counter batch_cnt. If the last row of the sample is processed, that is, the local 25 rows, then exit;

[0144] Step S605: record the PMU counter value;

[0145] Step S606: if the DCache memory access hit rate for x exceeds the single batch DCache miss rate tolerance threshold in step S601 during the single batch SpMV calculation process, that is, dcache_miss_cnt / dcache_access_cnt>batch_dcache_miss_threshold, then the batch counter is incremented by batch_use_sldm_cnt++;

[0146] Step S607: If all sampling batches have been processed, execute step S608, otherwise return to step S603;

[0147] Step S608: Divide the batch voting counter by the total number of sampled batches to obtain the row block shared LDM activation score batch_use_sldm_score=batch_use_sldm_cnt / batch_cnt. If the batch_use_sldm_score value exceeds the row block shared LDM activation threshold block_use_sldm_threshold in step S601, the shared LDM activation flag position is true.

[0148] Step S109: According to the decision result of step S108, the batch SpMV method based on DCache or the batch SpMV method based on shared LDM is selected according to the status of enabling the shared LDM flag.

[0149] Among them, Figure 4 As shown, for the batch SpMV method based on shared LDM, it includes the steps of:

[0150] Step S701: Searching for SpMV batch size;

[0151] Step S702: if the number of non-zero elements in a single row exceeds the size of the private LDM local memory space, use the hardware DCache to access the non-zero element vector val and the non-zero element column index vector ind in the main memory to perform SpMV, i.e. skip step S703 and execute step S704;

[0152] Step S703: According to the number of non-zero elements in a single batch, the corresponding fragments of the non-zero metadata vector val and the corresponding fragments of the non-zero element column index vector ind are loaded from the main memory by DMA into the single batch non-zero element vector dval and the single batch non-element column index vector dind in the LDM local memory;

[0153] Step S704: for a single batch of row loads, SpMV calculation is performed row by row, the process of accessing the main memory input vector x is replaced by accessing the vector sx in the shared LDM, and the result of multiplication and addition of the single row vector of the matrix and the vector x is written into the local position corresponding to the row block output vector dy in the LDM;

[0154] Step S705: if the row block has not been processed, the starting row number of the next batch of loads is refreshed and the process returns to step S701; otherwise, the process executes step S706;

[0155] Step S706: write the row block output vector dy in the LDM into the corresponding fragment position of the main memory output vector y in DMA mode according to the row block load size and the offset.

[0156] Among them, Figure 5 As shown, for the batch SpMV method based on hardware DCache, it includes the steps of:

[0157] Step S801: Searching for SpMV batch size;

[0158] Step S802: if the number of non-zero elements in a single row exceeds the size of the private LDM local memory space, use the hardware DCache to access the non-zero element vector val and the non-zero element column index vector ind in the main memory to perform SpMV, i.e. skip step S803 and execute step S804;

[0159] Step S803: According to the number of non-zero elements in a single batch, the corresponding fragments of the non-zero metadata vector val and the corresponding fragments of the non-zero element column index vector ind are loaded from the main memory by DMA into the single batch non-zero element vector dval and the single batch non-element column index vector dind in the LDM local memory;

[0160] Step S804: For a single batch of row loads, SpMV calculation is performed row by row. The process of accessing the main memory input vector x uses the hardware DCache on the slave core chip for cache optimization. The result of multiplication and addition of the single row vector of the matrix and the vector x is written into the local position corresponding to the row block output vector dy in the LDM.

[0161] Step S805: If the row block has not been processed, the starting row number of the next batch of loads is refreshed and the process returns to step S801; otherwise, the process executes step S806;

[0162] Step S806: write the row block output vector dy in the LDM into the corresponding fragment position of the main memory output vector y in DMA mode according to the row block load size and the offset.

[0163] In order to verify the actual effect of the present invention, the present invention was tested on the new generation Shenwei supercomputing platform, and the slave core optimized version of the present invention was compared with the master core version SpMV. The basic information of the test platform is as follows: equipped with the domestic Shenwei heterogeneous multi-core processor SW26010P, master-slave architecture, slave core LDM space is 256KB, which can be divided into three sections: private LDM, shared LDM and hardware Cache, the default hardware DCache size is 32KB, and mpicxx, mpicc, swg++ and swgcc are used for compilation.

[0164] The test matrix data comes from Suite Sparse. The original data format is Matrix Market (COO) format. In order to facilitate subsequent test verification, it has been preprocessed into CSR format. The experimental results are shown in Table 1. The number of row block load rows in the experiment is set to 256 rows, the single batch DCache miss rate tolerance threshold is set to 0.01, the row block SpMV strategy selection threshold is set to 0.5, and the row block load sampling rate is set to 0.1.

[0165] Table 1

[0166]

[0167] As shown in the results of Table 1, the SpMV method of the present invention has a good acceleration effect. The present invention uses row blocks as the granularity for fine-grained SpMV adaptive tuning, which has high flexibility. At the same time, the present invention uses the DCache PMU counter of the slave core hardware to characterize the row block load characteristics. Users can customize sampling parameters and thresholds, which can truly reflect the adaptability of SW26010P to the load, and has the characteristics of fine-grained, low overhead and high flexibility. In the real SpMV scenario, the sparsity characteristics of sparse matrices are diverse, and fine-grained SpMV strategy selection can improve the overall performance of SpMV.

[0168] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. An adaptive SpMV method based on a new generation of domestic many-core processors, characterized in that: The following steps are involved: Step S101, setting startup parameters; Step S102, obtaining SpMV parameters; Step S103, setting and loading the input vector x in the main memory into the vector sx in the shared LDM; Step S104, setting private LDM local storage space; Step S105, dividing the SpMV row block load; Step S106, if there are remaining rows to be processed, then fetch the rows from the core, otherwise exit; Step S107, loading the row block offset vector dptr and initializing the row block output vector dy; Step S108, SpMV adaptive decision; Step S109, batch calculating the remaining part in the row block, if the shared LDM flag of the row block is true, then using the batch SpMV method based on shared LDM for processing, otherwise using the batch SpMV method based on hardware DCache for processing; Step S110, return to step S106 to continue processing until there are no remaining row blocks to be processed.

2. The adaptive SpMV method based on a new generation domestic many-core processor as claimed in claim 1, characterized in that: Step S101, setting startup parameters, specifically including: Set the load partitioning parameters, including the number of row blocks for load rows; Set the adaptive SpMV decision parameters, including row block load sampling rate, single batch DCache miss rate tolerance threshold, and row block shared LDM enablement threshold; Set shared LDM configuration parameters, including the shared LDM default startup size.

3. The adaptive SpMV method based on a new generation domestic many-core processor according to claim 1, characterized in that: Step S102, obtaining SpMV parameters, specifically includes: Get matrix parameters, CSRMatrx type, including: row offset vector ptr main memory address, non-zero element vector val main memory address, non-zero element column index vector ind main memory address, matrix row number n, matrix non-zero element number nnz; Input vector x main memory address; Output vector y main memory address.

4. The adaptive SpMV method based on a new generation domestic many-core processor according to claim 1, characterized in that: Step S103, setting and loading the input vector x in the main memory into the vector sx in the shared LDM, including two steps of space size mode setting and input vector x loading, specifically including: Set the sharing mode and size of the shared LDM according to the size of the input vector x, that is, the number of matrix columns; Loads input vector x into shared LDM vector sx.

5. The adaptive SpMV method based on a new generation domestic many-core processor as claimed in claim 4, characterized in that: Load the input vector x into the shared LDM vector sx using a cluster-based high-affinity shared LDM loading method, which includes: Step S501: Calculate the slave core cluster number; Step S502: Calculate the local number of the slave core in the slave core cluster; Step S503: Calculate the slave core global number related to the slave core cluster according to the slave core cluster number and the slave core local number inside the slave core cluster; Step S504: evenly divide the x loading load by blocks according to the slave core global number associated with the slave core cluster; Step S505: Align the input vector x to load the payload size according to 8*loop unrolling times; Step S506: Use DMA to load the input vector x in the main memory into the LDM private space LMEM; Step S507: load the input vector x in the LDM private space LMEM into the vector sx in the shared LDM, and accelerate it by using SIMD and loop unrolling; Step S508: Synchronize the slave core array.

6. The adaptive SpMV method based on a new generation domestic many-core processor according to claim 1, characterized in that: Step S104, setting a private LDM local storage space for data cache space for row blocks and batches of SpMV.

7. The adaptive SpMV method based on a new generation domestic many-core processor as claimed in claim 6, characterized in that: Set up private LDM local storage space, including: The row block load related variables are set according to the row block load parameter configuration, including the row block result vector dy corresponding to the row block size, and the row block row offset vector dptr corresponding to the row block size + 1; Batch load related variables are set to determine the maximum single batch non-zero element vector dval and its column index vector dind length available to the batch SpMV based on the size of the available space of the private LDM.

8. The adaptive SpMV method based on a new generation domestic many-core processor according to claim 1, characterized in that: Step S105 , dividing the SpMV row block load, specifically dividing the row into a plurality of row blocks according to a preset BLOCK_SIZE row.

9. The adaptive SpMV method based on a new generation domestic many-core processor according to claim 1, characterized in that: Step S106, if there are remaining row blocks to be processed, then take the row blocks from the core, otherwise exit, specifically including: if there are remaining row blocks to be processed, then the core takes the row block load from the matrix according to the core number _PEN for calculation; if the remaining number of rows is less than the preset BLOCK_SIZE, then the remaining number of rows is used as a row block for calculation; if the actual number of row blocks block_size is calculated and there is no remaining row block, then exit from the core.

10. The adaptive SpMV method based on a new generation domestic many-core processor according to claim 1, characterized in that: Step S107, loading the row block offset vector dptr and initializing the row block output vector dy, specifically including loading the row block offset vector dptr, taking _PEN*BLOCK_SIZE as the offset row_gbgn, taking a fragment vector of type int with a length of block_size+1 from the main memory row offset vector ptr to the LDM local memory row block offset vector dptr.

Images