Statistical counting chip and statistical counting method

Abstract

The invention relates to the technical field of chip statistical counting, and discloses a statistical counting chip and a statistical counting method, and the chip comprises a statistical module which comprises at least one statistical unit, and each statistical unit comprises a preset number of counters; the cache module is used for storing the statistical count value of each counter; and the statistical processing module is used for sequentially polling each counter, reading the counting value of the current counter when polling the current counter, obtaining the statistical counting value corresponding to the current counter from the cache module, and writing the sum of the statistical counting value and the counting value back to the cache module after calculating the sum of the statistical counting value and the counting value so as to update the statistical counting value of the current counter. And the counting value in the current counter is reset. Through a counter + ram resource hybrid statistics architecture, resource consumption caused by counter resources with large bit width can be greatly reduced, statistical performance is not lost, EDA layout and wiring are facilitated, and a large number of statistical counting time sequences are easier to converge.

Description

Technical Field

[0001] The present invention relates to the technical field of large-scale chip counting processing, and in particular to a statistical counting chip and a statistical counting method. Background Art

[0002] The counting scheme of traditional chips directly uses a 64-bit counter. When the counting pulse is 1, the counter accumulates the count. When it is 0, the count value remains unchanged. If the user wants to read the statistics, he can directly read the counter. In fact, this counter serves as both a counting function and a cache function. It seems to be more convenient to operate, but it actually wastes a lot of chip logic resources. Summary of the invention

[0003] In view of this, the present invention provides a statistical counting chip and a statistical counting method, which can solve the problem of resource consumption caused by large-bit-width counter resources in the chip.

[0004] In a first aspect, an embodiment of the invention provides a statistical counting chip, including: a statistical module, a statistical processing module, and a cache module, wherein:

[0005] The statistical module includes at least one statistical unit, each statistical unit includes a preset number of counters; the cache module is used to store the statistical count values ​​of each counter;

[0006] The statistical processing module is used to cycle through each counter in turn, read the count value of the current counter when cycling through the current counter, and obtain the statistical count value corresponding to the current counter from the cache module, calculate the sum of the statistical count value and the count value and write it back to the cache module to update the statistical count value of the current counter, and clear the count value in the current counter.

[0007] The statistical counting chip provided by the embodiment of the present invention can greatly reduce the resource consumption caused by large-bit-width counter resources through a new architecture of mixed statistics of counter + RAM resources. It is functionally equivalent to the counter method that is completely built with logic resources, and there will be no loss in statistical performance. It is convenient for EDA synthesis tools to layout and route, and for a large number of statistical counts, the timing is easier to converge.

[0008] In an optional implementation, the cache module includes two ports, which are respectively used to update the statistical count value of each counter and read out the statistical count value of the corresponding counter based on a statistical request.

[0009] The embodiment of the present invention updates the statistical count values ​​of each counter through a dedicated port, which can ensure that the update operation will not be interfered by the read operation, can quickly process new data input, and ensure the timeliness of statistical data. Since the update and read operations are performed through different ports, the possibility of read-write conflicts is reduced. Since the functions of the two ports are relatively independent, modifying the operation of one port will not have much impact on the other port, which makes system maintenance and expansion easier and reduces the cost of system development and maintenance.

[0010] In an optional implementation, the number of the statistical units is determined according to the number of statistical items in the statistical module, and each statistical item corresponds to a counter.

[0011] In the embodiment of the present invention, since each statistical item has a unique counter corresponding thereto, the statistical process can accurately perform counting operations on each specific statistical item, and the clear corresponding relationship effectively prevents the confusion of counters between different statistical items. The statistical module can flexibly set the number of statistical items according to actual needs, and then determine the number of statistical units. This design can easily adapt to different statistical needs, so that the chip can play an effective statistical function in different application scenarios. When the entire statistical system needs to be upgraded or expanded, the statistical units and corresponding counters can be added in an orderly manner according to the newly added statistical items, and the relevant data processing modules can be appropriately adjusted to adapt to the new statistical scale and requirements; this method of determining the number of statistical units and the number of statistical items makes the architecture of the entire statistical chip clearer and easier to understand. Whether it is the developer who is developing and debugging the system, or the later maintenance personnel who are troubleshooting and optimizing the system, they can easily find the corresponding statistical units and counters according to the statistical items, clarify the functions and effects of each part, thereby improving the comprehensibility and maintainability of the entire system.

[0012] In an optional implementation, each statistical item in the statistical module corresponds to a unique address code, and the address code is used to query the statistical count value of the corresponding counter.

[0013] The embodiment of the present invention adopts this query method based on address coding to greatly improve the query efficiency. Compared with the method of traversing all counters to find the required statistical count value, the address coding can directly locate the target, saving a lot of time. When it is necessary to add a new statistical item in the statistical module, it is only necessary to assign a new unique address code to the new statistical item, and configure the counter corresponding to the statistical item and its related data processing logic accordingly, making the expansion of the system relatively simple.

[0014] In an optional embodiment, the chip further includes:

[0015] A request receiving module is used to obtain statistical requests sent by users;

[0016] A request parsing module, used to parse the statistical request and obtain the address of the statistical item to be queried in the statistical request;

[0017] The statistical count value reading module is used to search for a corresponding counter from the cache module based on the statistical item address to read the statistical count value.

[0018] Through the collaborative work of these three modules, the chip of the embodiment of the present invention can meet various statistical requests of users. Whether it is a simple query of a single statistical item or a complex query of multiple statistical items, it can be effectively processed. Since the statistical count values ​​in the cache module can be read quickly and accurately, users can obtain the latest data in a timely manner, and real-time performance and accuracy can be guaranteed.

[0019] In an optional implementation, the bit width of the cache module is greater than the bit width of the counter.

[0020] The larger bit width of the cache module in the embodiment of the present invention reserves enough space for data storage, and can easily accommodate newly added data content, without the need to frequently modify or upgrade the cache module at the hardware level, thereby improving the scalability of the system. In addition, counters with different bit widths may be used in different application scenarios. The larger bit width of the cache module enables it to be compatible with counters of multiple bit width specifications. Regardless of the bit width of the counter, its count value can be smoothly stored in the cache module, which makes the entire statistical system more flexible in selecting counters.

[0021] In a second aspect, an embodiment of the present invention provides a statistical counting method, based on the chip described in the first aspect of the embodiment of the present invention, comprising:

[0022] Cycle through each counter in the statistical module in turn, read the count value of the current counter when cycling through the current counter, and obtain the statistical count value corresponding to the current counter from the cache module, calculate the sum of the statistical count value and the count value and write it back to the cache module to update the statistical count value of the current counter, and clear the count value in the current counter.

[0023] The embodiment of the present invention can ensure that the data of all counters are updated in time by cycling each counter in turn. In each cycle, the newly generated count value (current value of the counter) is added to the statistical count value in the cache, which can accurately reflect the actual situation of the statistical item. After the statistical count value is updated, the count value in the counter is cleared so that the counter can be put into use again and count in a cycle. This effectively utilizes the counting range of the counter and avoids the situation where the counter cannot work normally due to count saturation. The process of round-robin update is a planned write and read operation on the cache module. This orderly operation method helps to optimize the use efficiency of the cache module. By reasonably updating the statistical count value, the data in the cache module can always be kept up to date, and space can be released in time to store new statistical data.

[0024] In an optional implementation, when it is monitored that a user sends a statistical request, the statistical request sent by the user is obtained and the statistical request is parsed to obtain the address of the statistical item to be queried in the statistical request;

[0025] Based on the address of the statistical item, a corresponding counter is searched from the cache module to read the statistical count value.

[0026] In an optional implementation, before the step of obtaining the statistical request sent by the user, the method further includes: address coding the statistical items that the user needs to count, and making a one-to-one correspondence with the timers in the statistical unit.

[0027] The embodiment of the present invention assigns a unique address code to each statistical item. When it is necessary to obtain the statistical count value of the counter corresponding to a certain statistical item, the corresponding counter can be accurately located by relying on the address code, which greatly improves the query efficiency. When it is necessary to add a new statistical item to the statistical module, it is only necessary to assign a new, unique address code to the new statistical item, and configure the counter corresponding to the statistical item and its related data processing logic accordingly. This method makes the expansion of the system relatively simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of the structure of a statistical counting chip according to an embodiment of the present invention;

[0030] Figure 2An example diagram of the application of a statistical module according to an embodiment of the present invention in a smart network card including five subsystems;

[0031] Figure 3 A schematic diagram of a statistical unit performing round-robin counting according to an embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a flow chart of a statistical processing module performing round-robin statistical counting according to an embodiment of the present invention;

[0033] Figure 5 It is a schematic diagram of the structure of another statistical counting chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0035] Nowadays, network services are diversified and data traffic is growing rapidly. In cloud service systems that process big data, some CPU core work is offloaded to smart network cards to improve data processing performance and save CPU computing overhead. As long as it is a cloud service provider, smart network cards are an unavoidable equipment requirement and a major technical difficulty. The current mainstream practice is to offload network forwarding functions and some storage functions to smart network cards. Therefore, smart network cards play a more important role in cloud services, and it is necessary to read relevant statistical counting information from the hardware for operation and maintenance. The more functions there are, the larger the scale of related statistical counting, the more logical resources need to be consumed, and the greater the challenge to hardware resources.

[0036] Generally, the statistics and counting contents of smart network cards include but are not limited to the statistics of the optical port's sent and received packets, the count of the number of read and write requests of the PCIe interface, etc., which are all transmitted by each system module through a 1-bit counting bus and connected to the statistics module. The statistics module detects once a clock, and if it is 1, the counter increases by 1. Generally, network cards run for a long time, so the counting bit width will be very large. Generally, a 64-bit bit width counter is commonly used to ensure that the long-term counting will not overflow and ensure the correctness of the statistical counting. A large bit width means more resource consumption.

[0037] The network cards of the servers are running for a long time, and the bit width of the statistical count is relatively large. Generally, the bit width of each statistical count is 64 bits, and the maximum count value is 2. 64, Smart NICs are generally composed of five subsystems: virtio_net, virtio_blk, ovs, pcie, and rdma, which requires at least 4096 64-bit wide counters.

[0038] Generally, smart network cards are developed by FPGA chips, and chip resources are limited. 4096 64-bit wide counters consume a huge amount of logic resources. A rough calculation shows that a 64-bit counter consumes about 64 ALMs (logic resources) after integration. If there are 4096 counters, 262,144 ALMs are needed. The commonly used FPGA chip is Intel's agilex027 device, which has a total of 912,800 ALMs. Statistics show that it accounts for about 1 / 4 of the total, and the functions of other subsystems cannot be stored at all.

[0039] The existing solution is to reduce the number of counters, which means reducing the monitoring of modules within the subsystem. If there is a problem online, it is impossible to obtain comprehensive and detailed statistics, and the problem cannot be located. Of course, it can be reduced appropriately, but the overall effect is not significant.

[0040] According to an embodiment of the present invention, a statistical counting chip is provided, which adopts a new architecture of counter + RAM resources mixed statistics, which can greatly reduce the resource consumption caused by large-bit-width counter resources, and at the same time there will be no loss in statistical performance. Figure 1 As shown, it includes: a statistical module, a statistical processing module, and a cache module, wherein:

[0041] The statistical module includes at least one statistical unit, each statistical unit includes a preset number of counters;

[0042] A cache module, used for storing the statistical count values ​​of each counter;

[0043] The statistical processing module is used to cycle through each counter in turn, read the count value of the current counter when cycling the current counter, and obtain the statistical count value corresponding to the current counter from the cache module, obtain the statistical count value corresponding to the current counter from the cache and add the count value of the current counter read, and then write it back to the cache module to update the statistical count value of the current counter and clear the count value in the current counter.

[0044] For example, Figure 2As shown in the figure, the five subsystems of virtio_net, virtio_blk, ovs, pcie, and rdma in the smart network card are used as functional modules that need to be counted. Assume that these five subsystems have 4096 statistical items. Each statistical item is a wire in the chip, and the wire can transmit high and low levels. When it is high, it means that the statistical count needs to be increased by 1. For example, there are 1024 statistical items and 1024 wires in the virtio_net subsystem, which are collectively called the statistical bus. These wires will be passed to the statistical module for statistics.

[0045] The statistical module is generally composed of multiple statistical units. The number of statistical units is determined by the number of statistical items in the statistical module. Each statistical item corresponds to a counter. For example, each statistical unit has 512 counters. Figure 3 According to the number of statistical items in the above example, the five modules need a total of 4096 statistical items, which are divided into 8 groups (i.e., including 8 groups such as Figure 3 The counter shown in the figure) can be directly instantiated into 8 copies when needed.

[0046] In the embodiment of the present invention, since each statistical item has a unique counter corresponding thereto, the statistical process can accurately perform counting operations on each specific statistical item, and the clear corresponding relationship effectively prevents the confusion of counters between different statistical items. The statistical module can flexibly set the number of statistical items according to actual needs, and then determine the number of statistical units. This design can easily adapt to different statistical needs, so that the chip can play an effective statistical function in different application scenarios. When the entire statistical system needs to be upgraded or expanded, the statistical units and corresponding counters can be added in an orderly manner according to the newly added statistical items, and the relevant data processing modules can be appropriately adjusted to adapt to the new statistical scale and requirements; this method of determining the number of statistical units and the number of statistical items makes the architecture of the entire statistical chip clearer and easier to understand. Whether it is the developer who is developing and debugging the system, or the later maintenance personnel who are troubleshooting and optimizing the system, they can easily find the corresponding statistical units and counters according to the statistical items, clarify the functions and effects of each part, thereby improving the comprehensibility and maintainability of the entire system.

[0047] In an embodiment of the present invention, the statistical items that need to be counted must be uniformly addressed when they are connected to the statistical module, so that users can access the statistical count values. In one embodiment, the following address coding can be done: the address coding range of virtio_net is 0-1023, the address range of virtio_blk is 1024-1223, and the address range of ovs is 1536-2047. If the user wants to access the second statistical item of virtio_blk, the address needs to be input as 1025 to obtain the statistical count value. Since the statistical items and counters are one-to-one corresponding, the corresponding counter of the query device can be obtained according to the address coding of the statistical item to obtain the corresponding statistical count value.

[0048] The embodiment of the present invention adopts a query method based on address coding to greatly improve the query efficiency. Compared with the method of traversing all counters to find the required statistical count value, the address coding can directly locate the target, saving a lot of time. When it is necessary to add a new statistical item in the statistical module, it is only necessary to assign a new, unique address code to the new statistical item, and configure the counter corresponding to the statistical item and its related data processing logic accordingly, making the expansion of the system relatively simple.

[0049] In the embodiment of the present invention, a statistical structure unit is formed for a preset number of RAMs corresponding to the storage of statistical timing values. The bit width of the RAM is greater than the bit width of the counter. Each statistical unit is composed of 512 12-bit bit width counters, plus a 64-bit wide, 512-deep RAM cache. 512 statistical count values ​​are stored in the cache RAM. Each statistical unit is connected to a maximum of 512 statistical count lines, that is, a maximum of 512 statistical items.

[0050] In the embodiment of the present invention, the bit width of the RAM is greater than the bit width of the counter because counters of different bit widths may be used in different application scenarios. The larger bit width of the cache module enables it to be compatible with counters of various bit width specifications. No matter how large the bit width of the counter is, its count value can be smoothly stored in the cache module. This makes the entire statistical system more flexible in selecting counters. In addition, as the system continues to develop and the amount of data gradually increases, the larger bit width of the cache module reserves sufficient space for data storage. For example, as the requirements for statistical accuracy increase, it may be necessary to divide the count value of the counter more finely, or to add more attribute information related to the count. At this time, the cache module can easily accommodate these newly added data contents by virtue of its larger bit width, without the need to frequently transform or upgrade the cache module at the hardware level, thereby improving the scalability of the system.

[0051] In the embodiment of the present invention, each counter works independently. When a high level appears on each statistical line, the counter will add 1. The round-robin mechanism will keep cycling through each counter in turn. If it cycles to the first counter, it will first read the value of the first counter from the RAM. For example, the value read out is 10. Then add the current count value of the first counter. For example, if the current value of the counter is 2, write it back to the RAM, and the value written back to the RAM is 10+2=12. At the same time, the count of the first counter is cleared and the counting starts again. When the round-robin mechanism cycles to the first counter again, it repeats the same operation. The value read out is 12. During the cycle, the first counter increases by 3 again. Then 12+3=15 is written to the RAM, and then the counter is cleared and counted again. This operation is repeated over and over again, which is equivalent to the counter only recording the "increment". The processing flow of the statistical processing module is as follows Figure 4 shown.

[0052] Since the bit width of the counter is 12 bits, when the count reaches 4096, the count value will roll back to 0. Because it takes a certain amount of time to cycle through 512 counters, to process a cnt, first read a data from RAM, which takes 2 clock cycles, then add it to cnt, which takes one clock cycle, and then write it back to RAM, which takes 1 clock cycle, a total of 4 clock cycles. There are a total of 512 counters, and a cycle consumes a total of 2048 clock cycles. So even if the statistical count is always counting, it is guaranteed to be processed before the count overflows and the increment is written back to RAM.

[0053] The cache module in the embodiment of the present invention includes two ports, which are respectively used to update the statistical values ​​of each counter and read the statistical values ​​of the corresponding counter based on the statistical request. That is, the update statistics occupy one port of the RAM, and the statistical count value is read from another port of the RAM. The interface for reading the statistical count value only needs to pass a RAM address to read the statistical count value. Updating the statistical count values ​​of each counter through a dedicated port can ensure that the update operation will not be interfered by the read operation, and can quickly process new data input to ensure the timeliness of the statistical data. Since the update and read operations are performed through different ports, the possibility of read-write conflicts is reduced. Since the functions of the two ports are relatively independent, modifying the operation of one port will not have much impact on the other port, which makes the maintenance and expansion of the system easier and reduces the cost of system development and maintenance.

[0054] Based on the system architecture of the statistical counting chip provided by the embodiment of the present invention, its resource utilization is that a 12-bit counter consumes about 12 ALMs, so a total of about 4096*12=49,152 ALMs are used. Compared with the previous saving of about 200,000 ALMs, the saving effect is still very obvious. The RAM resource consumption is about 4096*64=262,144 bits, which is about 14 M20Ks. For Intel's agilex027 device, there are a total of 13272 M20Ks, and the impact is also minimal.

[0055] The statistical counting chip provided by the embodiment of the present invention adopts a new architecture of mixed statistics of counter + RAM resources. The counter is only used for counting, and the cache needs to use a dedicated RAM for caching. Separating counting and caching can greatly reduce the resource consumption caused by large-bit-width counter resources, and is functionally equivalent to the counter method that is completely built with logic resources. There will be no loss in statistical performance, which is convenient for EDA synthesis tools to layout and route. For a large number of statistical counts, the timing is more easily converged.

[0056] The statistical counting chip provided in the embodiment of the present invention is as follows: Figure 5 As shown, it also includes:

[0057] A request receiving module is used to obtain statistical requests sent by users;

[0058] The request parsing module is used to parse the statistical request and obtain the address of the statistical item to be queried in the statistical request;

[0059] The statistical count value reading module is used to search for a corresponding counter from the cache module based on the statistical item address to read the statistical count value.

[0060] Through the collaborative work of these three modules, the chip of the embodiment of the present invention can meet various statistical requests of users. Whether it is a simple query of a single statistical item or a complex query of multiple statistical items, it can be effectively processed. Since the statistical count values ​​in the cache module can be read quickly and accurately, users can obtain the latest data in a timely manner, and real-time performance and accuracy can be guaranteed.

[0061] The embodiment of the present invention further provides a statistical counting method based on the above chip, comprising:

[0062] Cycle through each counter in the statistical module in turn, read the count value of the current counter when cycling through the current counter, and obtain the statistical count value corresponding to the current counter from the cache module, calculate the sum of the statistical count value and the count value and write it back to the cache module to update the statistical count value of the current counter, and clear the count value in the current counter.

[0063] The embodiment of the present invention can ensure that the data of all counters are updated in time by cycling each counter in turn. In each cycle, the newly generated count value (current value of the counter) is added to the statistical count value in the cache, which can accurately reflect the actual situation of the statistical item. After the statistical count value is updated, the count value in the counter is cleared so that the counter can be put into use again and count in a cycle. This effectively utilizes the counting range of the counter and avoids the situation where the counter cannot work normally due to count saturation. The process of round-robin update is a planned write and read operation on the cache module. This orderly operation method helps to optimize the use efficiency of the cache module. By reasonably updating the statistical count value, the data in the cache module can always be kept up to date, and space can be released in time to store new statistical data. For example, in a big data statistical scenario, the space of the cache module is limited. Through this round-robin update mechanism, it can be ensured that the cache space is reasonably utilized to store the most valuable statistical count values.

[0064] When a user sends a statistical request, the embodiment of the present invention obtains the statistical request sent by the user and parses the statistical request to obtain the address of the statistical item to be queried in the statistical request; based on the statistical item address, the corresponding counter is searched from the cache module to read the statistical count value. The query method based on address coding greatly improves the query efficiency.

[0065] Before the step of obtaining the statistical request sent by the user, the embodiment of the present invention also includes: address coding the statistical items that the user needs to count, and corresponding them one by one with the timer in the statistical unit. By assigning a unique address code to each statistical item, when it is necessary to obtain the statistical count value of the counter corresponding to a certain statistical item, the corresponding counter can be accurately located by relying on the address code, which greatly improves the query efficiency. When it is necessary to add a new statistical item to the statistical module, it is only necessary to assign a new, unique address code to the new statistical item, and configure the counter corresponding to the statistical item and its related data processing logic accordingly. This method makes the expansion of the system relatively simple.

[0066] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A statistical counting chip, characterized in that: include: Statistics module, statistics processing module, cache module, including: The statistical module includes at least one statistical unit, each statistical unit includes a preset number of counters; The cache module is used to store the statistical count values ​​of each counter; The statistical processing module is used to cycle through each counter in turn, read the count value of the current counter when cycling through the current counter, and obtain the statistical count value corresponding to the current counter from the cache module, calculate the sum of the statistical count value and the count value and write it back to the cache module to update the statistical count value of the current counter, and clear the count value in the current counter.

2. The chip according to claim 1, characterized in that: The cache module includes two ports, which are respectively used to update the statistical count value of each counter and read out the statistical count value of the corresponding counter based on a statistical request.

3. The chip according to claim 1, characterized in that: The number of the statistical units is determined according to the number of statistical items in the statistical module, and each statistical item corresponds to a counter.

4. The chip according to claim 3, characterized in that: Each statistical item in the statistical module corresponds to a unique address code, and the address code is used to query the statistical count value of the corresponding counter.

5. The chip according to claim 4, characterized in that: Also includes: A request receiving module is used to obtain statistical requests sent by users; A request parsing module, used to parse the statistical request and obtain the address of the statistical item to be queried in the statistical request; The statistical count value reading module is used to search for a corresponding counter from the cache module based on the statistical item address to read the statistical count value.

6. The chip according to claim 1, characterized in that: The bit width of the cache module is greater than the bit width of the counter.

7. A statistical counting method based on the chip according to any one of claims 1 to 6, characterized in that: include: Cycle through each counter in the statistical module in turn, read the count value of the current counter when cycling through the current counter, and obtain the statistical count value corresponding to the current counter from the cache module, calculate the sum of the statistical count value and the count value and write it back to the cache module to update the statistical count value of the current counter, and clear the count value in the current counter.

8. The method according to claim 7, characterized in that Also includes: When a user sends a statistical request, the statistical request sent by the user is obtained and parsed to obtain the address of the statistical item to be queried in the statistical request; Based on the address of the statistical item, a corresponding counter is searched from the cache module to read the statistical count value.

9. The method according to claim 8, characterized in that Before the step of obtaining the statistical request sent by the user, the method further includes: address coding the statistical items that the user needs to count, and making a one-to-one correspondence with the timers in the statistical unit.

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